1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Support for PC -- Routing of Interrupts
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/dmi.h>
15 #include <linux/smp.h>
16 #include <linux/spinlock.h>
17 #include <asm/io_apic.h>
18 #include <linux/irq.h>
19 #include <linux/acpi.h>
21 #include <asm/i8259.h>
22 #include <asm/pc-conf-reg.h>
23 #include <asm/pci_x86.h>
25 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
26 #define PIRQ_VERSION 0x0100
28 static int broken_hp_bios_irq9;
29 static int acer_tm360_irqrouting;
31 static struct irq_routing_table *pirq_table;
33 static int pirq_enable_irq(struct pci_dev *dev);
34 static void pirq_disable_irq(struct pci_dev *dev);
37 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
38 * Avoid using: 13, 14 and 15 (FP error and IDE).
39 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
41 unsigned int pcibios_irq_mask = 0xfff8;
43 static int pirq_penalty[16] = {
44 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
45 0, 0, 0, 0, 1000, 100000, 100000, 100000
51 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
52 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
54 int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq,
58 struct irq_router_handler {
60 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
63 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
64 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
67 * Check passed address for the PCI IRQ Routing Table signature
68 * and perform checksum verification.
71 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
73 struct irq_routing_table *rt;
77 rt = (struct irq_routing_table *) addr;
78 if (rt->signature != PIRQ_SIGNATURE ||
79 rt->version != PIRQ_VERSION ||
81 rt->size < sizeof(struct irq_routing_table))
84 for (i = 0; i < rt->size; i++)
87 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
97 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
100 static struct irq_routing_table * __init pirq_find_routing_table(void)
103 struct irq_routing_table *rt;
105 if (pirq_table_addr) {
106 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
109 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
111 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
112 rt = pirq_check_routing_table(addr);
120 * If we have a IRQ routing table, use it to search for peer host
121 * bridges. It's a gross hack, but since there are no other known
122 * ways how to get a list of buses, we have to go this way.
125 static void __init pirq_peer_trick(void)
127 struct irq_routing_table *rt = pirq_table;
132 memset(busmap, 0, sizeof(busmap));
133 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
138 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
139 for (j = 0; j < 4; j++)
140 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
146 for (i = 1; i < 256; i++) {
147 if (!busmap[i] || pci_find_bus(0, i))
149 pcibios_scan_root(i);
151 pcibios_last_bus = -1;
155 * Code for querying and setting of IRQ routes on various interrupt routers.
156 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
159 void elcr_set_level_irq(unsigned int irq)
161 unsigned char mask = 1 << (irq & 7);
162 unsigned int port = PIC_ELCR1 + (irq >> 3);
164 static u16 elcr_irq_mask;
166 if (irq >= 16 || (1 << irq) & elcr_irq_mask)
169 elcr_irq_mask |= (1 << irq);
170 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
173 DBG(KERN_DEBUG " -> edge");
174 outb(val | mask, port);
179 * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used
180 * with the ALi FinALi 486 chipset. The IBC is not decoded in the
181 * PCI configuration space, so we identify it by the accompanying
182 * M1489 Cache-Memory PCI Controller (CMP) ASIC.
184 * There are four 4-bit mappings provided, spread across two PCI
185 * INTx Routing Table Mapping Registers, available in the port I/O
186 * space accessible indirectly via the index/data register pair at
187 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2
188 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4
189 * lines are mapped in the low and the high 4-bit nibble of the
190 * corresponding register as follows:
209 * In addition to the usual ELCR register pair there is a separate
210 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O
211 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines
212 * respectively. Any bit set to 1 causes interrupts coming on the
213 * corresponding line to be passed to ISA as edge-triggered and
214 * otherwise they are passed as level-triggered. Manufacturer's
215 * documentation says this register has to be set consistently with
216 * the relevant ELCR register.
218 * Accesses to the port I/O space concerned here need to be unlocked
219 * by writing the value of 0xc5 to the Lock Register at index 0x03
220 * beforehand. Any other value written to said register prevents
221 * further accesses from reaching the register file, except for the
222 * Lock Register being written with 0xc5 again.
226 * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
230 #define PC_CONF_FINALI_LOCK 0x03u
231 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u
232 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u
233 #define PC_CONF_FINALI_PCI_INTX_SENS 0x44u
235 #define PC_CONF_FINALI_LOCK_KEY 0xc5u
237 static u8 read_pc_conf_nybble(u8 base, u8 index)
239 u8 reg = base + (index >> 1);
242 x = pc_conf_get(reg);
243 return index & 1 ? x >> 4 : x & 0xf;
246 static void write_pc_conf_nybble(u8 base, u8 index, u8 val)
248 u8 reg = base + (index >> 1);
251 x = pc_conf_get(reg);
252 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val;
257 * FinALi pirq rules are as follows:
259 * - bit 0 selects between INTx Routing Table Mapping Registers,
261 * - bit 3 selects the nibble within the INTx Routing Table Mapping Register,
263 * - bits 7:4 map to bits 3:0 of the PCI INTx Sensitivity Register.
265 static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev,
268 static const u8 irqmap[16] = {
269 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15
275 index = (pirq & 1) << 1 | (pirq & 8) >> 3;
276 raw_spin_lock_irqsave(&pc_conf_lock, flags);
277 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
278 x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index)];
279 pc_conf_set(PC_CONF_FINALI_LOCK, 0);
280 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
284 static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev,
287 static const u8 irqmap[16] = {
288 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15
290 u8 val = irqmap[irq];
297 index = (pirq & 1) << 1 | (pirq & 8) >> 3;
298 raw_spin_lock_irqsave(&pc_conf_lock, flags);
299 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
300 write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index, val);
301 pc_conf_set(PC_CONF_FINALI_LOCK, 0);
302 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
306 static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev,
309 u8 mask = ~((pirq & 0xf0u) >> 4);
313 elcr_set_level_irq(irq);
314 raw_spin_lock_irqsave(&pc_conf_lock, flags);
315 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
316 trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS);
318 pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, trig);
319 pc_conf_set(PC_CONF_FINALI_LOCK, 0);
320 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
325 * Common IRQ routing practice: nibbles in config space,
326 * offset by some magic constant.
328 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
331 unsigned reg = offset + (nr >> 1);
333 pci_read_config_byte(router, reg, &x);
334 return (nr & 1) ? (x >> 4) : (x & 0xf);
337 static void write_config_nybble(struct pci_dev *router, unsigned offset,
338 unsigned nr, unsigned int val)
341 unsigned reg = offset + (nr >> 1);
343 pci_read_config_byte(router, reg, &x);
344 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
345 pci_write_config_byte(router, reg, x);
349 * ALI pirq entries are damn ugly, and completely undocumented.
350 * This has been figured out from pirq tables, and it's not a pretty
353 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
355 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
357 WARN_ON_ONCE(pirq > 16);
358 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
361 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
363 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
364 unsigned int val = irqmap[irq];
366 WARN_ON_ONCE(pirq > 16);
368 write_config_nybble(router, 0x48, pirq-1, val);
375 * PIRQ routing for the 82374EB/82374SB EISA System Component (ESC)
376 * ASIC used with the Intel 82420 and 82430 PCIsets. The ESC is not
377 * decoded in the PCI configuration space, so we identify it by the
378 * accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC.
380 * There are four PIRQ Route Control registers, available in the
381 * port I/O space accessible indirectly via the index/data register
382 * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the
383 * PIRQ0/1/2/3# lines respectively. The semantics is the same as
384 * with the PIIX router.
386 * Accesses to the port I/O space concerned here need to be unlocked
387 * by writing the value of 0x0f to the ESC ID Register at index 0x02
388 * beforehand. Any other value written to said register prevents
389 * further accesses from reaching the register file, except for the
390 * ESC ID Register being written with 0x0f again.
394 * "82374EB/82374SB EISA System Component (ESC)", Intel Corporation,
395 * Order Number: 290476-004, March 1996
397 * "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order
398 * Number: 290477-004, March 1996
401 #define PC_CONF_I82374_ESC_ID 0x02u
402 #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u
404 #define PC_CONF_I82374_ESC_ID_KEY 0x0fu
406 static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
413 if (reg >= 1 && reg <= 4)
414 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1;
416 raw_spin_lock_irqsave(&pc_conf_lock, flags);
417 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY);
418 x = pc_conf_get(reg);
419 pc_conf_set(PC_CONF_I82374_ESC_ID, 0);
420 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
421 return (x < 16) ? x : 0;
424 static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
431 if (reg >= 1 && reg <= 4)
432 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1;
434 raw_spin_lock_irqsave(&pc_conf_lock, flags);
435 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY);
436 pc_conf_set(reg, irq);
437 pc_conf_set(PC_CONF_I82374_ESC_ID, 0);
438 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
443 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
444 * just a pointer to the config space.
446 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
450 pci_read_config_byte(router, pirq, &x);
451 return (x < 16) ? x : 0;
454 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
456 pci_write_config_byte(router, pirq, irq);
461 * PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the
462 * Intel 82420EX PCIset.
464 * There are only two PIRQ Route Control registers, available in the
465 * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67
466 * for the PIRQ0# and PIRQ1# lines respectively. The semantics is
467 * the same as with the PIIX router.
471 * "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC)
472 * and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
473 * 290488-004, December 1995
476 #define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u
478 static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
484 if (reg >= 1 && reg <= 2)
485 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
487 pci_read_config_byte(router, reg, &x);
488 return (x < 16) ? x : 0;
491 static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
497 if (reg >= 1 && reg <= 2)
498 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
500 pci_write_config_byte(router, reg, irq);
505 * The VIA pirq rules are nibble-based, like ALI,
506 * but without the ugly irq number munging.
507 * However, PIRQD is in the upper instead of lower 4 bits.
509 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
511 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
514 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
516 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
521 * The VIA pirq rules are nibble-based, like ALI,
522 * but without the ugly irq number munging.
523 * However, for 82C586, nibble map is different .
525 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
527 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
529 WARN_ON_ONCE(pirq > 5);
530 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
533 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
535 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
537 WARN_ON_ONCE(pirq > 5);
538 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
543 * ITE 8330G pirq rules are nibble-based
544 * FIXME: pirqmap may be { 1, 0, 3, 2 },
545 * 2+3 are both mapped to irq 9 on my system
547 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
549 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
551 WARN_ON_ONCE(pirq > 4);
552 return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
555 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
557 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
559 WARN_ON_ONCE(pirq > 4);
560 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
565 * OPTI: high four bits are nibble pointer..
566 * I wonder what the low bits do?
568 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
570 return read_config_nybble(router, 0xb8, pirq >> 4);
573 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
575 write_config_nybble(router, 0xb8, pirq >> 4, irq);
580 * Cyrix: nibble offset 0x5C
581 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
582 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
584 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
586 return read_config_nybble(router, 0x5C, (pirq-1)^1);
589 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
591 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
596 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
597 * We have to deal with the following issues here:
598 * - vendors have different ideas about the meaning of link values
599 * - some onboard devices (integrated in the chipset) have special
600 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
601 * - different revision of the router have a different layout for
602 * the routing registers, particularly for the onchip devices
604 * For all routing registers the common thing is we have one byte
605 * per routeable link which is defined as:
606 * bit 7 IRQ mapping enabled (0) or disabled (1)
607 * bits [6:4] reserved (sometimes used for onchip devices)
608 * bits [3:0] IRQ to map to
609 * allowed: 3-7, 9-12, 14-15
610 * reserved: 0, 1, 2, 8, 13
612 * The config-space registers located at 0x41/0x42/0x43/0x44 are
613 * always used to route the normal PCI INT A/B/C/D respectively.
614 * Apparently there are systems implementing PCI routing table using
615 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
616 * We try our best to handle both link mappings.
618 * Currently (2003-05-21) it appears most SiS chipsets follow the
619 * definition of routing registers from the SiS-5595 southbridge.
620 * According to the SiS 5595 datasheets the revision id's of the
621 * router (ISA-bridge) should be 0x01 or 0xb0.
623 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
624 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
625 * They seem to work with the current routing code. However there is
626 * some concern because of the two USB-OHCI HCs (original SiS 5595
627 * had only one). YMMV.
629 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
632 * bits [6:5] must be written 01
633 * bit 4 channel-select primary (0), secondary (1)
636 * bit 6 OHCI function disabled (0), enabled (1)
638 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
640 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
642 * We support USBIRQ (in addition to INTA-INTD) and keep the
643 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
645 * Currently the only reported exception is the new SiS 65x chipset
646 * which includes the SiS 69x southbridge. Here we have the 85C503
647 * router revision 0x04 and there are changes in the register layout
648 * mostly related to the different USB HCs with USB 2.0 support.
650 * Onchip routing for router rev-id 0x04 (try-and-error observation)
652 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
653 * bit 6-4 are probably unused, not like 5595
656 #define PIRQ_SIS_IRQ_MASK 0x0f
657 #define PIRQ_SIS_IRQ_DISABLE 0x80
658 #define PIRQ_SIS_USB_ENABLE 0x40
660 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
666 if (reg >= 0x01 && reg <= 0x04)
668 pci_read_config_byte(router, reg, &x);
669 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
672 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
678 if (reg >= 0x01 && reg <= 0x04)
680 pci_read_config_byte(router, reg, &x);
681 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
682 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
683 pci_write_config_byte(router, reg, x);
689 * VLSI: nibble offset 0x74 - educated guess due to routing table and
690 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
691 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
692 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
693 * for the busbridge to the docking station.
696 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
698 WARN_ON_ONCE(pirq >= 9);
700 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
703 return read_config_nybble(router, 0x74, pirq-1);
706 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
708 WARN_ON_ONCE(pirq >= 9);
710 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
713 write_config_nybble(router, 0x74, pirq-1, irq);
718 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
719 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
720 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
721 * register is a straight binary coding of desired PIC IRQ (low nibble).
723 * The 'link' value in the PIRQ table is already in the correct format
724 * for the Index register. There are some special index values:
725 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
726 * and 0x03 for SMBus.
728 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
731 return inb(0xc01) & 0xf;
734 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
742 /* Support for AMD756 PCI IRQ Routing
743 * Jhon H. Caicedo <jhcaiced@osso.org.co>
744 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
745 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
746 * The AMD756 pirq rules are nibble-based
747 * offset 0x56 0-3 PIRQA 4-7 PIRQB
748 * offset 0x57 0-3 PIRQC 4-7 PIRQD
750 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
755 irq = read_config_nybble(router, 0x56, pirq - 1);
757 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
758 dev->vendor, dev->device, pirq, irq);
762 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
765 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
766 dev->vendor, dev->device, pirq, irq);
768 write_config_nybble(router, 0x56, pirq - 1, irq);
775 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
777 outb(0x10 + ((pirq - 1) >> 1), 0x24);
778 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
781 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
785 outb(0x10 + ((pirq - 1) >> 1), 0x24);
787 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
792 #ifdef CONFIG_PCI_BIOS
794 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
796 struct pci_dev *bridge;
797 int pin = pci_get_interrupt_pin(dev, &bridge);
798 return pcibios_set_irq_routing(bridge, pin - 1, irq);
803 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
805 static struct pci_device_id __initdata pirq_440gx[] = {
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
811 /* 440GX has a proprietary PIRQ router -- don't use it */
812 if (pci_dev_present(pirq_440gx))
816 case PCI_DEVICE_ID_INTEL_82375:
817 r->name = "PCEB/ESC";
818 r->get = pirq_esc_get;
819 r->set = pirq_esc_set;
821 case PCI_DEVICE_ID_INTEL_82371FB_0:
822 case PCI_DEVICE_ID_INTEL_82371SB_0:
823 case PCI_DEVICE_ID_INTEL_82371AB_0:
824 case PCI_DEVICE_ID_INTEL_82371MX:
825 case PCI_DEVICE_ID_INTEL_82443MX_0:
826 case PCI_DEVICE_ID_INTEL_82801AA_0:
827 case PCI_DEVICE_ID_INTEL_82801AB_0:
828 case PCI_DEVICE_ID_INTEL_82801BA_0:
829 case PCI_DEVICE_ID_INTEL_82801BA_10:
830 case PCI_DEVICE_ID_INTEL_82801CA_0:
831 case PCI_DEVICE_ID_INTEL_82801CA_12:
832 case PCI_DEVICE_ID_INTEL_82801DB_0:
833 case PCI_DEVICE_ID_INTEL_82801E_0:
834 case PCI_DEVICE_ID_INTEL_82801EB_0:
835 case PCI_DEVICE_ID_INTEL_ESB_1:
836 case PCI_DEVICE_ID_INTEL_ICH6_0:
837 case PCI_DEVICE_ID_INTEL_ICH6_1:
838 case PCI_DEVICE_ID_INTEL_ICH7_0:
839 case PCI_DEVICE_ID_INTEL_ICH7_1:
840 case PCI_DEVICE_ID_INTEL_ICH7_30:
841 case PCI_DEVICE_ID_INTEL_ICH7_31:
842 case PCI_DEVICE_ID_INTEL_TGP_LPC:
843 case PCI_DEVICE_ID_INTEL_ESB2_0:
844 case PCI_DEVICE_ID_INTEL_ICH8_0:
845 case PCI_DEVICE_ID_INTEL_ICH8_1:
846 case PCI_DEVICE_ID_INTEL_ICH8_2:
847 case PCI_DEVICE_ID_INTEL_ICH8_3:
848 case PCI_DEVICE_ID_INTEL_ICH8_4:
849 case PCI_DEVICE_ID_INTEL_ICH9_0:
850 case PCI_DEVICE_ID_INTEL_ICH9_1:
851 case PCI_DEVICE_ID_INTEL_ICH9_2:
852 case PCI_DEVICE_ID_INTEL_ICH9_3:
853 case PCI_DEVICE_ID_INTEL_ICH9_4:
854 case PCI_DEVICE_ID_INTEL_ICH9_5:
855 case PCI_DEVICE_ID_INTEL_EP80579_0:
856 case PCI_DEVICE_ID_INTEL_ICH10_0:
857 case PCI_DEVICE_ID_INTEL_ICH10_1:
858 case PCI_DEVICE_ID_INTEL_ICH10_2:
859 case PCI_DEVICE_ID_INTEL_ICH10_3:
860 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
861 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
862 r->name = "PIIX/ICH";
863 r->get = pirq_piix_get;
864 r->set = pirq_piix_set;
866 case PCI_DEVICE_ID_INTEL_82425:
868 r->get = pirq_ib_get;
869 r->set = pirq_ib_set;
873 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
874 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
875 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
876 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
877 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
878 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
879 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
880 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
881 r->name = "PIIX/ICH";
882 r->get = pirq_piix_get;
883 r->set = pirq_piix_set;
890 static __init int via_router_probe(struct irq_router *r,
891 struct pci_dev *router, u16 device)
893 /* FIXME: We should move some of the quirk fixup stuff here */
896 * workarounds for some buggy BIOSes
898 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
899 switch (router->device) {
900 case PCI_DEVICE_ID_VIA_82C686:
902 * Asus k7m bios wrongly reports 82C686A
905 device = PCI_DEVICE_ID_VIA_82C686;
907 case PCI_DEVICE_ID_VIA_8235:
909 * Asus a7v-x bios wrongly reports 8235
912 device = PCI_DEVICE_ID_VIA_8235;
914 case PCI_DEVICE_ID_VIA_8237:
916 * Asus a7v600 bios wrongly reports 8237
919 device = PCI_DEVICE_ID_VIA_8237;
925 case PCI_DEVICE_ID_VIA_82C586_0:
927 r->get = pirq_via586_get;
928 r->set = pirq_via586_set;
930 case PCI_DEVICE_ID_VIA_82C596:
931 case PCI_DEVICE_ID_VIA_82C686:
932 case PCI_DEVICE_ID_VIA_8231:
933 case PCI_DEVICE_ID_VIA_8233A:
934 case PCI_DEVICE_ID_VIA_8235:
935 case PCI_DEVICE_ID_VIA_8237:
936 /* FIXME: add new ones for 8233/5 */
938 r->get = pirq_via_get;
939 r->set = pirq_via_set;
945 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
948 case PCI_DEVICE_ID_VLSI_82C534:
949 r->name = "VLSI 82C534";
950 r->get = pirq_vlsi_get;
951 r->set = pirq_vlsi_set;
958 static __init int serverworks_router_probe(struct irq_router *r,
959 struct pci_dev *router, u16 device)
962 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
963 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
964 r->name = "ServerWorks";
965 r->get = pirq_serverworks_get;
966 r->set = pirq_serverworks_set;
972 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
974 if (device != PCI_DEVICE_ID_SI_503)
978 r->get = pirq_sis_get;
979 r->set = pirq_sis_set;
983 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
986 case PCI_DEVICE_ID_CYRIX_5520:
988 r->get = pirq_cyrix_get;
989 r->set = pirq_cyrix_set;
995 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
998 case PCI_DEVICE_ID_OPTI_82C700:
1000 r->get = pirq_opti_get;
1001 r->set = pirq_opti_set;
1007 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1010 case PCI_DEVICE_ID_ITE_IT8330G_0:
1012 r->get = pirq_ite_get;
1013 r->set = pirq_ite_set;
1019 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1022 case PCI_DEVICE_ID_AL_M1489:
1024 r->get = pirq_finali_get;
1025 r->set = pirq_finali_set;
1026 r->lvl = pirq_finali_lvl;
1028 case PCI_DEVICE_ID_AL_M1533:
1029 case PCI_DEVICE_ID_AL_M1563:
1031 r->get = pirq_ali_get;
1032 r->set = pirq_ali_set;
1038 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1041 case PCI_DEVICE_ID_AMD_VIPER_740B:
1044 case PCI_DEVICE_ID_AMD_VIPER_7413:
1047 case PCI_DEVICE_ID_AMD_VIPER_7443:
1053 r->get = pirq_amd756_get;
1054 r->set = pirq_amd756_set;
1058 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1061 case PCI_DEVICE_ID_PICOPOWER_PT86C523:
1062 r->name = "PicoPower PT86C523";
1063 r->get = pirq_pico_get;
1064 r->set = pirq_pico_set;
1067 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
1068 r->name = "PicoPower PT86C523 rev. BB+";
1069 r->get = pirq_pico_get;
1070 r->set = pirq_pico_set;
1076 static __initdata struct irq_router_handler pirq_routers[] = {
1077 { PCI_VENDOR_ID_INTEL, intel_router_probe },
1078 { PCI_VENDOR_ID_AL, ali_router_probe },
1079 { PCI_VENDOR_ID_ITE, ite_router_probe },
1080 { PCI_VENDOR_ID_VIA, via_router_probe },
1081 { PCI_VENDOR_ID_OPTI, opti_router_probe },
1082 { PCI_VENDOR_ID_SI, sis_router_probe },
1083 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
1084 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
1085 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
1086 { PCI_VENDOR_ID_AMD, amd_router_probe },
1087 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
1088 /* Someone with docs needs to add the ATI Radeon IGP */
1091 static struct irq_router pirq_router;
1092 static struct pci_dev *pirq_router_dev;
1096 * FIXME: should we have an option to say "generic for
1100 static void __init pirq_find_router(struct irq_router *r)
1102 struct irq_routing_table *rt = pirq_table;
1103 struct irq_router_handler *h;
1105 #ifdef CONFIG_PCI_BIOS
1106 if (!rt->signature) {
1107 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
1108 r->set = pirq_bios_set;
1114 /* Default unless a driver reloads it */
1115 r->name = "default";
1119 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
1120 rt->rtr_vendor, rt->rtr_device);
1122 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus,
1124 if (!pirq_router_dev) {
1125 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
1126 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
1130 for (h = pirq_routers; h->vendor; h++) {
1131 /* First look for a router match */
1132 if (rt->rtr_vendor == h->vendor &&
1133 h->probe(r, pirq_router_dev, rt->rtr_device))
1135 /* Fall back to a device match */
1136 if (pirq_router_dev->vendor == h->vendor &&
1137 h->probe(r, pirq_router_dev, pirq_router_dev->device))
1140 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
1142 pirq_router_dev->vendor, pirq_router_dev->device);
1144 /* The device remains referenced for the kernel lifetime */
1147 static struct irq_info *pirq_get_info(struct pci_dev *dev)
1149 struct irq_routing_table *rt = pirq_table;
1150 int entries = (rt->size - sizeof(struct irq_routing_table)) /
1151 sizeof(struct irq_info);
1152 struct irq_info *info;
1154 for (info = rt->slots; entries--; info++)
1155 if (info->bus == dev->bus->number &&
1156 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
1161 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
1164 struct irq_info *info;
1165 int i, pirq, newirq;
1168 struct irq_router *r = &pirq_router;
1169 struct pci_dev *dev2 = NULL;
1173 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1175 dev_dbg(&dev->dev, "no interrupt pin\n");
1179 if (io_apic_assign_pci_irqs)
1182 /* Find IRQ routing entry */
1187 info = pirq_get_info(dev);
1189 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
1193 pirq = info->irq[pin - 1].link;
1194 mask = info->irq[pin - 1].bitmap;
1196 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
1199 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
1200 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
1201 mask &= pcibios_irq_mask;
1203 /* Work around broken HP Pavilion Notebooks which assign USB to
1204 IRQ 9 even though it is actually wired to IRQ 11 */
1206 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
1208 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
1209 r->set(pirq_router_dev, dev, pirq, 11);
1212 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
1213 if (acer_tm360_irqrouting && dev->irq == 11 &&
1214 dev->vendor == PCI_VENDOR_ID_O2) {
1217 dev->irq = r->get(pirq_router_dev, dev, pirq);
1218 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1222 * Find the best IRQ to assign: use the one
1223 * reported by the device if possible.
1226 if (newirq && !((1 << newirq) & mask)) {
1227 if (pci_probe & PCI_USE_PIRQ_MASK)
1230 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
1231 "%#x; try pci=usepirqmask\n", newirq, mask);
1233 if (!newirq && assign) {
1234 for (i = 0; i < 16; i++) {
1235 if (!(mask & (1 << i)))
1237 if (pirq_penalty[i] < pirq_penalty[newirq] &&
1238 can_request_irq(i, IRQF_SHARED))
1242 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
1244 /* Check if it is hardcoded */
1245 if ((pirq & 0xf0) == 0xf0) {
1248 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
1249 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
1252 r->lvl(pirq_router_dev, dev, pirq, irq);
1254 elcr_set_level_irq(irq);
1255 } else if (newirq && r->set &&
1256 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
1257 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
1259 r->lvl(pirq_router_dev, dev, pirq, newirq);
1261 elcr_set_level_irq(newirq);
1268 if (newirq && mask == (1 << newirq)) {
1272 dev_dbg(&dev->dev, "can't route interrupt\n");
1276 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
1278 /* Update IRQ for all devices with the same pirq value */
1279 for_each_pci_dev(dev2) {
1280 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
1284 info = pirq_get_info(dev2);
1287 if (info->irq[pin - 1].link == pirq) {
1289 * We refuse to override the dev->irq
1290 * information. Give a warning!
1292 if (dev2->irq && dev2->irq != irq && \
1293 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1294 ((1 << dev2->irq) & mask))) {
1295 #ifndef CONFIG_PCI_MSI
1296 dev_info(&dev2->dev, "IRQ routing conflict: "
1297 "have IRQ %d, want IRQ %d\n",
1303 pirq_penalty[irq]++;
1305 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1306 irq, pci_name(dev2));
1312 void __init pcibios_fixup_irqs(void)
1314 struct pci_dev *dev = NULL;
1317 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1318 for_each_pci_dev(dev) {
1320 * If the BIOS has set an out of range IRQ number, just
1321 * ignore it. Also keep track of which IRQ's are
1324 if (dev->irq >= 16) {
1325 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1329 * If the IRQ is already assigned to a PCI device,
1330 * ignore its ISA use penalty
1332 if (pirq_penalty[dev->irq] >= 100 &&
1333 pirq_penalty[dev->irq] < 100000)
1334 pirq_penalty[dev->irq] = 0;
1335 pirq_penalty[dev->irq]++;
1338 if (io_apic_assign_pci_irqs)
1342 for_each_pci_dev(dev) {
1343 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1348 * Still no IRQ? Try to lookup one...
1351 pcibios_lookup_irq(dev, 0);
1356 * Work around broken HP Pavilion Notebooks which assign USB to
1357 * IRQ 9 even though it is actually wired to IRQ 11
1359 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1361 if (!broken_hp_bios_irq9) {
1362 broken_hp_bios_irq9 = 1;
1363 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1370 * Work around broken Acer TravelMate 360 Notebooks which assign
1371 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1373 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1375 if (!acer_tm360_irqrouting) {
1376 acer_tm360_irqrouting = 1;
1377 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1383 static const struct dmi_system_id pciirq_dmi_table[] __initconst = {
1385 .callback = fix_broken_hp_bios_irq9,
1386 .ident = "HP Pavilion N5400 Series Laptop",
1388 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1389 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1390 DMI_MATCH(DMI_PRODUCT_VERSION,
1391 "HP Pavilion Notebook Model GE"),
1392 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1396 .callback = fix_acer_tm360_irqrouting,
1397 .ident = "Acer TravelMate 36x Laptop",
1399 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1400 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1406 void __init pcibios_irq_init(void)
1408 struct irq_routing_table *rtable = NULL;
1410 DBG(KERN_DEBUG "PCI: IRQ init\n");
1412 if (raw_pci_ops == NULL)
1415 dmi_check_system(pciirq_dmi_table);
1417 pirq_table = pirq_find_routing_table();
1419 #ifdef CONFIG_PCI_BIOS
1420 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
1421 pirq_table = pcibios_get_irq_routing_table();
1422 rtable = pirq_table;
1427 pirq_find_router(&pirq_router);
1428 if (pirq_table->exclusive_irqs) {
1430 for (i = 0; i < 16; i++)
1431 if (!(pirq_table->exclusive_irqs & (1 << i)))
1432 pirq_penalty[i] += 100;
1435 * If we're using the I/O APIC, avoid using the PCI IRQ
1438 if (io_apic_assign_pci_irqs) {
1444 x86_init.pci.fixup_irqs();
1446 if (io_apic_assign_pci_irqs && pci_routeirq) {
1447 struct pci_dev *dev = NULL;
1449 * PCI IRQ routing is set up by pci_enable_device(), but we
1450 * also do it here in case there are still broken drivers that
1451 * don't use pci_enable_device().
1453 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1454 for_each_pci_dev(dev)
1455 pirq_enable_irq(dev);
1459 static void pirq_penalize_isa_irq(int irq, int active)
1462 * If any ISAPnP device reports an IRQ in its list of possible
1463 * IRQ's, we try to avoid assigning it to PCI devices.
1467 pirq_penalty[irq] += 1000;
1469 pirq_penalty[irq] += 100;
1473 void pcibios_penalize_isa_irq(int irq, int active)
1477 acpi_penalize_isa_irq(irq, active);
1480 pirq_penalize_isa_irq(irq, active);
1483 static int pirq_enable_irq(struct pci_dev *dev)
1487 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1488 if (pin && !pcibios_lookup_irq(dev, 1)) {
1491 if (!io_apic_assign_pci_irqs && dev->irq)
1494 if (io_apic_assign_pci_irqs) {
1495 #ifdef CONFIG_X86_IO_APIC
1496 struct pci_dev *temp_dev;
1499 if (dev->irq_managed && dev->irq > 0)
1502 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1503 PCI_SLOT(dev->devfn), pin - 1);
1505 * Busses behind bridges are typically not listed in the MP-table.
1506 * In this case we have to look up the IRQ based on the parent bus,
1507 * parent slot, and pin number. The SMP code detects such bridged
1508 * busses itself so we should get into this branch reliably.
1511 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1512 struct pci_dev *bridge = dev->bus->self;
1514 pin = pci_swizzle_interrupt_pin(dev, pin);
1515 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1516 PCI_SLOT(bridge->devfn),
1519 dev_warn(&dev->dev, "using bridge %s "
1520 "INT %c to get IRQ %d\n",
1521 pci_name(bridge), 'A' + pin - 1,
1527 dev->irq_managed = 1;
1529 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1530 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1533 msg = "; probably buggy MP table";
1535 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1538 msg = "; please try using pci=biosirq";
1541 * With IDE legacy devices the IRQ lookup failure is not
1544 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1545 !(dev->class & 0x5))
1548 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1549 'A' + pin - 1, msg);
1554 bool mp_should_keep_irq(struct device *dev)
1556 if (dev->power.is_prepared)
1559 if (dev->power.runtime_status == RPM_SUSPENDING)
1566 static void pirq_disable_irq(struct pci_dev *dev)
1568 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
1569 dev->irq_managed && dev->irq) {
1570 mp_unmap_irq(dev->irq);
1572 dev->irq_managed = 0;