1 // SPDX-License-Identifier: GPL-2.0
3 * direct.c - Low-level direct PCI config space access
7 #include <linux/init.h>
9 #include <asm/pci_x86.h>
12 * Functions for accessing PCI base (first 256 bytes) and extended
13 * (4096 bytes per PCI function) configuration space with type 1
17 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
18 (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
19 | (devfn << 8) | (reg & 0xFC))
21 static int pci_conf1_read(unsigned int seg, unsigned int bus,
22 unsigned int devfn, int reg, int len, u32 *value)
26 if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) {
31 raw_spin_lock_irqsave(&pci_config_lock, flags);
33 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
37 *value = inb(0xCFC + (reg & 3));
40 *value = inw(0xCFC + (reg & 2));
47 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
52 static int pci_conf1_write(unsigned int seg, unsigned int bus,
53 unsigned int devfn, int reg, int len, u32 value)
57 if (seg || (bus > 255) || (devfn > 255) || (reg > 4095))
60 raw_spin_lock_irqsave(&pci_config_lock, flags);
62 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
66 outb((u8)value, 0xCFC + (reg & 3));
69 outw((u16)value, 0xCFC + (reg & 2));
72 outl((u32)value, 0xCFC);
76 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
81 #undef PCI_CONF1_ADDRESS
83 const struct pci_raw_ops pci_direct_conf1 = {
84 .read = pci_conf1_read,
85 .write = pci_conf1_write,
90 * Functions for accessing PCI configuration space with type 2 accesses
93 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
95 static int pci_conf2_read(unsigned int seg, unsigned int bus,
96 unsigned int devfn, int reg, int len, u32 *value)
102 if ((bus > 255) || (devfn > 255) || (reg > 255)) {
107 dev = PCI_SLOT(devfn);
108 fn = PCI_FUNC(devfn);
111 return PCIBIOS_DEVICE_NOT_FOUND;
113 raw_spin_lock_irqsave(&pci_config_lock, flags);
115 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
116 outb((u8)bus, 0xCFA);
120 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
123 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
126 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
132 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
137 static int pci_conf2_write(unsigned int seg, unsigned int bus,
138 unsigned int devfn, int reg, int len, u32 value)
144 if ((bus > 255) || (devfn > 255) || (reg > 255))
147 dev = PCI_SLOT(devfn);
148 fn = PCI_FUNC(devfn);
151 return PCIBIOS_DEVICE_NOT_FOUND;
153 raw_spin_lock_irqsave(&pci_config_lock, flags);
155 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
156 outb((u8)bus, 0xCFA);
160 outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
163 outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
166 outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
172 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
177 #undef PCI_CONF2_ADDRESS
179 static const struct pci_raw_ops pci_direct_conf2 = {
180 .read = pci_conf2_read,
181 .write = pci_conf2_write,
186 * Before we decide to use direct hardware access mechanisms, we try to do some
187 * trivial checks to ensure it at least _seems_ to be working -- we just test
188 * whether bus 00 contains a host bridge (this is similar to checking
189 * techniques used in XFree86, but ours should be more reliable since we
190 * attempt to make use of direct access hints provided by the PCI BIOS).
192 * This should be close to trivial, but it isn't, because there are buggy
193 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
195 static int __init pci_sanity_check(const struct pci_raw_ops *o)
200 if (pci_probe & PCI_NO_CHECKS)
202 /* Assume Type 1 works for newer systems.
203 This handles machines that don't have anything on PCI Bus 0. */
204 if (dmi_get_bios_year() >= 2001)
207 for (devfn = 0; devfn < 0x100; devfn++) {
208 if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
210 if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
213 if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
215 if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
219 DBG(KERN_WARNING "PCI: Sanity check failed\n");
223 static int __init pci_check_type1(void)
229 local_irq_save(flags);
233 outl(0x80000000, 0xCF8);
234 if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) {
238 local_irq_restore(flags);
243 static int __init pci_check_type2(void)
248 local_irq_save(flags);
253 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
254 pci_sanity_check(&pci_direct_conf2)) {
258 local_irq_restore(flags);
263 void __init pci_direct_init(int type)
267 printk(KERN_INFO "PCI: Using configuration type %d for base access\n",
270 raw_pci_ops = &pci_direct_conf1;
273 if (!(pci_probe & PCI_HAS_IO_ECS))
275 printk(KERN_INFO "PCI: Using configuration type 1 "
276 "for extended access\n");
277 raw_pci_ext_ops = &pci_direct_conf1;
280 raw_pci_ops = &pci_direct_conf2;
283 int __init pci_direct_probe(void)
285 if ((pci_probe & PCI_PROBE_CONF1) == 0)
287 if (!request_region(0xCF8, 8, "PCI conf1"))
290 if (pci_check_type1()) {
291 raw_pci_ops = &pci_direct_conf1;
292 port_cf9_safe = true;
295 release_region(0xCF8, 8);
298 if ((pci_probe & PCI_PROBE_CONF2) == 0)
300 if (!request_region(0xCF8, 4, "PCI conf2"))
302 if (!request_region(0xC000, 0x1000, "PCI conf2"))
305 if (pci_check_type2()) {
306 raw_pci_ops = &pci_direct_conf2;
307 port_cf9_safe = true;
311 release_region(0xC000, 0x1000);
313 release_region(0xCF8, 4);