arch/x86/net/bpf_jit_comp32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Just-In-Time compiler for eBPF filters on IA32 (32bit x86)
   4  *
   5  * Author: Wang YanQing (udknight@gmail.com)
   6  * The code based on code and ideas from:
   7  * Eric Dumazet (eric.dumazet@gmail.com)
   8  * and from:
   9  * Shubham Bansal <illusionist.neo@gmail.com>
  10  */
  11
  12 #include <linux/netdevice.h>
  13 #include <linux/filter.h>
  14 #include <linux/if_vlan.h>
  15 #include <asm/cacheflush.h>
  16 #include <asm/set_memory.h>
  17 #include <asm/nospec-branch.h>
  18 #include <linux/bpf.h>
  19
  20 /*
  21  * eBPF prog stack layout:
  22  *
  23  *                         high
  24  * original ESP =>        +-----+
  25  *                        |     | callee saved registers
  26  *                        +-----+
  27  *                        | ... | eBPF JIT scratch space
  28  * BPF_FP,IA32_EBP  =>    +-----+
  29  *                        | ... | eBPF prog stack
  30  *                        +-----+
  31  *                        |RSVD | JIT scratchpad
  32  * current ESP =>         +-----+
  33  *                        |     |
  34  *                        | ... | Function call stack
  35  *                        |     |
  36  *                        +-----+
  37  *                          low
  38  *
  39  * The callee saved registers:
  40  *
  41  *                                high
  42  * original ESP =>        +------------------+ \
  43  *                        |        ebp       | |
  44  * current EBP =>         +------------------+ } callee saved registers
  45  *                        |    ebx,esi,edi   | |
  46  *                        +------------------+ /
  47  *                                low
  48  */
  49
  50 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  51 {
  52         if (len == 1)
  53                 *ptr = bytes;
  54         else if (len == 2)
  55                 *(u16 *)ptr = bytes;
  56         else {
  57                 *(u32 *)ptr = bytes;
  58                 barrier();
  59         }
  60         return ptr + len;
  61 }
  62
  63 #define EMIT(bytes, len) \
  64         do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
  65
  66 #define EMIT1(b1)               EMIT(b1, 1)
  67 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  68 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  69 #define EMIT4(b1, b2, b3, b4)   \
  70         EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  71
  72 #define EMIT1_off32(b1, off) \
  73         do { EMIT1(b1); EMIT(off, 4); } while (0)
  74 #define EMIT2_off32(b1, b2, off) \
  75         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  76 #define EMIT3_off32(b1, b2, b3, off) \
  77         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  78 #define EMIT4_off32(b1, b2, b3, b4, off) \
  79         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  80
  81 #define jmp_label(label, jmp_insn_len) (label - cnt - jmp_insn_len)
  82
  83 static bool is_imm8(int value)
  84 {
  85         return value <= 127 && value >= -128;
  86 }
  87
  88 static bool is_simm32(s64 value)
  89 {
  90         return value == (s64) (s32) value;
  91 }
  92
  93 #define STACK_OFFSET(k) (k)
  94 #define TCALL_CNT       (MAX_BPF_JIT_REG + 0)   /* Tail Call Count */
  95
  96 #define IA32_EAX        (0x0)
  97 #define IA32_EBX        (0x3)
  98 #define IA32_ECX        (0x1)
  99 #define IA32_EDX        (0x2)
 100 #define IA32_ESI        (0x6)
 101 #define IA32_EDI        (0x7)
 102 #define IA32_EBP        (0x5)
 103 #define IA32_ESP        (0x4)
 104
 105 /*
 106  * List of x86 cond jumps opcodes (. + s8)
 107  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
 108  */
 109 #define IA32_JB  0x72
 110 #define IA32_JAE 0x73
 111 #define IA32_JE  0x74
 112 #define IA32_JNE 0x75
 113 #define IA32_JBE 0x76
 114 #define IA32_JA  0x77
 115 #define IA32_JL  0x7C
 116 #define IA32_JGE 0x7D
 117 #define IA32_JLE 0x7E
 118 #define IA32_JG  0x7F
 119
 120 #define COND_JMP_OPCODE_INVALID (0xFF)
 121
 122 /*
 123  * Map eBPF registers to IA32 32bit registers or stack scratch space.
 124  *
 125  * 1. All the registers, R0-R10, are mapped to scratch space on stack.
 126  * 2. We need two 64 bit temp registers to do complex operations on eBPF
 127  *    registers.
 128  * 3. For performance reason, the BPF_REG_AX for blinding constant, is
 129  *    mapped to real hardware register pair, IA32_ESI and IA32_EDI.
 130  *
 131  * As the eBPF registers are all 64 bit registers and IA32 has only 32 bit
 132  * registers, we have to map each eBPF registers with two IA32 32 bit regs
 133  * or scratch memory space and we have to build eBPF 64 bit register from those.
 134  *
 135  * We use IA32_EAX, IA32_EDX, IA32_ECX, IA32_EBX as temporary registers.
 136  */
 137 static const u8 bpf2ia32[][2] = {
 138         /* Return value from in-kernel function, and exit value from eBPF */
 139         [BPF_REG_0] = {STACK_OFFSET(0), STACK_OFFSET(4)},
 140
 141         /* The arguments from eBPF program to in-kernel function */
 142         /* Stored on stack scratch space */
 143         [BPF_REG_1] = {STACK_OFFSET(8), STACK_OFFSET(12)},
 144         [BPF_REG_2] = {STACK_OFFSET(16), STACK_OFFSET(20)},
 145         [BPF_REG_3] = {STACK_OFFSET(24), STACK_OFFSET(28)},
 146         [BPF_REG_4] = {STACK_OFFSET(32), STACK_OFFSET(36)},
 147         [BPF_REG_5] = {STACK_OFFSET(40), STACK_OFFSET(44)},
 148
 149         /* Callee saved registers that in-kernel function will preserve */
 150         /* Stored on stack scratch space */
 151         [BPF_REG_6] = {STACK_OFFSET(48), STACK_OFFSET(52)},
 152         [BPF_REG_7] = {STACK_OFFSET(56), STACK_OFFSET(60)},
 153         [BPF_REG_8] = {STACK_OFFSET(64), STACK_OFFSET(68)},
 154         [BPF_REG_9] = {STACK_OFFSET(72), STACK_OFFSET(76)},
 155
 156         /* Read only Frame Pointer to access Stack */
 157         [BPF_REG_FP] = {STACK_OFFSET(80), STACK_OFFSET(84)},
 158
 159         /* Temporary register for blinding constants. */
 160         [BPF_REG_AX] = {IA32_ESI, IA32_EDI},
 161
 162         /* Tail call count. Stored on stack scratch space. */
 163         [TCALL_CNT] = {STACK_OFFSET(88), STACK_OFFSET(92)},
 164 };
 165
 166 #define dst_lo  dst[0]
 167 #define dst_hi  dst[1]
 168 #define src_lo  src[0]
 169 #define src_hi  src[1]
 170
 171 #define STACK_ALIGNMENT 8
 172 /*
 173  * Stack space for BPF_REG_1, BPF_REG_2, BPF_REG_3, BPF_REG_4,
 174  * BPF_REG_5, BPF_REG_6, BPF_REG_7, BPF_REG_8, BPF_REG_9,
 175  * BPF_REG_FP, BPF_REG_AX and Tail call counts.
 176  */
 177 #define SCRATCH_SIZE 96
 178
 179 /* Total stack size used in JITed code */
 180 #define _STACK_SIZE     (stack_depth + SCRATCH_SIZE)
 181
 182 #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
 183
 184 /* Get the offset of eBPF REGISTERs stored on scratch space. */
 185 #define STACK_VAR(off) (off)
 186
 187 /* Encode 'dst_reg' register into IA32 opcode 'byte' */
 188 static u8 add_1reg(u8 byte, u32 dst_reg)
 189 {
 190         return byte + dst_reg;
 191 }
 192
 193 /* Encode 'dst_reg' and 'src_reg' registers into IA32 opcode 'byte' */
 194 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 195 {
 196         return byte + dst_reg + (src_reg << 3);
 197 }
 198
 199 static void jit_fill_hole(void *area, unsigned int size)
 200 {
 201         /* Fill whole space with int3 instructions */
 202         memset(area, 0xcc, size);
 203 }
 204
 205 static inline void emit_ia32_mov_i(const u8 dst, const u32 val, bool dstk,
 206                                    u8 **pprog)
 207 {
 208         u8 *prog = *pprog;
 209         int cnt = 0;
 210
 211         if (dstk) {
 212                 if (val == 0) {
 213                         /* xor eax,eax */
 214                         EMIT2(0x33, add_2reg(0xC0, IA32_EAX, IA32_EAX));
 215                         /* mov dword ptr [ebp+off],eax */
 216                         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
 217                               STACK_VAR(dst));
 218                 } else {
 219                         EMIT3_off32(0xC7, add_1reg(0x40, IA32_EBP),
 220                                     STACK_VAR(dst), val);
 221                 }
 222         } else {
 223                 if (val == 0)
 224                         EMIT2(0x33, add_2reg(0xC0, dst, dst));
 225                 else
 226                         EMIT2_off32(0xC7, add_1reg(0xC0, dst),
 227                                     val);
 228         }
 229         *pprog = prog;
 230 }
 231
 232 /* dst = imm (4 bytes)*/
 233 static inline void emit_ia32_mov_r(const u8 dst, const u8 src, bool dstk,
 234                                    bool sstk, u8 **pprog)
 235 {
 236         u8 *prog = *pprog;
 237         int cnt = 0;
 238         u8 sreg = sstk ? IA32_EAX : src;
 239
 240         if (sstk)
 241                 /* mov eax,dword ptr [ebp+off] */
 242                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
 243         if (dstk)
 244                 /* mov dword ptr [ebp+off],eax */
 245                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, sreg), STACK_VAR(dst));
 246         else
 247                 /* mov dst,sreg */
 248                 EMIT2(0x89, add_2reg(0xC0, dst, sreg));
 249
 250         *pprog = prog;
 251 }
 252
 253 /* dst = src */
 254 static inline void emit_ia32_mov_r64(const bool is64, const u8 dst[],
 255                                      const u8 src[], bool dstk,
 256                                      bool sstk, u8 **pprog)
 257 {
 258         emit_ia32_mov_r(dst_lo, src_lo, dstk, sstk, pprog);
 259         if (is64)
 260                 /* complete 8 byte move */
 261                 emit_ia32_mov_r(dst_hi, src_hi, dstk, sstk, pprog);
 262         else
 263                 /* zero out high 4 bytes */
 264                 emit_ia32_mov_i(dst_hi, 0, dstk, pprog);
 265 }
 266
 267 /* Sign extended move */
 268 static inline void emit_ia32_mov_i64(const bool is64, const u8 dst[],
 269                                      const u32 val, bool dstk, u8 **pprog)
 270 {
 271         u32 hi = 0;
 272
 273         if (is64 && (val & (1<<31)))
 274                 hi = (u32)~0;
 275         emit_ia32_mov_i(dst_lo, val, dstk, pprog);
 276         emit_ia32_mov_i(dst_hi, hi, dstk, pprog);
 277 }
 278
 279 /*
 280  * ALU operation (32 bit)
 281  * dst = dst * src
 282  */
 283 static inline void emit_ia32_mul_r(const u8 dst, const u8 src, bool dstk,
 284                                    bool sstk, u8 **pprog)
 285 {
 286         u8 *prog = *pprog;
 287         int cnt = 0;
 288         u8 sreg = sstk ? IA32_ECX : src;
 289
 290         if (sstk)
 291                 /* mov ecx,dword ptr [ebp+off] */
 292                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
 293
 294         if (dstk)
 295                 /* mov eax,dword ptr [ebp+off] */
 296                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
 297         else
 298                 /* mov eax,dst */
 299                 EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
 300
 301
 302         EMIT2(0xF7, add_1reg(0xE0, sreg));
 303
 304         if (dstk)
 305                 /* mov dword ptr [ebp+off],eax */
 306                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
 307                       STACK_VAR(dst));
 308         else
 309                 /* mov dst,eax */
 310                 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
 311
 312         *pprog = prog;
 313 }
 314
 315 static inline void emit_ia32_to_le_r64(const u8 dst[], s32 val,
 316                                          bool dstk, u8 **pprog)
 317 {
 318         u8 *prog = *pprog;
 319         int cnt = 0;
 320         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 321         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 322
 323         if (dstk && val != 64) {
 324                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 325                       STACK_VAR(dst_lo));
 326                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 327                       STACK_VAR(dst_hi));
 328         }
 329         switch (val) {
 330         case 16:
 331                 /*
 332                  * Emit 'movzwl eax,ax' to zero extend 16-bit
 333                  * into 64 bit
 334                  */
 335                 EMIT2(0x0F, 0xB7);
 336                 EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
 337                 /* xor dreg_hi,dreg_hi */
 338                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 339                 break;
 340         case 32:
 341                 /* xor dreg_hi,dreg_hi */
 342                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 343                 break;
 344         case 64:
 345                 /* nop */
 346                 break;
 347         }
 348
 349         if (dstk && val != 64) {
 350                 /* mov dword ptr [ebp+off],dreg_lo */
 351                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 352                       STACK_VAR(dst_lo));
 353                 /* mov dword ptr [ebp+off],dreg_hi */
 354                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 355                       STACK_VAR(dst_hi));
 356         }
 357         *pprog = prog;
 358 }
 359
 360 static inline void emit_ia32_to_be_r64(const u8 dst[], s32 val,
 361                                        bool dstk, u8 **pprog)
 362 {
 363         u8 *prog = *pprog;
 364         int cnt = 0;
 365         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 366         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 367
 368         if (dstk) {
 369                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 370                       STACK_VAR(dst_lo));
 371                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 372                       STACK_VAR(dst_hi));
 373         }
 374         switch (val) {
 375         case 16:
 376                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
 377                 EMIT1(0x66);
 378                 EMIT3(0xC1, add_1reg(0xC8, dreg_lo), 8);
 379
 380                 EMIT2(0x0F, 0xB7);
 381                 EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
 382
 383                 /* xor dreg_hi,dreg_hi */
 384                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 385                 break;
 386         case 32:
 387                 /* Emit 'bswap eax' to swap lower 4 bytes */
 388                 EMIT1(0x0F);
 389                 EMIT1(add_1reg(0xC8, dreg_lo));
 390
 391                 /* xor dreg_hi,dreg_hi */
 392                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 393                 break;
 394         case 64:
 395                 /* Emit 'bswap eax' to swap lower 4 bytes */
 396                 EMIT1(0x0F);
 397                 EMIT1(add_1reg(0xC8, dreg_lo));
 398
 399                 /* Emit 'bswap edx' to swap lower 4 bytes */
 400                 EMIT1(0x0F);
 401                 EMIT1(add_1reg(0xC8, dreg_hi));
 402
 403                 /* mov ecx,dreg_hi */
 404                 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, dreg_hi));
 405                 /* mov dreg_hi,dreg_lo */
 406                 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
 407                 /* mov dreg_lo,ecx */
 408                 EMIT2(0x89, add_2reg(0xC0, dreg_lo, IA32_ECX));
 409
 410                 break;
 411         }
 412         if (dstk) {
 413                 /* mov dword ptr [ebp+off],dreg_lo */
 414                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 415                       STACK_VAR(dst_lo));
 416                 /* mov dword ptr [ebp+off],dreg_hi */
 417                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 418                       STACK_VAR(dst_hi));
 419         }
 420         *pprog = prog;
 421 }
 422
 423 /*
 424  * ALU operation (32 bit)
 425  * dst = dst (div|mod) src
 426  */
 427 static inline void emit_ia32_div_mod_r(const u8 op, const u8 dst, const u8 src,
 428                                        bool dstk, bool sstk, u8 **pprog)
 429 {
 430         u8 *prog = *pprog;
 431         int cnt = 0;
 432
 433         if (sstk)
 434                 /* mov ecx,dword ptr [ebp+off] */
 435                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
 436                       STACK_VAR(src));
 437         else if (src != IA32_ECX)
 438                 /* mov ecx,src */
 439                 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX));
 440
 441         if (dstk)
 442                 /* mov eax,dword ptr [ebp+off] */
 443                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 444                       STACK_VAR(dst));
 445         else
 446                 /* mov eax,dst */
 447                 EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
 448
 449         /* xor edx,edx */
 450         EMIT2(0x31, add_2reg(0xC0, IA32_EDX, IA32_EDX));
 451         /* div ecx */
 452         EMIT2(0xF7, add_1reg(0xF0, IA32_ECX));
 453
 454         if (op == BPF_MOD) {
 455                 if (dstk)
 456                         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
 457                               STACK_VAR(dst));
 458                 else
 459                         EMIT2(0x89, add_2reg(0xC0, dst, IA32_EDX));
 460         } else {
 461                 if (dstk)
 462                         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
 463                               STACK_VAR(dst));
 464                 else
 465                         EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
 466         }
 467         *pprog = prog;
 468 }
 469
 470 /*
 471  * ALU operation (32 bit)
 472  * dst = dst (shift) src
 473  */
 474 static inline void emit_ia32_shift_r(const u8 op, const u8 dst, const u8 src,
 475                                      bool dstk, bool sstk, u8 **pprog)
 476 {
 477         u8 *prog = *pprog;
 478         int cnt = 0;
 479         u8 dreg = dstk ? IA32_EAX : dst;
 480         u8 b2;
 481
 482         if (dstk)
 483                 /* mov eax,dword ptr [ebp+off] */
 484                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
 485
 486         if (sstk)
 487                 /* mov ecx,dword ptr [ebp+off] */
 488                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
 489         else if (src != IA32_ECX)
 490                 /* mov ecx,src */
 491                 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX));
 492
 493         switch (op) {
 494         case BPF_LSH:
 495                 b2 = 0xE0; break;
 496         case BPF_RSH:
 497                 b2 = 0xE8; break;
 498         case BPF_ARSH:
 499                 b2 = 0xF8; break;
 500         default:
 501                 return;
 502         }
 503         EMIT2(0xD3, add_1reg(b2, dreg));
 504
 505         if (dstk)
 506                 /* mov dword ptr [ebp+off],dreg */
 507                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg), STACK_VAR(dst));
 508         *pprog = prog;
 509 }
 510
 511 /*
 512  * ALU operation (32 bit)
 513  * dst = dst (op) src
 514  */
 515 static inline void emit_ia32_alu_r(const bool is64, const bool hi, const u8 op,
 516                                    const u8 dst, const u8 src, bool dstk,
 517                                    bool sstk, u8 **pprog)
 518 {
 519         u8 *prog = *pprog;
 520         int cnt = 0;
 521         u8 sreg = sstk ? IA32_EAX : src;
 522         u8 dreg = dstk ? IA32_EDX : dst;
 523
 524         if (sstk)
 525                 /* mov eax,dword ptr [ebp+off] */
 526                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
 527
 528         if (dstk)
 529                 /* mov eax,dword ptr [ebp+off] */
 530                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(dst));
 531
 532         switch (BPF_OP(op)) {
 533         /* dst = dst + src */
 534         case BPF_ADD:
 535                 if (hi && is64)
 536                         EMIT2(0x11, add_2reg(0xC0, dreg, sreg));
 537                 else
 538                         EMIT2(0x01, add_2reg(0xC0, dreg, sreg));
 539                 break;
 540         /* dst = dst - src */
 541         case BPF_SUB:
 542                 if (hi && is64)
 543                         EMIT2(0x19, add_2reg(0xC0, dreg, sreg));
 544                 else
 545                         EMIT2(0x29, add_2reg(0xC0, dreg, sreg));
 546                 break;
 547         /* dst = dst | src */
 548         case BPF_OR:
 549                 EMIT2(0x09, add_2reg(0xC0, dreg, sreg));
 550                 break;
 551         /* dst = dst & src */
 552         case BPF_AND:
 553                 EMIT2(0x21, add_2reg(0xC0, dreg, sreg));
 554                 break;
 555         /* dst = dst ^ src */
 556         case BPF_XOR:
 557                 EMIT2(0x31, add_2reg(0xC0, dreg, sreg));
 558                 break;
 559         }
 560
 561         if (dstk)
 562                 /* mov dword ptr [ebp+off],dreg */
 563                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
 564                       STACK_VAR(dst));
 565         *pprog = prog;
 566 }
 567
 568 /* ALU operation (64 bit) */
 569 static inline void emit_ia32_alu_r64(const bool is64, const u8 op,
 570                                      const u8 dst[], const u8 src[],
 571                                      bool dstk,  bool sstk,
 572                                      u8 **pprog)
 573 {
 574         u8 *prog = *pprog;
 575
 576         emit_ia32_alu_r(is64, false, op, dst_lo, src_lo, dstk, sstk, &prog);
 577         if (is64)
 578                 emit_ia32_alu_r(is64, true, op, dst_hi, src_hi, dstk, sstk,
 579                                 &prog);
 580         else
 581                 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
 582         *pprog = prog;
 583 }
 584
 585 /*
 586  * ALU operation (32 bit)
 587  * dst = dst (op) val
 588  */
 589 static inline void emit_ia32_alu_i(const bool is64, const bool hi, const u8 op,
 590                                    const u8 dst, const s32 val, bool dstk,
 591                                    u8 **pprog)
 592 {
 593         u8 *prog = *pprog;
 594         int cnt = 0;
 595         u8 dreg = dstk ? IA32_EAX : dst;
 596         u8 sreg = IA32_EDX;
 597
 598         if (dstk)
 599                 /* mov eax,dword ptr [ebp+off] */
 600                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
 601
 602         if (!is_imm8(val))
 603                 /* mov edx,imm32*/
 604                 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val);
 605
 606         switch (op) {
 607         /* dst = dst + val */
 608         case BPF_ADD:
 609                 if (hi && is64) {
 610                         if (is_imm8(val))
 611                                 EMIT3(0x83, add_1reg(0xD0, dreg), val);
 612                         else
 613                                 EMIT2(0x11, add_2reg(0xC0, dreg, sreg));
 614                 } else {
 615                         if (is_imm8(val))
 616                                 EMIT3(0x83, add_1reg(0xC0, dreg), val);
 617                         else
 618                                 EMIT2(0x01, add_2reg(0xC0, dreg, sreg));
 619                 }
 620                 break;
 621         /* dst = dst - val */
 622         case BPF_SUB:
 623                 if (hi && is64) {
 624                         if (is_imm8(val))
 625                                 EMIT3(0x83, add_1reg(0xD8, dreg), val);
 626                         else
 627                                 EMIT2(0x19, add_2reg(0xC0, dreg, sreg));
 628                 } else {
 629                         if (is_imm8(val))
 630                                 EMIT3(0x83, add_1reg(0xE8, dreg), val);
 631                         else
 632                                 EMIT2(0x29, add_2reg(0xC0, dreg, sreg));
 633                 }
 634                 break;
 635         /* dst = dst | val */
 636         case BPF_OR:
 637                 if (is_imm8(val))
 638                         EMIT3(0x83, add_1reg(0xC8, dreg), val);
 639                 else
 640                         EMIT2(0x09, add_2reg(0xC0, dreg, sreg));
 641                 break;
 642         /* dst = dst & val */
 643         case BPF_AND:
 644                 if (is_imm8(val))
 645                         EMIT3(0x83, add_1reg(0xE0, dreg), val);
 646                 else
 647                         EMIT2(0x21, add_2reg(0xC0, dreg, sreg));
 648                 break;
 649         /* dst = dst ^ val */
 650         case BPF_XOR:
 651                 if (is_imm8(val))
 652                         EMIT3(0x83, add_1reg(0xF0, dreg), val);
 653                 else
 654                         EMIT2(0x31, add_2reg(0xC0, dreg, sreg));
 655                 break;
 656         case BPF_NEG:
 657                 EMIT2(0xF7, add_1reg(0xD8, dreg));
 658                 break;
 659         }
 660
 661         if (dstk)
 662                 /* mov dword ptr [ebp+off],dreg */
 663                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
 664                       STACK_VAR(dst));
 665         *pprog = prog;
 666 }
 667
 668 /* ALU operation (64 bit) */
 669 static inline void emit_ia32_alu_i64(const bool is64, const u8 op,
 670                                      const u8 dst[], const u32 val,
 671                                      bool dstk, u8 **pprog)
 672 {
 673         u8 *prog = *pprog;
 674         u32 hi = 0;
 675
 676         if (is64 && (val & (1<<31)))
 677                 hi = (u32)~0;
 678
 679         emit_ia32_alu_i(is64, false, op, dst_lo, val, dstk, &prog);
 680         if (is64)
 681                 emit_ia32_alu_i(is64, true, op, dst_hi, hi, dstk, &prog);
 682         else
 683                 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
 684
 685         *pprog = prog;
 686 }
 687
 688 /* dst = ~dst (64 bit) */
 689 static inline void emit_ia32_neg64(const u8 dst[], bool dstk, u8 **pprog)
 690 {
 691         u8 *prog = *pprog;
 692         int cnt = 0;
 693         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 694         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 695
 696         if (dstk) {
 697                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 698                       STACK_VAR(dst_lo));
 699                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 700                       STACK_VAR(dst_hi));
 701         }
 702
 703         /* neg dreg_lo */
 704         EMIT2(0xF7, add_1reg(0xD8, dreg_lo));
 705         /* adc dreg_hi,0x0 */
 706         EMIT3(0x83, add_1reg(0xD0, dreg_hi), 0x00);
 707         /* neg dreg_hi */
 708         EMIT2(0xF7, add_1reg(0xD8, dreg_hi));
 709
 710         if (dstk) {
 711                 /* mov dword ptr [ebp+off],dreg_lo */
 712                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 713                       STACK_VAR(dst_lo));
 714                 /* mov dword ptr [ebp+off],dreg_hi */
 715                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 716                       STACK_VAR(dst_hi));
 717         }
 718         *pprog = prog;
 719 }
 720
 721 /* dst = dst << src */
 722 static inline void emit_ia32_lsh_r64(const u8 dst[], const u8 src[],
 723                                      bool dstk, bool sstk, u8 **pprog)
 724 {
 725         u8 *prog = *pprog;
 726         int cnt = 0;
 727         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 728         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 729
 730         if (dstk) {
 731                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 732                       STACK_VAR(dst_lo));
 733                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 734                       STACK_VAR(dst_hi));
 735         }
 736
 737         if (sstk)
 738                 /* mov ecx,dword ptr [ebp+off] */
 739                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
 740                       STACK_VAR(src_lo));
 741         else
 742                 /* mov ecx,src_lo */
 743                 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
 744
 745         /* shld dreg_hi,dreg_lo,cl */
 746         EMIT3(0x0F, 0xA5, add_2reg(0xC0, dreg_hi, dreg_lo));
 747         /* shl dreg_lo,cl */
 748         EMIT2(0xD3, add_1reg(0xE0, dreg_lo));
 749
 750         /* if ecx >= 32, mov dreg_lo into dreg_hi and clear dreg_lo */
 751
 752         /* cmp ecx,32 */
 753         EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
 754         /* skip the next two instructions (4 bytes) when < 32 */
 755         EMIT2(IA32_JB, 4);
 756
 757         /* mov dreg_hi,dreg_lo */
 758         EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
 759         /* xor dreg_lo,dreg_lo */
 760         EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
 761
 762         if (dstk) {
 763                 /* mov dword ptr [ebp+off],dreg_lo */
 764                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 765                       STACK_VAR(dst_lo));
 766                 /* mov dword ptr [ebp+off],dreg_hi */
 767                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 768                       STACK_VAR(dst_hi));
 769         }
 770         /* out: */
 771         *pprog = prog;
 772 }
 773
 774 /* dst = dst >> src (signed)*/
 775 static inline void emit_ia32_arsh_r64(const u8 dst[], const u8 src[],
 776                                       bool dstk, bool sstk, u8 **pprog)
 777 {
 778         u8 *prog = *pprog;
 779         int cnt = 0;
 780         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 781         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 782
 783         if (dstk) {
 784                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 785                       STACK_VAR(dst_lo));
 786                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 787                       STACK_VAR(dst_hi));
 788         }
 789
 790         if (sstk)
 791                 /* mov ecx,dword ptr [ebp+off] */
 792                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
 793                       STACK_VAR(src_lo));
 794         else
 795                 /* mov ecx,src_lo */
 796                 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
 797
 798         /* shrd dreg_lo,dreg_hi,cl */
 799         EMIT3(0x0F, 0xAD, add_2reg(0xC0, dreg_lo, dreg_hi));
 800         /* sar dreg_hi,cl */
 801         EMIT2(0xD3, add_1reg(0xF8, dreg_hi));
 802
 803         /* if ecx >= 32, mov dreg_hi to dreg_lo and set/clear dreg_hi depending on sign */
 804
 805         /* cmp ecx,32 */
 806         EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
 807         /* skip the next two instructions (5 bytes) when < 32 */
 808         EMIT2(IA32_JB, 5);
 809
 810         /* mov dreg_lo,dreg_hi */
 811         EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
 812         /* sar dreg_hi,31 */
 813         EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
 814
 815         if (dstk) {
 816                 /* mov dword ptr [ebp+off],dreg_lo */
 817                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 818                       STACK_VAR(dst_lo));
 819                 /* mov dword ptr [ebp+off],dreg_hi */
 820                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 821                       STACK_VAR(dst_hi));
 822         }
 823         /* out: */
 824         *pprog = prog;
 825 }
 826
 827 /* dst = dst >> src */
 828 static inline void emit_ia32_rsh_r64(const u8 dst[], const u8 src[], bool dstk,
 829                                      bool sstk, u8 **pprog)
 830 {
 831         u8 *prog = *pprog;
 832         int cnt = 0;
 833         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 834         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 835
 836         if (dstk) {
 837                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 838                       STACK_VAR(dst_lo));
 839                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 840                       STACK_VAR(dst_hi));
 841         }
 842
 843         if (sstk)
 844                 /* mov ecx,dword ptr [ebp+off] */
 845                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
 846                       STACK_VAR(src_lo));
 847         else
 848                 /* mov ecx,src_lo */
 849                 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
 850
 851         /* shrd dreg_lo,dreg_hi,cl */
 852         EMIT3(0x0F, 0xAD, add_2reg(0xC0, dreg_lo, dreg_hi));
 853         /* shr dreg_hi,cl */
 854         EMIT2(0xD3, add_1reg(0xE8, dreg_hi));
 855
 856         /* if ecx >= 32, mov dreg_hi to dreg_lo and clear dreg_hi */
 857
 858         /* cmp ecx,32 */
 859         EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
 860         /* skip the next two instructions (4 bytes) when < 32 */
 861         EMIT2(IA32_JB, 4);
 862
 863         /* mov dreg_lo,dreg_hi */
 864         EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
 865         /* xor dreg_hi,dreg_hi */
 866         EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 867
 868         if (dstk) {
 869                 /* mov dword ptr [ebp+off],dreg_lo */
 870                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 871                       STACK_VAR(dst_lo));
 872                 /* mov dword ptr [ebp+off],dreg_hi */
 873                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 874                       STACK_VAR(dst_hi));
 875         }
 876         /* out: */
 877         *pprog = prog;
 878 }
 879
 880 /* dst = dst << val */
 881 static inline void emit_ia32_lsh_i64(const u8 dst[], const u32 val,
 882                                      bool dstk, u8 **pprog)
 883 {
 884         u8 *prog = *pprog;
 885         int cnt = 0;
 886         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 887         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 888
 889         if (dstk) {
 890                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 891                       STACK_VAR(dst_lo));
 892                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 893                       STACK_VAR(dst_hi));
 894         }
 895         /* Do LSH operation */
 896         if (val < 32) {
 897                 /* shld dreg_hi,dreg_lo,imm8 */
 898                 EMIT4(0x0F, 0xA4, add_2reg(0xC0, dreg_hi, dreg_lo), val);
 899                 /* shl dreg_lo,imm8 */
 900                 EMIT3(0xC1, add_1reg(0xE0, dreg_lo), val);
 901         } else if (val >= 32 && val < 64) {
 902                 u32 value = val - 32;
 903
 904                 /* shl dreg_lo,imm8 */
 905                 EMIT3(0xC1, add_1reg(0xE0, dreg_lo), value);
 906                 /* mov dreg_hi,dreg_lo */
 907                 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
 908                 /* xor dreg_lo,dreg_lo */
 909                 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
 910         } else {
 911                 /* xor dreg_lo,dreg_lo */
 912                 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
 913                 /* xor dreg_hi,dreg_hi */
 914                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 915         }
 916
 917         if (dstk) {
 918                 /* mov dword ptr [ebp+off],dreg_lo */
 919                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 920                       STACK_VAR(dst_lo));
 921                 /* mov dword ptr [ebp+off],dreg_hi */
 922                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 923                       STACK_VAR(dst_hi));
 924         }
 925         *pprog = prog;
 926 }
 927
 928 /* dst = dst >> val */
 929 static inline void emit_ia32_rsh_i64(const u8 dst[], const u32 val,
 930                                      bool dstk, u8 **pprog)
 931 {
 932         u8 *prog = *pprog;
 933         int cnt = 0;
 934         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 935         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 936
 937         if (dstk) {
 938                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 939                       STACK_VAR(dst_lo));
 940                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 941                       STACK_VAR(dst_hi));
 942         }
 943
 944         /* Do RSH operation */
 945         if (val < 32) {
 946                 /* shrd dreg_lo,dreg_hi,imm8 */
 947                 EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val);
 948                 /* shr dreg_hi,imm8 */
 949                 EMIT3(0xC1, add_1reg(0xE8, dreg_hi), val);
 950         } else if (val >= 32 && val < 64) {
 951                 u32 value = val - 32;
 952
 953                 /* shr dreg_hi,imm8 */
 954                 EMIT3(0xC1, add_1reg(0xE8, dreg_hi), value);
 955                 /* mov dreg_lo,dreg_hi */
 956                 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
 957                 /* xor dreg_hi,dreg_hi */
 958                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 959         } else {
 960                 /* xor dreg_lo,dreg_lo */
 961                 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
 962                 /* xor dreg_hi,dreg_hi */
 963                 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
 964         }
 965
 966         if (dstk) {
 967                 /* mov dword ptr [ebp+off],dreg_lo */
 968                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
 969                       STACK_VAR(dst_lo));
 970                 /* mov dword ptr [ebp+off],dreg_hi */
 971                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
 972                       STACK_VAR(dst_hi));
 973         }
 974         *pprog = prog;
 975 }
 976
 977 /* dst = dst >> val (signed) */
 978 static inline void emit_ia32_arsh_i64(const u8 dst[], const u32 val,
 979                                       bool dstk, u8 **pprog)
 980 {
 981         u8 *prog = *pprog;
 982         int cnt = 0;
 983         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
 984         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
 985
 986         if (dstk) {
 987                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
 988                       STACK_VAR(dst_lo));
 989                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
 990                       STACK_VAR(dst_hi));
 991         }
 992         /* Do RSH operation */
 993         if (val < 32) {
 994                 /* shrd dreg_lo,dreg_hi,imm8 */
 995                 EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val);
 996                 /* ashr dreg_hi,imm8 */
 997                 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), val);
 998         } else if (val >= 32 && val < 64) {
 999                 u32 value = val - 32;
1000
1001                 /* ashr dreg_hi,imm8 */
1002                 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), value);
1003                 /* mov dreg_lo,dreg_hi */
1004                 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1005
1006                 /* ashr dreg_hi,imm8 */
1007                 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1008         } else {
1009                 /* ashr dreg_hi,imm8 */
1010                 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1011                 /* mov dreg_lo,dreg_hi */
1012                 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1013         }
1014
1015         if (dstk) {
1016                 /* mov dword ptr [ebp+off],dreg_lo */
1017                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
1018                       STACK_VAR(dst_lo));
1019                 /* mov dword ptr [ebp+off],dreg_hi */
1020                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
1021                       STACK_VAR(dst_hi));
1022         }
1023         *pprog = prog;
1024 }
1025
1026 static inline void emit_ia32_mul_r64(const u8 dst[], const u8 src[], bool dstk,
1027                                      bool sstk, u8 **pprog)
1028 {
1029         u8 *prog = *pprog;
1030         int cnt = 0;
1031
1032         if (dstk)
1033                 /* mov eax,dword ptr [ebp+off] */
1034                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1035                       STACK_VAR(dst_hi));
1036         else
1037                 /* mov eax,dst_hi */
1038                 EMIT2(0x8B, add_2reg(0xC0, dst_hi, IA32_EAX));
1039
1040         if (sstk)
1041                 /* mul dword ptr [ebp+off] */
1042                 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
1043         else
1044                 /* mul src_lo */
1045                 EMIT2(0xF7, add_1reg(0xE0, src_lo));
1046
1047         /* mov ecx,eax */
1048         EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1049
1050         if (dstk)
1051                 /* mov eax,dword ptr [ebp+off] */
1052                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1053                       STACK_VAR(dst_lo));
1054         else
1055                 /* mov eax,dst_lo */
1056                 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1057
1058         if (sstk)
1059                 /* mul dword ptr [ebp+off] */
1060                 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_hi));
1061         else
1062                 /* mul src_hi */
1063                 EMIT2(0xF7, add_1reg(0xE0, src_hi));
1064
1065         /* add eax,eax */
1066         EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1067
1068         if (dstk)
1069                 /* mov eax,dword ptr [ebp+off] */
1070                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1071                       STACK_VAR(dst_lo));
1072         else
1073                 /* mov eax,dst_lo */
1074                 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1075
1076         if (sstk)
1077                 /* mul dword ptr [ebp+off] */
1078                 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
1079         else
1080                 /* mul src_lo */
1081                 EMIT2(0xF7, add_1reg(0xE0, src_lo));
1082
1083         /* add ecx,edx */
1084         EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
1085
1086         if (dstk) {
1087                 /* mov dword ptr [ebp+off],eax */
1088                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1089                       STACK_VAR(dst_lo));
1090                 /* mov dword ptr [ebp+off],ecx */
1091                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
1092                       STACK_VAR(dst_hi));
1093         } else {
1094                 /* mov dst_lo,eax */
1095                 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
1096                 /* mov dst_hi,ecx */
1097                 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX));
1098         }
1099
1100         *pprog = prog;
1101 }
1102
1103 static inline void emit_ia32_mul_i64(const u8 dst[], const u32 val,
1104                                      bool dstk, u8 **pprog)
1105 {
1106         u8 *prog = *pprog;
1107         int cnt = 0;
1108         u32 hi;
1109
1110         hi = val & (1<<31) ? (u32)~0 : 0;
1111         /* movl eax,imm32 */
1112         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
1113         if (dstk)
1114                 /* mul dword ptr [ebp+off] */
1115                 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi));
1116         else
1117                 /* mul dst_hi */
1118                 EMIT2(0xF7, add_1reg(0xE0, dst_hi));
1119
1120         /* mov ecx,eax */
1121         EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1122
1123         /* movl eax,imm32 */
1124         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), hi);
1125         if (dstk)
1126                 /* mul dword ptr [ebp+off] */
1127                 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
1128         else
1129                 /* mul dst_lo */
1130                 EMIT2(0xF7, add_1reg(0xE0, dst_lo));
1131         /* add ecx,eax */
1132         EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1133
1134         /* movl eax,imm32 */
1135         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
1136         if (dstk)
1137                 /* mul dword ptr [ebp+off] */
1138                 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
1139         else
1140                 /* mul dst_lo */
1141                 EMIT2(0xF7, add_1reg(0xE0, dst_lo));
1142
1143         /* add ecx,edx */
1144         EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
1145
1146         if (dstk) {
1147                 /* mov dword ptr [ebp+off],eax */
1148                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1149                       STACK_VAR(dst_lo));
1150                 /* mov dword ptr [ebp+off],ecx */
1151                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
1152                       STACK_VAR(dst_hi));
1153         } else {
1154                 /* mov dword ptr [ebp+off],eax */
1155                 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
1156                 /* mov dword ptr [ebp+off],ecx */
1157                 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX));
1158         }
1159
1160         *pprog = prog;
1161 }
1162
1163 static int bpf_size_to_x86_bytes(int bpf_size)
1164 {
1165         if (bpf_size == BPF_W)
1166                 return 4;
1167         else if (bpf_size == BPF_H)
1168                 return 2;
1169         else if (bpf_size == BPF_B)
1170                 return 1;
1171         else if (bpf_size == BPF_DW)
1172                 return 4; /* imm32 */
1173         else
1174                 return 0;
1175 }
1176
1177 struct jit_context {
1178         int cleanup_addr; /* Epilogue code offset */
1179 };
1180
1181 /* Maximum number of bytes emitted while JITing one eBPF insn */
1182 #define BPF_MAX_INSN_SIZE       128
1183 #define BPF_INSN_SAFETY         64
1184
1185 #define PROLOGUE_SIZE 35
1186
1187 /*
1188  * Emit prologue code for BPF program and check it's size.
1189  * bpf_tail_call helper will skip it while jumping into another program.
1190  */
1191 static void emit_prologue(u8 **pprog, u32 stack_depth)
1192 {
1193         u8 *prog = *pprog;
1194         int cnt = 0;
1195         const u8 *r1 = bpf2ia32[BPF_REG_1];
1196         const u8 fplo = bpf2ia32[BPF_REG_FP][0];
1197         const u8 fphi = bpf2ia32[BPF_REG_FP][1];
1198         const u8 *tcc = bpf2ia32[TCALL_CNT];
1199
1200         /* push ebp */
1201         EMIT1(0x55);
1202         /* mov ebp,esp */
1203         EMIT2(0x89, 0xE5);
1204         /* push edi */
1205         EMIT1(0x57);
1206         /* push esi */
1207         EMIT1(0x56);
1208         /* push ebx */
1209         EMIT1(0x53);
1210
1211         /* sub esp,STACK_SIZE */
1212         EMIT2_off32(0x81, 0xEC, STACK_SIZE);
1213         /* sub ebp,SCRATCH_SIZE+12*/
1214         EMIT3(0x83, add_1reg(0xE8, IA32_EBP), SCRATCH_SIZE + 12);
1215         /* xor ebx,ebx */
1216         EMIT2(0x31, add_2reg(0xC0, IA32_EBX, IA32_EBX));
1217
1218         /* Set up BPF prog stack base register */
1219         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBP), STACK_VAR(fplo));
1220         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(fphi));
1221
1222         /* Move BPF_CTX (EAX) to BPF_REG_R1 */
1223         /* mov dword ptr [ebp+off],eax */
1224         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
1225         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(r1[1]));
1226
1227         /* Initialize Tail Count */
1228         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[0]));
1229         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1230
1231         BUILD_BUG_ON(cnt != PROLOGUE_SIZE);
1232         *pprog = prog;
1233 }
1234
1235 /* Emit epilogue code for BPF program */
1236 static void emit_epilogue(u8 **pprog, u32 stack_depth)
1237 {
1238         u8 *prog = *pprog;
1239         const u8 *r0 = bpf2ia32[BPF_REG_0];
1240         int cnt = 0;
1241
1242         /* mov eax,dword ptr [ebp+off]*/
1243         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r0[0]));
1244         /* mov edx,dword ptr [ebp+off]*/
1245         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r0[1]));
1246
1247         /* add ebp,SCRATCH_SIZE+12*/
1248         EMIT3(0x83, add_1reg(0xC0, IA32_EBP), SCRATCH_SIZE + 12);
1249
1250         /* mov ebx,dword ptr [ebp-12]*/
1251         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), -12);
1252         /* mov esi,dword ptr [ebp-8]*/
1253         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ESI), -8);
1254         /* mov edi,dword ptr [ebp-4]*/
1255         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDI), -4);
1256
1257         EMIT1(0xC9); /* leave */
1258         EMIT1(0xC3); /* ret */
1259         *pprog = prog;
1260 }
1261
1262 /*
1263  * Generate the following code:
1264  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
1265  *   if (index >= array->map.max_entries)
1266  *     goto out;
1267  *   if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
1268  *     goto out;
1269  *   prog = array->ptrs[index];
1270  *   if (prog == NULL)
1271  *     goto out;
1272  *   goto *(prog->bpf_func + prologue_size);
1273  * out:
1274  */
1275 static void emit_bpf_tail_call(u8 **pprog)
1276 {
1277         u8 *prog = *pprog;
1278         int cnt = 0;
1279         const u8 *r1 = bpf2ia32[BPF_REG_1];
1280         const u8 *r2 = bpf2ia32[BPF_REG_2];
1281         const u8 *r3 = bpf2ia32[BPF_REG_3];
1282         const u8 *tcc = bpf2ia32[TCALL_CNT];
1283         u32 lo, hi;
1284         static int jmp_label1 = -1;
1285
1286         /*
1287          * if (index >= array->map.max_entries)
1288          *     goto out;
1289          */
1290         /* mov eax,dword ptr [ebp+off] */
1291         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r2[0]));
1292         /* mov edx,dword ptr [ebp+off] */
1293         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r3[0]));
1294
1295         /* cmp dword ptr [eax+off],edx */
1296         EMIT3(0x39, add_2reg(0x40, IA32_EAX, IA32_EDX),
1297               offsetof(struct bpf_array, map.max_entries));
1298         /* jbe out */
1299         EMIT2(IA32_JBE, jmp_label(jmp_label1, 2));
1300
1301         /*
1302          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
1303          *     goto out;
1304          */
1305         lo = (u32)MAX_TAIL_CALL_CNT;
1306         hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1307         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
1308         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1309
1310         /* cmp edx,hi */
1311         EMIT3(0x83, add_1reg(0xF8, IA32_EBX), hi);
1312         EMIT2(IA32_JNE, 3);
1313         /* cmp ecx,lo */
1314         EMIT3(0x83, add_1reg(0xF8, IA32_ECX), lo);
1315
1316         /* ja out */
1317         EMIT2(IA32_JAE, jmp_label(jmp_label1, 2));
1318
1319         /* add eax,0x1 */
1320         EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 0x01);
1321         /* adc ebx,0x0 */
1322         EMIT3(0x83, add_1reg(0xD0, IA32_EBX), 0x00);
1323
1324         /* mov dword ptr [ebp+off],eax */
1325         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
1326         /* mov dword ptr [ebp+off],edx */
1327         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1328
1329         /* prog = array->ptrs[index]; */
1330         /* mov edx, [eax + edx * 4 + offsetof(...)] */
1331         EMIT3_off32(0x8B, 0x94, 0x90, offsetof(struct bpf_array, ptrs));
1332
1333         /*
1334          * if (prog == NULL)
1335          *     goto out;
1336          */
1337         /* test edx,edx */
1338         EMIT2(0x85, add_2reg(0xC0, IA32_EDX, IA32_EDX));
1339         /* je out */
1340         EMIT2(IA32_JE, jmp_label(jmp_label1, 2));
1341
1342         /* goto *(prog->bpf_func + prologue_size); */
1343         /* mov edx, dword ptr [edx + 32] */
1344         EMIT3(0x8B, add_2reg(0x40, IA32_EDX, IA32_EDX),
1345               offsetof(struct bpf_prog, bpf_func));
1346         /* add edx,prologue_size */
1347         EMIT3(0x83, add_1reg(0xC0, IA32_EDX), PROLOGUE_SIZE);
1348
1349         /* mov eax,dword ptr [ebp+off] */
1350         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
1351
1352         /*
1353          * Now we're ready to jump into next BPF program:
1354          * eax == ctx (1st arg)
1355          * edx == prog->bpf_func + prologue_size
1356          */
1357         RETPOLINE_EDX_BPF_JIT();
1358
1359         if (jmp_label1 == -1)
1360                 jmp_label1 = cnt;
1361
1362         /* out: */
1363         *pprog = prog;
1364 }
1365
1366 /* Push the scratch stack register on top of the stack. */
1367 static inline void emit_push_r64(const u8 src[], u8 **pprog)
1368 {
1369         u8 *prog = *pprog;
1370         int cnt = 0;
1371
1372         /* mov ecx,dword ptr [ebp+off] */
1373         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_hi));
1374         /* push ecx */
1375         EMIT1(0x51);
1376
1377         /* mov ecx,dword ptr [ebp+off] */
1378         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo));
1379         /* push ecx */
1380         EMIT1(0x51);
1381
1382         *pprog = prog;
1383 }
1384
1385 static u8 get_cond_jmp_opcode(const u8 op, bool is_cmp_lo)
1386 {
1387         u8 jmp_cond;
1388
1389         /* Convert BPF opcode to x86 */
1390         switch (op) {
1391         case BPF_JEQ:
1392                 jmp_cond = IA32_JE;
1393                 break;
1394         case BPF_JSET:
1395         case BPF_JNE:
1396                 jmp_cond = IA32_JNE;
1397                 break;
1398         case BPF_JGT:
1399                 /* GT is unsigned '>', JA in x86 */
1400                 jmp_cond = IA32_JA;
1401                 break;
1402         case BPF_JLT:
1403                 /* LT is unsigned '<', JB in x86 */
1404                 jmp_cond = IA32_JB;
1405                 break;
1406         case BPF_JGE:
1407                 /* GE is unsigned '>=', JAE in x86 */
1408                 jmp_cond = IA32_JAE;
1409                 break;
1410         case BPF_JLE:
1411                 /* LE is unsigned '<=', JBE in x86 */
1412                 jmp_cond = IA32_JBE;
1413                 break;
1414         case BPF_JSGT:
1415                 if (!is_cmp_lo)
1416                         /* Signed '>', GT in x86 */
1417                         jmp_cond = IA32_JG;
1418                 else
1419                         /* GT is unsigned '>', JA in x86 */
1420                         jmp_cond = IA32_JA;
1421                 break;
1422         case BPF_JSLT:
1423                 if (!is_cmp_lo)
1424                         /* Signed '<', LT in x86 */
1425                         jmp_cond = IA32_JL;
1426                 else
1427                         /* LT is unsigned '<', JB in x86 */
1428                         jmp_cond = IA32_JB;
1429                 break;
1430         case BPF_JSGE:
1431                 if (!is_cmp_lo)
1432                         /* Signed '>=', GE in x86 */
1433                         jmp_cond = IA32_JGE;
1434                 else
1435                         /* GE is unsigned '>=', JAE in x86 */
1436                         jmp_cond = IA32_JAE;
1437                 break;
1438         case BPF_JSLE:
1439                 if (!is_cmp_lo)
1440                         /* Signed '<=', LE in x86 */
1441                         jmp_cond = IA32_JLE;
1442                 else
1443                         /* LE is unsigned '<=', JBE in x86 */
1444                         jmp_cond = IA32_JBE;
1445                 break;
1446         default: /* to silence GCC warning */
1447                 jmp_cond = COND_JMP_OPCODE_INVALID;
1448                 break;
1449         }
1450
1451         return jmp_cond;
1452 }
1453
1454 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
1455                   int oldproglen, struct jit_context *ctx)
1456 {
1457         struct bpf_insn *insn = bpf_prog->insnsi;
1458         int insn_cnt = bpf_prog->len;
1459         bool seen_exit = false;
1460         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
1461         int i, cnt = 0;
1462         int proglen = 0;
1463         u8 *prog = temp;
1464
1465         emit_prologue(&prog, bpf_prog->aux->stack_depth);
1466
1467         for (i = 0; i < insn_cnt; i++, insn++) {
1468                 const s32 imm32 = insn->imm;
1469                 const bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1470                 const bool dstk = insn->dst_reg == BPF_REG_AX ? false : true;
1471                 const bool sstk = insn->src_reg == BPF_REG_AX ? false : true;
1472                 const u8 code = insn->code;
1473                 const u8 *dst = bpf2ia32[insn->dst_reg];
1474                 const u8 *src = bpf2ia32[insn->src_reg];
1475                 const u8 *r0 = bpf2ia32[BPF_REG_0];
1476                 s64 jmp_offset;
1477                 u8 jmp_cond;
1478                 int ilen;
1479                 u8 *func;
1480
1481                 switch (code) {
1482                 /* ALU operations */
1483                 /* dst = src */
1484                 case BPF_ALU | BPF_MOV | BPF_K:
1485                 case BPF_ALU | BPF_MOV | BPF_X:
1486                 case BPF_ALU64 | BPF_MOV | BPF_K:
1487                 case BPF_ALU64 | BPF_MOV | BPF_X:
1488                         switch (BPF_SRC(code)) {
1489                         case BPF_X:
1490                                 emit_ia32_mov_r64(is64, dst, src, dstk,
1491                                                   sstk, &prog);
1492                                 break;
1493                         case BPF_K:
1494                                 /* Sign-extend immediate value to dst reg */
1495                                 emit_ia32_mov_i64(is64, dst, imm32,
1496                                                   dstk, &prog);
1497                                 break;
1498                         }
1499                         break;
1500                 /* dst = dst + src/imm */
1501                 /* dst = dst - src/imm */
1502                 /* dst = dst | src/imm */
1503                 /* dst = dst & src/imm */
1504                 /* dst = dst ^ src/imm */
1505                 /* dst = dst * src/imm */
1506                 /* dst = dst << src */
1507                 /* dst = dst >> src */
1508                 case BPF_ALU | BPF_ADD | BPF_K:
1509                 case BPF_ALU | BPF_ADD | BPF_X:
1510                 case BPF_ALU | BPF_SUB | BPF_K:
1511                 case BPF_ALU | BPF_SUB | BPF_X:
1512                 case BPF_ALU | BPF_OR | BPF_K:
1513                 case BPF_ALU | BPF_OR | BPF_X:
1514                 case BPF_ALU | BPF_AND | BPF_K:
1515                 case BPF_ALU | BPF_AND | BPF_X:
1516                 case BPF_ALU | BPF_XOR | BPF_K:
1517                 case BPF_ALU | BPF_XOR | BPF_X:
1518                 case BPF_ALU64 | BPF_ADD | BPF_K:
1519                 case BPF_ALU64 | BPF_ADD | BPF_X:
1520                 case BPF_ALU64 | BPF_SUB | BPF_K:
1521                 case BPF_ALU64 | BPF_SUB | BPF_X:
1522                 case BPF_ALU64 | BPF_OR | BPF_K:
1523                 case BPF_ALU64 | BPF_OR | BPF_X:
1524                 case BPF_ALU64 | BPF_AND | BPF_K:
1525                 case BPF_ALU64 | BPF_AND | BPF_X:
1526                 case BPF_ALU64 | BPF_XOR | BPF_K:
1527                 case BPF_ALU64 | BPF_XOR | BPF_X:
1528                         switch (BPF_SRC(code)) {
1529                         case BPF_X:
1530                                 emit_ia32_alu_r64(is64, BPF_OP(code), dst,
1531                                                   src, dstk, sstk, &prog);
1532                                 break;
1533                         case BPF_K:
1534                                 emit_ia32_alu_i64(is64, BPF_OP(code), dst,
1535                                                   imm32, dstk, &prog);
1536                                 break;
1537                         }
1538                         break;
1539                 case BPF_ALU | BPF_MUL | BPF_K:
1540                 case BPF_ALU | BPF_MUL | BPF_X:
1541                         switch (BPF_SRC(code)) {
1542                         case BPF_X:
1543                                 emit_ia32_mul_r(dst_lo, src_lo, dstk,
1544                                                 sstk, &prog);
1545                                 break;
1546                         case BPF_K:
1547                                 /* mov ecx,imm32*/
1548                                 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1549                                             imm32);
1550                                 emit_ia32_mul_r(dst_lo, IA32_ECX, dstk,
1551                                                 false, &prog);
1552                                 break;
1553                         }
1554                         emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1555                         break;
1556                 case BPF_ALU | BPF_LSH | BPF_X:
1557                 case BPF_ALU | BPF_RSH | BPF_X:
1558                 case BPF_ALU | BPF_ARSH | BPF_K:
1559                 case BPF_ALU | BPF_ARSH | BPF_X:
1560                         switch (BPF_SRC(code)) {
1561                         case BPF_X:
1562                                 emit_ia32_shift_r(BPF_OP(code), dst_lo, src_lo,
1563                                                   dstk, sstk, &prog);
1564                                 break;
1565                         case BPF_K:
1566                                 /* mov ecx,imm32*/
1567                                 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1568                                             imm32);
1569                                 emit_ia32_shift_r(BPF_OP(code), dst_lo,
1570                                                   IA32_ECX, dstk, false,
1571                                                   &prog);
1572                                 break;
1573                         }
1574                         emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1575                         break;
1576                 /* dst = dst / src(imm) */
1577                 /* dst = dst % src(imm) */
1578                 case BPF_ALU | BPF_DIV | BPF_K:
1579                 case BPF_ALU | BPF_DIV | BPF_X:
1580                 case BPF_ALU | BPF_MOD | BPF_K:
1581                 case BPF_ALU | BPF_MOD | BPF_X:
1582                         switch (BPF_SRC(code)) {
1583                         case BPF_X:
1584                                 emit_ia32_div_mod_r(BPF_OP(code), dst_lo,
1585                                                     src_lo, dstk, sstk, &prog);
1586                                 break;
1587                         case BPF_K:
1588                                 /* mov ecx,imm32*/
1589                                 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1590                                             imm32);
1591                                 emit_ia32_div_mod_r(BPF_OP(code), dst_lo,
1592                                                     IA32_ECX, dstk, false,
1593                                                     &prog);
1594                                 break;
1595                         }
1596                         emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1597                         break;
1598                 case BPF_ALU64 | BPF_DIV | BPF_K:
1599                 case BPF_ALU64 | BPF_DIV | BPF_X:
1600                 case BPF_ALU64 | BPF_MOD | BPF_K:
1601                 case BPF_ALU64 | BPF_MOD | BPF_X:
1602                         goto notyet;
1603                 /* dst = dst >> imm */
1604                 /* dst = dst << imm */
1605                 case BPF_ALU | BPF_RSH | BPF_K:
1606                 case BPF_ALU | BPF_LSH | BPF_K:
1607                         if (unlikely(imm32 > 31))
1608                                 return -EINVAL;
1609                         /* mov ecx,imm32*/
1610                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
1611                         emit_ia32_shift_r(BPF_OP(code), dst_lo, IA32_ECX, dstk,
1612                                           false, &prog);
1613                         emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1614                         break;
1615                 /* dst = dst << imm */
1616                 case BPF_ALU64 | BPF_LSH | BPF_K:
1617                         if (unlikely(imm32 > 63))
1618                                 return -EINVAL;
1619                         emit_ia32_lsh_i64(dst, imm32, dstk, &prog);
1620                         break;
1621                 /* dst = dst >> imm */
1622                 case BPF_ALU64 | BPF_RSH | BPF_K:
1623                         if (unlikely(imm32 > 63))
1624                                 return -EINVAL;
1625                         emit_ia32_rsh_i64(dst, imm32, dstk, &prog);
1626                         break;
1627                 /* dst = dst << src */
1628                 case BPF_ALU64 | BPF_LSH | BPF_X:
1629                         emit_ia32_lsh_r64(dst, src, dstk, sstk, &prog);
1630                         break;
1631                 /* dst = dst >> src */
1632                 case BPF_ALU64 | BPF_RSH | BPF_X:
1633                         emit_ia32_rsh_r64(dst, src, dstk, sstk, &prog);
1634                         break;
1635                 /* dst = dst >> src (signed) */
1636                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1637                         emit_ia32_arsh_r64(dst, src, dstk, sstk, &prog);
1638                         break;
1639                 /* dst = dst >> imm (signed) */
1640                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1641                         if (unlikely(imm32 > 63))
1642                                 return -EINVAL;
1643                         emit_ia32_arsh_i64(dst, imm32, dstk, &prog);
1644                         break;
1645                 /* dst = ~dst */
1646                 case BPF_ALU | BPF_NEG:
1647                         emit_ia32_alu_i(is64, false, BPF_OP(code),
1648                                         dst_lo, 0, dstk, &prog);
1649                         emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1650                         break;
1651                 /* dst = ~dst (64 bit) */
1652                 case BPF_ALU64 | BPF_NEG:
1653                         emit_ia32_neg64(dst, dstk, &prog);
1654                         break;
1655                 /* dst = dst * src/imm */
1656                 case BPF_ALU64 | BPF_MUL | BPF_X:
1657                 case BPF_ALU64 | BPF_MUL | BPF_K:
1658                         switch (BPF_SRC(code)) {
1659                         case BPF_X:
1660                                 emit_ia32_mul_r64(dst, src, dstk, sstk, &prog);
1661                                 break;
1662                         case BPF_K:
1663                                 emit_ia32_mul_i64(dst, imm32, dstk, &prog);
1664                                 break;
1665                         }
1666                         break;
1667                 /* dst = htole(dst) */
1668                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1669                         emit_ia32_to_le_r64(dst, imm32, dstk, &prog);
1670                         break;
1671                 /* dst = htobe(dst) */
1672                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1673                         emit_ia32_to_be_r64(dst, imm32, dstk, &prog);
1674                         break;
1675                 /* dst = imm64 */
1676                 case BPF_LD | BPF_IMM | BPF_DW: {
1677                         s32 hi, lo = imm32;
1678
1679                         hi = insn[1].imm;
1680                         emit_ia32_mov_i(dst_lo, lo, dstk, &prog);
1681                         emit_ia32_mov_i(dst_hi, hi, dstk, &prog);
1682                         insn++;
1683                         i++;
1684                         break;
1685                 }
1686                 /* speculation barrier */
1687                 case BPF_ST | BPF_NOSPEC:
1688                         if (boot_cpu_has(X86_FEATURE_XMM2))
1689                                 /* Emit 'lfence' */
1690                                 EMIT3(0x0F, 0xAE, 0xE8);
1691                         break;
1692                 /* ST: *(u8*)(dst_reg + off) = imm */
1693                 case BPF_ST | BPF_MEM | BPF_H:
1694                 case BPF_ST | BPF_MEM | BPF_B:
1695                 case BPF_ST | BPF_MEM | BPF_W:
1696                 case BPF_ST | BPF_MEM | BPF_DW:
1697                         if (dstk)
1698                                 /* mov eax,dword ptr [ebp+off] */
1699                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1700                                       STACK_VAR(dst_lo));
1701                         else
1702                                 /* mov eax,dst_lo */
1703                                 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1704
1705                         switch (BPF_SIZE(code)) {
1706                         case BPF_B:
1707                                 EMIT(0xC6, 1); break;
1708                         case BPF_H:
1709                                 EMIT2(0x66, 0xC7); break;
1710                         case BPF_W:
1711                         case BPF_DW:
1712                                 EMIT(0xC7, 1); break;
1713                         }
1714
1715                         if (is_imm8(insn->off))
1716                                 EMIT2(add_1reg(0x40, IA32_EAX), insn->off);
1717                         else
1718                                 EMIT1_off32(add_1reg(0x80, IA32_EAX),
1719                                             insn->off);
1720                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(code)));
1721
1722                         if (BPF_SIZE(code) == BPF_DW) {
1723                                 u32 hi;
1724
1725                                 hi = imm32 & (1<<31) ? (u32)~0 : 0;
1726                                 EMIT2_off32(0xC7, add_1reg(0x80, IA32_EAX),
1727                                             insn->off + 4);
1728                                 EMIT(hi, 4);
1729                         }
1730                         break;
1731
1732                 /* STX: *(u8*)(dst_reg + off) = src_reg */
1733                 case BPF_STX | BPF_MEM | BPF_B:
1734                 case BPF_STX | BPF_MEM | BPF_H:
1735                 case BPF_STX | BPF_MEM | BPF_W:
1736                 case BPF_STX | BPF_MEM | BPF_DW:
1737                         if (dstk)
1738                                 /* mov eax,dword ptr [ebp+off] */
1739                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1740                                       STACK_VAR(dst_lo));
1741                         else
1742                                 /* mov eax,dst_lo */
1743                                 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1744
1745                         if (sstk)
1746                                 /* mov edx,dword ptr [ebp+off] */
1747                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1748                                       STACK_VAR(src_lo));
1749                         else
1750                                 /* mov edx,src_lo */
1751                                 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EDX));
1752
1753                         switch (BPF_SIZE(code)) {
1754                         case BPF_B:
1755                                 EMIT(0x88, 1); break;
1756                         case BPF_H:
1757                                 EMIT2(0x66, 0x89); break;
1758                         case BPF_W:
1759                         case BPF_DW:
1760                                 EMIT(0x89, 1); break;
1761                         }
1762
1763                         if (is_imm8(insn->off))
1764                                 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
1765                                       insn->off);
1766                         else
1767                                 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
1768                                             insn->off);
1769
1770                         if (BPF_SIZE(code) == BPF_DW) {
1771                                 if (sstk)
1772                                         /* mov edi,dword ptr [ebp+off] */
1773                                         EMIT3(0x8B, add_2reg(0x40, IA32_EBP,
1774                                                              IA32_EDX),
1775                                               STACK_VAR(src_hi));
1776                                 else
1777                                         /* mov edi,src_hi */
1778                                         EMIT2(0x8B, add_2reg(0xC0, src_hi,
1779                                                              IA32_EDX));
1780                                 EMIT1(0x89);
1781                                 if (is_imm8(insn->off + 4)) {
1782                                         EMIT2(add_2reg(0x40, IA32_EAX,
1783                                                        IA32_EDX),
1784                                               insn->off + 4);
1785                                 } else {
1786                                         EMIT1(add_2reg(0x80, IA32_EAX,
1787                                                        IA32_EDX));
1788                                         EMIT(insn->off + 4, 4);
1789                                 }
1790                         }
1791                         break;
1792
1793                 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1794                 case BPF_LDX | BPF_MEM | BPF_B:
1795                 case BPF_LDX | BPF_MEM | BPF_H:
1796                 case BPF_LDX | BPF_MEM | BPF_W:
1797                 case BPF_LDX | BPF_MEM | BPF_DW:
1798                         if (sstk)
1799                                 /* mov eax,dword ptr [ebp+off] */
1800                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1801                                       STACK_VAR(src_lo));
1802                         else
1803                                 /* mov eax,dword ptr [ebp+off] */
1804                                 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EAX));
1805
1806                         switch (BPF_SIZE(code)) {
1807                         case BPF_B:
1808                                 EMIT2(0x0F, 0xB6); break;
1809                         case BPF_H:
1810                                 EMIT2(0x0F, 0xB7); break;
1811                         case BPF_W:
1812                         case BPF_DW:
1813                                 EMIT(0x8B, 1); break;
1814                         }
1815
1816                         if (is_imm8(insn->off))
1817                                 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
1818                                       insn->off);
1819                         else
1820                                 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
1821                                             insn->off);
1822
1823                         if (dstk)
1824                                 /* mov dword ptr [ebp+off],edx */
1825                                 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
1826                                       STACK_VAR(dst_lo));
1827                         else
1828                                 /* mov dst_lo,edx */
1829                                 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EDX));
1830                         switch (BPF_SIZE(code)) {
1831                         case BPF_B:
1832                         case BPF_H:
1833                         case BPF_W:
1834                                 if (dstk) {
1835                                         EMIT3(0xC7, add_1reg(0x40, IA32_EBP),
1836                                               STACK_VAR(dst_hi));
1837                                         EMIT(0x0, 4);
1838                                 } else {
1839                                         /* xor dst_hi,dst_hi */
1840                                         EMIT2(0x33,
1841                                               add_2reg(0xC0, dst_hi, dst_hi));
1842                                 }
1843                                 break;
1844                         case BPF_DW:
1845                                 EMIT2_off32(0x8B,
1846                                             add_2reg(0x80, IA32_EAX, IA32_EDX),
1847                                             insn->off + 4);
1848                                 if (dstk)
1849                                         EMIT3(0x89,
1850                                               add_2reg(0x40, IA32_EBP,
1851                                                        IA32_EDX),
1852                                               STACK_VAR(dst_hi));
1853                                 else
1854                                         EMIT2(0x89,
1855                                               add_2reg(0xC0, dst_hi, IA32_EDX));
1856                                 break;
1857                         default:
1858                                 break;
1859                         }
1860                         break;
1861                 /* call */
1862                 case BPF_JMP | BPF_CALL:
1863                 {
1864                         const u8 *r1 = bpf2ia32[BPF_REG_1];
1865                         const u8 *r2 = bpf2ia32[BPF_REG_2];
1866                         const u8 *r3 = bpf2ia32[BPF_REG_3];
1867                         const u8 *r4 = bpf2ia32[BPF_REG_4];
1868                         const u8 *r5 = bpf2ia32[BPF_REG_5];
1869
1870                         if (insn->src_reg == BPF_PSEUDO_CALL)
1871                                 goto notyet;
1872
1873                         func = (u8 *) __bpf_call_base + imm32;
1874                         jmp_offset = func - (image + addrs[i]);
1875
1876                         if (!imm32 || !is_simm32(jmp_offset)) {
1877                                 pr_err("unsupported BPF func %d addr %p image %p\n",
1878                                        imm32, func, image);
1879                                 return -EINVAL;
1880                         }
1881
1882                         /* mov eax,dword ptr [ebp+off] */
1883                         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1884                               STACK_VAR(r1[0]));
1885                         /* mov edx,dword ptr [ebp+off] */
1886                         EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1887                               STACK_VAR(r1[1]));
1888
1889                         emit_push_r64(r5, &prog);
1890                         emit_push_r64(r4, &prog);
1891                         emit_push_r64(r3, &prog);
1892                         emit_push_r64(r2, &prog);
1893
1894                         EMIT1_off32(0xE8, jmp_offset + 9);
1895
1896                         /* mov dword ptr [ebp+off],eax */
1897                         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1898                               STACK_VAR(r0[0]));
1899                         /* mov dword ptr [ebp+off],edx */
1900                         EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
1901                               STACK_VAR(r0[1]));
1902
1903                         /* add esp,32 */
1904                         EMIT3(0x83, add_1reg(0xC0, IA32_ESP), 32);
1905                         break;
1906                 }
1907                 case BPF_JMP | BPF_TAIL_CALL:
1908                         emit_bpf_tail_call(&prog);
1909                         break;
1910
1911                 /* cond jump */
1912                 case BPF_JMP | BPF_JEQ | BPF_X:
1913                 case BPF_JMP | BPF_JNE | BPF_X:
1914                 case BPF_JMP | BPF_JGT | BPF_X:
1915                 case BPF_JMP | BPF_JLT | BPF_X:
1916                 case BPF_JMP | BPF_JGE | BPF_X:
1917                 case BPF_JMP | BPF_JLE | BPF_X: {
1918                         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1919                         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1920                         u8 sreg_lo = sstk ? IA32_ECX : src_lo;
1921                         u8 sreg_hi = sstk ? IA32_EBX : src_hi;
1922
1923                         if (dstk) {
1924                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1925                                       STACK_VAR(dst_lo));
1926                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1927                                       STACK_VAR(dst_hi));
1928                         }
1929
1930                         if (sstk) {
1931                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
1932                                       STACK_VAR(src_lo));
1933                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX),
1934                                       STACK_VAR(src_hi));
1935                         }
1936
1937                         /* cmp dreg_hi,sreg_hi */
1938                         EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
1939                         EMIT2(IA32_JNE, 2);
1940                         /* cmp dreg_lo,sreg_lo */
1941                         EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
1942                         goto emit_cond_jmp;
1943                 }
1944                 case BPF_JMP | BPF_JSGT | BPF_X:
1945                 case BPF_JMP | BPF_JSLE | BPF_X:
1946                 case BPF_JMP | BPF_JSLT | BPF_X:
1947                 case BPF_JMP | BPF_JSGE | BPF_X: {
1948                         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1949                         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1950                         u8 sreg_lo = sstk ? IA32_ECX : src_lo;
1951                         u8 sreg_hi = sstk ? IA32_EBX : src_hi;
1952
1953                         if (dstk) {
1954                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1955                                       STACK_VAR(dst_lo));
1956                                 EMIT3(0x8B,
1957                                       add_2reg(0x40, IA32_EBP,
1958                                                IA32_EDX),
1959                                       STACK_VAR(dst_hi));
1960                         }
1961
1962                         if (sstk) {
1963                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
1964                                       STACK_VAR(src_lo));
1965                                 EMIT3(0x8B,
1966                                       add_2reg(0x40, IA32_EBP,
1967                                                IA32_EBX),
1968                                       STACK_VAR(src_hi));
1969                         }
1970
1971                         /* cmp dreg_hi,sreg_hi */
1972                         EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
1973                         EMIT2(IA32_JNE, 10);
1974                         /* cmp dreg_lo,sreg_lo */
1975                         EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
1976                         goto emit_cond_jmp_signed;
1977                 }
1978                 case BPF_JMP | BPF_JSET | BPF_X: {
1979                         u8 dreg_lo = IA32_EAX;
1980                         u8 dreg_hi = IA32_EDX;
1981                         u8 sreg_lo = sstk ? IA32_ECX : src_lo;
1982                         u8 sreg_hi = sstk ? IA32_EBX : src_hi;
1983
1984                         if (dstk) {
1985                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1986                                       STACK_VAR(dst_lo));
1987                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1988                                       STACK_VAR(dst_hi));
1989                         } else {
1990                                 /* mov dreg_lo,dst_lo */
1991                                 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dst_lo));
1992                                 /* mov dreg_hi,dst_hi */
1993                                 EMIT2(0x89,
1994                                       add_2reg(0xC0, dreg_hi, dst_hi));
1995                         }
1996
1997                         if (sstk) {
1998                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
1999                                       STACK_VAR(src_lo));
2000                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX),
2001                                       STACK_VAR(src_hi));
2002                         }
2003                         /* and dreg_lo,sreg_lo */
2004                         EMIT2(0x23, add_2reg(0xC0, sreg_lo, dreg_lo));
2005                         /* and dreg_hi,sreg_hi */
2006                         EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2007                         /* or dreg_lo,dreg_hi */
2008                         EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2009                         goto emit_cond_jmp;
2010                 }
2011                 case BPF_JMP | BPF_JSET | BPF_K: {
2012                         u32 hi;
2013                         u8 dreg_lo = IA32_EAX;
2014                         u8 dreg_hi = IA32_EDX;
2015                         u8 sreg_lo = IA32_ECX;
2016                         u8 sreg_hi = IA32_EBX;
2017
2018                         if (dstk) {
2019                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2020                                       STACK_VAR(dst_lo));
2021                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
2022                                       STACK_VAR(dst_hi));
2023                         } else {
2024                                 /* mov dreg_lo,dst_lo */
2025                                 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dst_lo));
2026                                 /* mov dreg_hi,dst_hi */
2027                                 EMIT2(0x89,
2028                                       add_2reg(0xC0, dreg_hi, dst_hi));
2029                         }
2030                         hi = imm32 & (1<<31) ? (u32)~0 : 0;
2031
2032                         /* mov ecx,imm32 */
2033                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2034                         /* mov ebx,imm32 */
2035                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2036
2037                         /* and dreg_lo,sreg_lo */
2038                         EMIT2(0x23, add_2reg(0xC0, sreg_lo, dreg_lo));
2039                         /* and dreg_hi,sreg_hi */
2040                         EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2041                         /* or dreg_lo,dreg_hi */
2042                         EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2043                         goto emit_cond_jmp;
2044                 }
2045                 case BPF_JMP | BPF_JEQ | BPF_K:
2046                 case BPF_JMP | BPF_JNE | BPF_K:
2047                 case BPF_JMP | BPF_JGT | BPF_K:
2048                 case BPF_JMP | BPF_JLT | BPF_K:
2049                 case BPF_JMP | BPF_JGE | BPF_K:
2050                 case BPF_JMP | BPF_JLE | BPF_K: {
2051                         u32 hi;
2052                         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2053                         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2054                         u8 sreg_lo = IA32_ECX;
2055                         u8 sreg_hi = IA32_EBX;
2056
2057                         if (dstk) {
2058                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2059                                       STACK_VAR(dst_lo));
2060                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
2061                                       STACK_VAR(dst_hi));
2062                         }
2063
2064                         hi = imm32 & (1<<31) ? (u32)~0 : 0;
2065                         /* mov ecx,imm32 */
2066                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2067                         /* mov ebx,imm32 */
2068                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2069
2070                         /* cmp dreg_hi,sreg_hi */
2071                         EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2072                         EMIT2(IA32_JNE, 2);
2073                         /* cmp dreg_lo,sreg_lo */
2074                         EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2075
2076 emit_cond_jmp:          jmp_cond = get_cond_jmp_opcode(BPF_OP(code), false);
2077                         if (jmp_cond == COND_JMP_OPCODE_INVALID)
2078                                 return -EFAULT;
2079                         jmp_offset = addrs[i + insn->off] - addrs[i];
2080                         if (is_imm8(jmp_offset)) {
2081                                 EMIT2(jmp_cond, jmp_offset);
2082                         } else if (is_simm32(jmp_offset)) {
2083                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2084                         } else {
2085                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2086                                 return -EFAULT;
2087                         }
2088                         break;
2089                 }
2090                 case BPF_JMP | BPF_JSGT | BPF_K:
2091                 case BPF_JMP | BPF_JSLE | BPF_K:
2092                 case BPF_JMP | BPF_JSLT | BPF_K:
2093                 case BPF_JMP | BPF_JSGE | BPF_K: {
2094                         u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2095                         u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2096                         u8 sreg_lo = IA32_ECX;
2097                         u8 sreg_hi = IA32_EBX;
2098                         u32 hi;
2099
2100                         if (dstk) {
2101                                 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2102                                       STACK_VAR(dst_lo));
2103                                 EMIT3(0x8B,
2104                                       add_2reg(0x40, IA32_EBP,
2105                                                IA32_EDX),
2106                                       STACK_VAR(dst_hi));
2107                         }
2108
2109                         /* mov ecx,imm32 */
2110                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2111                         hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2112                         /* mov ebx,imm32 */
2113                         EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2114                         /* cmp dreg_hi,sreg_hi */
2115                         EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2116                         EMIT2(IA32_JNE, 10);
2117                         /* cmp dreg_lo,sreg_lo */
2118                         EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2119
2120                         /*
2121                          * For simplicity of branch offset computation,
2122                          * let's use fixed jump coding here.
2123                          */
2124 emit_cond_jmp_signed:   /* Check the condition for low 32-bit comparison */
2125                         jmp_cond = get_cond_jmp_opcode(BPF_OP(code), true);
2126                         if (jmp_cond == COND_JMP_OPCODE_INVALID)
2127                                 return -EFAULT;
2128                         jmp_offset = addrs[i + insn->off] - addrs[i] + 8;
2129                         if (is_simm32(jmp_offset)) {
2130                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2131                         } else {
2132                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2133                                 return -EFAULT;
2134                         }
2135                         EMIT2(0xEB, 6);
2136
2137                         /* Check the condition for high 32-bit comparison */
2138                         jmp_cond = get_cond_jmp_opcode(BPF_OP(code), false);
2139                         if (jmp_cond == COND_JMP_OPCODE_INVALID)
2140                                 return -EFAULT;
2141                         jmp_offset = addrs[i + insn->off] - addrs[i];
2142                         if (is_simm32(jmp_offset)) {
2143                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2144                         } else {
2145                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2146                                 return -EFAULT;
2147                         }
2148                         break;
2149                 }
2150                 case BPF_JMP | BPF_JA:
2151                         if (insn->off == -1)
2152                                 /* -1 jmp instructions will always jump
2153                                  * backwards two bytes. Explicitly handling
2154                                  * this case avoids wasting too many passes
2155                                  * when there are long sequences of replaced
2156                                  * dead code.
2157                                  */
2158                                 jmp_offset = -2;
2159                         else
2160                                 jmp_offset = addrs[i + insn->off] - addrs[i];
2161
2162                         if (!jmp_offset)
2163                                 /* Optimize out nop jumps */
2164                                 break;
2165 emit_jmp:
2166                         if (is_imm8(jmp_offset)) {
2167                                 EMIT2(0xEB, jmp_offset);
2168                         } else if (is_simm32(jmp_offset)) {
2169                                 EMIT1_off32(0xE9, jmp_offset);
2170                         } else {
2171                                 pr_err("jmp gen bug %llx\n", jmp_offset);
2172                                 return -EFAULT;
2173                         }
2174                         break;
2175                 /* STX XADD: lock *(u32 *)(dst + off) += src */
2176                 case BPF_STX | BPF_XADD | BPF_W:
2177                 /* STX XADD: lock *(u64 *)(dst + off) += src */
2178                 case BPF_STX | BPF_XADD | BPF_DW:
2179                         goto notyet;
2180                 case BPF_JMP | BPF_EXIT:
2181                         if (seen_exit) {
2182                                 jmp_offset = ctx->cleanup_addr - addrs[i];
2183                                 goto emit_jmp;
2184                         }
2185                         seen_exit = true;
2186                         /* Update cleanup_addr */
2187                         ctx->cleanup_addr = proglen;
2188                         emit_epilogue(&prog, bpf_prog->aux->stack_depth);
2189                         break;
2190 notyet:
2191                         pr_info_once("*** NOT YET: opcode %02x ***\n", code);
2192                         return -EFAULT;
2193                 default:
2194                         /*
2195                          * This error will be seen if new instruction was added
2196                          * to interpreter, but not to JIT or if there is junk in
2197                          * bpf_prog
2198                          */
2199                         pr_err("bpf_jit: unknown opcode %02x\n", code);
2200                         return -EINVAL;
2201                 }
2202
2203                 ilen = prog - temp;
2204                 if (ilen > BPF_MAX_INSN_SIZE) {
2205                         pr_err("bpf_jit: fatal insn size error\n");
2206                         return -EFAULT;
2207                 }
2208
2209                 if (image) {
2210                         /*
2211                          * When populating the image, assert that:
2212                          *
2213                          *  i) We do not write beyond the allocated space, and
2214                          * ii) addrs[i] did not change from the prior run, in order
2215                          *     to validate assumptions made for computing branch
2216                          *     displacements.
2217                          */
2218                         if (unlikely(proglen + ilen > oldproglen ||
2219                                      proglen + ilen != addrs[i])) {
2220                                 pr_err("bpf_jit: fatal error\n");
2221                                 return -EFAULT;
2222                         }
2223                         memcpy(image + proglen, temp, ilen);
2224                 }
2225                 proglen += ilen;
2226                 addrs[i] = proglen;
2227                 prog = temp;
2228         }
2229         return proglen;
2230 }
2231
2232 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2233 {
2234         struct bpf_binary_header *header = NULL;
2235         struct bpf_prog *tmp, *orig_prog = prog;
2236         int proglen, oldproglen = 0;
2237         struct jit_context ctx = {};
2238         bool tmp_blinded = false;
2239         u8 *image = NULL;
2240         int *addrs;
2241         int pass;
2242         int i;
2243
2244         if (!prog->jit_requested)
2245                 return orig_prog;
2246
2247         tmp = bpf_jit_blind_constants(prog);
2248         /*
2249          * If blinding was requested and we failed during blinding,
2250          * we must fall back to the interpreter.
2251          */
2252         if (IS_ERR(tmp))
2253                 return orig_prog;
2254         if (tmp != prog) {
2255                 tmp_blinded = true;
2256                 prog = tmp;
2257         }
2258
2259         addrs = kmalloc_array(prog->len, sizeof(*addrs), GFP_KERNEL);
2260         if (!addrs) {
2261                 prog = orig_prog;
2262                 goto out;
2263         }
2264
2265         /*
2266          * Before first pass, make a rough estimation of addrs[]
2267          * each BPF instruction is translated to less than 64 bytes
2268          */
2269         for (proglen = 0, i = 0; i < prog->len; i++) {
2270                 proglen += 64;
2271                 addrs[i] = proglen;
2272         }
2273         ctx.cleanup_addr = proglen;
2274
2275         /*
2276          * JITed image shrinks with every pass and the loop iterates
2277          * until the image stops shrinking. Very large BPF programs
2278          * may converge on the last pass. In such case do one more
2279          * pass to emit the final image.
2280          */
2281         for (pass = 0; pass < 20 || image; pass++) {
2282                 proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
2283                 if (proglen <= 0) {
2284 out_image:
2285                         image = NULL;
2286                         if (header)
2287                                 bpf_jit_binary_free(header);
2288                         prog = orig_prog;
2289                         goto out_addrs;
2290                 }
2291                 if (image) {
2292                         if (proglen != oldproglen) {
2293                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2294                                        proglen, oldproglen);
2295                                 goto out_image;
2296                         }
2297                         break;
2298                 }
2299                 if (proglen == oldproglen) {
2300                         header = bpf_jit_binary_alloc(proglen, &image,
2301                                                       1, jit_fill_hole);
2302                         if (!header) {
2303                                 prog = orig_prog;
2304                                 goto out_addrs;
2305                         }
2306                 }
2307                 oldproglen = proglen;
2308                 cond_resched();
2309         }
2310
2311         if (bpf_jit_enable > 1)
2312                 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2313
2314         if (image) {
2315                 bpf_jit_binary_lock_ro(header);
2316                 prog->bpf_func = (void *)image;
2317                 prog->jited = 1;
2318                 prog->jited_len = proglen;
2319         } else {
2320                 prog = orig_prog;
2321         }
2322
2323 out_addrs:
2324         kfree(addrs);
2325 out:
2326         if (tmp_blinded)
2327                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2328                                            tmp : orig_prog);
2329         return prog;
2330 }