arch/x86/net/bpf_jit_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * bpf_jit_comp.c: BPF JIT compiler
   4  *
   5  * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
   6  * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
   7  */
   8 #include <linux/netdevice.h>
   9 #include <linux/filter.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/bpf.h>
  12 #include <linux/memory.h>
  13 #include <linux/sort.h>
  14 #include <asm/extable.h>
  15 #include <asm/set_memory.h>
  16 #include <asm/nospec-branch.h>
  17 #include <asm/text-patching.h>
  18 #include <asm/asm-prototypes.h>
  19
  20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  21 {
  22         if (len == 1)
  23                 *ptr = bytes;
  24         else if (len == 2)
  25                 *(u16 *)ptr = bytes;
  26         else {
  27                 *(u32 *)ptr = bytes;
  28                 barrier();
  29         }
  30         return ptr + len;
  31 }
  32
  33 #define EMIT(bytes, len) \
  34         do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
  35
  36 #define EMIT1(b1)               EMIT(b1, 1)
  37 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  38 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  39 #define EMIT4(b1, b2, b3, b4)   EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  40
  41 #define EMIT1_off32(b1, off) \
  42         do { EMIT1(b1); EMIT(off, 4); } while (0)
  43 #define EMIT2_off32(b1, b2, off) \
  44         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  45 #define EMIT3_off32(b1, b2, b3, off) \
  46         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  47 #define EMIT4_off32(b1, b2, b3, b4, off) \
  48         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  49
  50 static bool is_imm8(int value)
  51 {
  52         return value <= 127 && value >= -128;
  53 }
  54
  55 static bool is_simm32(s64 value)
  56 {
  57         return value == (s64)(s32)value;
  58 }
  59
  60 static bool is_uimm32(u64 value)
  61 {
  62         return value == (u64)(u32)value;
  63 }
  64
  65 /* mov dst, src */
  66 #define EMIT_mov(DST, SRC)                                                               \
  67         do {                                                                             \
  68                 if (DST != SRC)                                                          \
  69                         EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
  70         } while (0)
  71
  72 static int bpf_size_to_x86_bytes(int bpf_size)
  73 {
  74         if (bpf_size == BPF_W)
  75                 return 4;
  76         else if (bpf_size == BPF_H)
  77                 return 2;
  78         else if (bpf_size == BPF_B)
  79                 return 1;
  80         else if (bpf_size == BPF_DW)
  81                 return 4; /* imm32 */
  82         else
  83                 return 0;
  84 }
  85
  86 /*
  87  * List of x86 cond jumps opcodes (. + s8)
  88  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
  89  */
  90 #define X86_JB  0x72
  91 #define X86_JAE 0x73
  92 #define X86_JE  0x74
  93 #define X86_JNE 0x75
  94 #define X86_JBE 0x76
  95 #define X86_JA  0x77
  96 #define X86_JL  0x7C
  97 #define X86_JGE 0x7D
  98 #define X86_JLE 0x7E
  99 #define X86_JG  0x7F
 100
 101 /* Pick a register outside of BPF range for JIT internal work */
 102 #define AUX_REG (MAX_BPF_JIT_REG + 1)
 103 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
 104
 105 /*
 106  * The following table maps BPF registers to x86-64 registers.
 107  *
 108  * x86-64 register R12 is unused, since if used as base address
 109  * register in load/store instructions, it always needs an
 110  * extra byte of encoding and is callee saved.
 111  *
 112  * x86-64 register R9 is not used by BPF programs, but can be used by BPF
 113  * trampoline. x86-64 register R10 is used for blinding (if enabled).
 114  */
 115 static const int reg2hex[] = {
 116         [BPF_REG_0] = 0,  /* RAX */
 117         [BPF_REG_1] = 7,  /* RDI */
 118         [BPF_REG_2] = 6,  /* RSI */
 119         [BPF_REG_3] = 2,  /* RDX */
 120         [BPF_REG_4] = 1,  /* RCX */
 121         [BPF_REG_5] = 0,  /* R8  */
 122         [BPF_REG_6] = 3,  /* RBX callee saved */
 123         [BPF_REG_7] = 5,  /* R13 callee saved */
 124         [BPF_REG_8] = 6,  /* R14 callee saved */
 125         [BPF_REG_9] = 7,  /* R15 callee saved */
 126         [BPF_REG_FP] = 5, /* RBP readonly */
 127         [BPF_REG_AX] = 2, /* R10 temp register */
 128         [AUX_REG] = 3,    /* R11 temp register */
 129         [X86_REG_R9] = 1, /* R9 register, 6th function argument */
 130 };
 131
 132 static const int reg2pt_regs[] = {
 133         [BPF_REG_0] = offsetof(struct pt_regs, ax),
 134         [BPF_REG_1] = offsetof(struct pt_regs, di),
 135         [BPF_REG_2] = offsetof(struct pt_regs, si),
 136         [BPF_REG_3] = offsetof(struct pt_regs, dx),
 137         [BPF_REG_4] = offsetof(struct pt_regs, cx),
 138         [BPF_REG_5] = offsetof(struct pt_regs, r8),
 139         [BPF_REG_6] = offsetof(struct pt_regs, bx),
 140         [BPF_REG_7] = offsetof(struct pt_regs, r13),
 141         [BPF_REG_8] = offsetof(struct pt_regs, r14),
 142         [BPF_REG_9] = offsetof(struct pt_regs, r15),
 143 };
 144
 145 /*
 146  * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
 147  * which need extra byte of encoding.
 148  * rax,rcx,...,rbp have simpler encoding
 149  */
 150 static bool is_ereg(u32 reg)
 151 {
 152         return (1 << reg) & (BIT(BPF_REG_5) |
 153                              BIT(AUX_REG) |
 154                              BIT(BPF_REG_7) |
 155                              BIT(BPF_REG_8) |
 156                              BIT(BPF_REG_9) |
 157                              BIT(X86_REG_R9) |
 158                              BIT(BPF_REG_AX));
 159 }
 160
 161 /*
 162  * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
 163  * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
 164  * of encoding. al,cl,dl,bl have simpler encoding.
 165  */
 166 static bool is_ereg_8l(u32 reg)
 167 {
 168         return is_ereg(reg) ||
 169             (1 << reg) & (BIT(BPF_REG_1) |
 170                           BIT(BPF_REG_2) |
 171                           BIT(BPF_REG_FP));
 172 }
 173
 174 static bool is_axreg(u32 reg)
 175 {
 176         return reg == BPF_REG_0;
 177 }
 178
 179 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
 180 static u8 add_1mod(u8 byte, u32 reg)
 181 {
 182         if (is_ereg(reg))
 183                 byte |= 1;
 184         return byte;
 185 }
 186
 187 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
 188 {
 189         if (is_ereg(r1))
 190                 byte |= 1;
 191         if (is_ereg(r2))
 192                 byte |= 4;
 193         return byte;
 194 }
 195
 196 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
 197 static u8 add_1reg(u8 byte, u32 dst_reg)
 198 {
 199         return byte + reg2hex[dst_reg];
 200 }
 201
 202 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
 203 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 204 {
 205         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 206 }
 207
 208 /* Some 1-byte opcodes for binary ALU operations */
 209 static u8 simple_alu_opcodes[] = {
 210         [BPF_ADD] = 0x01,
 211         [BPF_SUB] = 0x29,
 212         [BPF_AND] = 0x21,
 213         [BPF_OR] = 0x09,
 214         [BPF_XOR] = 0x31,
 215         [BPF_LSH] = 0xE0,
 216         [BPF_RSH] = 0xE8,
 217         [BPF_ARSH] = 0xF8,
 218 };
 219
 220 static void jit_fill_hole(void *area, unsigned int size)
 221 {
 222         /* Fill whole space with INT3 instructions */
 223         memset(area, 0xcc, size);
 224 }
 225
 226 struct jit_context {
 227         int cleanup_addr; /* Epilogue code offset */
 228 };
 229
 230 /* Maximum number of bytes emitted while JITing one eBPF insn */
 231 #define BPF_MAX_INSN_SIZE       128
 232 #define BPF_INSN_SAFETY         64
 233
 234 /* Number of bytes emit_patch() needs to generate instructions */
 235 #define X86_PATCH_SIZE          5
 236 /* Number of bytes that will be skipped on tailcall */
 237 #define X86_TAIL_CALL_OFFSET    11
 238
 239 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
 240 {
 241         u8 *prog = *pprog;
 242         int cnt = 0;
 243
 244         if (callee_regs_used[0])
 245                 EMIT1(0x53);         /* push rbx */
 246         if (callee_regs_used[1])
 247                 EMIT2(0x41, 0x55);   /* push r13 */
 248         if (callee_regs_used[2])
 249                 EMIT2(0x41, 0x56);   /* push r14 */
 250         if (callee_regs_used[3])
 251                 EMIT2(0x41, 0x57);   /* push r15 */
 252         *pprog = prog;
 253 }
 254
 255 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
 256 {
 257         u8 *prog = *pprog;
 258         int cnt = 0;
 259
 260         if (callee_regs_used[3])
 261                 EMIT2(0x41, 0x5F);   /* pop r15 */
 262         if (callee_regs_used[2])
 263                 EMIT2(0x41, 0x5E);   /* pop r14 */
 264         if (callee_regs_used[1])
 265                 EMIT2(0x41, 0x5D);   /* pop r13 */
 266         if (callee_regs_used[0])
 267                 EMIT1(0x5B);         /* pop rbx */
 268         *pprog = prog;
 269 }
 270
 271 /*
 272  * Emit x86-64 prologue code for BPF program.
 273  * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
 274  * while jumping to another program
 275  */
 276 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
 277                           bool tail_call_reachable, bool is_subprog)
 278 {
 279         u8 *prog = *pprog;
 280         int cnt = X86_PATCH_SIZE;
 281
 282         /* BPF trampoline can be made to work without these nops,
 283          * but let's waste 5 bytes for now and optimize later
 284          */
 285         memcpy(prog, x86_nops[5], cnt);
 286         prog += cnt;
 287         if (!ebpf_from_cbpf) {
 288                 if (tail_call_reachable && !is_subprog)
 289                         EMIT2(0x31, 0xC0); /* xor eax, eax */
 290                 else
 291                         EMIT2(0x66, 0x90); /* nop2 */
 292         }
 293         EMIT1(0x55);             /* push rbp */
 294         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
 295         /* sub rsp, rounded_stack_depth */
 296         if (stack_depth)
 297                 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
 298         if (tail_call_reachable)
 299                 EMIT1(0x50);         /* push rax */
 300         *pprog = prog;
 301 }
 302
 303 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
 304 {
 305         u8 *prog = *pprog;
 306         int cnt = 0;
 307         s64 offset;
 308
 309         offset = func - (ip + X86_PATCH_SIZE);
 310         if (!is_simm32(offset)) {
 311                 pr_err("Target call %p is out of range\n", func);
 312                 return -ERANGE;
 313         }
 314         EMIT1_off32(opcode, offset);
 315         *pprog = prog;
 316         return 0;
 317 }
 318
 319 static int emit_call(u8 **pprog, void *func, void *ip)
 320 {
 321         return emit_patch(pprog, func, ip, 0xE8);
 322 }
 323
 324 static int emit_jump(u8 **pprog, void *func, void *ip)
 325 {
 326         return emit_patch(pprog, func, ip, 0xE9);
 327 }
 328
 329 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 330                                 void *old_addr, void *new_addr,
 331                                 const bool text_live)
 332 {
 333         const u8 *nop_insn = x86_nops[5];
 334         u8 old_insn[X86_PATCH_SIZE];
 335         u8 new_insn[X86_PATCH_SIZE];
 336         u8 *prog;
 337         int ret;
 338
 339         memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
 340         if (old_addr) {
 341                 prog = old_insn;
 342                 ret = t == BPF_MOD_CALL ?
 343                       emit_call(&prog, old_addr, ip) :
 344                       emit_jump(&prog, old_addr, ip);
 345                 if (ret)
 346                         return ret;
 347         }
 348
 349         memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
 350         if (new_addr) {
 351                 prog = new_insn;
 352                 ret = t == BPF_MOD_CALL ?
 353                       emit_call(&prog, new_addr, ip) :
 354                       emit_jump(&prog, new_addr, ip);
 355                 if (ret)
 356                         return ret;
 357         }
 358
 359         ret = -EBUSY;
 360         mutex_lock(&text_mutex);
 361         if (memcmp(ip, old_insn, X86_PATCH_SIZE))
 362                 goto out;
 363         ret = 1;
 364         if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
 365                 if (text_live)
 366                         text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
 367                 else
 368                         memcpy(ip, new_insn, X86_PATCH_SIZE);
 369                 ret = 0;
 370         }
 371 out:
 372         mutex_unlock(&text_mutex);
 373         return ret;
 374 }
 375
 376 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 377                        void *old_addr, void *new_addr)
 378 {
 379         if (!is_kernel_text((long)ip) &&
 380             !is_bpf_text_address((long)ip))
 381                 /* BPF poking in modules is not supported */
 382                 return -EINVAL;
 383
 384         return __bpf_arch_text_poke(ip, t, old_addr, new_addr, true);
 385 }
 386
 387 static int get_pop_bytes(bool *callee_regs_used)
 388 {
 389         int bytes = 0;
 390
 391         if (callee_regs_used[3])
 392                 bytes += 2;
 393         if (callee_regs_used[2])
 394                 bytes += 2;
 395         if (callee_regs_used[1])
 396                 bytes += 2;
 397         if (callee_regs_used[0])
 398                 bytes += 1;
 399
 400         return bytes;
 401 }
 402
 403 /*
 404  * Generate the following code:
 405  *
 406  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
 407  *   if (index >= array->map.max_entries)
 408  *     goto out;
 409  *   if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
 410  *     goto out;
 411  *   prog = array->ptrs[index];
 412  *   if (prog == NULL)
 413  *     goto out;
 414  *   goto *(prog->bpf_func + prologue_size);
 415  * out:
 416  */
 417 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
 418                                         u32 stack_depth)
 419 {
 420         int tcc_off = -4 - round_up(stack_depth, 8);
 421         u8 *prog = *pprog;
 422         int pop_bytes = 0;
 423         int off1 = 42;
 424         int off2 = 31;
 425         int off3 = 9;
 426         int cnt = 0;
 427
 428         /* count the additional bytes used for popping callee regs from stack
 429          * that need to be taken into account for each of the offsets that
 430          * are used for bailing out of the tail call
 431          */
 432         pop_bytes = get_pop_bytes(callee_regs_used);
 433         off1 += pop_bytes;
 434         off2 += pop_bytes;
 435         off3 += pop_bytes;
 436
 437         if (stack_depth) {
 438                 off1 += 7;
 439                 off2 += 7;
 440                 off3 += 7;
 441         }
 442
 443         /*
 444          * rdi - pointer to ctx
 445          * rsi - pointer to bpf_array
 446          * rdx - index in bpf_array
 447          */
 448
 449         /*
 450          * if (index >= array->map.max_entries)
 451          *      goto out;
 452          */
 453         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
 454         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 455               offsetof(struct bpf_array, map.max_entries));
 456 #define OFFSET1 (off1 + RETPOLINE_RCX_BPF_JIT_SIZE) /* Number of bytes to jump */
 457         EMIT2(X86_JBE, OFFSET1);                  /* jbe out */
 458
 459         /*
 460          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
 461          *      goto out;
 462          */
 463         EMIT2_off32(0x8B, 0x85, tcc_off);         /* mov eax, dword ptr [rbp - tcc_off] */
 464         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
 465 #define OFFSET2 (off2 + RETPOLINE_RCX_BPF_JIT_SIZE)
 466         EMIT2(X86_JA, OFFSET2);                   /* ja out */
 467         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
 468         EMIT2_off32(0x89, 0x85, tcc_off);         /* mov dword ptr [rbp - tcc_off], eax */
 469
 470         /* prog = array->ptrs[index]; */
 471         EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6,       /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
 472                     offsetof(struct bpf_array, ptrs));
 473
 474         /*
 475          * if (prog == NULL)
 476          *      goto out;
 477          */
 478         EMIT3(0x48, 0x85, 0xC9);                  /* test rcx,rcx */
 479 #define OFFSET3 (off3 + RETPOLINE_RCX_BPF_JIT_SIZE)
 480         EMIT2(X86_JE, OFFSET3);                   /* je out */
 481
 482         *pprog = prog;
 483         pop_callee_regs(pprog, callee_regs_used);
 484         prog = *pprog;
 485
 486         EMIT1(0x58);                              /* pop rax */
 487         if (stack_depth)
 488                 EMIT3_off32(0x48, 0x81, 0xC4,     /* add rsp, sd */
 489                             round_up(stack_depth, 8));
 490
 491         /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
 492         EMIT4(0x48, 0x8B, 0x49,                   /* mov rcx, qword ptr [rcx + 32] */
 493               offsetof(struct bpf_prog, bpf_func));
 494         EMIT4(0x48, 0x83, 0xC1,                   /* add rcx, X86_TAIL_CALL_OFFSET */
 495               X86_TAIL_CALL_OFFSET);
 496         /*
 497          * Now we're ready to jump into next BPF program
 498          * rdi == ctx (1st arg)
 499          * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
 500          */
 501         RETPOLINE_RCX_BPF_JIT();
 502
 503         /* out: */
 504         *pprog = prog;
 505 }
 506
 507 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
 508                                       u8 **pprog, int addr, u8 *image,
 509                                       bool *callee_regs_used, u32 stack_depth)
 510 {
 511         int tcc_off = -4 - round_up(stack_depth, 8);
 512         u8 *prog = *pprog;
 513         int pop_bytes = 0;
 514         int off1 = 20;
 515         int poke_off;
 516         int cnt = 0;
 517
 518         /* count the additional bytes used for popping callee regs to stack
 519          * that need to be taken into account for jump offset that is used for
 520          * bailing out from of the tail call when limit is reached
 521          */
 522         pop_bytes = get_pop_bytes(callee_regs_used);
 523         off1 += pop_bytes;
 524
 525         /*
 526          * total bytes for:
 527          * - nop5/ jmpq $off
 528          * - pop callee regs
 529          * - sub rsp, $val if depth > 0
 530          * - pop rax
 531          */
 532         poke_off = X86_PATCH_SIZE + pop_bytes + 1;
 533         if (stack_depth) {
 534                 poke_off += 7;
 535                 off1 += 7;
 536         }
 537
 538         /*
 539          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
 540          *      goto out;
 541          */
 542         EMIT2_off32(0x8B, 0x85, tcc_off);             /* mov eax, dword ptr [rbp - tcc_off] */
 543         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);         /* cmp eax, MAX_TAIL_CALL_CNT */
 544         EMIT2(X86_JA, off1);                          /* ja out */
 545         EMIT3(0x83, 0xC0, 0x01);                      /* add eax, 1 */
 546         EMIT2_off32(0x89, 0x85, tcc_off);             /* mov dword ptr [rbp - tcc_off], eax */
 547
 548         poke->tailcall_bypass = image + (addr - poke_off - X86_PATCH_SIZE);
 549         poke->adj_off = X86_TAIL_CALL_OFFSET;
 550         poke->tailcall_target = image + (addr - X86_PATCH_SIZE);
 551         poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
 552
 553         emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
 554                   poke->tailcall_bypass);
 555
 556         *pprog = prog;
 557         pop_callee_regs(pprog, callee_regs_used);
 558         prog = *pprog;
 559         EMIT1(0x58);                                  /* pop rax */
 560         if (stack_depth)
 561                 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
 562
 563         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 564         prog += X86_PATCH_SIZE;
 565         /* out: */
 566
 567         *pprog = prog;
 568 }
 569
 570 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
 571 {
 572         struct bpf_jit_poke_descriptor *poke;
 573         struct bpf_array *array;
 574         struct bpf_prog *target;
 575         int i, ret;
 576
 577         for (i = 0; i < prog->aux->size_poke_tab; i++) {
 578                 poke = &prog->aux->poke_tab[i];
 579                 if (poke->aux && poke->aux != prog->aux)
 580                         continue;
 581
 582                 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
 583
 584                 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
 585                         continue;
 586
 587                 array = container_of(poke->tail_call.map, struct bpf_array, map);
 588                 mutex_lock(&array->aux->poke_mutex);
 589                 target = array->ptrs[poke->tail_call.key];
 590                 if (target) {
 591                         /* Plain memcpy is used when image is not live yet
 592                          * and still not locked as read-only. Once poke
 593                          * location is active (poke->tailcall_target_stable),
 594                          * any parallel bpf_arch_text_poke() might occur
 595                          * still on the read-write image until we finally
 596                          * locked it as read-only. Both modifications on
 597                          * the given image are under text_mutex to avoid
 598                          * interference.
 599                          */
 600                         ret = __bpf_arch_text_poke(poke->tailcall_target,
 601                                                    BPF_MOD_JUMP, NULL,
 602                                                    (u8 *)target->bpf_func +
 603                                                    poke->adj_off, false);
 604                         BUG_ON(ret < 0);
 605                         ret = __bpf_arch_text_poke(poke->tailcall_bypass,
 606                                                    BPF_MOD_JUMP,
 607                                                    (u8 *)poke->tailcall_target +
 608                                                    X86_PATCH_SIZE, NULL, false);
 609                         BUG_ON(ret < 0);
 610                 }
 611                 WRITE_ONCE(poke->tailcall_target_stable, true);
 612                 mutex_unlock(&array->aux->poke_mutex);
 613         }
 614 }
 615
 616 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
 617                            u32 dst_reg, const u32 imm32)
 618 {
 619         u8 *prog = *pprog;
 620         u8 b1, b2, b3;
 621         int cnt = 0;
 622
 623         /*
 624          * Optimization: if imm32 is positive, use 'mov %eax, imm32'
 625          * (which zero-extends imm32) to save 2 bytes.
 626          */
 627         if (sign_propagate && (s32)imm32 < 0) {
 628                 /* 'mov %rax, imm32' sign extends imm32 */
 629                 b1 = add_1mod(0x48, dst_reg);
 630                 b2 = 0xC7;
 631                 b3 = 0xC0;
 632                 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
 633                 goto done;
 634         }
 635
 636         /*
 637          * Optimization: if imm32 is zero, use 'xor %eax, %eax'
 638          * to save 3 bytes.
 639          */
 640         if (imm32 == 0) {
 641                 if (is_ereg(dst_reg))
 642                         EMIT1(add_2mod(0x40, dst_reg, dst_reg));
 643                 b2 = 0x31; /* xor */
 644                 b3 = 0xC0;
 645                 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
 646                 goto done;
 647         }
 648
 649         /* mov %eax, imm32 */
 650         if (is_ereg(dst_reg))
 651                 EMIT1(add_1mod(0x40, dst_reg));
 652         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
 653 done:
 654         *pprog = prog;
 655 }
 656
 657 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
 658                            const u32 imm32_hi, const u32 imm32_lo)
 659 {
 660         u8 *prog = *pprog;
 661         int cnt = 0;
 662
 663         if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
 664                 /*
 665                  * For emitting plain u32, where sign bit must not be
 666                  * propagated LLVM tends to load imm64 over mov32
 667                  * directly, so save couple of bytes by just doing
 668                  * 'mov %eax, imm32' instead.
 669                  */
 670                 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
 671         } else {
 672                 /* movabsq %rax, imm64 */
 673                 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
 674                 EMIT(imm32_lo, 4);
 675                 EMIT(imm32_hi, 4);
 676         }
 677
 678         *pprog = prog;
 679 }
 680
 681 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
 682 {
 683         u8 *prog = *pprog;
 684         int cnt = 0;
 685
 686         if (is64) {
 687                 /* mov dst, src */
 688                 EMIT_mov(dst_reg, src_reg);
 689         } else {
 690                 /* mov32 dst, src */
 691                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 692                         EMIT1(add_2mod(0x40, dst_reg, src_reg));
 693                 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
 694         }
 695
 696         *pprog = prog;
 697 }
 698
 699 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
 700 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
 701 {
 702         u8 *prog = *pprog;
 703         int cnt = 0;
 704
 705         if (is_imm8(off)) {
 706                 /* 1-byte signed displacement.
 707                  *
 708                  * If off == 0 we could skip this and save one extra byte, but
 709                  * special case of x86 R13 which always needs an offset is not
 710                  * worth the hassle
 711                  */
 712                 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
 713         } else {
 714                 /* 4-byte signed displacement */
 715                 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
 716         }
 717         *pprog = prog;
 718 }
 719
 720 /*
 721  * Emit a REX byte if it will be necessary to address these registers
 722  */
 723 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
 724 {
 725         u8 *prog = *pprog;
 726         int cnt = 0;
 727
 728         if (is64)
 729                 EMIT1(add_2mod(0x48, dst_reg, src_reg));
 730         else if (is_ereg(dst_reg) || is_ereg(src_reg))
 731                 EMIT1(add_2mod(0x40, dst_reg, src_reg));
 732         *pprog = prog;
 733 }
 734
 735 /* LDX: dst_reg = *(u8*)(src_reg + off) */
 736 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 737 {
 738         u8 *prog = *pprog;
 739         int cnt = 0;
 740
 741         switch (size) {
 742         case BPF_B:
 743                 /* Emit 'movzx rax, byte ptr [rax + off]' */
 744                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
 745                 break;
 746         case BPF_H:
 747                 /* Emit 'movzx rax, word ptr [rax + off]' */
 748                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
 749                 break;
 750         case BPF_W:
 751                 /* Emit 'mov eax, dword ptr [rax+0x14]' */
 752                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 753                         EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
 754                 else
 755                         EMIT1(0x8B);
 756                 break;
 757         case BPF_DW:
 758                 /* Emit 'mov rax, qword ptr [rax+0x14]' */
 759                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
 760                 break;
 761         }
 762         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 763         *pprog = prog;
 764 }
 765
 766 /* STX: *(u8*)(dst_reg + off) = src_reg */
 767 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 768 {
 769         u8 *prog = *pprog;
 770         int cnt = 0;
 771
 772         switch (size) {
 773         case BPF_B:
 774                 /* Emit 'mov byte ptr [rax + off], al' */
 775                 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
 776                         /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
 777                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
 778                 else
 779                         EMIT1(0x88);
 780                 break;
 781         case BPF_H:
 782                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 783                         EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
 784                 else
 785                         EMIT2(0x66, 0x89);
 786                 break;
 787         case BPF_W:
 788                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 789                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
 790                 else
 791                         EMIT1(0x89);
 792                 break;
 793         case BPF_DW:
 794                 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
 795                 break;
 796         }
 797         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 798         *pprog = prog;
 799 }
 800
 801 static int emit_atomic(u8 **pprog, u8 atomic_op,
 802                        u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
 803 {
 804         u8 *prog = *pprog;
 805         int cnt = 0;
 806
 807         EMIT1(0xF0); /* lock prefix */
 808
 809         maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
 810
 811         /* emit opcode */
 812         switch (atomic_op) {
 813         case BPF_ADD:
 814         case BPF_SUB:
 815         case BPF_AND:
 816         case BPF_OR:
 817         case BPF_XOR:
 818                 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
 819                 EMIT1(simple_alu_opcodes[atomic_op]);
 820                 break;
 821         case BPF_ADD | BPF_FETCH:
 822                 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
 823                 EMIT2(0x0F, 0xC1);
 824                 break;
 825         case BPF_XCHG:
 826                 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
 827                 EMIT1(0x87);
 828                 break;
 829         case BPF_CMPXCHG:
 830                 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
 831                 EMIT2(0x0F, 0xB1);
 832                 break;
 833         default:
 834                 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
 835                 return -EFAULT;
 836         }
 837
 838         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 839
 840         *pprog = prog;
 841         return 0;
 842 }
 843
 844 static bool ex_handler_bpf(const struct exception_table_entry *x,
 845                            struct pt_regs *regs, int trapnr,
 846                            unsigned long error_code, unsigned long fault_addr)
 847 {
 848         u32 reg = x->fixup >> 8;
 849
 850         /* jump over faulting load and clear dest register */
 851         *(unsigned long *)((void *)regs + reg) = 0;
 852         regs->ip += x->fixup & 0xff;
 853         return true;
 854 }
 855
 856 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
 857                              bool *regs_used, bool *tail_call_seen)
 858 {
 859         int i;
 860
 861         for (i = 1; i <= insn_cnt; i++, insn++) {
 862                 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
 863                         *tail_call_seen = true;
 864                 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
 865                         regs_used[0] = true;
 866                 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
 867                         regs_used[1] = true;
 868                 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
 869                         regs_used[2] = true;
 870                 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
 871                         regs_used[3] = true;
 872         }
 873 }
 874
 875 static int emit_nops(u8 **pprog, int len)
 876 {
 877         u8 *prog = *pprog;
 878         int i, noplen, cnt = 0;
 879
 880         while (len > 0) {
 881                 noplen = len;
 882
 883                 if (noplen > ASM_NOP_MAX)
 884                         noplen = ASM_NOP_MAX;
 885
 886                 for (i = 0; i < noplen; i++)
 887                         EMIT1(x86_nops[noplen][i]);
 888                 len -= noplen;
 889         }
 890
 891         *pprog = prog;
 892
 893         return cnt;
 894 }
 895
 896 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
 897
 898 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
 899                   int oldproglen, struct jit_context *ctx, bool jmp_padding)
 900 {
 901         bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
 902         struct bpf_insn *insn = bpf_prog->insnsi;
 903         bool callee_regs_used[4] = {};
 904         int insn_cnt = bpf_prog->len;
 905         bool tail_call_seen = false;
 906         bool seen_exit = false;
 907         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
 908         int i, cnt = 0, excnt = 0;
 909         int ilen, proglen = 0;
 910         u8 *prog = temp;
 911         int err;
 912
 913         detect_reg_usage(insn, insn_cnt, callee_regs_used,
 914                          &tail_call_seen);
 915
 916         /* tail call's presence in current prog implies it is reachable */
 917         tail_call_reachable |= tail_call_seen;
 918
 919         emit_prologue(&prog, bpf_prog->aux->stack_depth,
 920                       bpf_prog_was_classic(bpf_prog), tail_call_reachable,
 921                       bpf_prog->aux->func_idx != 0);
 922         push_callee_regs(&prog, callee_regs_used);
 923
 924         ilen = prog - temp;
 925         if (image)
 926                 memcpy(image + proglen, temp, ilen);
 927         proglen += ilen;
 928         addrs[0] = proglen;
 929         prog = temp;
 930
 931         for (i = 1; i <= insn_cnt; i++, insn++) {
 932                 const s32 imm32 = insn->imm;
 933                 u32 dst_reg = insn->dst_reg;
 934                 u32 src_reg = insn->src_reg;
 935                 u8 b2 = 0, b3 = 0;
 936                 u8 *start_of_ldx;
 937                 s64 jmp_offset;
 938                 u8 jmp_cond;
 939                 u8 *func;
 940                 int nops;
 941
 942                 switch (insn->code) {
 943                         /* ALU */
 944                 case BPF_ALU | BPF_ADD | BPF_X:
 945                 case BPF_ALU | BPF_SUB | BPF_X:
 946                 case BPF_ALU | BPF_AND | BPF_X:
 947                 case BPF_ALU | BPF_OR | BPF_X:
 948                 case BPF_ALU | BPF_XOR | BPF_X:
 949                 case BPF_ALU64 | BPF_ADD | BPF_X:
 950                 case BPF_ALU64 | BPF_SUB | BPF_X:
 951                 case BPF_ALU64 | BPF_AND | BPF_X:
 952                 case BPF_ALU64 | BPF_OR | BPF_X:
 953                 case BPF_ALU64 | BPF_XOR | BPF_X:
 954                         maybe_emit_mod(&prog, dst_reg, src_reg,
 955                                        BPF_CLASS(insn->code) == BPF_ALU64);
 956                         b2 = simple_alu_opcodes[BPF_OP(insn->code)];
 957                         EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
 958                         break;
 959
 960                 case BPF_ALU64 | BPF_MOV | BPF_X:
 961                 case BPF_ALU | BPF_MOV | BPF_X:
 962                         emit_mov_reg(&prog,
 963                                      BPF_CLASS(insn->code) == BPF_ALU64,
 964                                      dst_reg, src_reg);
 965                         break;
 966
 967                         /* neg dst */
 968                 case BPF_ALU | BPF_NEG:
 969                 case BPF_ALU64 | BPF_NEG:
 970                         if (BPF_CLASS(insn->code) == BPF_ALU64)
 971                                 EMIT1(add_1mod(0x48, dst_reg));
 972                         else if (is_ereg(dst_reg))
 973                                 EMIT1(add_1mod(0x40, dst_reg));
 974                         EMIT2(0xF7, add_1reg(0xD8, dst_reg));
 975                         break;
 976
 977                 case BPF_ALU | BPF_ADD | BPF_K:
 978                 case BPF_ALU | BPF_SUB | BPF_K:
 979                 case BPF_ALU | BPF_AND | BPF_K:
 980                 case BPF_ALU | BPF_OR | BPF_K:
 981                 case BPF_ALU | BPF_XOR | BPF_K:
 982                 case BPF_ALU64 | BPF_ADD | BPF_K:
 983                 case BPF_ALU64 | BPF_SUB | BPF_K:
 984                 case BPF_ALU64 | BPF_AND | BPF_K:
 985                 case BPF_ALU64 | BPF_OR | BPF_K:
 986                 case BPF_ALU64 | BPF_XOR | BPF_K:
 987                         if (BPF_CLASS(insn->code) == BPF_ALU64)
 988                                 EMIT1(add_1mod(0x48, dst_reg));
 989                         else if (is_ereg(dst_reg))
 990                                 EMIT1(add_1mod(0x40, dst_reg));
 991
 992                         /*
 993                          * b3 holds 'normal' opcode, b2 short form only valid
 994                          * in case dst is eax/rax.
 995                          */
 996                         switch (BPF_OP(insn->code)) {
 997                         case BPF_ADD:
 998                                 b3 = 0xC0;
 999                                 b2 = 0x05;
1000                                 break;
1001                         case BPF_SUB:
1002                                 b3 = 0xE8;
1003                                 b2 = 0x2D;
1004                                 break;
1005                         case BPF_AND:
1006                                 b3 = 0xE0;
1007                                 b2 = 0x25;
1008                                 break;
1009                         case BPF_OR:
1010                                 b3 = 0xC8;
1011                                 b2 = 0x0D;
1012                                 break;
1013                         case BPF_XOR:
1014                                 b3 = 0xF0;
1015                                 b2 = 0x35;
1016                                 break;
1017                         }
1018
1019                         if (is_imm8(imm32))
1020                                 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1021                         else if (is_axreg(dst_reg))
1022                                 EMIT1_off32(b2, imm32);
1023                         else
1024                                 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1025                         break;
1026
1027                 case BPF_ALU64 | BPF_MOV | BPF_K:
1028                 case BPF_ALU | BPF_MOV | BPF_K:
1029                         emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1030                                        dst_reg, imm32);
1031                         break;
1032
1033                 case BPF_LD | BPF_IMM | BPF_DW:
1034                         emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1035                         insn++;
1036                         i++;
1037                         break;
1038
1039                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1040                 case BPF_ALU | BPF_MOD | BPF_X:
1041                 case BPF_ALU | BPF_DIV | BPF_X:
1042                 case BPF_ALU | BPF_MOD | BPF_K:
1043                 case BPF_ALU | BPF_DIV | BPF_K:
1044                 case BPF_ALU64 | BPF_MOD | BPF_X:
1045                 case BPF_ALU64 | BPF_DIV | BPF_X:
1046                 case BPF_ALU64 | BPF_MOD | BPF_K:
1047                 case BPF_ALU64 | BPF_DIV | BPF_K:
1048                         EMIT1(0x50); /* push rax */
1049                         EMIT1(0x52); /* push rdx */
1050
1051                         if (BPF_SRC(insn->code) == BPF_X)
1052                                 /* mov r11, src_reg */
1053                                 EMIT_mov(AUX_REG, src_reg);
1054                         else
1055                                 /* mov r11, imm32 */
1056                                 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1057
1058                         /* mov rax, dst_reg */
1059                         EMIT_mov(BPF_REG_0, dst_reg);
1060
1061                         /*
1062                          * xor edx, edx
1063                          * equivalent to 'xor rdx, rdx', but one byte less
1064                          */
1065                         EMIT2(0x31, 0xd2);
1066
1067                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1068                                 /* div r11 */
1069                                 EMIT3(0x49, 0xF7, 0xF3);
1070                         else
1071                                 /* div r11d */
1072                                 EMIT3(0x41, 0xF7, 0xF3);
1073
1074                         if (BPF_OP(insn->code) == BPF_MOD)
1075                                 /* mov r11, rdx */
1076                                 EMIT3(0x49, 0x89, 0xD3);
1077                         else
1078                                 /* mov r11, rax */
1079                                 EMIT3(0x49, 0x89, 0xC3);
1080
1081                         EMIT1(0x5A); /* pop rdx */
1082                         EMIT1(0x58); /* pop rax */
1083
1084                         /* mov dst_reg, r11 */
1085                         EMIT_mov(dst_reg, AUX_REG);
1086                         break;
1087
1088                 case BPF_ALU | BPF_MUL | BPF_K:
1089                 case BPF_ALU | BPF_MUL | BPF_X:
1090                 case BPF_ALU64 | BPF_MUL | BPF_K:
1091                 case BPF_ALU64 | BPF_MUL | BPF_X:
1092                 {
1093                         bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1094
1095                         if (dst_reg != BPF_REG_0)
1096                                 EMIT1(0x50); /* push rax */
1097                         if (dst_reg != BPF_REG_3)
1098                                 EMIT1(0x52); /* push rdx */
1099
1100                         /* mov r11, dst_reg */
1101                         EMIT_mov(AUX_REG, dst_reg);
1102
1103                         if (BPF_SRC(insn->code) == BPF_X)
1104                                 emit_mov_reg(&prog, is64, BPF_REG_0, src_reg);
1105                         else
1106                                 emit_mov_imm32(&prog, is64, BPF_REG_0, imm32);
1107
1108                         if (is64)
1109                                 EMIT1(add_1mod(0x48, AUX_REG));
1110                         else if (is_ereg(AUX_REG))
1111                                 EMIT1(add_1mod(0x40, AUX_REG));
1112                         /* mul(q) r11 */
1113                         EMIT2(0xF7, add_1reg(0xE0, AUX_REG));
1114
1115                         if (dst_reg != BPF_REG_3)
1116                                 EMIT1(0x5A); /* pop rdx */
1117                         if (dst_reg != BPF_REG_0) {
1118                                 /* mov dst_reg, rax */
1119                                 EMIT_mov(dst_reg, BPF_REG_0);
1120                                 EMIT1(0x58); /* pop rax */
1121                         }
1122                         break;
1123                 }
1124                         /* Shifts */
1125                 case BPF_ALU | BPF_LSH | BPF_K:
1126                 case BPF_ALU | BPF_RSH | BPF_K:
1127                 case BPF_ALU | BPF_ARSH | BPF_K:
1128                 case BPF_ALU64 | BPF_LSH | BPF_K:
1129                 case BPF_ALU64 | BPF_RSH | BPF_K:
1130                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1131                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1132                                 EMIT1(add_1mod(0x48, dst_reg));
1133                         else if (is_ereg(dst_reg))
1134                                 EMIT1(add_1mod(0x40, dst_reg));
1135
1136                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1137                         if (imm32 == 1)
1138                                 EMIT2(0xD1, add_1reg(b3, dst_reg));
1139                         else
1140                                 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1141                         break;
1142
1143                 case BPF_ALU | BPF_LSH | BPF_X:
1144                 case BPF_ALU | BPF_RSH | BPF_X:
1145                 case BPF_ALU | BPF_ARSH | BPF_X:
1146                 case BPF_ALU64 | BPF_LSH | BPF_X:
1147                 case BPF_ALU64 | BPF_RSH | BPF_X:
1148                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1149
1150                         /* Check for bad case when dst_reg == rcx */
1151                         if (dst_reg == BPF_REG_4) {
1152                                 /* mov r11, dst_reg */
1153                                 EMIT_mov(AUX_REG, dst_reg);
1154                                 dst_reg = AUX_REG;
1155                         }
1156
1157                         if (src_reg != BPF_REG_4) { /* common case */
1158                                 EMIT1(0x51); /* push rcx */
1159
1160                                 /* mov rcx, src_reg */
1161                                 EMIT_mov(BPF_REG_4, src_reg);
1162                         }
1163
1164                         /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1165                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1166                                 EMIT1(add_1mod(0x48, dst_reg));
1167                         else if (is_ereg(dst_reg))
1168                                 EMIT1(add_1mod(0x40, dst_reg));
1169
1170                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1171                         EMIT2(0xD3, add_1reg(b3, dst_reg));
1172
1173                         if (src_reg != BPF_REG_4)
1174                                 EMIT1(0x59); /* pop rcx */
1175
1176                         if (insn->dst_reg == BPF_REG_4)
1177                                 /* mov dst_reg, r11 */
1178                                 EMIT_mov(insn->dst_reg, AUX_REG);
1179                         break;
1180
1181                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1182                         switch (imm32) {
1183                         case 16:
1184                                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1185                                 EMIT1(0x66);
1186                                 if (is_ereg(dst_reg))
1187                                         EMIT1(0x41);
1188                                 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1189
1190                                 /* Emit 'movzwl eax, ax' */
1191                                 if (is_ereg(dst_reg))
1192                                         EMIT3(0x45, 0x0F, 0xB7);
1193                                 else
1194                                         EMIT2(0x0F, 0xB7);
1195                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1196                                 break;
1197                         case 32:
1198                                 /* Emit 'bswap eax' to swap lower 4 bytes */
1199                                 if (is_ereg(dst_reg))
1200                                         EMIT2(0x41, 0x0F);
1201                                 else
1202                                         EMIT1(0x0F);
1203                                 EMIT1(add_1reg(0xC8, dst_reg));
1204                                 break;
1205                         case 64:
1206                                 /* Emit 'bswap rax' to swap 8 bytes */
1207                                 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1208                                       add_1reg(0xC8, dst_reg));
1209                                 break;
1210                         }
1211                         break;
1212
1213                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1214                         switch (imm32) {
1215                         case 16:
1216                                 /*
1217                                  * Emit 'movzwl eax, ax' to zero extend 16-bit
1218                                  * into 64 bit
1219                                  */
1220                                 if (is_ereg(dst_reg))
1221                                         EMIT3(0x45, 0x0F, 0xB7);
1222                                 else
1223                                         EMIT2(0x0F, 0xB7);
1224                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1225                                 break;
1226                         case 32:
1227                                 /* Emit 'mov eax, eax' to clear upper 32-bits */
1228                                 if (is_ereg(dst_reg))
1229                                         EMIT1(0x45);
1230                                 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1231                                 break;
1232                         case 64:
1233                                 /* nop */
1234                                 break;
1235                         }
1236                         break;
1237
1238                         /* speculation barrier */
1239                 case BPF_ST | BPF_NOSPEC:
1240                         if (boot_cpu_has(X86_FEATURE_XMM2))
1241                                 /* Emit 'lfence' */
1242                                 EMIT3(0x0F, 0xAE, 0xE8);
1243                         break;
1244
1245                         /* ST: *(u8*)(dst_reg + off) = imm */
1246                 case BPF_ST | BPF_MEM | BPF_B:
1247                         if (is_ereg(dst_reg))
1248                                 EMIT2(0x41, 0xC6);
1249                         else
1250                                 EMIT1(0xC6);
1251                         goto st;
1252                 case BPF_ST | BPF_MEM | BPF_H:
1253                         if (is_ereg(dst_reg))
1254                                 EMIT3(0x66, 0x41, 0xC7);
1255                         else
1256                                 EMIT2(0x66, 0xC7);
1257                         goto st;
1258                 case BPF_ST | BPF_MEM | BPF_W:
1259                         if (is_ereg(dst_reg))
1260                                 EMIT2(0x41, 0xC7);
1261                         else
1262                                 EMIT1(0xC7);
1263                         goto st;
1264                 case BPF_ST | BPF_MEM | BPF_DW:
1265                         EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1266
1267 st:                     if (is_imm8(insn->off))
1268                                 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1269                         else
1270                                 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1271
1272                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1273                         break;
1274
1275                         /* STX: *(u8*)(dst_reg + off) = src_reg */
1276                 case BPF_STX | BPF_MEM | BPF_B:
1277                 case BPF_STX | BPF_MEM | BPF_H:
1278                 case BPF_STX | BPF_MEM | BPF_W:
1279                 case BPF_STX | BPF_MEM | BPF_DW:
1280                         emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1281                         break;
1282
1283                         /* LDX: dst_reg = *(u8*)(src_reg + off) */
1284                 case BPF_LDX | BPF_MEM | BPF_B:
1285                 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1286                 case BPF_LDX | BPF_MEM | BPF_H:
1287                 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1288                 case BPF_LDX | BPF_MEM | BPF_W:
1289                 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1290                 case BPF_LDX | BPF_MEM | BPF_DW:
1291                 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1292                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1293                                 /* test src_reg, src_reg */
1294                                 maybe_emit_mod(&prog, src_reg, src_reg, true); /* always 1 byte */
1295                                 EMIT2(0x85, add_2reg(0xC0, src_reg, src_reg));
1296                                 /* jne start_of_ldx */
1297                                 EMIT2(X86_JNE, 0);
1298                                 /* xor dst_reg, dst_reg */
1299                                 emit_mov_imm32(&prog, false, dst_reg, 0);
1300                                 /* jmp byte_after_ldx */
1301                                 EMIT2(0xEB, 0);
1302
1303                                 /* populate jmp_offset for JNE above */
1304                                 temp[4] = prog - temp - 5 /* sizeof(test + jne) */;
1305                                 start_of_ldx = prog;
1306                         }
1307                         emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1308                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1309                                 struct exception_table_entry *ex;
1310                                 u8 *_insn = image + proglen + (start_of_ldx - temp);
1311                                 s64 delta;
1312
1313                                 /* populate jmp_offset for JMP above */
1314                                 start_of_ldx[-1] = prog - start_of_ldx;
1315
1316                                 if (!bpf_prog->aux->extable)
1317                                         break;
1318
1319                                 if (excnt >= bpf_prog->aux->num_exentries) {
1320                                         pr_err("ex gen bug\n");
1321                                         return -EFAULT;
1322                                 }
1323                                 ex = &bpf_prog->aux->extable[excnt++];
1324
1325                                 delta = _insn - (u8 *)&ex->insn;
1326                                 if (!is_simm32(delta)) {
1327                                         pr_err("extable->insn doesn't fit into 32-bit\n");
1328                                         return -EFAULT;
1329                                 }
1330                                 ex->insn = delta;
1331
1332                                 delta = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
1333                                 if (!is_simm32(delta)) {
1334                                         pr_err("extable->handler doesn't fit into 32-bit\n");
1335                                         return -EFAULT;
1336                                 }
1337                                 ex->handler = delta;
1338
1339                                 if (dst_reg > BPF_REG_9) {
1340                                         pr_err("verifier error\n");
1341                                         return -EFAULT;
1342                                 }
1343                                 /*
1344                                  * Compute size of x86 insn and its target dest x86 register.
1345                                  * ex_handler_bpf() will use lower 8 bits to adjust
1346                                  * pt_regs->ip to jump over this x86 instruction
1347                                  * and upper bits to figure out which pt_regs to zero out.
1348                                  * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1349                                  * of 4 bytes will be ignored and rbx will be zero inited.
1350                                  */
1351                                 ex->fixup = (prog - temp) | (reg2pt_regs[dst_reg] << 8);
1352                         }
1353                         break;
1354
1355                 case BPF_STX | BPF_ATOMIC | BPF_W:
1356                 case BPF_STX | BPF_ATOMIC | BPF_DW:
1357                         if (insn->imm == (BPF_AND | BPF_FETCH) ||
1358                             insn->imm == (BPF_OR | BPF_FETCH) ||
1359                             insn->imm == (BPF_XOR | BPF_FETCH)) {
1360                                 u8 *branch_target;
1361                                 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1362                                 u32 real_src_reg = src_reg;
1363
1364                                 /*
1365                                  * Can't be implemented with a single x86 insn.
1366                                  * Need to do a CMPXCHG loop.
1367                                  */
1368
1369                                 /* Will need RAX as a CMPXCHG operand so save R0 */
1370                                 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1371                                 if (src_reg == BPF_REG_0)
1372                                         real_src_reg = BPF_REG_AX;
1373
1374                                 branch_target = prog;
1375                                 /* Load old value */
1376                                 emit_ldx(&prog, BPF_SIZE(insn->code),
1377                                          BPF_REG_0, dst_reg, insn->off);
1378                                 /*
1379                                  * Perform the (commutative) operation locally,
1380                                  * put the result in the AUX_REG.
1381                                  */
1382                                 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1383                                 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1384                                 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1385                                       add_2reg(0xC0, AUX_REG, real_src_reg));
1386                                 /* Attempt to swap in new value */
1387                                 err = emit_atomic(&prog, BPF_CMPXCHG,
1388                                                   dst_reg, AUX_REG, insn->off,
1389                                                   BPF_SIZE(insn->code));
1390                                 if (WARN_ON(err))
1391                                         return err;
1392                                 /*
1393                                  * ZF tells us whether we won the race. If it's
1394                                  * cleared we need to try again.
1395                                  */
1396                                 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1397                                 /* Return the pre-modification value */
1398                                 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1399                                 /* Restore R0 after clobbering RAX */
1400                                 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1401                                 break;
1402
1403                         }
1404
1405                         err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1406                                                   insn->off, BPF_SIZE(insn->code));
1407                         if (err)
1408                                 return err;
1409                         break;
1410
1411                         /* call */
1412                 case BPF_JMP | BPF_CALL:
1413                         func = (u8 *) __bpf_call_base + imm32;
1414                         if (tail_call_reachable) {
1415                                 EMIT3_off32(0x48, 0x8B, 0x85,
1416                                             -(bpf_prog->aux->stack_depth + 8));
1417                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
1418                                         return -EINVAL;
1419                         } else {
1420                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1]))
1421                                         return -EINVAL;
1422                         }
1423                         break;
1424
1425                 case BPF_JMP | BPF_TAIL_CALL:
1426                         if (imm32)
1427                                 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1428                                                           &prog, addrs[i], image,
1429                                                           callee_regs_used,
1430                                                           bpf_prog->aux->stack_depth);
1431                         else
1432                                 emit_bpf_tail_call_indirect(&prog,
1433                                                             callee_regs_used,
1434                                                             bpf_prog->aux->stack_depth);
1435                         break;
1436
1437                         /* cond jump */
1438                 case BPF_JMP | BPF_JEQ | BPF_X:
1439                 case BPF_JMP | BPF_JNE | BPF_X:
1440                 case BPF_JMP | BPF_JGT | BPF_X:
1441                 case BPF_JMP | BPF_JLT | BPF_X:
1442                 case BPF_JMP | BPF_JGE | BPF_X:
1443                 case BPF_JMP | BPF_JLE | BPF_X:
1444                 case BPF_JMP | BPF_JSGT | BPF_X:
1445                 case BPF_JMP | BPF_JSLT | BPF_X:
1446                 case BPF_JMP | BPF_JSGE | BPF_X:
1447                 case BPF_JMP | BPF_JSLE | BPF_X:
1448                 case BPF_JMP32 | BPF_JEQ | BPF_X:
1449                 case BPF_JMP32 | BPF_JNE | BPF_X:
1450                 case BPF_JMP32 | BPF_JGT | BPF_X:
1451                 case BPF_JMP32 | BPF_JLT | BPF_X:
1452                 case BPF_JMP32 | BPF_JGE | BPF_X:
1453                 case BPF_JMP32 | BPF_JLE | BPF_X:
1454                 case BPF_JMP32 | BPF_JSGT | BPF_X:
1455                 case BPF_JMP32 | BPF_JSLT | BPF_X:
1456                 case BPF_JMP32 | BPF_JSGE | BPF_X:
1457                 case BPF_JMP32 | BPF_JSLE | BPF_X:
1458                         /* cmp dst_reg, src_reg */
1459                         maybe_emit_mod(&prog, dst_reg, src_reg,
1460                                        BPF_CLASS(insn->code) == BPF_JMP);
1461                         EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1462                         goto emit_cond_jmp;
1463
1464                 case BPF_JMP | BPF_JSET | BPF_X:
1465                 case BPF_JMP32 | BPF_JSET | BPF_X:
1466                         /* test dst_reg, src_reg */
1467                         maybe_emit_mod(&prog, dst_reg, src_reg,
1468                                        BPF_CLASS(insn->code) == BPF_JMP);
1469                         EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1470                         goto emit_cond_jmp;
1471
1472                 case BPF_JMP | BPF_JSET | BPF_K:
1473                 case BPF_JMP32 | BPF_JSET | BPF_K:
1474                         /* test dst_reg, imm32 */
1475                         if (BPF_CLASS(insn->code) == BPF_JMP)
1476                                 EMIT1(add_1mod(0x48, dst_reg));
1477                         else if (is_ereg(dst_reg))
1478                                 EMIT1(add_1mod(0x40, dst_reg));
1479                         EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1480                         goto emit_cond_jmp;
1481
1482                 case BPF_JMP | BPF_JEQ | BPF_K:
1483                 case BPF_JMP | BPF_JNE | BPF_K:
1484                 case BPF_JMP | BPF_JGT | BPF_K:
1485                 case BPF_JMP | BPF_JLT | BPF_K:
1486                 case BPF_JMP | BPF_JGE | BPF_K:
1487                 case BPF_JMP | BPF_JLE | BPF_K:
1488                 case BPF_JMP | BPF_JSGT | BPF_K:
1489                 case BPF_JMP | BPF_JSLT | BPF_K:
1490                 case BPF_JMP | BPF_JSGE | BPF_K:
1491                 case BPF_JMP | BPF_JSLE | BPF_K:
1492                 case BPF_JMP32 | BPF_JEQ | BPF_K:
1493                 case BPF_JMP32 | BPF_JNE | BPF_K:
1494                 case BPF_JMP32 | BPF_JGT | BPF_K:
1495                 case BPF_JMP32 | BPF_JLT | BPF_K:
1496                 case BPF_JMP32 | BPF_JGE | BPF_K:
1497                 case BPF_JMP32 | BPF_JLE | BPF_K:
1498                 case BPF_JMP32 | BPF_JSGT | BPF_K:
1499                 case BPF_JMP32 | BPF_JSLT | BPF_K:
1500                 case BPF_JMP32 | BPF_JSGE | BPF_K:
1501                 case BPF_JMP32 | BPF_JSLE | BPF_K:
1502                         /* test dst_reg, dst_reg to save one extra byte */
1503                         if (imm32 == 0) {
1504                                 maybe_emit_mod(&prog, dst_reg, dst_reg,
1505                                                BPF_CLASS(insn->code) == BPF_JMP);
1506                                 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1507                                 goto emit_cond_jmp;
1508                         }
1509
1510                         /* cmp dst_reg, imm8/32 */
1511                         if (BPF_CLASS(insn->code) == BPF_JMP)
1512                                 EMIT1(add_1mod(0x48, dst_reg));
1513                         else if (is_ereg(dst_reg))
1514                                 EMIT1(add_1mod(0x40, dst_reg));
1515
1516                         if (is_imm8(imm32))
1517                                 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1518                         else
1519                                 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1520
1521 emit_cond_jmp:          /* Convert BPF opcode to x86 */
1522                         switch (BPF_OP(insn->code)) {
1523                         case BPF_JEQ:
1524                                 jmp_cond = X86_JE;
1525                                 break;
1526                         case BPF_JSET:
1527                         case BPF_JNE:
1528                                 jmp_cond = X86_JNE;
1529                                 break;
1530                         case BPF_JGT:
1531                                 /* GT is unsigned '>', JA in x86 */
1532                                 jmp_cond = X86_JA;
1533                                 break;
1534                         case BPF_JLT:
1535                                 /* LT is unsigned '<', JB in x86 */
1536                                 jmp_cond = X86_JB;
1537                                 break;
1538                         case BPF_JGE:
1539                                 /* GE is unsigned '>=', JAE in x86 */
1540                                 jmp_cond = X86_JAE;
1541                                 break;
1542                         case BPF_JLE:
1543                                 /* LE is unsigned '<=', JBE in x86 */
1544                                 jmp_cond = X86_JBE;
1545                                 break;
1546                         case BPF_JSGT:
1547                                 /* Signed '>', GT in x86 */
1548                                 jmp_cond = X86_JG;
1549                                 break;
1550                         case BPF_JSLT:
1551                                 /* Signed '<', LT in x86 */
1552                                 jmp_cond = X86_JL;
1553                                 break;
1554                         case BPF_JSGE:
1555                                 /* Signed '>=', GE in x86 */
1556                                 jmp_cond = X86_JGE;
1557                                 break;
1558                         case BPF_JSLE:
1559                                 /* Signed '<=', LE in x86 */
1560                                 jmp_cond = X86_JLE;
1561                                 break;
1562                         default: /* to silence GCC warning */
1563                                 return -EFAULT;
1564                         }
1565                         jmp_offset = addrs[i + insn->off] - addrs[i];
1566                         if (is_imm8(jmp_offset)) {
1567                                 if (jmp_padding) {
1568                                         /* To keep the jmp_offset valid, the extra bytes are
1569                                          * padded before the jump insn, so we subtract the
1570                                          * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1571                                          *
1572                                          * If the previous pass already emits an imm8
1573                                          * jmp_cond, then this BPF insn won't shrink, so
1574                                          * "nops" is 0.
1575                                          *
1576                                          * On the other hand, if the previous pass emits an
1577                                          * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1578                                          * keep the image from shrinking further.
1579                                          *
1580                                          * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1581                                          *     is 2 bytes, so the size difference is 4 bytes.
1582                                          */
1583                                         nops = INSN_SZ_DIFF - 2;
1584                                         if (nops != 0 && nops != 4) {
1585                                                 pr_err("unexpected jmp_cond padding: %d bytes\n",
1586                                                        nops);
1587                                                 return -EFAULT;
1588                                         }
1589                                         cnt += emit_nops(&prog, nops);
1590                                 }
1591                                 EMIT2(jmp_cond, jmp_offset);
1592                         } else if (is_simm32(jmp_offset)) {
1593                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1594                         } else {
1595                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1596                                 return -EFAULT;
1597                         }
1598
1599                         break;
1600
1601                 case BPF_JMP | BPF_JA:
1602                         if (insn->off == -1)
1603                                 /* -1 jmp instructions will always jump
1604                                  * backwards two bytes. Explicitly handling
1605                                  * this case avoids wasting too many passes
1606                                  * when there are long sequences of replaced
1607                                  * dead code.
1608                                  */
1609                                 jmp_offset = -2;
1610                         else
1611                                 jmp_offset = addrs[i + insn->off] - addrs[i];
1612
1613                         if (!jmp_offset) {
1614                                 /*
1615                                  * If jmp_padding is enabled, the extra nops will
1616                                  * be inserted. Otherwise, optimize out nop jumps.
1617                                  */
1618                                 if (jmp_padding) {
1619                                         /* There are 3 possible conditions.
1620                                          * (1) This BPF_JA is already optimized out in
1621                                          *     the previous run, so there is no need
1622                                          *     to pad any extra byte (0 byte).
1623                                          * (2) The previous pass emits an imm8 jmp,
1624                                          *     so we pad 2 bytes to match the previous
1625                                          *     insn size.
1626                                          * (3) Similarly, the previous pass emits an
1627                                          *     imm32 jmp, and 5 bytes is padded.
1628                                          */
1629                                         nops = INSN_SZ_DIFF;
1630                                         if (nops != 0 && nops != 2 && nops != 5) {
1631                                                 pr_err("unexpected nop jump padding: %d bytes\n",
1632                                                        nops);
1633                                                 return -EFAULT;
1634                                         }
1635                                         cnt += emit_nops(&prog, nops);
1636                                 }
1637                                 break;
1638                         }
1639 emit_jmp:
1640                         if (is_imm8(jmp_offset)) {
1641                                 if (jmp_padding) {
1642                                         /* To avoid breaking jmp_offset, the extra bytes
1643                                          * are padded before the actual jmp insn, so
1644                                          * 2 bytes is subtracted from INSN_SZ_DIFF.
1645                                          *
1646                                          * If the previous pass already emits an imm8
1647                                          * jmp, there is nothing to pad (0 byte).
1648                                          *
1649                                          * If it emits an imm32 jmp (5 bytes) previously
1650                                          * and now an imm8 jmp (2 bytes), then we pad
1651                                          * (5 - 2 = 3) bytes to stop the image from
1652                                          * shrinking further.
1653                                          */
1654                                         nops = INSN_SZ_DIFF - 2;
1655                                         if (nops != 0 && nops != 3) {
1656                                                 pr_err("unexpected jump padding: %d bytes\n",
1657                                                        nops);
1658                                                 return -EFAULT;
1659                                         }
1660                                         cnt += emit_nops(&prog, INSN_SZ_DIFF - 2);
1661                                 }
1662                                 EMIT2(0xEB, jmp_offset);
1663                         } else if (is_simm32(jmp_offset)) {
1664                                 EMIT1_off32(0xE9, jmp_offset);
1665                         } else {
1666                                 pr_err("jmp gen bug %llx\n", jmp_offset);
1667                                 return -EFAULT;
1668                         }
1669                         break;
1670
1671                 case BPF_JMP | BPF_EXIT:
1672                         if (seen_exit) {
1673                                 jmp_offset = ctx->cleanup_addr - addrs[i];
1674                                 goto emit_jmp;
1675                         }
1676                         seen_exit = true;
1677                         /* Update cleanup_addr */
1678                         ctx->cleanup_addr = proglen;
1679                         pop_callee_regs(&prog, callee_regs_used);
1680                         EMIT1(0xC9);         /* leave */
1681                         EMIT1(0xC3);         /* ret */
1682                         break;
1683
1684                 default:
1685                         /*
1686                          * By design x86-64 JIT should support all BPF instructions.
1687                          * This error will be seen if new instruction was added
1688                          * to the interpreter, but not to the JIT, or if there is
1689                          * junk in bpf_prog.
1690                          */
1691                         pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1692                         return -EINVAL;
1693                 }
1694
1695                 ilen = prog - temp;
1696                 if (ilen > BPF_MAX_INSN_SIZE) {
1697                         pr_err("bpf_jit: fatal insn size error\n");
1698                         return -EFAULT;
1699                 }
1700
1701                 if (image) {
1702                         /*
1703                          * When populating the image, assert that:
1704                          *
1705                          *  i) We do not write beyond the allocated space, and
1706                          * ii) addrs[i] did not change from the prior run, in order
1707                          *     to validate assumptions made for computing branch
1708                          *     displacements.
1709                          */
1710                         if (unlikely(proglen + ilen > oldproglen ||
1711                                      proglen + ilen != addrs[i])) {
1712                                 pr_err("bpf_jit: fatal error\n");
1713                                 return -EFAULT;
1714                         }
1715                         memcpy(image + proglen, temp, ilen);
1716                 }
1717                 proglen += ilen;
1718                 addrs[i] = proglen;
1719                 prog = temp;
1720         }
1721
1722         if (image && excnt != bpf_prog->aux->num_exentries) {
1723                 pr_err("extable is not populated\n");
1724                 return -EFAULT;
1725         }
1726         return proglen;
1727 }
1728
1729 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1730                       int stack_size)
1731 {
1732         int i;
1733         /* Store function arguments to stack.
1734          * For a function that accepts two pointers the sequence will be:
1735          * mov QWORD PTR [rbp-0x10],rdi
1736          * mov QWORD PTR [rbp-0x8],rsi
1737          */
1738         for (i = 0; i < min(nr_args, 6); i++)
1739                 emit_stx(prog, bytes_to_bpf_size(m->arg_size[i]),
1740                          BPF_REG_FP,
1741                          i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1742                          -(stack_size - i * 8));
1743 }
1744
1745 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1746                          int stack_size)
1747 {
1748         int i;
1749
1750         /* Restore function arguments from stack.
1751          * For a function that accepts two pointers the sequence will be:
1752          * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1753          * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1754          */
1755         for (i = 0; i < min(nr_args, 6); i++)
1756                 emit_ldx(prog, bytes_to_bpf_size(m->arg_size[i]),
1757                          i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1758                          BPF_REG_FP,
1759                          -(stack_size - i * 8));
1760 }
1761
1762 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1763                            struct bpf_prog *p, int stack_size, bool mod_ret)
1764 {
1765         u8 *prog = *pprog;
1766         u8 *jmp_insn;
1767         int cnt = 0;
1768
1769         /* arg1: mov rdi, progs[i] */
1770         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1771         if (emit_call(&prog,
1772                       p->aux->sleepable ? __bpf_prog_enter_sleepable :
1773                       __bpf_prog_enter, prog))
1774                         return -EINVAL;
1775         /* remember prog start time returned by __bpf_prog_enter */
1776         emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1777
1778         /* if (__bpf_prog_enter*(prog) == 0)
1779          *      goto skip_exec_of_prog;
1780          */
1781         EMIT3(0x48, 0x85, 0xC0);  /* test rax,rax */
1782         /* emit 2 nops that will be replaced with JE insn */
1783         jmp_insn = prog;
1784         emit_nops(&prog, 2);
1785
1786         /* arg1: lea rdi, [rbp - stack_size] */
1787         EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1788         /* arg2: progs[i]->insnsi for interpreter */
1789         if (!p->jited)
1790                 emit_mov_imm64(&prog, BPF_REG_2,
1791                                (long) p->insnsi >> 32,
1792                                (u32) (long) p->insnsi);
1793         /* call JITed bpf program or interpreter */
1794         if (emit_call(&prog, p->bpf_func, prog))
1795                 return -EINVAL;
1796
1797         /* BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1798          * of the previous call which is then passed on the stack to
1799          * the next BPF program.
1800          */
1801         if (mod_ret)
1802                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1803
1804         /* replace 2 nops with JE insn, since jmp target is known */
1805         jmp_insn[0] = X86_JE;
1806         jmp_insn[1] = prog - jmp_insn - 2;
1807
1808         /* arg1: mov rdi, progs[i] */
1809         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1810         /* arg2: mov rsi, rbx <- start time in nsec */
1811         emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1812         if (emit_call(&prog,
1813                       p->aux->sleepable ? __bpf_prog_exit_sleepable :
1814                       __bpf_prog_exit, prog))
1815                         return -EINVAL;
1816
1817         *pprog = prog;
1818         return 0;
1819 }
1820
1821 static void emit_align(u8 **pprog, u32 align)
1822 {
1823         u8 *target, *prog = *pprog;
1824
1825         target = PTR_ALIGN(prog, align);
1826         if (target != prog)
1827                 emit_nops(&prog, target - prog);
1828
1829         *pprog = prog;
1830 }
1831
1832 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
1833 {
1834         u8 *prog = *pprog;
1835         int cnt = 0;
1836         s64 offset;
1837
1838         offset = func - (ip + 2 + 4);
1839         if (!is_simm32(offset)) {
1840                 pr_err("Target %p is out of range\n", func);
1841                 return -EINVAL;
1842         }
1843         EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
1844         *pprog = prog;
1845         return 0;
1846 }
1847
1848 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
1849                       struct bpf_tramp_progs *tp, int stack_size)
1850 {
1851         int i;
1852         u8 *prog = *pprog;
1853
1854         for (i = 0; i < tp->nr_progs; i++) {
1855                 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, false))
1856                         return -EINVAL;
1857         }
1858         *pprog = prog;
1859         return 0;
1860 }
1861
1862 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
1863                               struct bpf_tramp_progs *tp, int stack_size,
1864                               u8 **branches)
1865 {
1866         u8 *prog = *pprog;
1867         int i, cnt = 0;
1868
1869         /* The first fmod_ret program will receive a garbage return value.
1870          * Set this to 0 to avoid confusing the program.
1871          */
1872         emit_mov_imm32(&prog, false, BPF_REG_0, 0);
1873         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1874         for (i = 0; i < tp->nr_progs; i++) {
1875                 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, true))
1876                         return -EINVAL;
1877
1878                 /* mod_ret prog stored return value into [rbp - 8]. Emit:
1879                  * if (*(u64 *)(rbp - 8) !=  0)
1880                  *      goto do_fexit;
1881                  */
1882                 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
1883                 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
1884
1885                 /* Save the location of the branch and Generate 6 nops
1886                  * (4 bytes for an offset and 2 bytes for the jump) These nops
1887                  * are replaced with a conditional jump once do_fexit (i.e. the
1888                  * start of the fexit invocation) is finalized.
1889                  */
1890                 branches[i] = prog;
1891                 emit_nops(&prog, 4 + 2);
1892         }
1893
1894         *pprog = prog;
1895         return 0;
1896 }
1897
1898 /* Example:
1899  * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
1900  * its 'struct btf_func_model' will be nr_args=2
1901  * The assembly code when eth_type_trans is executing after trampoline:
1902  *
1903  * push rbp
1904  * mov rbp, rsp
1905  * sub rsp, 16                     // space for skb and dev
1906  * push rbx                        // temp regs to pass start time
1907  * mov qword ptr [rbp - 16], rdi   // save skb pointer to stack
1908  * mov qword ptr [rbp - 8], rsi    // save dev pointer to stack
1909  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1910  * mov rbx, rax                    // remember start time in bpf stats are enabled
1911  * lea rdi, [rbp - 16]             // R1==ctx of bpf prog
1912  * call addr_of_jited_FENTRY_prog
1913  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1914  * mov rsi, rbx                    // prog start time
1915  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1916  * mov rdi, qword ptr [rbp - 16]   // restore skb pointer from stack
1917  * mov rsi, qword ptr [rbp - 8]    // restore dev pointer from stack
1918  * pop rbx
1919  * leave
1920  * ret
1921  *
1922  * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
1923  * replaced with 'call generated_bpf_trampoline'. When it returns
1924  * eth_type_trans will continue executing with original skb and dev pointers.
1925  *
1926  * The assembly code when eth_type_trans is called from trampoline:
1927  *
1928  * push rbp
1929  * mov rbp, rsp
1930  * sub rsp, 24                     // space for skb, dev, return value
1931  * push rbx                        // temp regs to pass start time
1932  * mov qword ptr [rbp - 24], rdi   // save skb pointer to stack
1933  * mov qword ptr [rbp - 16], rsi   // save dev pointer to stack
1934  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1935  * mov rbx, rax                    // remember start time if bpf stats are enabled
1936  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
1937  * call addr_of_jited_FENTRY_prog  // bpf prog can access skb and dev
1938  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1939  * mov rsi, rbx                    // prog start time
1940  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1941  * mov rdi, qword ptr [rbp - 24]   // restore skb pointer from stack
1942  * mov rsi, qword ptr [rbp - 16]   // restore dev pointer from stack
1943  * call eth_type_trans+5           // execute body of eth_type_trans
1944  * mov qword ptr [rbp - 8], rax    // save return value
1945  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1946  * mov rbx, rax                    // remember start time in bpf stats are enabled
1947  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
1948  * call addr_of_jited_FEXIT_prog   // bpf prog can access skb, dev, return value
1949  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1950  * mov rsi, rbx                    // prog start time
1951  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1952  * mov rax, qword ptr [rbp - 8]    // restore eth_type_trans's return value
1953  * pop rbx
1954  * leave
1955  * add rsp, 8                      // skip eth_type_trans's frame
1956  * ret                             // return to its caller
1957  */
1958 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
1959                                 const struct btf_func_model *m, u32 flags,
1960                                 struct bpf_tramp_progs *tprogs,
1961                                 void *orig_call)
1962 {
1963         int ret, i, cnt = 0, nr_args = m->nr_args;
1964         int stack_size = nr_args * 8;
1965         struct bpf_tramp_progs *fentry = &tprogs[BPF_TRAMP_FENTRY];
1966         struct bpf_tramp_progs *fexit = &tprogs[BPF_TRAMP_FEXIT];
1967         struct bpf_tramp_progs *fmod_ret = &tprogs[BPF_TRAMP_MODIFY_RETURN];
1968         u8 **branches = NULL;
1969         u8 *prog;
1970
1971         /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
1972         if (nr_args > 6)
1973                 return -ENOTSUPP;
1974
1975         if ((flags & BPF_TRAMP_F_RESTORE_REGS) &&
1976             (flags & BPF_TRAMP_F_SKIP_FRAME))
1977                 return -EINVAL;
1978
1979         if (flags & BPF_TRAMP_F_CALL_ORIG)
1980                 stack_size += 8; /* room for return value of orig_call */
1981
1982         if (flags & BPF_TRAMP_F_SKIP_FRAME)
1983                 /* skip patched call instruction and point orig_call to actual
1984                  * body of the kernel function.
1985                  */
1986                 orig_call += X86_PATCH_SIZE;
1987
1988         prog = image;
1989
1990         EMIT1(0x55);             /* push rbp */
1991         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
1992         EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
1993         EMIT1(0x53);             /* push rbx */
1994
1995         save_regs(m, &prog, nr_args, stack_size);
1996
1997         if (flags & BPF_TRAMP_F_CALL_ORIG) {
1998                 /* arg1: mov rdi, im */
1999                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2000                 if (emit_call(&prog, __bpf_tramp_enter, prog)) {
2001                         ret = -EINVAL;
2002                         goto cleanup;
2003                 }
2004         }
2005
2006         if (fentry->nr_progs)
2007                 if (invoke_bpf(m, &prog, fentry, stack_size))
2008                         return -EINVAL;
2009
2010         if (fmod_ret->nr_progs) {
2011                 branches = kcalloc(fmod_ret->nr_progs, sizeof(u8 *),
2012                                    GFP_KERNEL);
2013                 if (!branches)
2014                         return -ENOMEM;
2015
2016                 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, stack_size,
2017                                        branches)) {
2018                         ret = -EINVAL;
2019                         goto cleanup;
2020                 }
2021         }
2022
2023         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2024                 restore_regs(m, &prog, nr_args, stack_size);
2025
2026                 /* call original function */
2027                 if (emit_call(&prog, orig_call, prog)) {
2028                         ret = -EINVAL;
2029                         goto cleanup;
2030                 }
2031                 /* remember return value in a stack for bpf prog to access */
2032                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2033                 im->ip_after_call = prog;
2034                 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2035                 prog += X86_PATCH_SIZE;
2036         }
2037
2038         if (fmod_ret->nr_progs) {
2039                 /* From Intel 64 and IA-32 Architectures Optimization
2040                  * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2041                  * Coding Rule 11: All branch targets should be 16-byte
2042                  * aligned.
2043                  */
2044                 emit_align(&prog, 16);
2045                 /* Update the branches saved in invoke_bpf_mod_ret with the
2046                  * aligned address of do_fexit.
2047                  */
2048                 for (i = 0; i < fmod_ret->nr_progs; i++)
2049                         emit_cond_near_jump(&branches[i], prog, branches[i],
2050                                             X86_JNE);
2051         }
2052
2053         if (fexit->nr_progs)
2054                 if (invoke_bpf(m, &prog, fexit, stack_size)) {
2055                         ret = -EINVAL;
2056                         goto cleanup;
2057                 }
2058
2059         if (flags & BPF_TRAMP_F_RESTORE_REGS)
2060                 restore_regs(m, &prog, nr_args, stack_size);
2061
2062         /* This needs to be done regardless. If there were fmod_ret programs,
2063          * the return value is only updated on the stack and still needs to be
2064          * restored to R0.
2065          */
2066         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2067                 im->ip_epilogue = prog;
2068                 /* arg1: mov rdi, im */
2069                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2070                 if (emit_call(&prog, __bpf_tramp_exit, prog)) {
2071                         ret = -EINVAL;
2072                         goto cleanup;
2073                 }
2074                 /* restore original return value back into RAX */
2075                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2076         }
2077
2078         EMIT1(0x5B); /* pop rbx */
2079         EMIT1(0xC9); /* leave */
2080         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2081                 /* skip our return address and return to parent */
2082                 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2083         EMIT1(0xC3); /* ret */
2084         /* Make sure the trampoline generation logic doesn't overflow */
2085         if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2086                 ret = -EFAULT;
2087                 goto cleanup;
2088         }
2089         ret = prog - (u8 *)image;
2090
2091 cleanup:
2092         kfree(branches);
2093         return ret;
2094 }
2095
2096 static int emit_fallback_jump(u8 **pprog)
2097 {
2098         u8 *prog = *pprog;
2099         int err = 0;
2100
2101 #ifdef CONFIG_RETPOLINE
2102         /* Note that this assumes the the compiler uses external
2103          * thunks for indirect calls. Both clang and GCC use the same
2104          * naming convention for external thunks.
2105          */
2106         err = emit_jump(&prog, __x86_indirect_thunk_rdx, prog);
2107 #else
2108         int cnt = 0;
2109
2110         EMIT2(0xFF, 0xE2);      /* jmp rdx */
2111 #endif
2112         *pprog = prog;
2113         return err;
2114 }
2115
2116 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs)
2117 {
2118         u8 *jg_reloc, *prog = *pprog;
2119         int pivot, err, jg_bytes = 1, cnt = 0;
2120         s64 jg_offset;
2121
2122         if (a == b) {
2123                 /* Leaf node of recursion, i.e. not a range of indices
2124                  * anymore.
2125                  */
2126                 EMIT1(add_1mod(0x48, BPF_REG_3));       /* cmp rdx,func */
2127                 if (!is_simm32(progs[a]))
2128                         return -1;
2129                 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2130                             progs[a]);
2131                 err = emit_cond_near_jump(&prog,        /* je func */
2132                                           (void *)progs[a], prog,
2133                                           X86_JE);
2134                 if (err)
2135                         return err;
2136
2137                 err = emit_fallback_jump(&prog);        /* jmp thunk/indirect */
2138                 if (err)
2139                         return err;
2140
2141                 *pprog = prog;
2142                 return 0;
2143         }
2144
2145         /* Not a leaf node, so we pivot, and recursively descend into
2146          * the lower and upper ranges.
2147          */
2148         pivot = (b - a) / 2;
2149         EMIT1(add_1mod(0x48, BPF_REG_3));               /* cmp rdx,func */
2150         if (!is_simm32(progs[a + pivot]))
2151                 return -1;
2152         EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2153
2154         if (pivot > 2) {                                /* jg upper_part */
2155                 /* Require near jump. */
2156                 jg_bytes = 4;
2157                 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2158         } else {
2159                 EMIT2(X86_JG, 0);
2160         }
2161         jg_reloc = prog;
2162
2163         err = emit_bpf_dispatcher(&prog, a, a + pivot,  /* emit lower_part */
2164                                   progs);
2165         if (err)
2166                 return err;
2167
2168         /* From Intel 64 and IA-32 Architectures Optimization
2169          * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2170          * Coding Rule 11: All branch targets should be 16-byte
2171          * aligned.
2172          */
2173         emit_align(&prog, 16);
2174         jg_offset = prog - jg_reloc;
2175         emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2176
2177         err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2178                                   b, progs);
2179         if (err)
2180                 return err;
2181
2182         *pprog = prog;
2183         return 0;
2184 }
2185
2186 static int cmp_ips(const void *a, const void *b)
2187 {
2188         const s64 *ipa = a;
2189         const s64 *ipb = b;
2190
2191         if (*ipa > *ipb)
2192                 return 1;
2193         if (*ipa < *ipb)
2194                 return -1;
2195         return 0;
2196 }
2197
2198 int arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs)
2199 {
2200         u8 *prog = image;
2201
2202         sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2203         return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs);
2204 }
2205
2206 struct x64_jit_data {
2207         struct bpf_binary_header *header;
2208         int *addrs;
2209         u8 *image;
2210         int proglen;
2211         struct jit_context ctx;
2212 };
2213
2214 #define MAX_PASSES 20
2215 #define PADDING_PASSES (MAX_PASSES - 5)
2216
2217 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2218 {
2219         struct bpf_binary_header *header = NULL;
2220         struct bpf_prog *tmp, *orig_prog = prog;
2221         struct x64_jit_data *jit_data;
2222         int proglen, oldproglen = 0;
2223         struct jit_context ctx = {};
2224         bool tmp_blinded = false;
2225         bool extra_pass = false;
2226         bool padding = false;
2227         u8 *image = NULL;
2228         int *addrs;
2229         int pass;
2230         int i;
2231
2232         if (!prog->jit_requested)
2233                 return orig_prog;
2234
2235         tmp = bpf_jit_blind_constants(prog);
2236         /*
2237          * If blinding was requested and we failed during blinding,
2238          * we must fall back to the interpreter.
2239          */
2240         if (IS_ERR(tmp))
2241                 return orig_prog;
2242         if (tmp != prog) {
2243                 tmp_blinded = true;
2244                 prog = tmp;
2245         }
2246
2247         jit_data = prog->aux->jit_data;
2248         if (!jit_data) {
2249                 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2250                 if (!jit_data) {
2251                         prog = orig_prog;
2252                         goto out;
2253                 }
2254                 prog->aux->jit_data = jit_data;
2255         }
2256         addrs = jit_data->addrs;
2257         if (addrs) {
2258                 ctx = jit_data->ctx;
2259                 oldproglen = jit_data->proglen;
2260                 image = jit_data->image;
2261                 header = jit_data->header;
2262                 extra_pass = true;
2263                 padding = true;
2264                 goto skip_init_addrs;
2265         }
2266         addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2267         if (!addrs) {
2268                 prog = orig_prog;
2269                 goto out_addrs;
2270         }
2271
2272         /*
2273          * Before first pass, make a rough estimation of addrs[]
2274          * each BPF instruction is translated to less than 64 bytes
2275          */
2276         for (proglen = 0, i = 0; i <= prog->len; i++) {
2277                 proglen += 64;
2278                 addrs[i] = proglen;
2279         }
2280         ctx.cleanup_addr = proglen;
2281 skip_init_addrs:
2282
2283         /*
2284          * JITed image shrinks with every pass and the loop iterates
2285          * until the image stops shrinking. Very large BPF programs
2286          * may converge on the last pass. In such case do one more
2287          * pass to emit the final image.
2288          */
2289         for (pass = 0; pass < MAX_PASSES || image; pass++) {
2290                 if (!padding && pass >= PADDING_PASSES)
2291                         padding = true;
2292                 proglen = do_jit(prog, addrs, image, oldproglen, &ctx, padding);
2293                 if (proglen <= 0) {
2294 out_image:
2295                         image = NULL;
2296                         if (header)
2297                                 bpf_jit_binary_free(header);
2298                         prog = orig_prog;
2299                         goto out_addrs;
2300                 }
2301                 if (image) {
2302                         if (proglen != oldproglen) {
2303                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2304                                        proglen, oldproglen);
2305                                 goto out_image;
2306                         }
2307                         break;
2308                 }
2309                 if (proglen == oldproglen) {
2310                         /*
2311                          * The number of entries in extable is the number of BPF_LDX
2312                          * insns that access kernel memory via "pointer to BTF type".
2313                          * The verifier changed their opcode from LDX|MEM|size
2314                          * to LDX|PROBE_MEM|size to make JITing easier.
2315                          */
2316                         u32 align = __alignof__(struct exception_table_entry);
2317                         u32 extable_size = prog->aux->num_exentries *
2318                                 sizeof(struct exception_table_entry);
2319
2320                         /* allocate module memory for x86 insns and extable */
2321                         header = bpf_jit_binary_alloc(roundup(proglen, align) + extable_size,
2322                                                       &image, align, jit_fill_hole);
2323                         if (!header) {
2324                                 prog = orig_prog;
2325                                 goto out_addrs;
2326                         }
2327                         prog->aux->extable = (void *) image + roundup(proglen, align);
2328                 }
2329                 oldproglen = proglen;
2330                 cond_resched();
2331         }
2332
2333         if (bpf_jit_enable > 1)
2334                 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2335
2336         if (image) {
2337                 if (!prog->is_func || extra_pass) {
2338                         bpf_tail_call_direct_fixup(prog);
2339                         bpf_jit_binary_lock_ro(header);
2340                 } else {
2341                         jit_data->addrs = addrs;
2342                         jit_data->ctx = ctx;
2343                         jit_data->proglen = proglen;
2344                         jit_data->image = image;
2345                         jit_data->header = header;
2346                 }
2347                 prog->bpf_func = (void *)image;
2348                 prog->jited = 1;
2349                 prog->jited_len = proglen;
2350         } else {
2351                 prog = orig_prog;
2352         }
2353
2354         if (!image || !prog->is_func || extra_pass) {
2355                 if (image)
2356                         bpf_prog_fill_jited_linfo(prog, addrs + 1);
2357 out_addrs:
2358                 kvfree(addrs);
2359                 kfree(jit_data);
2360                 prog->aux->jit_data = NULL;
2361         }
2362 out:
2363         if (tmp_blinded)
2364                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2365                                            tmp : orig_prog);
2366         return prog;
2367 }
2368
2369 bool bpf_jit_supports_kfunc_call(void)
2370 {
2371         return true;
2372 }