arch/x86/net/bpf_jit_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * BPF JIT compiler
   4  *
   5  * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
   6  * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
   7  */
   8 #include <linux/netdevice.h>
   9 #include <linux/filter.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/bpf.h>
  12 #include <linux/memory.h>
  13 #include <linux/sort.h>
  14 #include <asm/extable.h>
  15 #include <asm/set_memory.h>
  16 #include <asm/nospec-branch.h>
  17 #include <asm/text-patching.h>
  18
  19 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  20 {
  21         if (len == 1)
  22                 *ptr = bytes;
  23         else if (len == 2)
  24                 *(u16 *)ptr = bytes;
  25         else {
  26                 *(u32 *)ptr = bytes;
  27                 barrier();
  28         }
  29         return ptr + len;
  30 }
  31
  32 #define EMIT(bytes, len) \
  33         do { prog = emit_code(prog, bytes, len); } while (0)
  34
  35 #define EMIT1(b1)               EMIT(b1, 1)
  36 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  37 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  38 #define EMIT4(b1, b2, b3, b4)   EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  39
  40 #define EMIT1_off32(b1, off) \
  41         do { EMIT1(b1); EMIT(off, 4); } while (0)
  42 #define EMIT2_off32(b1, b2, off) \
  43         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  44 #define EMIT3_off32(b1, b2, b3, off) \
  45         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  46 #define EMIT4_off32(b1, b2, b3, b4, off) \
  47         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  48
  49 #ifdef CONFIG_X86_KERNEL_IBT
  50 #define EMIT_ENDBR()    EMIT(gen_endbr(), 4)
  51 #else
  52 #define EMIT_ENDBR()
  53 #endif
  54
  55 static bool is_imm8(int value)
  56 {
  57         return value <= 127 && value >= -128;
  58 }
  59
  60 static bool is_simm32(s64 value)
  61 {
  62         return value == (s64)(s32)value;
  63 }
  64
  65 static bool is_uimm32(u64 value)
  66 {
  67         return value == (u64)(u32)value;
  68 }
  69
  70 /* mov dst, src */
  71 #define EMIT_mov(DST, SRC)                                                               \
  72         do {                                                                             \
  73                 if (DST != SRC)                                                          \
  74                         EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
  75         } while (0)
  76
  77 static int bpf_size_to_x86_bytes(int bpf_size)
  78 {
  79         if (bpf_size == BPF_W)
  80                 return 4;
  81         else if (bpf_size == BPF_H)
  82                 return 2;
  83         else if (bpf_size == BPF_B)
  84                 return 1;
  85         else if (bpf_size == BPF_DW)
  86                 return 4; /* imm32 */
  87         else
  88                 return 0;
  89 }
  90
  91 /*
  92  * List of x86 cond jumps opcodes (. + s8)
  93  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
  94  */
  95 #define X86_JB  0x72
  96 #define X86_JAE 0x73
  97 #define X86_JE  0x74
  98 #define X86_JNE 0x75
  99 #define X86_JBE 0x76
 100 #define X86_JA  0x77
 101 #define X86_JL  0x7C
 102 #define X86_JGE 0x7D
 103 #define X86_JLE 0x7E
 104 #define X86_JG  0x7F
 105
 106 /* Pick a register outside of BPF range for JIT internal work */
 107 #define AUX_REG (MAX_BPF_JIT_REG + 1)
 108 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
 109
 110 /*
 111  * The following table maps BPF registers to x86-64 registers.
 112  *
 113  * x86-64 register R12 is unused, since if used as base address
 114  * register in load/store instructions, it always needs an
 115  * extra byte of encoding and is callee saved.
 116  *
 117  * x86-64 register R9 is not used by BPF programs, but can be used by BPF
 118  * trampoline. x86-64 register R10 is used for blinding (if enabled).
 119  */
 120 static const int reg2hex[] = {
 121         [BPF_REG_0] = 0,  /* RAX */
 122         [BPF_REG_1] = 7,  /* RDI */
 123         [BPF_REG_2] = 6,  /* RSI */
 124         [BPF_REG_3] = 2,  /* RDX */
 125         [BPF_REG_4] = 1,  /* RCX */
 126         [BPF_REG_5] = 0,  /* R8  */
 127         [BPF_REG_6] = 3,  /* RBX callee saved */
 128         [BPF_REG_7] = 5,  /* R13 callee saved */
 129         [BPF_REG_8] = 6,  /* R14 callee saved */
 130         [BPF_REG_9] = 7,  /* R15 callee saved */
 131         [BPF_REG_FP] = 5, /* RBP readonly */
 132         [BPF_REG_AX] = 2, /* R10 temp register */
 133         [AUX_REG] = 3,    /* R11 temp register */
 134         [X86_REG_R9] = 1, /* R9 register, 6th function argument */
 135 };
 136
 137 static const int reg2pt_regs[] = {
 138         [BPF_REG_0] = offsetof(struct pt_regs, ax),
 139         [BPF_REG_1] = offsetof(struct pt_regs, di),
 140         [BPF_REG_2] = offsetof(struct pt_regs, si),
 141         [BPF_REG_3] = offsetof(struct pt_regs, dx),
 142         [BPF_REG_4] = offsetof(struct pt_regs, cx),
 143         [BPF_REG_5] = offsetof(struct pt_regs, r8),
 144         [BPF_REG_6] = offsetof(struct pt_regs, bx),
 145         [BPF_REG_7] = offsetof(struct pt_regs, r13),
 146         [BPF_REG_8] = offsetof(struct pt_regs, r14),
 147         [BPF_REG_9] = offsetof(struct pt_regs, r15),
 148 };
 149
 150 /*
 151  * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
 152  * which need extra byte of encoding.
 153  * rax,rcx,...,rbp have simpler encoding
 154  */
 155 static bool is_ereg(u32 reg)
 156 {
 157         return (1 << reg) & (BIT(BPF_REG_5) |
 158                              BIT(AUX_REG) |
 159                              BIT(BPF_REG_7) |
 160                              BIT(BPF_REG_8) |
 161                              BIT(BPF_REG_9) |
 162                              BIT(X86_REG_R9) |
 163                              BIT(BPF_REG_AX));
 164 }
 165
 166 /*
 167  * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
 168  * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
 169  * of encoding. al,cl,dl,bl have simpler encoding.
 170  */
 171 static bool is_ereg_8l(u32 reg)
 172 {
 173         return is_ereg(reg) ||
 174             (1 << reg) & (BIT(BPF_REG_1) |
 175                           BIT(BPF_REG_2) |
 176                           BIT(BPF_REG_FP));
 177 }
 178
 179 static bool is_axreg(u32 reg)
 180 {
 181         return reg == BPF_REG_0;
 182 }
 183
 184 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
 185 static u8 add_1mod(u8 byte, u32 reg)
 186 {
 187         if (is_ereg(reg))
 188                 byte |= 1;
 189         return byte;
 190 }
 191
 192 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
 193 {
 194         if (is_ereg(r1))
 195                 byte |= 1;
 196         if (is_ereg(r2))
 197                 byte |= 4;
 198         return byte;
 199 }
 200
 201 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
 202 static u8 add_1reg(u8 byte, u32 dst_reg)
 203 {
 204         return byte + reg2hex[dst_reg];
 205 }
 206
 207 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
 208 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 209 {
 210         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 211 }
 212
 213 /* Some 1-byte opcodes for binary ALU operations */
 214 static u8 simple_alu_opcodes[] = {
 215         [BPF_ADD] = 0x01,
 216         [BPF_SUB] = 0x29,
 217         [BPF_AND] = 0x21,
 218         [BPF_OR] = 0x09,
 219         [BPF_XOR] = 0x31,
 220         [BPF_LSH] = 0xE0,
 221         [BPF_RSH] = 0xE8,
 222         [BPF_ARSH] = 0xF8,
 223 };
 224
 225 static void jit_fill_hole(void *area, unsigned int size)
 226 {
 227         /* Fill whole space with INT3 instructions */
 228         memset(area, 0xcc, size);
 229 }
 230
 231 int bpf_arch_text_invalidate(void *dst, size_t len)
 232 {
 233         return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
 234 }
 235
 236 struct jit_context {
 237         int cleanup_addr; /* Epilogue code offset */
 238
 239         /*
 240          * Program specific offsets of labels in the code; these rely on the
 241          * JIT doing at least 2 passes, recording the position on the first
 242          * pass, only to generate the correct offset on the second pass.
 243          */
 244         int tail_call_direct_label;
 245         int tail_call_indirect_label;
 246 };
 247
 248 /* Maximum number of bytes emitted while JITing one eBPF insn */
 249 #define BPF_MAX_INSN_SIZE       128
 250 #define BPF_INSN_SAFETY         64
 251
 252 /* Number of bytes emit_patch() needs to generate instructions */
 253 #define X86_PATCH_SIZE          5
 254 /* Number of bytes that will be skipped on tailcall */
 255 #define X86_TAIL_CALL_OFFSET    (11 + ENDBR_INSN_SIZE)
 256
 257 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
 258 {
 259         u8 *prog = *pprog;
 260
 261         if (callee_regs_used[0])
 262                 EMIT1(0x53);         /* push rbx */
 263         if (callee_regs_used[1])
 264                 EMIT2(0x41, 0x55);   /* push r13 */
 265         if (callee_regs_used[2])
 266                 EMIT2(0x41, 0x56);   /* push r14 */
 267         if (callee_regs_used[3])
 268                 EMIT2(0x41, 0x57);   /* push r15 */
 269         *pprog = prog;
 270 }
 271
 272 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
 273 {
 274         u8 *prog = *pprog;
 275
 276         if (callee_regs_used[3])
 277                 EMIT2(0x41, 0x5F);   /* pop r15 */
 278         if (callee_regs_used[2])
 279                 EMIT2(0x41, 0x5E);   /* pop r14 */
 280         if (callee_regs_used[1])
 281                 EMIT2(0x41, 0x5D);   /* pop r13 */
 282         if (callee_regs_used[0])
 283                 EMIT1(0x5B);         /* pop rbx */
 284         *pprog = prog;
 285 }
 286
 287 /*
 288  * Emit x86-64 prologue code for BPF program.
 289  * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
 290  * while jumping to another program
 291  */
 292 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
 293                           bool tail_call_reachable, bool is_subprog)
 294 {
 295         u8 *prog = *pprog;
 296
 297         /* BPF trampoline can be made to work without these nops,
 298          * but let's waste 5 bytes for now and optimize later
 299          */
 300         EMIT_ENDBR();
 301         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 302         prog += X86_PATCH_SIZE;
 303         if (!ebpf_from_cbpf) {
 304                 if (tail_call_reachable && !is_subprog)
 305                         EMIT2(0x31, 0xC0); /* xor eax, eax */
 306                 else
 307                         EMIT2(0x66, 0x90); /* nop2 */
 308         }
 309         EMIT1(0x55);             /* push rbp */
 310         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
 311
 312         /* X86_TAIL_CALL_OFFSET is here */
 313         EMIT_ENDBR();
 314
 315         /* sub rsp, rounded_stack_depth */
 316         if (stack_depth)
 317                 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
 318         if (tail_call_reachable)
 319                 EMIT1(0x50);         /* push rax */
 320         *pprog = prog;
 321 }
 322
 323 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
 324 {
 325         u8 *prog = *pprog;
 326         s64 offset;
 327
 328         offset = func - (ip + X86_PATCH_SIZE);
 329         if (!is_simm32(offset)) {
 330                 pr_err("Target call %p is out of range\n", func);
 331                 return -ERANGE;
 332         }
 333         EMIT1_off32(opcode, offset);
 334         *pprog = prog;
 335         return 0;
 336 }
 337
 338 static int emit_call(u8 **pprog, void *func, void *ip)
 339 {
 340         return emit_patch(pprog, func, ip, 0xE8);
 341 }
 342
 343 static int emit_jump(u8 **pprog, void *func, void *ip)
 344 {
 345         return emit_patch(pprog, func, ip, 0xE9);
 346 }
 347
 348 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 349                                 void *old_addr, void *new_addr)
 350 {
 351         const u8 *nop_insn = x86_nops[5];
 352         u8 old_insn[X86_PATCH_SIZE];
 353         u8 new_insn[X86_PATCH_SIZE];
 354         u8 *prog;
 355         int ret;
 356
 357         memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
 358         if (old_addr) {
 359                 prog = old_insn;
 360                 ret = t == BPF_MOD_CALL ?
 361                       emit_call(&prog, old_addr, ip) :
 362                       emit_jump(&prog, old_addr, ip);
 363                 if (ret)
 364                         return ret;
 365         }
 366
 367         memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
 368         if (new_addr) {
 369                 prog = new_insn;
 370                 ret = t == BPF_MOD_CALL ?
 371                       emit_call(&prog, new_addr, ip) :
 372                       emit_jump(&prog, new_addr, ip);
 373                 if (ret)
 374                         return ret;
 375         }
 376
 377         ret = -EBUSY;
 378         mutex_lock(&text_mutex);
 379         if (memcmp(ip, old_insn, X86_PATCH_SIZE))
 380                 goto out;
 381         ret = 1;
 382         if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
 383                 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
 384                 ret = 0;
 385         }
 386 out:
 387         mutex_unlock(&text_mutex);
 388         return ret;
 389 }
 390
 391 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 392                        void *old_addr, void *new_addr)
 393 {
 394         if (!is_kernel_text((long)ip) &&
 395             !is_bpf_text_address((long)ip))
 396                 /* BPF poking in modules is not supported */
 397                 return -EINVAL;
 398
 399         /*
 400          * See emit_prologue(), for IBT builds the trampoline hook is preceded
 401          * with an ENDBR instruction.
 402          */
 403         if (is_endbr(*(u32 *)ip))
 404                 ip += ENDBR_INSN_SIZE;
 405
 406         return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
 407 }
 408
 409 #define EMIT_LFENCE()   EMIT3(0x0F, 0xAE, 0xE8)
 410
 411 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
 412 {
 413         u8 *prog = *pprog;
 414
 415         if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
 416                 EMIT_LFENCE();
 417                 EMIT2(0xFF, 0xE0 + reg);
 418         } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
 419                 OPTIMIZER_HIDE_VAR(reg);
 420                 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
 421         } else {
 422                 EMIT2(0xFF, 0xE0 + reg);        /* jmp *%\reg */
 423                 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS))
 424                         EMIT1(0xCC);            /* int3 */
 425         }
 426
 427         *pprog = prog;
 428 }
 429
 430 static void emit_return(u8 **pprog, u8 *ip)
 431 {
 432         u8 *prog = *pprog;
 433
 434         if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
 435                 emit_jump(&prog, &__x86_return_thunk, ip);
 436         } else {
 437                 EMIT1(0xC3);            /* ret */
 438                 if (IS_ENABLED(CONFIG_SLS))
 439                         EMIT1(0xCC);    /* int3 */
 440         }
 441
 442         *pprog = prog;
 443 }
 444
 445 /*
 446  * Generate the following code:
 447  *
 448  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
 449  *   if (index >= array->map.max_entries)
 450  *     goto out;
 451  *   if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 452  *     goto out;
 453  *   prog = array->ptrs[index];
 454  *   if (prog == NULL)
 455  *     goto out;
 456  *   goto *(prog->bpf_func + prologue_size);
 457  * out:
 458  */
 459 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
 460                                         u32 stack_depth, u8 *ip,
 461                                         struct jit_context *ctx)
 462 {
 463         int tcc_off = -4 - round_up(stack_depth, 8);
 464         u8 *prog = *pprog, *start = *pprog;
 465         int offset;
 466
 467         /*
 468          * rdi - pointer to ctx
 469          * rsi - pointer to bpf_array
 470          * rdx - index in bpf_array
 471          */
 472
 473         /*
 474          * if (index >= array->map.max_entries)
 475          *      goto out;
 476          */
 477         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
 478         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 479               offsetof(struct bpf_array, map.max_entries));
 480
 481         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 482         EMIT2(X86_JBE, offset);                   /* jbe out */
 483
 484         /*
 485          * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 486          *      goto out;
 487          */
 488         EMIT2_off32(0x8B, 0x85, tcc_off);         /* mov eax, dword ptr [rbp - tcc_off] */
 489         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
 490
 491         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 492         EMIT2(X86_JAE, offset);                   /* jae out */
 493         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
 494         EMIT2_off32(0x89, 0x85, tcc_off);         /* mov dword ptr [rbp - tcc_off], eax */
 495
 496         /* prog = array->ptrs[index]; */
 497         EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6,       /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
 498                     offsetof(struct bpf_array, ptrs));
 499
 500         /*
 501          * if (prog == NULL)
 502          *      goto out;
 503          */
 504         EMIT3(0x48, 0x85, 0xC9);                  /* test rcx,rcx */
 505
 506         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 507         EMIT2(X86_JE, offset);                    /* je out */
 508
 509         pop_callee_regs(&prog, callee_regs_used);
 510
 511         EMIT1(0x58);                              /* pop rax */
 512         if (stack_depth)
 513                 EMIT3_off32(0x48, 0x81, 0xC4,     /* add rsp, sd */
 514                             round_up(stack_depth, 8));
 515
 516         /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
 517         EMIT4(0x48, 0x8B, 0x49,                   /* mov rcx, qword ptr [rcx + 32] */
 518               offsetof(struct bpf_prog, bpf_func));
 519         EMIT4(0x48, 0x83, 0xC1,                   /* add rcx, X86_TAIL_CALL_OFFSET */
 520               X86_TAIL_CALL_OFFSET);
 521         /*
 522          * Now we're ready to jump into next BPF program
 523          * rdi == ctx (1st arg)
 524          * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
 525          */
 526         emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
 527
 528         /* out: */
 529         ctx->tail_call_indirect_label = prog - start;
 530         *pprog = prog;
 531 }
 532
 533 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
 534                                       u8 **pprog, u8 *ip,
 535                                       bool *callee_regs_used, u32 stack_depth,
 536                                       struct jit_context *ctx)
 537 {
 538         int tcc_off = -4 - round_up(stack_depth, 8);
 539         u8 *prog = *pprog, *start = *pprog;
 540         int offset;
 541
 542         /*
 543          * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 544          *      goto out;
 545          */
 546         EMIT2_off32(0x8B, 0x85, tcc_off);             /* mov eax, dword ptr [rbp - tcc_off] */
 547         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);         /* cmp eax, MAX_TAIL_CALL_CNT */
 548
 549         offset = ctx->tail_call_direct_label - (prog + 2 - start);
 550         EMIT2(X86_JAE, offset);                       /* jae out */
 551         EMIT3(0x83, 0xC0, 0x01);                      /* add eax, 1 */
 552         EMIT2_off32(0x89, 0x85, tcc_off);             /* mov dword ptr [rbp - tcc_off], eax */
 553
 554         poke->tailcall_bypass = ip + (prog - start);
 555         poke->adj_off = X86_TAIL_CALL_OFFSET;
 556         poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
 557         poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
 558
 559         emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
 560                   poke->tailcall_bypass);
 561
 562         pop_callee_regs(&prog, callee_regs_used);
 563         EMIT1(0x58);                                  /* pop rax */
 564         if (stack_depth)
 565                 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
 566
 567         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 568         prog += X86_PATCH_SIZE;
 569
 570         /* out: */
 571         ctx->tail_call_direct_label = prog - start;
 572
 573         *pprog = prog;
 574 }
 575
 576 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
 577 {
 578         struct bpf_jit_poke_descriptor *poke;
 579         struct bpf_array *array;
 580         struct bpf_prog *target;
 581         int i, ret;
 582
 583         for (i = 0; i < prog->aux->size_poke_tab; i++) {
 584                 poke = &prog->aux->poke_tab[i];
 585                 if (poke->aux && poke->aux != prog->aux)
 586                         continue;
 587
 588                 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
 589
 590                 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
 591                         continue;
 592
 593                 array = container_of(poke->tail_call.map, struct bpf_array, map);
 594                 mutex_lock(&array->aux->poke_mutex);
 595                 target = array->ptrs[poke->tail_call.key];
 596                 if (target) {
 597                         ret = __bpf_arch_text_poke(poke->tailcall_target,
 598                                                    BPF_MOD_JUMP, NULL,
 599                                                    (u8 *)target->bpf_func +
 600                                                    poke->adj_off);
 601                         BUG_ON(ret < 0);
 602                         ret = __bpf_arch_text_poke(poke->tailcall_bypass,
 603                                                    BPF_MOD_JUMP,
 604                                                    (u8 *)poke->tailcall_target +
 605                                                    X86_PATCH_SIZE, NULL);
 606                         BUG_ON(ret < 0);
 607                 }
 608                 WRITE_ONCE(poke->tailcall_target_stable, true);
 609                 mutex_unlock(&array->aux->poke_mutex);
 610         }
 611 }
 612
 613 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
 614                            u32 dst_reg, const u32 imm32)
 615 {
 616         u8 *prog = *pprog;
 617         u8 b1, b2, b3;
 618
 619         /*
 620          * Optimization: if imm32 is positive, use 'mov %eax, imm32'
 621          * (which zero-extends imm32) to save 2 bytes.
 622          */
 623         if (sign_propagate && (s32)imm32 < 0) {
 624                 /* 'mov %rax, imm32' sign extends imm32 */
 625                 b1 = add_1mod(0x48, dst_reg);
 626                 b2 = 0xC7;
 627                 b3 = 0xC0;
 628                 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
 629                 goto done;
 630         }
 631
 632         /*
 633          * Optimization: if imm32 is zero, use 'xor %eax, %eax'
 634          * to save 3 bytes.
 635          */
 636         if (imm32 == 0) {
 637                 if (is_ereg(dst_reg))
 638                         EMIT1(add_2mod(0x40, dst_reg, dst_reg));
 639                 b2 = 0x31; /* xor */
 640                 b3 = 0xC0;
 641                 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
 642                 goto done;
 643         }
 644
 645         /* mov %eax, imm32 */
 646         if (is_ereg(dst_reg))
 647                 EMIT1(add_1mod(0x40, dst_reg));
 648         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
 649 done:
 650         *pprog = prog;
 651 }
 652
 653 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
 654                            const u32 imm32_hi, const u32 imm32_lo)
 655 {
 656         u8 *prog = *pprog;
 657
 658         if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
 659                 /*
 660                  * For emitting plain u32, where sign bit must not be
 661                  * propagated LLVM tends to load imm64 over mov32
 662                  * directly, so save couple of bytes by just doing
 663                  * 'mov %eax, imm32' instead.
 664                  */
 665                 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
 666         } else {
 667                 /* movabsq rax, imm64 */
 668                 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
 669                 EMIT(imm32_lo, 4);
 670                 EMIT(imm32_hi, 4);
 671         }
 672
 673         *pprog = prog;
 674 }
 675
 676 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
 677 {
 678         u8 *prog = *pprog;
 679
 680         if (is64) {
 681                 /* mov dst, src */
 682                 EMIT_mov(dst_reg, src_reg);
 683         } else {
 684                 /* mov32 dst, src */
 685                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 686                         EMIT1(add_2mod(0x40, dst_reg, src_reg));
 687                 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
 688         }
 689
 690         *pprog = prog;
 691 }
 692
 693 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
 694 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
 695 {
 696         u8 *prog = *pprog;
 697
 698         if (is_imm8(off)) {
 699                 /* 1-byte signed displacement.
 700                  *
 701                  * If off == 0 we could skip this and save one extra byte, but
 702                  * special case of x86 R13 which always needs an offset is not
 703                  * worth the hassle
 704                  */
 705                 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
 706         } else {
 707                 /* 4-byte signed displacement */
 708                 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
 709         }
 710         *pprog = prog;
 711 }
 712
 713 /*
 714  * Emit a REX byte if it will be necessary to address these registers
 715  */
 716 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
 717 {
 718         u8 *prog = *pprog;
 719
 720         if (is64)
 721                 EMIT1(add_2mod(0x48, dst_reg, src_reg));
 722         else if (is_ereg(dst_reg) || is_ereg(src_reg))
 723                 EMIT1(add_2mod(0x40, dst_reg, src_reg));
 724         *pprog = prog;
 725 }
 726
 727 /*
 728  * Similar version of maybe_emit_mod() for a single register
 729  */
 730 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
 731 {
 732         u8 *prog = *pprog;
 733
 734         if (is64)
 735                 EMIT1(add_1mod(0x48, reg));
 736         else if (is_ereg(reg))
 737                 EMIT1(add_1mod(0x40, reg));
 738         *pprog = prog;
 739 }
 740
 741 /* LDX: dst_reg = *(u8*)(src_reg + off) */
 742 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 743 {
 744         u8 *prog = *pprog;
 745
 746         switch (size) {
 747         case BPF_B:
 748                 /* Emit 'movzx rax, byte ptr [rax + off]' */
 749                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
 750                 break;
 751         case BPF_H:
 752                 /* Emit 'movzx rax, word ptr [rax + off]' */
 753                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
 754                 break;
 755         case BPF_W:
 756                 /* Emit 'mov eax, dword ptr [rax+0x14]' */
 757                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 758                         EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
 759                 else
 760                         EMIT1(0x8B);
 761                 break;
 762         case BPF_DW:
 763                 /* Emit 'mov rax, qword ptr [rax+0x14]' */
 764                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
 765                 break;
 766         }
 767         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 768         *pprog = prog;
 769 }
 770
 771 /* STX: *(u8*)(dst_reg + off) = src_reg */
 772 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 773 {
 774         u8 *prog = *pprog;
 775
 776         switch (size) {
 777         case BPF_B:
 778                 /* Emit 'mov byte ptr [rax + off], al' */
 779                 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
 780                         /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
 781                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
 782                 else
 783                         EMIT1(0x88);
 784                 break;
 785         case BPF_H:
 786                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 787                         EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
 788                 else
 789                         EMIT2(0x66, 0x89);
 790                 break;
 791         case BPF_W:
 792                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 793                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
 794                 else
 795                         EMIT1(0x89);
 796                 break;
 797         case BPF_DW:
 798                 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
 799                 break;
 800         }
 801         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 802         *pprog = prog;
 803 }
 804
 805 static int emit_atomic(u8 **pprog, u8 atomic_op,
 806                        u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
 807 {
 808         u8 *prog = *pprog;
 809
 810         EMIT1(0xF0); /* lock prefix */
 811
 812         maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
 813
 814         /* emit opcode */
 815         switch (atomic_op) {
 816         case BPF_ADD:
 817         case BPF_AND:
 818         case BPF_OR:
 819         case BPF_XOR:
 820                 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
 821                 EMIT1(simple_alu_opcodes[atomic_op]);
 822                 break;
 823         case BPF_ADD | BPF_FETCH:
 824                 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
 825                 EMIT2(0x0F, 0xC1);
 826                 break;
 827         case BPF_XCHG:
 828                 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
 829                 EMIT1(0x87);
 830                 break;
 831         case BPF_CMPXCHG:
 832                 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
 833                 EMIT2(0x0F, 0xB1);
 834                 break;
 835         default:
 836                 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
 837                 return -EFAULT;
 838         }
 839
 840         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 841
 842         *pprog = prog;
 843         return 0;
 844 }
 845
 846 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
 847 {
 848         u32 reg = x->fixup >> 8;
 849
 850         /* jump over faulting load and clear dest register */
 851         *(unsigned long *)((void *)regs + reg) = 0;
 852         regs->ip += x->fixup & 0xff;
 853         return true;
 854 }
 855
 856 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
 857                              bool *regs_used, bool *tail_call_seen)
 858 {
 859         int i;
 860
 861         for (i = 1; i <= insn_cnt; i++, insn++) {
 862                 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
 863                         *tail_call_seen = true;
 864                 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
 865                         regs_used[0] = true;
 866                 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
 867                         regs_used[1] = true;
 868                 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
 869                         regs_used[2] = true;
 870                 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
 871                         regs_used[3] = true;
 872         }
 873 }
 874
 875 static void emit_nops(u8 **pprog, int len)
 876 {
 877         u8 *prog = *pprog;
 878         int i, noplen;
 879
 880         while (len > 0) {
 881                 noplen = len;
 882
 883                 if (noplen > ASM_NOP_MAX)
 884                         noplen = ASM_NOP_MAX;
 885
 886                 for (i = 0; i < noplen; i++)
 887                         EMIT1(x86_nops[noplen][i]);
 888                 len -= noplen;
 889         }
 890
 891         *pprog = prog;
 892 }
 893
 894 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
 895
 896 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
 897                   int oldproglen, struct jit_context *ctx, bool jmp_padding)
 898 {
 899         bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
 900         struct bpf_insn *insn = bpf_prog->insnsi;
 901         bool callee_regs_used[4] = {};
 902         int insn_cnt = bpf_prog->len;
 903         bool tail_call_seen = false;
 904         bool seen_exit = false;
 905         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
 906         int i, excnt = 0;
 907         int ilen, proglen = 0;
 908         u8 *prog = temp;
 909         int err;
 910
 911         detect_reg_usage(insn, insn_cnt, callee_regs_used,
 912                          &tail_call_seen);
 913
 914         /* tail call's presence in current prog implies it is reachable */
 915         tail_call_reachable |= tail_call_seen;
 916
 917         emit_prologue(&prog, bpf_prog->aux->stack_depth,
 918                       bpf_prog_was_classic(bpf_prog), tail_call_reachable,
 919                       bpf_prog->aux->func_idx != 0);
 920         push_callee_regs(&prog, callee_regs_used);
 921
 922         ilen = prog - temp;
 923         if (rw_image)
 924                 memcpy(rw_image + proglen, temp, ilen);
 925         proglen += ilen;
 926         addrs[0] = proglen;
 927         prog = temp;
 928
 929         for (i = 1; i <= insn_cnt; i++, insn++) {
 930                 const s32 imm32 = insn->imm;
 931                 u32 dst_reg = insn->dst_reg;
 932                 u32 src_reg = insn->src_reg;
 933                 u8 b2 = 0, b3 = 0;
 934                 u8 *start_of_ldx;
 935                 s64 jmp_offset;
 936                 u8 jmp_cond;
 937                 u8 *func;
 938                 int nops;
 939
 940                 switch (insn->code) {
 941                         /* ALU */
 942                 case BPF_ALU | BPF_ADD | BPF_X:
 943                 case BPF_ALU | BPF_SUB | BPF_X:
 944                 case BPF_ALU | BPF_AND | BPF_X:
 945                 case BPF_ALU | BPF_OR | BPF_X:
 946                 case BPF_ALU | BPF_XOR | BPF_X:
 947                 case BPF_ALU64 | BPF_ADD | BPF_X:
 948                 case BPF_ALU64 | BPF_SUB | BPF_X:
 949                 case BPF_ALU64 | BPF_AND | BPF_X:
 950                 case BPF_ALU64 | BPF_OR | BPF_X:
 951                 case BPF_ALU64 | BPF_XOR | BPF_X:
 952                         maybe_emit_mod(&prog, dst_reg, src_reg,
 953                                        BPF_CLASS(insn->code) == BPF_ALU64);
 954                         b2 = simple_alu_opcodes[BPF_OP(insn->code)];
 955                         EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
 956                         break;
 957
 958                 case BPF_ALU64 | BPF_MOV | BPF_X:
 959                 case BPF_ALU | BPF_MOV | BPF_X:
 960                         emit_mov_reg(&prog,
 961                                      BPF_CLASS(insn->code) == BPF_ALU64,
 962                                      dst_reg, src_reg);
 963                         break;
 964
 965                         /* neg dst */
 966                 case BPF_ALU | BPF_NEG:
 967                 case BPF_ALU64 | BPF_NEG:
 968                         maybe_emit_1mod(&prog, dst_reg,
 969                                         BPF_CLASS(insn->code) == BPF_ALU64);
 970                         EMIT2(0xF7, add_1reg(0xD8, dst_reg));
 971                         break;
 972
 973                 case BPF_ALU | BPF_ADD | BPF_K:
 974                 case BPF_ALU | BPF_SUB | BPF_K:
 975                 case BPF_ALU | BPF_AND | BPF_K:
 976                 case BPF_ALU | BPF_OR | BPF_K:
 977                 case BPF_ALU | BPF_XOR | BPF_K:
 978                 case BPF_ALU64 | BPF_ADD | BPF_K:
 979                 case BPF_ALU64 | BPF_SUB | BPF_K:
 980                 case BPF_ALU64 | BPF_AND | BPF_K:
 981                 case BPF_ALU64 | BPF_OR | BPF_K:
 982                 case BPF_ALU64 | BPF_XOR | BPF_K:
 983                         maybe_emit_1mod(&prog, dst_reg,
 984                                         BPF_CLASS(insn->code) == BPF_ALU64);
 985
 986                         /*
 987                          * b3 holds 'normal' opcode, b2 short form only valid
 988                          * in case dst is eax/rax.
 989                          */
 990                         switch (BPF_OP(insn->code)) {
 991                         case BPF_ADD:
 992                                 b3 = 0xC0;
 993                                 b2 = 0x05;
 994                                 break;
 995                         case BPF_SUB:
 996                                 b3 = 0xE8;
 997                                 b2 = 0x2D;
 998                                 break;
 999                         case BPF_AND:
1000                                 b3 = 0xE0;
1001                                 b2 = 0x25;
1002                                 break;
1003                         case BPF_OR:
1004                                 b3 = 0xC8;
1005                                 b2 = 0x0D;
1006                                 break;
1007                         case BPF_XOR:
1008                                 b3 = 0xF0;
1009                                 b2 = 0x35;
1010                                 break;
1011                         }
1012
1013                         if (is_imm8(imm32))
1014                                 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1015                         else if (is_axreg(dst_reg))
1016                                 EMIT1_off32(b2, imm32);
1017                         else
1018                                 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1019                         break;
1020
1021                 case BPF_ALU64 | BPF_MOV | BPF_K:
1022                 case BPF_ALU | BPF_MOV | BPF_K:
1023                         emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1024                                        dst_reg, imm32);
1025                         break;
1026
1027                 case BPF_LD | BPF_IMM | BPF_DW:
1028                         emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1029                         insn++;
1030                         i++;
1031                         break;
1032
1033                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1034                 case BPF_ALU | BPF_MOD | BPF_X:
1035                 case BPF_ALU | BPF_DIV | BPF_X:
1036                 case BPF_ALU | BPF_MOD | BPF_K:
1037                 case BPF_ALU | BPF_DIV | BPF_K:
1038                 case BPF_ALU64 | BPF_MOD | BPF_X:
1039                 case BPF_ALU64 | BPF_DIV | BPF_X:
1040                 case BPF_ALU64 | BPF_MOD | BPF_K:
1041                 case BPF_ALU64 | BPF_DIV | BPF_K: {
1042                         bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1043
1044                         if (dst_reg != BPF_REG_0)
1045                                 EMIT1(0x50); /* push rax */
1046                         if (dst_reg != BPF_REG_3)
1047                                 EMIT1(0x52); /* push rdx */
1048
1049                         if (BPF_SRC(insn->code) == BPF_X) {
1050                                 if (src_reg == BPF_REG_0 ||
1051                                     src_reg == BPF_REG_3) {
1052                                         /* mov r11, src_reg */
1053                                         EMIT_mov(AUX_REG, src_reg);
1054                                         src_reg = AUX_REG;
1055                                 }
1056                         } else {
1057                                 /* mov r11, imm32 */
1058                                 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1059                                 src_reg = AUX_REG;
1060                         }
1061
1062                         if (dst_reg != BPF_REG_0)
1063                                 /* mov rax, dst_reg */
1064                                 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1065
1066                         /*
1067                          * xor edx, edx
1068                          * equivalent to 'xor rdx, rdx', but one byte less
1069                          */
1070                         EMIT2(0x31, 0xd2);
1071
1072                         /* div src_reg */
1073                         maybe_emit_1mod(&prog, src_reg, is64);
1074                         EMIT2(0xF7, add_1reg(0xF0, src_reg));
1075
1076                         if (BPF_OP(insn->code) == BPF_MOD &&
1077                             dst_reg != BPF_REG_3)
1078                                 /* mov dst_reg, rdx */
1079                                 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1080                         else if (BPF_OP(insn->code) == BPF_DIV &&
1081                                  dst_reg != BPF_REG_0)
1082                                 /* mov dst_reg, rax */
1083                                 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1084
1085                         if (dst_reg != BPF_REG_3)
1086                                 EMIT1(0x5A); /* pop rdx */
1087                         if (dst_reg != BPF_REG_0)
1088                                 EMIT1(0x58); /* pop rax */
1089                         break;
1090                 }
1091
1092                 case BPF_ALU | BPF_MUL | BPF_K:
1093                 case BPF_ALU64 | BPF_MUL | BPF_K:
1094                         maybe_emit_mod(&prog, dst_reg, dst_reg,
1095                                        BPF_CLASS(insn->code) == BPF_ALU64);
1096
1097                         if (is_imm8(imm32))
1098                                 /* imul dst_reg, dst_reg, imm8 */
1099                                 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1100                                       imm32);
1101                         else
1102                                 /* imul dst_reg, dst_reg, imm32 */
1103                                 EMIT2_off32(0x69,
1104                                             add_2reg(0xC0, dst_reg, dst_reg),
1105                                             imm32);
1106                         break;
1107
1108                 case BPF_ALU | BPF_MUL | BPF_X:
1109                 case BPF_ALU64 | BPF_MUL | BPF_X:
1110                         maybe_emit_mod(&prog, src_reg, dst_reg,
1111                                        BPF_CLASS(insn->code) == BPF_ALU64);
1112
1113                         /* imul dst_reg, src_reg */
1114                         EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1115                         break;
1116
1117                         /* Shifts */
1118                 case BPF_ALU | BPF_LSH | BPF_K:
1119                 case BPF_ALU | BPF_RSH | BPF_K:
1120                 case BPF_ALU | BPF_ARSH | BPF_K:
1121                 case BPF_ALU64 | BPF_LSH | BPF_K:
1122                 case BPF_ALU64 | BPF_RSH | BPF_K:
1123                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1124                         maybe_emit_1mod(&prog, dst_reg,
1125                                         BPF_CLASS(insn->code) == BPF_ALU64);
1126
1127                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1128                         if (imm32 == 1)
1129                                 EMIT2(0xD1, add_1reg(b3, dst_reg));
1130                         else
1131                                 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1132                         break;
1133
1134                 case BPF_ALU | BPF_LSH | BPF_X:
1135                 case BPF_ALU | BPF_RSH | BPF_X:
1136                 case BPF_ALU | BPF_ARSH | BPF_X:
1137                 case BPF_ALU64 | BPF_LSH | BPF_X:
1138                 case BPF_ALU64 | BPF_RSH | BPF_X:
1139                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1140
1141                         /* Check for bad case when dst_reg == rcx */
1142                         if (dst_reg == BPF_REG_4) {
1143                                 /* mov r11, dst_reg */
1144                                 EMIT_mov(AUX_REG, dst_reg);
1145                                 dst_reg = AUX_REG;
1146                         }
1147
1148                         if (src_reg != BPF_REG_4) { /* common case */
1149                                 EMIT1(0x51); /* push rcx */
1150
1151                                 /* mov rcx, src_reg */
1152                                 EMIT_mov(BPF_REG_4, src_reg);
1153                         }
1154
1155                         /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1156                         maybe_emit_1mod(&prog, dst_reg,
1157                                         BPF_CLASS(insn->code) == BPF_ALU64);
1158
1159                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1160                         EMIT2(0xD3, add_1reg(b3, dst_reg));
1161
1162                         if (src_reg != BPF_REG_4)
1163                                 EMIT1(0x59); /* pop rcx */
1164
1165                         if (insn->dst_reg == BPF_REG_4)
1166                                 /* mov dst_reg, r11 */
1167                                 EMIT_mov(insn->dst_reg, AUX_REG);
1168                         break;
1169
1170                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1171                         switch (imm32) {
1172                         case 16:
1173                                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1174                                 EMIT1(0x66);
1175                                 if (is_ereg(dst_reg))
1176                                         EMIT1(0x41);
1177                                 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1178
1179                                 /* Emit 'movzwl eax, ax' */
1180                                 if (is_ereg(dst_reg))
1181                                         EMIT3(0x45, 0x0F, 0xB7);
1182                                 else
1183                                         EMIT2(0x0F, 0xB7);
1184                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1185                                 break;
1186                         case 32:
1187                                 /* Emit 'bswap eax' to swap lower 4 bytes */
1188                                 if (is_ereg(dst_reg))
1189                                         EMIT2(0x41, 0x0F);
1190                                 else
1191                                         EMIT1(0x0F);
1192                                 EMIT1(add_1reg(0xC8, dst_reg));
1193                                 break;
1194                         case 64:
1195                                 /* Emit 'bswap rax' to swap 8 bytes */
1196                                 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1197                                       add_1reg(0xC8, dst_reg));
1198                                 break;
1199                         }
1200                         break;
1201
1202                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1203                         switch (imm32) {
1204                         case 16:
1205                                 /*
1206                                  * Emit 'movzwl eax, ax' to zero extend 16-bit
1207                                  * into 64 bit
1208                                  */
1209                                 if (is_ereg(dst_reg))
1210                                         EMIT3(0x45, 0x0F, 0xB7);
1211                                 else
1212                                         EMIT2(0x0F, 0xB7);
1213                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1214                                 break;
1215                         case 32:
1216                                 /* Emit 'mov eax, eax' to clear upper 32-bits */
1217                                 if (is_ereg(dst_reg))
1218                                         EMIT1(0x45);
1219                                 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1220                                 break;
1221                         case 64:
1222                                 /* nop */
1223                                 break;
1224                         }
1225                         break;
1226
1227                         /* speculation barrier */
1228                 case BPF_ST | BPF_NOSPEC:
1229                         if (boot_cpu_has(X86_FEATURE_XMM2))
1230                                 EMIT_LFENCE();
1231                         break;
1232
1233                         /* ST: *(u8*)(dst_reg + off) = imm */
1234                 case BPF_ST | BPF_MEM | BPF_B:
1235                         if (is_ereg(dst_reg))
1236                                 EMIT2(0x41, 0xC6);
1237                         else
1238                                 EMIT1(0xC6);
1239                         goto st;
1240                 case BPF_ST | BPF_MEM | BPF_H:
1241                         if (is_ereg(dst_reg))
1242                                 EMIT3(0x66, 0x41, 0xC7);
1243                         else
1244                                 EMIT2(0x66, 0xC7);
1245                         goto st;
1246                 case BPF_ST | BPF_MEM | BPF_W:
1247                         if (is_ereg(dst_reg))
1248                                 EMIT2(0x41, 0xC7);
1249                         else
1250                                 EMIT1(0xC7);
1251                         goto st;
1252                 case BPF_ST | BPF_MEM | BPF_DW:
1253                         EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1254
1255 st:                     if (is_imm8(insn->off))
1256                                 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1257                         else
1258                                 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1259
1260                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1261                         break;
1262
1263                         /* STX: *(u8*)(dst_reg + off) = src_reg */
1264                 case BPF_STX | BPF_MEM | BPF_B:
1265                 case BPF_STX | BPF_MEM | BPF_H:
1266                 case BPF_STX | BPF_MEM | BPF_W:
1267                 case BPF_STX | BPF_MEM | BPF_DW:
1268                         emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1269                         break;
1270
1271                         /* LDX: dst_reg = *(u8*)(src_reg + off) */
1272                 case BPF_LDX | BPF_MEM | BPF_B:
1273                 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1274                 case BPF_LDX | BPF_MEM | BPF_H:
1275                 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1276                 case BPF_LDX | BPF_MEM | BPF_W:
1277                 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1278                 case BPF_LDX | BPF_MEM | BPF_DW:
1279                 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1280                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1281                                 /* Though the verifier prevents negative insn->off in BPF_PROBE_MEM
1282                                  * add abs(insn->off) to the limit to make sure that negative
1283                                  * offset won't be an issue.
1284                                  * insn->off is s16, so it won't affect valid pointers.
1285                                  */
1286                                 u64 limit = TASK_SIZE_MAX + PAGE_SIZE + abs(insn->off);
1287                                 u8 *end_of_jmp1, *end_of_jmp2;
1288
1289                                 /* Conservatively check that src_reg + insn->off is a kernel address:
1290                                  * 1. src_reg + insn->off >= limit
1291                                  * 2. src_reg + insn->off doesn't become small positive.
1292                                  * Cannot do src_reg + insn->off >= limit in one branch,
1293                                  * since it needs two spare registers, but JIT has only one.
1294                                  */
1295
1296                                 /* movabsq r11, limit */
1297                                 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1298                                 EMIT((u32)limit, 4);
1299                                 EMIT(limit >> 32, 4);
1300                                 /* cmp src_reg, r11 */
1301                                 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1302                                 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1303                                 /* if unsigned '<' goto end_of_jmp2 */
1304                                 EMIT2(X86_JB, 0);
1305                                 end_of_jmp1 = prog;
1306
1307                                 /* mov r11, src_reg */
1308                                 emit_mov_reg(&prog, true, AUX_REG, src_reg);
1309                                 /* add r11, insn->off */
1310                                 maybe_emit_1mod(&prog, AUX_REG, true);
1311                                 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1312                                 /* jmp if not carry to start_of_ldx
1313                                  * Otherwise ERR_PTR(-EINVAL) + 128 will be the user addr
1314                                  * that has to be rejected.
1315                                  */
1316                                 EMIT2(0x73 /* JNC */, 0);
1317                                 end_of_jmp2 = prog;
1318
1319                                 /* xor dst_reg, dst_reg */
1320                                 emit_mov_imm32(&prog, false, dst_reg, 0);
1321                                 /* jmp byte_after_ldx */
1322                                 EMIT2(0xEB, 0);
1323
1324                                 /* populate jmp_offset for JB above to jump to xor dst_reg */
1325                                 end_of_jmp1[-1] = end_of_jmp2 - end_of_jmp1;
1326                                 /* populate jmp_offset for JNC above to jump to start_of_ldx */
1327                                 start_of_ldx = prog;
1328                                 end_of_jmp2[-1] = start_of_ldx - end_of_jmp2;
1329                         }
1330                         emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1331                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1332                                 struct exception_table_entry *ex;
1333                                 u8 *_insn = image + proglen + (start_of_ldx - temp);
1334                                 s64 delta;
1335
1336                                 /* populate jmp_offset for JMP above */
1337                                 start_of_ldx[-1] = prog - start_of_ldx;
1338
1339                                 if (!bpf_prog->aux->extable)
1340                                         break;
1341
1342                                 if (excnt >= bpf_prog->aux->num_exentries) {
1343                                         pr_err("ex gen bug\n");
1344                                         return -EFAULT;
1345                                 }
1346                                 ex = &bpf_prog->aux->extable[excnt++];
1347
1348                                 delta = _insn - (u8 *)&ex->insn;
1349                                 if (!is_simm32(delta)) {
1350                                         pr_err("extable->insn doesn't fit into 32-bit\n");
1351                                         return -EFAULT;
1352                                 }
1353                                 /* switch ex to rw buffer for writes */
1354                                 ex = (void *)rw_image + ((void *)ex - (void *)image);
1355
1356                                 ex->insn = delta;
1357
1358                                 ex->data = EX_TYPE_BPF;
1359
1360                                 if (dst_reg > BPF_REG_9) {
1361                                         pr_err("verifier error\n");
1362                                         return -EFAULT;
1363                                 }
1364                                 /*
1365                                  * Compute size of x86 insn and its target dest x86 register.
1366                                  * ex_handler_bpf() will use lower 8 bits to adjust
1367                                  * pt_regs->ip to jump over this x86 instruction
1368                                  * and upper bits to figure out which pt_regs to zero out.
1369                                  * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1370                                  * of 4 bytes will be ignored and rbx will be zero inited.
1371                                  */
1372                                 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1373                         }
1374                         break;
1375
1376                 case BPF_STX | BPF_ATOMIC | BPF_W:
1377                 case BPF_STX | BPF_ATOMIC | BPF_DW:
1378                         if (insn->imm == (BPF_AND | BPF_FETCH) ||
1379                             insn->imm == (BPF_OR | BPF_FETCH) ||
1380                             insn->imm == (BPF_XOR | BPF_FETCH)) {
1381                                 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1382                                 u32 real_src_reg = src_reg;
1383                                 u32 real_dst_reg = dst_reg;
1384                                 u8 *branch_target;
1385
1386                                 /*
1387                                  * Can't be implemented with a single x86 insn.
1388                                  * Need to do a CMPXCHG loop.
1389                                  */
1390
1391                                 /* Will need RAX as a CMPXCHG operand so save R0 */
1392                                 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1393                                 if (src_reg == BPF_REG_0)
1394                                         real_src_reg = BPF_REG_AX;
1395                                 if (dst_reg == BPF_REG_0)
1396                                         real_dst_reg = BPF_REG_AX;
1397
1398                                 branch_target = prog;
1399                                 /* Load old value */
1400                                 emit_ldx(&prog, BPF_SIZE(insn->code),
1401                                          BPF_REG_0, real_dst_reg, insn->off);
1402                                 /*
1403                                  * Perform the (commutative) operation locally,
1404                                  * put the result in the AUX_REG.
1405                                  */
1406                                 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1407                                 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1408                                 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1409                                       add_2reg(0xC0, AUX_REG, real_src_reg));
1410                                 /* Attempt to swap in new value */
1411                                 err = emit_atomic(&prog, BPF_CMPXCHG,
1412                                                   real_dst_reg, AUX_REG,
1413                                                   insn->off,
1414                                                   BPF_SIZE(insn->code));
1415                                 if (WARN_ON(err))
1416                                         return err;
1417                                 /*
1418                                  * ZF tells us whether we won the race. If it's
1419                                  * cleared we need to try again.
1420                                  */
1421                                 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1422                                 /* Return the pre-modification value */
1423                                 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1424                                 /* Restore R0 after clobbering RAX */
1425                                 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1426                                 break;
1427                         }
1428
1429                         err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1430                                           insn->off, BPF_SIZE(insn->code));
1431                         if (err)
1432                                 return err;
1433                         break;
1434
1435                         /* call */
1436                 case BPF_JMP | BPF_CALL:
1437                         func = (u8 *) __bpf_call_base + imm32;
1438                         if (tail_call_reachable) {
1439                                 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1440                                 EMIT3_off32(0x48, 0x8B, 0x85,
1441                                             -round_up(bpf_prog->aux->stack_depth, 8) - 8);
1442                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
1443                                         return -EINVAL;
1444                         } else {
1445                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1]))
1446                                         return -EINVAL;
1447                         }
1448                         break;
1449
1450                 case BPF_JMP | BPF_TAIL_CALL:
1451                         if (imm32)
1452                                 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1453                                                           &prog, image + addrs[i - 1],
1454                                                           callee_regs_used,
1455                                                           bpf_prog->aux->stack_depth,
1456                                                           ctx);
1457                         else
1458                                 emit_bpf_tail_call_indirect(&prog,
1459                                                             callee_regs_used,
1460                                                             bpf_prog->aux->stack_depth,
1461                                                             image + addrs[i - 1],
1462                                                             ctx);
1463                         break;
1464
1465                         /* cond jump */
1466                 case BPF_JMP | BPF_JEQ | BPF_X:
1467                 case BPF_JMP | BPF_JNE | BPF_X:
1468                 case BPF_JMP | BPF_JGT | BPF_X:
1469                 case BPF_JMP | BPF_JLT | BPF_X:
1470                 case BPF_JMP | BPF_JGE | BPF_X:
1471                 case BPF_JMP | BPF_JLE | BPF_X:
1472                 case BPF_JMP | BPF_JSGT | BPF_X:
1473                 case BPF_JMP | BPF_JSLT | BPF_X:
1474                 case BPF_JMP | BPF_JSGE | BPF_X:
1475                 case BPF_JMP | BPF_JSLE | BPF_X:
1476                 case BPF_JMP32 | BPF_JEQ | BPF_X:
1477                 case BPF_JMP32 | BPF_JNE | BPF_X:
1478                 case BPF_JMP32 | BPF_JGT | BPF_X:
1479                 case BPF_JMP32 | BPF_JLT | BPF_X:
1480                 case BPF_JMP32 | BPF_JGE | BPF_X:
1481                 case BPF_JMP32 | BPF_JLE | BPF_X:
1482                 case BPF_JMP32 | BPF_JSGT | BPF_X:
1483                 case BPF_JMP32 | BPF_JSLT | BPF_X:
1484                 case BPF_JMP32 | BPF_JSGE | BPF_X:
1485                 case BPF_JMP32 | BPF_JSLE | BPF_X:
1486                         /* cmp dst_reg, src_reg */
1487                         maybe_emit_mod(&prog, dst_reg, src_reg,
1488                                        BPF_CLASS(insn->code) == BPF_JMP);
1489                         EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1490                         goto emit_cond_jmp;
1491
1492                 case BPF_JMP | BPF_JSET | BPF_X:
1493                 case BPF_JMP32 | BPF_JSET | BPF_X:
1494                         /* test dst_reg, src_reg */
1495                         maybe_emit_mod(&prog, dst_reg, src_reg,
1496                                        BPF_CLASS(insn->code) == BPF_JMP);
1497                         EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1498                         goto emit_cond_jmp;
1499
1500                 case BPF_JMP | BPF_JSET | BPF_K:
1501                 case BPF_JMP32 | BPF_JSET | BPF_K:
1502                         /* test dst_reg, imm32 */
1503                         maybe_emit_1mod(&prog, dst_reg,
1504                                         BPF_CLASS(insn->code) == BPF_JMP);
1505                         EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1506                         goto emit_cond_jmp;
1507
1508                 case BPF_JMP | BPF_JEQ | BPF_K:
1509                 case BPF_JMP | BPF_JNE | BPF_K:
1510                 case BPF_JMP | BPF_JGT | BPF_K:
1511                 case BPF_JMP | BPF_JLT | BPF_K:
1512                 case BPF_JMP | BPF_JGE | BPF_K:
1513                 case BPF_JMP | BPF_JLE | BPF_K:
1514                 case BPF_JMP | BPF_JSGT | BPF_K:
1515                 case BPF_JMP | BPF_JSLT | BPF_K:
1516                 case BPF_JMP | BPF_JSGE | BPF_K:
1517                 case BPF_JMP | BPF_JSLE | BPF_K:
1518                 case BPF_JMP32 | BPF_JEQ | BPF_K:
1519                 case BPF_JMP32 | BPF_JNE | BPF_K:
1520                 case BPF_JMP32 | BPF_JGT | BPF_K:
1521                 case BPF_JMP32 | BPF_JLT | BPF_K:
1522                 case BPF_JMP32 | BPF_JGE | BPF_K:
1523                 case BPF_JMP32 | BPF_JLE | BPF_K:
1524                 case BPF_JMP32 | BPF_JSGT | BPF_K:
1525                 case BPF_JMP32 | BPF_JSLT | BPF_K:
1526                 case BPF_JMP32 | BPF_JSGE | BPF_K:
1527                 case BPF_JMP32 | BPF_JSLE | BPF_K:
1528                         /* test dst_reg, dst_reg to save one extra byte */
1529                         if (imm32 == 0) {
1530                                 maybe_emit_mod(&prog, dst_reg, dst_reg,
1531                                                BPF_CLASS(insn->code) == BPF_JMP);
1532                                 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1533                                 goto emit_cond_jmp;
1534                         }
1535
1536                         /* cmp dst_reg, imm8/32 */
1537                         maybe_emit_1mod(&prog, dst_reg,
1538                                         BPF_CLASS(insn->code) == BPF_JMP);
1539
1540                         if (is_imm8(imm32))
1541                                 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1542                         else
1543                                 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1544
1545 emit_cond_jmp:          /* Convert BPF opcode to x86 */
1546                         switch (BPF_OP(insn->code)) {
1547                         case BPF_JEQ:
1548                                 jmp_cond = X86_JE;
1549                                 break;
1550                         case BPF_JSET:
1551                         case BPF_JNE:
1552                                 jmp_cond = X86_JNE;
1553                                 break;
1554                         case BPF_JGT:
1555                                 /* GT is unsigned '>', JA in x86 */
1556                                 jmp_cond = X86_JA;
1557                                 break;
1558                         case BPF_JLT:
1559                                 /* LT is unsigned '<', JB in x86 */
1560                                 jmp_cond = X86_JB;
1561                                 break;
1562                         case BPF_JGE:
1563                                 /* GE is unsigned '>=', JAE in x86 */
1564                                 jmp_cond = X86_JAE;
1565                                 break;
1566                         case BPF_JLE:
1567                                 /* LE is unsigned '<=', JBE in x86 */
1568                                 jmp_cond = X86_JBE;
1569                                 break;
1570                         case BPF_JSGT:
1571                                 /* Signed '>', GT in x86 */
1572                                 jmp_cond = X86_JG;
1573                                 break;
1574                         case BPF_JSLT:
1575                                 /* Signed '<', LT in x86 */
1576                                 jmp_cond = X86_JL;
1577                                 break;
1578                         case BPF_JSGE:
1579                                 /* Signed '>=', GE in x86 */
1580                                 jmp_cond = X86_JGE;
1581                                 break;
1582                         case BPF_JSLE:
1583                                 /* Signed '<=', LE in x86 */
1584                                 jmp_cond = X86_JLE;
1585                                 break;
1586                         default: /* to silence GCC warning */
1587                                 return -EFAULT;
1588                         }
1589                         jmp_offset = addrs[i + insn->off] - addrs[i];
1590                         if (is_imm8(jmp_offset)) {
1591                                 if (jmp_padding) {
1592                                         /* To keep the jmp_offset valid, the extra bytes are
1593                                          * padded before the jump insn, so we subtract the
1594                                          * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1595                                          *
1596                                          * If the previous pass already emits an imm8
1597                                          * jmp_cond, then this BPF insn won't shrink, so
1598                                          * "nops" is 0.
1599                                          *
1600                                          * On the other hand, if the previous pass emits an
1601                                          * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1602                                          * keep the image from shrinking further.
1603                                          *
1604                                          * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1605                                          *     is 2 bytes, so the size difference is 4 bytes.
1606                                          */
1607                                         nops = INSN_SZ_DIFF - 2;
1608                                         if (nops != 0 && nops != 4) {
1609                                                 pr_err("unexpected jmp_cond padding: %d bytes\n",
1610                                                        nops);
1611                                                 return -EFAULT;
1612                                         }
1613                                         emit_nops(&prog, nops);
1614                                 }
1615                                 EMIT2(jmp_cond, jmp_offset);
1616                         } else if (is_simm32(jmp_offset)) {
1617                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1618                         } else {
1619                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1620                                 return -EFAULT;
1621                         }
1622
1623                         break;
1624
1625                 case BPF_JMP | BPF_JA:
1626                         if (insn->off == -1)
1627                                 /* -1 jmp instructions will always jump
1628                                  * backwards two bytes. Explicitly handling
1629                                  * this case avoids wasting too many passes
1630                                  * when there are long sequences of replaced
1631                                  * dead code.
1632                                  */
1633                                 jmp_offset = -2;
1634                         else
1635                                 jmp_offset = addrs[i + insn->off] - addrs[i];
1636
1637                         if (!jmp_offset) {
1638                                 /*
1639                                  * If jmp_padding is enabled, the extra nops will
1640                                  * be inserted. Otherwise, optimize out nop jumps.
1641                                  */
1642                                 if (jmp_padding) {
1643                                         /* There are 3 possible conditions.
1644                                          * (1) This BPF_JA is already optimized out in
1645                                          *     the previous run, so there is no need
1646                                          *     to pad any extra byte (0 byte).
1647                                          * (2) The previous pass emits an imm8 jmp,
1648                                          *     so we pad 2 bytes to match the previous
1649                                          *     insn size.
1650                                          * (3) Similarly, the previous pass emits an
1651                                          *     imm32 jmp, and 5 bytes is padded.
1652                                          */
1653                                         nops = INSN_SZ_DIFF;
1654                                         if (nops != 0 && nops != 2 && nops != 5) {
1655                                                 pr_err("unexpected nop jump padding: %d bytes\n",
1656                                                        nops);
1657                                                 return -EFAULT;
1658                                         }
1659                                         emit_nops(&prog, nops);
1660                                 }
1661                                 break;
1662                         }
1663 emit_jmp:
1664                         if (is_imm8(jmp_offset)) {
1665                                 if (jmp_padding) {
1666                                         /* To avoid breaking jmp_offset, the extra bytes
1667                                          * are padded before the actual jmp insn, so
1668                                          * 2 bytes is subtracted from INSN_SZ_DIFF.
1669                                          *
1670                                          * If the previous pass already emits an imm8
1671                                          * jmp, there is nothing to pad (0 byte).
1672                                          *
1673                                          * If it emits an imm32 jmp (5 bytes) previously
1674                                          * and now an imm8 jmp (2 bytes), then we pad
1675                                          * (5 - 2 = 3) bytes to stop the image from
1676                                          * shrinking further.
1677                                          */
1678                                         nops = INSN_SZ_DIFF - 2;
1679                                         if (nops != 0 && nops != 3) {
1680                                                 pr_err("unexpected jump padding: %d bytes\n",
1681                                                        nops);
1682                                                 return -EFAULT;
1683                                         }
1684                                         emit_nops(&prog, INSN_SZ_DIFF - 2);
1685                                 }
1686                                 EMIT2(0xEB, jmp_offset);
1687                         } else if (is_simm32(jmp_offset)) {
1688                                 EMIT1_off32(0xE9, jmp_offset);
1689                         } else {
1690                                 pr_err("jmp gen bug %llx\n", jmp_offset);
1691                                 return -EFAULT;
1692                         }
1693                         break;
1694
1695                 case BPF_JMP | BPF_EXIT:
1696                         if (seen_exit) {
1697                                 jmp_offset = ctx->cleanup_addr - addrs[i];
1698                                 goto emit_jmp;
1699                         }
1700                         seen_exit = true;
1701                         /* Update cleanup_addr */
1702                         ctx->cleanup_addr = proglen;
1703                         pop_callee_regs(&prog, callee_regs_used);
1704                         EMIT1(0xC9);         /* leave */
1705                         emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1706                         break;
1707
1708                 default:
1709                         /*
1710                          * By design x86-64 JIT should support all BPF instructions.
1711                          * This error will be seen if new instruction was added
1712                          * to the interpreter, but not to the JIT, or if there is
1713                          * junk in bpf_prog.
1714                          */
1715                         pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1716                         return -EINVAL;
1717                 }
1718
1719                 ilen = prog - temp;
1720                 if (ilen > BPF_MAX_INSN_SIZE) {
1721                         pr_err("bpf_jit: fatal insn size error\n");
1722                         return -EFAULT;
1723                 }
1724
1725                 if (image) {
1726                         /*
1727                          * When populating the image, assert that:
1728                          *
1729                          *  i) We do not write beyond the allocated space, and
1730                          * ii) addrs[i] did not change from the prior run, in order
1731                          *     to validate assumptions made for computing branch
1732                          *     displacements.
1733                          */
1734                         if (unlikely(proglen + ilen > oldproglen ||
1735                                      proglen + ilen != addrs[i])) {
1736                                 pr_err("bpf_jit: fatal error\n");
1737                                 return -EFAULT;
1738                         }
1739                         memcpy(rw_image + proglen, temp, ilen);
1740                 }
1741                 proglen += ilen;
1742                 addrs[i] = proglen;
1743                 prog = temp;
1744         }
1745
1746         if (image && excnt != bpf_prog->aux->num_exentries) {
1747                 pr_err("extable is not populated\n");
1748                 return -EFAULT;
1749         }
1750         return proglen;
1751 }
1752
1753 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1754                       int stack_size)
1755 {
1756         int i, j, arg_size, nr_regs;
1757         /* Store function arguments to stack.
1758          * For a function that accepts two pointers the sequence will be:
1759          * mov QWORD PTR [rbp-0x10],rdi
1760          * mov QWORD PTR [rbp-0x8],rsi
1761          */
1762         for (i = 0, j = 0; i < min(nr_args, 6); i++) {
1763                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) {
1764                         nr_regs = (m->arg_size[i] + 7) / 8;
1765                         arg_size = 8;
1766                 } else {
1767                         nr_regs = 1;
1768                         arg_size = m->arg_size[i];
1769                 }
1770
1771                 while (nr_regs) {
1772                         emit_stx(prog, bytes_to_bpf_size(arg_size),
1773                                  BPF_REG_FP,
1774                                  j == 5 ? X86_REG_R9 : BPF_REG_1 + j,
1775                                  -(stack_size - j * 8));
1776                         nr_regs--;
1777                         j++;
1778                 }
1779         }
1780 }
1781
1782 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1783                          int stack_size)
1784 {
1785         int i, j, arg_size, nr_regs;
1786
1787         /* Restore function arguments from stack.
1788          * For a function that accepts two pointers the sequence will be:
1789          * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1790          * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1791          */
1792         for (i = 0, j = 0; i < min(nr_args, 6); i++) {
1793                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) {
1794                         nr_regs = (m->arg_size[i] + 7) / 8;
1795                         arg_size = 8;
1796                 } else {
1797                         nr_regs = 1;
1798                         arg_size = m->arg_size[i];
1799                 }
1800
1801                 while (nr_regs) {
1802                         emit_ldx(prog, bytes_to_bpf_size(arg_size),
1803                                  j == 5 ? X86_REG_R9 : BPF_REG_1 + j,
1804                                  BPF_REG_FP,
1805                                  -(stack_size - j * 8));
1806                         nr_regs--;
1807                         j++;
1808                 }
1809         }
1810 }
1811
1812 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1813                            struct bpf_tramp_link *l, int stack_size,
1814                            int run_ctx_off, bool save_ret)
1815 {
1816         void (*exit)(struct bpf_prog *prog, u64 start,
1817                      struct bpf_tramp_run_ctx *run_ctx) = __bpf_prog_exit;
1818         u64 (*enter)(struct bpf_prog *prog,
1819                      struct bpf_tramp_run_ctx *run_ctx) = __bpf_prog_enter;
1820         u8 *prog = *pprog;
1821         u8 *jmp_insn;
1822         int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
1823         struct bpf_prog *p = l->link.prog;
1824         u64 cookie = l->cookie;
1825
1826         /* mov rdi, cookie */
1827         emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
1828
1829         /* Prepare struct bpf_tramp_run_ctx.
1830          *
1831          * bpf_tramp_run_ctx is already preserved by
1832          * arch_prepare_bpf_trampoline().
1833          *
1834          * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
1835          */
1836         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
1837
1838         if (p->aux->sleepable) {
1839                 enter = __bpf_prog_enter_sleepable;
1840                 exit = __bpf_prog_exit_sleepable;
1841         } else if (p->type == BPF_PROG_TYPE_STRUCT_OPS) {
1842                 enter = __bpf_prog_enter_struct_ops;
1843                 exit = __bpf_prog_exit_struct_ops;
1844         } else if (p->expected_attach_type == BPF_LSM_CGROUP) {
1845                 enter = __bpf_prog_enter_lsm_cgroup;
1846                 exit = __bpf_prog_exit_lsm_cgroup;
1847         }
1848
1849         /* arg1: mov rdi, progs[i] */
1850         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1851         /* arg2: lea rsi, [rbp - ctx_cookie_off] */
1852         EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
1853
1854         if (emit_call(&prog, enter, prog))
1855                 return -EINVAL;
1856         /* remember prog start time returned by __bpf_prog_enter */
1857         emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1858
1859         /* if (__bpf_prog_enter*(prog) == 0)
1860          *      goto skip_exec_of_prog;
1861          */
1862         EMIT3(0x48, 0x85, 0xC0);  /* test rax,rax */
1863         /* emit 2 nops that will be replaced with JE insn */
1864         jmp_insn = prog;
1865         emit_nops(&prog, 2);
1866
1867         /* arg1: lea rdi, [rbp - stack_size] */
1868         EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1869         /* arg2: progs[i]->insnsi for interpreter */
1870         if (!p->jited)
1871                 emit_mov_imm64(&prog, BPF_REG_2,
1872                                (long) p->insnsi >> 32,
1873                                (u32) (long) p->insnsi);
1874         /* call JITed bpf program or interpreter */
1875         if (emit_call(&prog, p->bpf_func, prog))
1876                 return -EINVAL;
1877
1878         /*
1879          * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1880          * of the previous call which is then passed on the stack to
1881          * the next BPF program.
1882          *
1883          * BPF_TRAMP_FENTRY trampoline may need to return the return
1884          * value of BPF_PROG_TYPE_STRUCT_OPS prog.
1885          */
1886         if (save_ret)
1887                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1888
1889         /* replace 2 nops with JE insn, since jmp target is known */
1890         jmp_insn[0] = X86_JE;
1891         jmp_insn[1] = prog - jmp_insn - 2;
1892
1893         /* arg1: mov rdi, progs[i] */
1894         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1895         /* arg2: mov rsi, rbx <- start time in nsec */
1896         emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1897         /* arg3: lea rdx, [rbp - run_ctx_off] */
1898         EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
1899         if (emit_call(&prog, exit, prog))
1900                 return -EINVAL;
1901
1902         *pprog = prog;
1903         return 0;
1904 }
1905
1906 static void emit_align(u8 **pprog, u32 align)
1907 {
1908         u8 *target, *prog = *pprog;
1909
1910         target = PTR_ALIGN(prog, align);
1911         if (target != prog)
1912                 emit_nops(&prog, target - prog);
1913
1914         *pprog = prog;
1915 }
1916
1917 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
1918 {
1919         u8 *prog = *pprog;
1920         s64 offset;
1921
1922         offset = func - (ip + 2 + 4);
1923         if (!is_simm32(offset)) {
1924                 pr_err("Target %p is out of range\n", func);
1925                 return -EINVAL;
1926         }
1927         EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
1928         *pprog = prog;
1929         return 0;
1930 }
1931
1932 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
1933                       struct bpf_tramp_links *tl, int stack_size,
1934                       int run_ctx_off, bool save_ret)
1935 {
1936         int i;
1937         u8 *prog = *pprog;
1938
1939         for (i = 0; i < tl->nr_links; i++) {
1940                 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
1941                                     run_ctx_off, save_ret))
1942                         return -EINVAL;
1943         }
1944         *pprog = prog;
1945         return 0;
1946 }
1947
1948 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
1949                               struct bpf_tramp_links *tl, int stack_size,
1950                               int run_ctx_off, u8 **branches)
1951 {
1952         u8 *prog = *pprog;
1953         int i;
1954
1955         /* The first fmod_ret program will receive a garbage return value.
1956          * Set this to 0 to avoid confusing the program.
1957          */
1958         emit_mov_imm32(&prog, false, BPF_REG_0, 0);
1959         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1960         for (i = 0; i < tl->nr_links; i++) {
1961                 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true))
1962                         return -EINVAL;
1963
1964                 /* mod_ret prog stored return value into [rbp - 8]. Emit:
1965                  * if (*(u64 *)(rbp - 8) !=  0)
1966                  *      goto do_fexit;
1967                  */
1968                 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
1969                 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
1970
1971                 /* Save the location of the branch and Generate 6 nops
1972                  * (4 bytes for an offset and 2 bytes for the jump) These nops
1973                  * are replaced with a conditional jump once do_fexit (i.e. the
1974                  * start of the fexit invocation) is finalized.
1975                  */
1976                 branches[i] = prog;
1977                 emit_nops(&prog, 4 + 2);
1978         }
1979
1980         *pprog = prog;
1981         return 0;
1982 }
1983
1984 /* Example:
1985  * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
1986  * its 'struct btf_func_model' will be nr_args=2
1987  * The assembly code when eth_type_trans is executing after trampoline:
1988  *
1989  * push rbp
1990  * mov rbp, rsp
1991  * sub rsp, 16                     // space for skb and dev
1992  * push rbx                        // temp regs to pass start time
1993  * mov qword ptr [rbp - 16], rdi   // save skb pointer to stack
1994  * mov qword ptr [rbp - 8], rsi    // save dev pointer to stack
1995  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1996  * mov rbx, rax                    // remember start time in bpf stats are enabled
1997  * lea rdi, [rbp - 16]             // R1==ctx of bpf prog
1998  * call addr_of_jited_FENTRY_prog
1999  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2000  * mov rsi, rbx                    // prog start time
2001  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2002  * mov rdi, qword ptr [rbp - 16]   // restore skb pointer from stack
2003  * mov rsi, qword ptr [rbp - 8]    // restore dev pointer from stack
2004  * pop rbx
2005  * leave
2006  * ret
2007  *
2008  * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
2009  * replaced with 'call generated_bpf_trampoline'. When it returns
2010  * eth_type_trans will continue executing with original skb and dev pointers.
2011  *
2012  * The assembly code when eth_type_trans is called from trampoline:
2013  *
2014  * push rbp
2015  * mov rbp, rsp
2016  * sub rsp, 24                     // space for skb, dev, return value
2017  * push rbx                        // temp regs to pass start time
2018  * mov qword ptr [rbp - 24], rdi   // save skb pointer to stack
2019  * mov qword ptr [rbp - 16], rsi   // save dev pointer to stack
2020  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2021  * mov rbx, rax                    // remember start time if bpf stats are enabled
2022  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
2023  * call addr_of_jited_FENTRY_prog  // bpf prog can access skb and dev
2024  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2025  * mov rsi, rbx                    // prog start time
2026  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2027  * mov rdi, qword ptr [rbp - 24]   // restore skb pointer from stack
2028  * mov rsi, qword ptr [rbp - 16]   // restore dev pointer from stack
2029  * call eth_type_trans+5           // execute body of eth_type_trans
2030  * mov qword ptr [rbp - 8], rax    // save return value
2031  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2032  * mov rbx, rax                    // remember start time in bpf stats are enabled
2033  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
2034  * call addr_of_jited_FEXIT_prog   // bpf prog can access skb, dev, return value
2035  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2036  * mov rsi, rbx                    // prog start time
2037  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2038  * mov rax, qword ptr [rbp - 8]    // restore eth_type_trans's return value
2039  * pop rbx
2040  * leave
2041  * add rsp, 8                      // skip eth_type_trans's frame
2042  * ret                             // return to its caller
2043  */
2044 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2045                                 const struct btf_func_model *m, u32 flags,
2046                                 struct bpf_tramp_links *tlinks,
2047                                 void *func_addr)
2048 {
2049         int ret, i, nr_args = m->nr_args, extra_nregs = 0;
2050         int regs_off, ip_off, args_off, stack_size = nr_args * 8, run_ctx_off;
2051         struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2052         struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2053         struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2054         void *orig_call = func_addr;
2055         u8 **branches = NULL;
2056         u8 *prog;
2057         bool save_ret;
2058
2059         /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
2060         if (nr_args > 6)
2061                 return -ENOTSUPP;
2062
2063         for (i = 0; i < MAX_BPF_FUNC_ARGS; i++) {
2064                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2065                         extra_nregs += (m->arg_size[i] + 7) / 8 - 1;
2066         }
2067         if (nr_args + extra_nregs > 6)
2068                 return -ENOTSUPP;
2069         stack_size += extra_nregs * 8;
2070
2071         /* Generated trampoline stack layout:
2072          *
2073          * RBP + 8         [ return address  ]
2074          * RBP + 0         [ RBP             ]
2075          *
2076          * RBP - 8         [ return value    ]  BPF_TRAMP_F_CALL_ORIG or
2077          *                                      BPF_TRAMP_F_RET_FENTRY_RET flags
2078          *
2079          *                 [ reg_argN        ]  always
2080          *                 [ ...             ]
2081          * RBP - regs_off  [ reg_arg1        ]  program's ctx pointer
2082          *
2083          * RBP - args_off  [ arg regs count  ]  always
2084          *
2085          * RBP - ip_off    [ traced function ]  BPF_TRAMP_F_IP_ARG flag
2086          *
2087          * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2088          */
2089
2090         /* room for return value of orig_call or fentry prog */
2091         save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2092         if (save_ret)
2093                 stack_size += 8;
2094
2095         regs_off = stack_size;
2096
2097         /* args count  */
2098         stack_size += 8;
2099         args_off = stack_size;
2100
2101         if (flags & BPF_TRAMP_F_IP_ARG)
2102                 stack_size += 8; /* room for IP address argument */
2103
2104         ip_off = stack_size;
2105
2106         stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2107         run_ctx_off = stack_size;
2108
2109         if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2110                 /* skip patched call instruction and point orig_call to actual
2111                  * body of the kernel function.
2112                  */
2113                 if (is_endbr(*(u32 *)orig_call))
2114                         orig_call += ENDBR_INSN_SIZE;
2115                 orig_call += X86_PATCH_SIZE;
2116         }
2117
2118         prog = image;
2119
2120         EMIT_ENDBR();
2121         EMIT1(0x55);             /* push rbp */
2122         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2123         EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
2124         EMIT1(0x53);             /* push rbx */
2125
2126         /* Store number of argument registers of the traced function:
2127          *   mov rax, nr_args + extra_nregs
2128          *   mov QWORD PTR [rbp - args_off], rax
2129          */
2130         emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_args + extra_nregs);
2131         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -args_off);
2132
2133         if (flags & BPF_TRAMP_F_IP_ARG) {
2134                 /* Store IP address of the traced function:
2135                  * movabsq rax, func_addr
2136                  * mov QWORD PTR [rbp - ip_off], rax
2137                  */
2138                 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2139                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2140         }
2141
2142         save_regs(m, &prog, nr_args, regs_off);
2143
2144         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2145                 /* arg1: mov rdi, im */
2146                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2147                 if (emit_call(&prog, __bpf_tramp_enter, prog)) {
2148                         ret = -EINVAL;
2149                         goto cleanup;
2150                 }
2151         }
2152
2153         if (fentry->nr_links)
2154                 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2155                                flags & BPF_TRAMP_F_RET_FENTRY_RET))
2156                         return -EINVAL;
2157
2158         if (fmod_ret->nr_links) {
2159                 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2160                                    GFP_KERNEL);
2161                 if (!branches)
2162                         return -ENOMEM;
2163
2164                 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2165                                        run_ctx_off, branches)) {
2166                         ret = -EINVAL;
2167                         goto cleanup;
2168                 }
2169         }
2170
2171         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2172                 restore_regs(m, &prog, nr_args, regs_off);
2173
2174                 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2175                         emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
2176                         EMIT2(0xff, 0xd0); /* call *rax */
2177                 } else {
2178                         /* call original function */
2179                         if (emit_call(&prog, orig_call, prog)) {
2180                                 ret = -EINVAL;
2181                                 goto cleanup;
2182                         }
2183                 }
2184                 /* remember return value in a stack for bpf prog to access */
2185                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2186                 im->ip_after_call = prog;
2187                 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2188                 prog += X86_PATCH_SIZE;
2189         }
2190
2191         if (fmod_ret->nr_links) {
2192                 /* From Intel 64 and IA-32 Architectures Optimization
2193                  * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2194                  * Coding Rule 11: All branch targets should be 16-byte
2195                  * aligned.
2196                  */
2197                 emit_align(&prog, 16);
2198                 /* Update the branches saved in invoke_bpf_mod_ret with the
2199                  * aligned address of do_fexit.
2200                  */
2201                 for (i = 0; i < fmod_ret->nr_links; i++)
2202                         emit_cond_near_jump(&branches[i], prog, branches[i],
2203                                             X86_JNE);
2204         }
2205
2206         if (fexit->nr_links)
2207                 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) {
2208                         ret = -EINVAL;
2209                         goto cleanup;
2210                 }
2211
2212         if (flags & BPF_TRAMP_F_RESTORE_REGS)
2213                 restore_regs(m, &prog, nr_args, regs_off);
2214
2215         /* This needs to be done regardless. If there were fmod_ret programs,
2216          * the return value is only updated on the stack and still needs to be
2217          * restored to R0.
2218          */
2219         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2220                 im->ip_epilogue = prog;
2221                 /* arg1: mov rdi, im */
2222                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2223                 if (emit_call(&prog, __bpf_tramp_exit, prog)) {
2224                         ret = -EINVAL;
2225                         goto cleanup;
2226                 }
2227         }
2228         /* restore return value of orig_call or fentry prog back into RAX */
2229         if (save_ret)
2230                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2231
2232         EMIT1(0x5B); /* pop rbx */
2233         EMIT1(0xC9); /* leave */
2234         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2235                 /* skip our return address and return to parent */
2236                 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2237         emit_return(&prog, prog);
2238         /* Make sure the trampoline generation logic doesn't overflow */
2239         if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2240                 ret = -EFAULT;
2241                 goto cleanup;
2242         }
2243         ret = prog - (u8 *)image;
2244
2245 cleanup:
2246         kfree(branches);
2247         return ret;
2248 }
2249
2250 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
2251 {
2252         u8 *jg_reloc, *prog = *pprog;
2253         int pivot, err, jg_bytes = 1;
2254         s64 jg_offset;
2255
2256         if (a == b) {
2257                 /* Leaf node of recursion, i.e. not a range of indices
2258                  * anymore.
2259                  */
2260                 EMIT1(add_1mod(0x48, BPF_REG_3));       /* cmp rdx,func */
2261                 if (!is_simm32(progs[a]))
2262                         return -1;
2263                 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2264                             progs[a]);
2265                 err = emit_cond_near_jump(&prog,        /* je func */
2266                                           (void *)progs[a], image + (prog - buf),
2267                                           X86_JE);
2268                 if (err)
2269                         return err;
2270
2271                 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
2272
2273                 *pprog = prog;
2274                 return 0;
2275         }
2276
2277         /* Not a leaf node, so we pivot, and recursively descend into
2278          * the lower and upper ranges.
2279          */
2280         pivot = (b - a) / 2;
2281         EMIT1(add_1mod(0x48, BPF_REG_3));               /* cmp rdx,func */
2282         if (!is_simm32(progs[a + pivot]))
2283                 return -1;
2284         EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2285
2286         if (pivot > 2) {                                /* jg upper_part */
2287                 /* Require near jump. */
2288                 jg_bytes = 4;
2289                 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2290         } else {
2291                 EMIT2(X86_JG, 0);
2292         }
2293         jg_reloc = prog;
2294
2295         err = emit_bpf_dispatcher(&prog, a, a + pivot,  /* emit lower_part */
2296                                   progs, image, buf);
2297         if (err)
2298                 return err;
2299
2300         /* From Intel 64 and IA-32 Architectures Optimization
2301          * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2302          * Coding Rule 11: All branch targets should be 16-byte
2303          * aligned.
2304          */
2305         emit_align(&prog, 16);
2306         jg_offset = prog - jg_reloc;
2307         emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2308
2309         err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2310                                   b, progs, image, buf);
2311         if (err)
2312                 return err;
2313
2314         *pprog = prog;
2315         return 0;
2316 }
2317
2318 static int cmp_ips(const void *a, const void *b)
2319 {
2320         const s64 *ipa = a;
2321         const s64 *ipb = b;
2322
2323         if (*ipa > *ipb)
2324                 return 1;
2325         if (*ipa < *ipb)
2326                 return -1;
2327         return 0;
2328 }
2329
2330 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
2331 {
2332         u8 *prog = buf;
2333
2334         sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2335         return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
2336 }
2337
2338 struct x64_jit_data {
2339         struct bpf_binary_header *rw_header;
2340         struct bpf_binary_header *header;
2341         int *addrs;
2342         u8 *image;
2343         int proglen;
2344         struct jit_context ctx;
2345 };
2346
2347 #define MAX_PASSES 20
2348 #define PADDING_PASSES (MAX_PASSES - 5)
2349
2350 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2351 {
2352         struct bpf_binary_header *rw_header = NULL;
2353         struct bpf_binary_header *header = NULL;
2354         struct bpf_prog *tmp, *orig_prog = prog;
2355         struct x64_jit_data *jit_data;
2356         int proglen, oldproglen = 0;
2357         struct jit_context ctx = {};
2358         bool tmp_blinded = false;
2359         bool extra_pass = false;
2360         bool padding = false;
2361         u8 *rw_image = NULL;
2362         u8 *image = NULL;
2363         int *addrs;
2364         int pass;
2365         int i;
2366
2367         if (!prog->jit_requested)
2368                 return orig_prog;
2369
2370         tmp = bpf_jit_blind_constants(prog);
2371         /*
2372          * If blinding was requested and we failed during blinding,
2373          * we must fall back to the interpreter.
2374          */
2375         if (IS_ERR(tmp))
2376                 return orig_prog;
2377         if (tmp != prog) {
2378                 tmp_blinded = true;
2379                 prog = tmp;
2380         }
2381
2382         jit_data = prog->aux->jit_data;
2383         if (!jit_data) {
2384                 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2385                 if (!jit_data) {
2386                         prog = orig_prog;
2387                         goto out;
2388                 }
2389                 prog->aux->jit_data = jit_data;
2390         }
2391         addrs = jit_data->addrs;
2392         if (addrs) {
2393                 ctx = jit_data->ctx;
2394                 oldproglen = jit_data->proglen;
2395                 image = jit_data->image;
2396                 header = jit_data->header;
2397                 rw_header = jit_data->rw_header;
2398                 rw_image = (void *)rw_header + ((void *)image - (void *)header);
2399                 extra_pass = true;
2400                 padding = true;
2401                 goto skip_init_addrs;
2402         }
2403         addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2404         if (!addrs) {
2405                 prog = orig_prog;
2406                 goto out_addrs;
2407         }
2408
2409         /*
2410          * Before first pass, make a rough estimation of addrs[]
2411          * each BPF instruction is translated to less than 64 bytes
2412          */
2413         for (proglen = 0, i = 0; i <= prog->len; i++) {
2414                 proglen += 64;
2415                 addrs[i] = proglen;
2416         }
2417         ctx.cleanup_addr = proglen;
2418 skip_init_addrs:
2419
2420         /*
2421          * JITed image shrinks with every pass and the loop iterates
2422          * until the image stops shrinking. Very large BPF programs
2423          * may converge on the last pass. In such case do one more
2424          * pass to emit the final image.
2425          */
2426         for (pass = 0; pass < MAX_PASSES || image; pass++) {
2427                 if (!padding && pass >= PADDING_PASSES)
2428                         padding = true;
2429                 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
2430                 if (proglen <= 0) {
2431 out_image:
2432                         image = NULL;
2433                         if (header) {
2434                                 bpf_arch_text_copy(&header->size, &rw_header->size,
2435                                                    sizeof(rw_header->size));
2436                                 bpf_jit_binary_pack_free(header, rw_header);
2437                         }
2438                         /* Fall back to interpreter mode */
2439                         prog = orig_prog;
2440                         if (extra_pass) {
2441                                 prog->bpf_func = NULL;
2442                                 prog->jited = 0;
2443                                 prog->jited_len = 0;
2444                         }
2445                         goto out_addrs;
2446                 }
2447                 if (image) {
2448                         if (proglen != oldproglen) {
2449                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2450                                        proglen, oldproglen);
2451                                 goto out_image;
2452                         }
2453                         break;
2454                 }
2455                 if (proglen == oldproglen) {
2456                         /*
2457                          * The number of entries in extable is the number of BPF_LDX
2458                          * insns that access kernel memory via "pointer to BTF type".
2459                          * The verifier changed their opcode from LDX|MEM|size
2460                          * to LDX|PROBE_MEM|size to make JITing easier.
2461                          */
2462                         u32 align = __alignof__(struct exception_table_entry);
2463                         u32 extable_size = prog->aux->num_exentries *
2464                                 sizeof(struct exception_table_entry);
2465
2466                         /* allocate module memory for x86 insns and extable */
2467                         header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
2468                                                            &image, align, &rw_header, &rw_image,
2469                                                            jit_fill_hole);
2470                         if (!header) {
2471                                 prog = orig_prog;
2472                                 goto out_addrs;
2473                         }
2474                         prog->aux->extable = (void *) image + roundup(proglen, align);
2475                 }
2476                 oldproglen = proglen;
2477                 cond_resched();
2478         }
2479
2480         if (bpf_jit_enable > 1)
2481                 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2482
2483         if (image) {
2484                 if (!prog->is_func || extra_pass) {
2485                         /*
2486                          * bpf_jit_binary_pack_finalize fails in two scenarios:
2487                          *   1) header is not pointing to proper module memory;
2488                          *   2) the arch doesn't support bpf_arch_text_copy().
2489                          *
2490                          * Both cases are serious bugs and justify WARN_ON.
2491                          */
2492                         if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
2493                                 /* header has been freed */
2494                                 header = NULL;
2495                                 goto out_image;
2496                         }
2497
2498                         bpf_tail_call_direct_fixup(prog);
2499                 } else {
2500                         jit_data->addrs = addrs;
2501                         jit_data->ctx = ctx;
2502                         jit_data->proglen = proglen;
2503                         jit_data->image = image;
2504                         jit_data->header = header;
2505                         jit_data->rw_header = rw_header;
2506                 }
2507                 prog->bpf_func = (void *)image;
2508                 prog->jited = 1;
2509                 prog->jited_len = proglen;
2510         } else {
2511                 prog = orig_prog;
2512         }
2513
2514         if (!image || !prog->is_func || extra_pass) {
2515                 if (image)
2516                         bpf_prog_fill_jited_linfo(prog, addrs + 1);
2517 out_addrs:
2518                 kvfree(addrs);
2519                 kfree(jit_data);
2520                 prog->aux->jit_data = NULL;
2521         }
2522 out:
2523         if (tmp_blinded)
2524                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2525                                            tmp : orig_prog);
2526         return prog;
2527 }
2528
2529 bool bpf_jit_supports_kfunc_call(void)
2530 {
2531         return true;
2532 }
2533
2534 void *bpf_arch_text_copy(void *dst, void *src, size_t len)
2535 {
2536         if (text_poke_copy(dst, src, len) == NULL)
2537                 return ERR_PTR(-EINVAL);
2538         return dst;
2539 }
2540
2541 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
2542 bool bpf_jit_supports_subprog_tailcalls(void)
2543 {
2544         return true;
2545 }
2546
2547 void bpf_jit_free(struct bpf_prog *prog)
2548 {
2549         if (prog->jited) {
2550                 struct x64_jit_data *jit_data = prog->aux->jit_data;
2551                 struct bpf_binary_header *hdr;
2552
2553                 /*
2554                  * If we fail the final pass of JIT (from jit_subprogs),
2555                  * the program may not be finalized yet. Call finalize here
2556                  * before freeing it.
2557                  */
2558                 if (jit_data) {
2559                         bpf_jit_binary_pack_finalize(prog, jit_data->header,
2560                                                      jit_data->rw_header);
2561                         kvfree(jit_data->addrs);
2562                         kfree(jit_data);
2563                 }
2564                 hdr = bpf_jit_binary_pack_hdr(prog);
2565                 bpf_jit_binary_pack_free(hdr, NULL);
2566                 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
2567         }
2568
2569         bpf_prog_unlock_free(prog);
2570 }