arch/x86/net/bpf_jit_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * bpf_jit_comp.c: BPF JIT compiler
   4  *
   5  * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
   6  * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
   7  */
   8 #include <linux/netdevice.h>
   9 #include <linux/filter.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/bpf.h>
  12 #include <linux/memory.h>
  13 #include <linux/sort.h>
  14 #include <asm/extable.h>
  15 #include <asm/set_memory.h>
  16 #include <asm/nospec-branch.h>
  17 #include <asm/text-patching.h>
  18 #include <asm/asm-prototypes.h>
  19
  20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  21 {
  22         if (len == 1)
  23                 *ptr = bytes;
  24         else if (len == 2)
  25                 *(u16 *)ptr = bytes;
  26         else {
  27                 *(u32 *)ptr = bytes;
  28                 barrier();
  29         }
  30         return ptr + len;
  31 }
  32
  33 #define EMIT(bytes, len) \
  34         do { prog = emit_code(prog, bytes, len); } while (0)
  35
  36 #define EMIT1(b1)               EMIT(b1, 1)
  37 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  38 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  39 #define EMIT4(b1, b2, b3, b4)   EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  40
  41 #define EMIT1_off32(b1, off) \
  42         do { EMIT1(b1); EMIT(off, 4); } while (0)
  43 #define EMIT2_off32(b1, b2, off) \
  44         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  45 #define EMIT3_off32(b1, b2, b3, off) \
  46         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  47 #define EMIT4_off32(b1, b2, b3, b4, off) \
  48         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  49
  50 static bool is_imm8(int value)
  51 {
  52         return value <= 127 && value >= -128;
  53 }
  54
  55 static bool is_simm32(s64 value)
  56 {
  57         return value == (s64)(s32)value;
  58 }
  59
  60 static bool is_uimm32(u64 value)
  61 {
  62         return value == (u64)(u32)value;
  63 }
  64
  65 /* mov dst, src */
  66 #define EMIT_mov(DST, SRC)                                                               \
  67         do {                                                                             \
  68                 if (DST != SRC)                                                          \
  69                         EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
  70         } while (0)
  71
  72 static int bpf_size_to_x86_bytes(int bpf_size)
  73 {
  74         if (bpf_size == BPF_W)
  75                 return 4;
  76         else if (bpf_size == BPF_H)
  77                 return 2;
  78         else if (bpf_size == BPF_B)
  79                 return 1;
  80         else if (bpf_size == BPF_DW)
  81                 return 4; /* imm32 */
  82         else
  83                 return 0;
  84 }
  85
  86 /*
  87  * List of x86 cond jumps opcodes (. + s8)
  88  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
  89  */
  90 #define X86_JB  0x72
  91 #define X86_JAE 0x73
  92 #define X86_JE  0x74
  93 #define X86_JNE 0x75
  94 #define X86_JBE 0x76
  95 #define X86_JA  0x77
  96 #define X86_JL  0x7C
  97 #define X86_JGE 0x7D
  98 #define X86_JLE 0x7E
  99 #define X86_JG  0x7F
 100
 101 /* Pick a register outside of BPF range for JIT internal work */
 102 #define AUX_REG (MAX_BPF_JIT_REG + 1)
 103 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
 104
 105 /*
 106  * The following table maps BPF registers to x86-64 registers.
 107  *
 108  * x86-64 register R12 is unused, since if used as base address
 109  * register in load/store instructions, it always needs an
 110  * extra byte of encoding and is callee saved.
 111  *
 112  * x86-64 register R9 is not used by BPF programs, but can be used by BPF
 113  * trampoline. x86-64 register R10 is used for blinding (if enabled).
 114  */
 115 static const int reg2hex[] = {
 116         [BPF_REG_0] = 0,  /* RAX */
 117         [BPF_REG_1] = 7,  /* RDI */
 118         [BPF_REG_2] = 6,  /* RSI */
 119         [BPF_REG_3] = 2,  /* RDX */
 120         [BPF_REG_4] = 1,  /* RCX */
 121         [BPF_REG_5] = 0,  /* R8  */
 122         [BPF_REG_6] = 3,  /* RBX callee saved */
 123         [BPF_REG_7] = 5,  /* R13 callee saved */
 124         [BPF_REG_8] = 6,  /* R14 callee saved */
 125         [BPF_REG_9] = 7,  /* R15 callee saved */
 126         [BPF_REG_FP] = 5, /* RBP readonly */
 127         [BPF_REG_AX] = 2, /* R10 temp register */
 128         [AUX_REG] = 3,    /* R11 temp register */
 129         [X86_REG_R9] = 1, /* R9 register, 6th function argument */
 130 };
 131
 132 static const int reg2pt_regs[] = {
 133         [BPF_REG_0] = offsetof(struct pt_regs, ax),
 134         [BPF_REG_1] = offsetof(struct pt_regs, di),
 135         [BPF_REG_2] = offsetof(struct pt_regs, si),
 136         [BPF_REG_3] = offsetof(struct pt_regs, dx),
 137         [BPF_REG_4] = offsetof(struct pt_regs, cx),
 138         [BPF_REG_5] = offsetof(struct pt_regs, r8),
 139         [BPF_REG_6] = offsetof(struct pt_regs, bx),
 140         [BPF_REG_7] = offsetof(struct pt_regs, r13),
 141         [BPF_REG_8] = offsetof(struct pt_regs, r14),
 142         [BPF_REG_9] = offsetof(struct pt_regs, r15),
 143 };
 144
 145 /*
 146  * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
 147  * which need extra byte of encoding.
 148  * rax,rcx,...,rbp have simpler encoding
 149  */
 150 static bool is_ereg(u32 reg)
 151 {
 152         return (1 << reg) & (BIT(BPF_REG_5) |
 153                              BIT(AUX_REG) |
 154                              BIT(BPF_REG_7) |
 155                              BIT(BPF_REG_8) |
 156                              BIT(BPF_REG_9) |
 157                              BIT(X86_REG_R9) |
 158                              BIT(BPF_REG_AX));
 159 }
 160
 161 /*
 162  * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
 163  * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
 164  * of encoding. al,cl,dl,bl have simpler encoding.
 165  */
 166 static bool is_ereg_8l(u32 reg)
 167 {
 168         return is_ereg(reg) ||
 169             (1 << reg) & (BIT(BPF_REG_1) |
 170                           BIT(BPF_REG_2) |
 171                           BIT(BPF_REG_FP));
 172 }
 173
 174 static bool is_axreg(u32 reg)
 175 {
 176         return reg == BPF_REG_0;
 177 }
 178
 179 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
 180 static u8 add_1mod(u8 byte, u32 reg)
 181 {
 182         if (is_ereg(reg))
 183                 byte |= 1;
 184         return byte;
 185 }
 186
 187 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
 188 {
 189         if (is_ereg(r1))
 190                 byte |= 1;
 191         if (is_ereg(r2))
 192                 byte |= 4;
 193         return byte;
 194 }
 195
 196 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
 197 static u8 add_1reg(u8 byte, u32 dst_reg)
 198 {
 199         return byte + reg2hex[dst_reg];
 200 }
 201
 202 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
 203 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 204 {
 205         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 206 }
 207
 208 /* Some 1-byte opcodes for binary ALU operations */
 209 static u8 simple_alu_opcodes[] = {
 210         [BPF_ADD] = 0x01,
 211         [BPF_SUB] = 0x29,
 212         [BPF_AND] = 0x21,
 213         [BPF_OR] = 0x09,
 214         [BPF_XOR] = 0x31,
 215         [BPF_LSH] = 0xE0,
 216         [BPF_RSH] = 0xE8,
 217         [BPF_ARSH] = 0xF8,
 218 };
 219
 220 static void jit_fill_hole(void *area, unsigned int size)
 221 {
 222         /* Fill whole space with INT3 instructions */
 223         memset(area, 0xcc, size);
 224 }
 225
 226 struct jit_context {
 227         int cleanup_addr; /* Epilogue code offset */
 228 };
 229
 230 /* Maximum number of bytes emitted while JITing one eBPF insn */
 231 #define BPF_MAX_INSN_SIZE       128
 232 #define BPF_INSN_SAFETY         64
 233
 234 /* Number of bytes emit_patch() needs to generate instructions */
 235 #define X86_PATCH_SIZE          5
 236 /* Number of bytes that will be skipped on tailcall */
 237 #define X86_TAIL_CALL_OFFSET    11
 238
 239 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
 240 {
 241         u8 *prog = *pprog;
 242
 243         if (callee_regs_used[0])
 244                 EMIT1(0x53);         /* push rbx */
 245         if (callee_regs_used[1])
 246                 EMIT2(0x41, 0x55);   /* push r13 */
 247         if (callee_regs_used[2])
 248                 EMIT2(0x41, 0x56);   /* push r14 */
 249         if (callee_regs_used[3])
 250                 EMIT2(0x41, 0x57);   /* push r15 */
 251         *pprog = prog;
 252 }
 253
 254 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
 255 {
 256         u8 *prog = *pprog;
 257
 258         if (callee_regs_used[3])
 259                 EMIT2(0x41, 0x5F);   /* pop r15 */
 260         if (callee_regs_used[2])
 261                 EMIT2(0x41, 0x5E);   /* pop r14 */
 262         if (callee_regs_used[1])
 263                 EMIT2(0x41, 0x5D);   /* pop r13 */
 264         if (callee_regs_used[0])
 265                 EMIT1(0x5B);         /* pop rbx */
 266         *pprog = prog;
 267 }
 268
 269 /*
 270  * Emit x86-64 prologue code for BPF program.
 271  * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
 272  * while jumping to another program
 273  */
 274 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
 275                           bool tail_call_reachable, bool is_subprog)
 276 {
 277         u8 *prog = *pprog;
 278
 279         /* BPF trampoline can be made to work without these nops,
 280          * but let's waste 5 bytes for now and optimize later
 281          */
 282         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 283         prog += X86_PATCH_SIZE;
 284         if (!ebpf_from_cbpf) {
 285                 if (tail_call_reachable && !is_subprog)
 286                         EMIT2(0x31, 0xC0); /* xor eax, eax */
 287                 else
 288                         EMIT2(0x66, 0x90); /* nop2 */
 289         }
 290         EMIT1(0x55);             /* push rbp */
 291         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
 292         /* sub rsp, rounded_stack_depth */
 293         if (stack_depth)
 294                 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
 295         if (tail_call_reachable)
 296                 EMIT1(0x50);         /* push rax */
 297         *pprog = prog;
 298 }
 299
 300 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
 301 {
 302         u8 *prog = *pprog;
 303         s64 offset;
 304
 305         offset = func - (ip + X86_PATCH_SIZE);
 306         if (!is_simm32(offset)) {
 307                 pr_err("Target call %p is out of range\n", func);
 308                 return -ERANGE;
 309         }
 310         EMIT1_off32(opcode, offset);
 311         *pprog = prog;
 312         return 0;
 313 }
 314
 315 static int emit_call(u8 **pprog, void *func, void *ip)
 316 {
 317         return emit_patch(pprog, func, ip, 0xE8);
 318 }
 319
 320 static int emit_jump(u8 **pprog, void *func, void *ip)
 321 {
 322         return emit_patch(pprog, func, ip, 0xE9);
 323 }
 324
 325 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 326                                 void *old_addr, void *new_addr,
 327                                 const bool text_live)
 328 {
 329         const u8 *nop_insn = x86_nops[5];
 330         u8 old_insn[X86_PATCH_SIZE];
 331         u8 new_insn[X86_PATCH_SIZE];
 332         u8 *prog;
 333         int ret;
 334
 335         memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
 336         if (old_addr) {
 337                 prog = old_insn;
 338                 ret = t == BPF_MOD_CALL ?
 339                       emit_call(&prog, old_addr, ip) :
 340                       emit_jump(&prog, old_addr, ip);
 341                 if (ret)
 342                         return ret;
 343         }
 344
 345         memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
 346         if (new_addr) {
 347                 prog = new_insn;
 348                 ret = t == BPF_MOD_CALL ?
 349                       emit_call(&prog, new_addr, ip) :
 350                       emit_jump(&prog, new_addr, ip);
 351                 if (ret)
 352                         return ret;
 353         }
 354
 355         ret = -EBUSY;
 356         mutex_lock(&text_mutex);
 357         if (memcmp(ip, old_insn, X86_PATCH_SIZE))
 358                 goto out;
 359         ret = 1;
 360         if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
 361                 if (text_live)
 362                         text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
 363                 else
 364                         memcpy(ip, new_insn, X86_PATCH_SIZE);
 365                 ret = 0;
 366         }
 367 out:
 368         mutex_unlock(&text_mutex);
 369         return ret;
 370 }
 371
 372 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 373                        void *old_addr, void *new_addr)
 374 {
 375         if (!is_kernel_text((long)ip) &&
 376             !is_bpf_text_address((long)ip))
 377                 /* BPF poking in modules is not supported */
 378                 return -EINVAL;
 379
 380         return __bpf_arch_text_poke(ip, t, old_addr, new_addr, true);
 381 }
 382
 383 static int get_pop_bytes(bool *callee_regs_used)
 384 {
 385         int bytes = 0;
 386
 387         if (callee_regs_used[3])
 388                 bytes += 2;
 389         if (callee_regs_used[2])
 390                 bytes += 2;
 391         if (callee_regs_used[1])
 392                 bytes += 2;
 393         if (callee_regs_used[0])
 394                 bytes += 1;
 395
 396         return bytes;
 397 }
 398
 399 /*
 400  * Generate the following code:
 401  *
 402  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
 403  *   if (index >= array->map.max_entries)
 404  *     goto out;
 405  *   if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
 406  *     goto out;
 407  *   prog = array->ptrs[index];
 408  *   if (prog == NULL)
 409  *     goto out;
 410  *   goto *(prog->bpf_func + prologue_size);
 411  * out:
 412  */
 413 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
 414                                         u32 stack_depth)
 415 {
 416         int tcc_off = -4 - round_up(stack_depth, 8);
 417         u8 *prog = *pprog;
 418         int pop_bytes = 0;
 419         int off1 = 42;
 420         int off2 = 31;
 421         int off3 = 9;
 422
 423         /* count the additional bytes used for popping callee regs from stack
 424          * that need to be taken into account for each of the offsets that
 425          * are used for bailing out of the tail call
 426          */
 427         pop_bytes = get_pop_bytes(callee_regs_used);
 428         off1 += pop_bytes;
 429         off2 += pop_bytes;
 430         off3 += pop_bytes;
 431
 432         if (stack_depth) {
 433                 off1 += 7;
 434                 off2 += 7;
 435                 off3 += 7;
 436         }
 437
 438         /*
 439          * rdi - pointer to ctx
 440          * rsi - pointer to bpf_array
 441          * rdx - index in bpf_array
 442          */
 443
 444         /*
 445          * if (index >= array->map.max_entries)
 446          *      goto out;
 447          */
 448         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
 449         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 450               offsetof(struct bpf_array, map.max_entries));
 451 #define OFFSET1 (off1 + RETPOLINE_RCX_BPF_JIT_SIZE) /* Number of bytes to jump */
 452         EMIT2(X86_JBE, OFFSET1);                  /* jbe out */
 453
 454         /*
 455          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
 456          *      goto out;
 457          */
 458         EMIT2_off32(0x8B, 0x85, tcc_off);         /* mov eax, dword ptr [rbp - tcc_off] */
 459         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
 460 #define OFFSET2 (off2 + RETPOLINE_RCX_BPF_JIT_SIZE)
 461         EMIT2(X86_JA, OFFSET2);                   /* ja out */
 462         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
 463         EMIT2_off32(0x89, 0x85, tcc_off);         /* mov dword ptr [rbp - tcc_off], eax */
 464
 465         /* prog = array->ptrs[index]; */
 466         EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6,       /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
 467                     offsetof(struct bpf_array, ptrs));
 468
 469         /*
 470          * if (prog == NULL)
 471          *      goto out;
 472          */
 473         EMIT3(0x48, 0x85, 0xC9);                  /* test rcx,rcx */
 474 #define OFFSET3 (off3 + RETPOLINE_RCX_BPF_JIT_SIZE)
 475         EMIT2(X86_JE, OFFSET3);                   /* je out */
 476
 477         *pprog = prog;
 478         pop_callee_regs(pprog, callee_regs_used);
 479         prog = *pprog;
 480
 481         EMIT1(0x58);                              /* pop rax */
 482         if (stack_depth)
 483                 EMIT3_off32(0x48, 0x81, 0xC4,     /* add rsp, sd */
 484                             round_up(stack_depth, 8));
 485
 486         /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
 487         EMIT4(0x48, 0x8B, 0x49,                   /* mov rcx, qword ptr [rcx + 32] */
 488               offsetof(struct bpf_prog, bpf_func));
 489         EMIT4(0x48, 0x83, 0xC1,                   /* add rcx, X86_TAIL_CALL_OFFSET */
 490               X86_TAIL_CALL_OFFSET);
 491         /*
 492          * Now we're ready to jump into next BPF program
 493          * rdi == ctx (1st arg)
 494          * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
 495          */
 496         RETPOLINE_RCX_BPF_JIT();
 497
 498         /* out: */
 499         *pprog = prog;
 500 }
 501
 502 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
 503                                       u8 **pprog, int addr, u8 *image,
 504                                       bool *callee_regs_used, u32 stack_depth)
 505 {
 506         int tcc_off = -4 - round_up(stack_depth, 8);
 507         u8 *prog = *pprog;
 508         int pop_bytes = 0;
 509         int off1 = 20;
 510         int poke_off;
 511
 512         /* count the additional bytes used for popping callee regs to stack
 513          * that need to be taken into account for jump offset that is used for
 514          * bailing out from of the tail call when limit is reached
 515          */
 516         pop_bytes = get_pop_bytes(callee_regs_used);
 517         off1 += pop_bytes;
 518
 519         /*
 520          * total bytes for:
 521          * - nop5/ jmpq $off
 522          * - pop callee regs
 523          * - sub rsp, $val if depth > 0
 524          * - pop rax
 525          */
 526         poke_off = X86_PATCH_SIZE + pop_bytes + 1;
 527         if (stack_depth) {
 528                 poke_off += 7;
 529                 off1 += 7;
 530         }
 531
 532         /*
 533          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
 534          *      goto out;
 535          */
 536         EMIT2_off32(0x8B, 0x85, tcc_off);             /* mov eax, dword ptr [rbp - tcc_off] */
 537         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);         /* cmp eax, MAX_TAIL_CALL_CNT */
 538         EMIT2(X86_JA, off1);                          /* ja out */
 539         EMIT3(0x83, 0xC0, 0x01);                      /* add eax, 1 */
 540         EMIT2_off32(0x89, 0x85, tcc_off);             /* mov dword ptr [rbp - tcc_off], eax */
 541
 542         poke->tailcall_bypass = image + (addr - poke_off - X86_PATCH_SIZE);
 543         poke->adj_off = X86_TAIL_CALL_OFFSET;
 544         poke->tailcall_target = image + (addr - X86_PATCH_SIZE);
 545         poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
 546
 547         emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
 548                   poke->tailcall_bypass);
 549
 550         *pprog = prog;
 551         pop_callee_regs(pprog, callee_regs_used);
 552         prog = *pprog;
 553         EMIT1(0x58);                                  /* pop rax */
 554         if (stack_depth)
 555                 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
 556
 557         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 558         prog += X86_PATCH_SIZE;
 559         /* out: */
 560
 561         *pprog = prog;
 562 }
 563
 564 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
 565 {
 566         struct bpf_jit_poke_descriptor *poke;
 567         struct bpf_array *array;
 568         struct bpf_prog *target;
 569         int i, ret;
 570
 571         for (i = 0; i < prog->aux->size_poke_tab; i++) {
 572                 poke = &prog->aux->poke_tab[i];
 573                 if (poke->aux && poke->aux != prog->aux)
 574                         continue;
 575
 576                 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
 577
 578                 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
 579                         continue;
 580
 581                 array = container_of(poke->tail_call.map, struct bpf_array, map);
 582                 mutex_lock(&array->aux->poke_mutex);
 583                 target = array->ptrs[poke->tail_call.key];
 584                 if (target) {
 585                         /* Plain memcpy is used when image is not live yet
 586                          * and still not locked as read-only. Once poke
 587                          * location is active (poke->tailcall_target_stable),
 588                          * any parallel bpf_arch_text_poke() might occur
 589                          * still on the read-write image until we finally
 590                          * locked it as read-only. Both modifications on
 591                          * the given image are under text_mutex to avoid
 592                          * interference.
 593                          */
 594                         ret = __bpf_arch_text_poke(poke->tailcall_target,
 595                                                    BPF_MOD_JUMP, NULL,
 596                                                    (u8 *)target->bpf_func +
 597                                                    poke->adj_off, false);
 598                         BUG_ON(ret < 0);
 599                         ret = __bpf_arch_text_poke(poke->tailcall_bypass,
 600                                                    BPF_MOD_JUMP,
 601                                                    (u8 *)poke->tailcall_target +
 602                                                    X86_PATCH_SIZE, NULL, false);
 603                         BUG_ON(ret < 0);
 604                 }
 605                 WRITE_ONCE(poke->tailcall_target_stable, true);
 606                 mutex_unlock(&array->aux->poke_mutex);
 607         }
 608 }
 609
 610 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
 611                            u32 dst_reg, const u32 imm32)
 612 {
 613         u8 *prog = *pprog;
 614         u8 b1, b2, b3;
 615
 616         /*
 617          * Optimization: if imm32 is positive, use 'mov %eax, imm32'
 618          * (which zero-extends imm32) to save 2 bytes.
 619          */
 620         if (sign_propagate && (s32)imm32 < 0) {
 621                 /* 'mov %rax, imm32' sign extends imm32 */
 622                 b1 = add_1mod(0x48, dst_reg);
 623                 b2 = 0xC7;
 624                 b3 = 0xC0;
 625                 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
 626                 goto done;
 627         }
 628
 629         /*
 630          * Optimization: if imm32 is zero, use 'xor %eax, %eax'
 631          * to save 3 bytes.
 632          */
 633         if (imm32 == 0) {
 634                 if (is_ereg(dst_reg))
 635                         EMIT1(add_2mod(0x40, dst_reg, dst_reg));
 636                 b2 = 0x31; /* xor */
 637                 b3 = 0xC0;
 638                 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
 639                 goto done;
 640         }
 641
 642         /* mov %eax, imm32 */
 643         if (is_ereg(dst_reg))
 644                 EMIT1(add_1mod(0x40, dst_reg));
 645         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
 646 done:
 647         *pprog = prog;
 648 }
 649
 650 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
 651                            const u32 imm32_hi, const u32 imm32_lo)
 652 {
 653         u8 *prog = *pprog;
 654
 655         if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
 656                 /*
 657                  * For emitting plain u32, where sign bit must not be
 658                  * propagated LLVM tends to load imm64 over mov32
 659                  * directly, so save couple of bytes by just doing
 660                  * 'mov %eax, imm32' instead.
 661                  */
 662                 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
 663         } else {
 664                 /* movabsq %rax, imm64 */
 665                 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
 666                 EMIT(imm32_lo, 4);
 667                 EMIT(imm32_hi, 4);
 668         }
 669
 670         *pprog = prog;
 671 }
 672
 673 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
 674 {
 675         u8 *prog = *pprog;
 676
 677         if (is64) {
 678                 /* mov dst, src */
 679                 EMIT_mov(dst_reg, src_reg);
 680         } else {
 681                 /* mov32 dst, src */
 682                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 683                         EMIT1(add_2mod(0x40, dst_reg, src_reg));
 684                 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
 685         }
 686
 687         *pprog = prog;
 688 }
 689
 690 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
 691 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
 692 {
 693         u8 *prog = *pprog;
 694
 695         if (is_imm8(off)) {
 696                 /* 1-byte signed displacement.
 697                  *
 698                  * If off == 0 we could skip this and save one extra byte, but
 699                  * special case of x86 R13 which always needs an offset is not
 700                  * worth the hassle
 701                  */
 702                 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
 703         } else {
 704                 /* 4-byte signed displacement */
 705                 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
 706         }
 707         *pprog = prog;
 708 }
 709
 710 /*
 711  * Emit a REX byte if it will be necessary to address these registers
 712  */
 713 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
 714 {
 715         u8 *prog = *pprog;
 716
 717         if (is64)
 718                 EMIT1(add_2mod(0x48, dst_reg, src_reg));
 719         else if (is_ereg(dst_reg) || is_ereg(src_reg))
 720                 EMIT1(add_2mod(0x40, dst_reg, src_reg));
 721         *pprog = prog;
 722 }
 723
 724 /*
 725  * Similar version of maybe_emit_mod() for a single register
 726  */
 727 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
 728 {
 729         u8 *prog = *pprog;
 730
 731         if (is64)
 732                 EMIT1(add_1mod(0x48, reg));
 733         else if (is_ereg(reg))
 734                 EMIT1(add_1mod(0x40, reg));
 735         *pprog = prog;
 736 }
 737
 738 /* LDX: dst_reg = *(u8*)(src_reg + off) */
 739 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 740 {
 741         u8 *prog = *pprog;
 742
 743         switch (size) {
 744         case BPF_B:
 745                 /* Emit 'movzx rax, byte ptr [rax + off]' */
 746                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
 747                 break;
 748         case BPF_H:
 749                 /* Emit 'movzx rax, word ptr [rax + off]' */
 750                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
 751                 break;
 752         case BPF_W:
 753                 /* Emit 'mov eax, dword ptr [rax+0x14]' */
 754                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 755                         EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
 756                 else
 757                         EMIT1(0x8B);
 758                 break;
 759         case BPF_DW:
 760                 /* Emit 'mov rax, qword ptr [rax+0x14]' */
 761                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
 762                 break;
 763         }
 764         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 765         *pprog = prog;
 766 }
 767
 768 /* STX: *(u8*)(dst_reg + off) = src_reg */
 769 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 770 {
 771         u8 *prog = *pprog;
 772
 773         switch (size) {
 774         case BPF_B:
 775                 /* Emit 'mov byte ptr [rax + off], al' */
 776                 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
 777                         /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
 778                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
 779                 else
 780                         EMIT1(0x88);
 781                 break;
 782         case BPF_H:
 783                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 784                         EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
 785                 else
 786                         EMIT2(0x66, 0x89);
 787                 break;
 788         case BPF_W:
 789                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 790                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
 791                 else
 792                         EMIT1(0x89);
 793                 break;
 794         case BPF_DW:
 795                 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
 796                 break;
 797         }
 798         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 799         *pprog = prog;
 800 }
 801
 802 static int emit_atomic(u8 **pprog, u8 atomic_op,
 803                        u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
 804 {
 805         u8 *prog = *pprog;
 806
 807         EMIT1(0xF0); /* lock prefix */
 808
 809         maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
 810
 811         /* emit opcode */
 812         switch (atomic_op) {
 813         case BPF_ADD:
 814         case BPF_SUB:
 815         case BPF_AND:
 816         case BPF_OR:
 817         case BPF_XOR:
 818                 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
 819                 EMIT1(simple_alu_opcodes[atomic_op]);
 820                 break;
 821         case BPF_ADD | BPF_FETCH:
 822                 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
 823                 EMIT2(0x0F, 0xC1);
 824                 break;
 825         case BPF_XCHG:
 826                 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
 827                 EMIT1(0x87);
 828                 break;
 829         case BPF_CMPXCHG:
 830                 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
 831                 EMIT2(0x0F, 0xB1);
 832                 break;
 833         default:
 834                 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
 835                 return -EFAULT;
 836         }
 837
 838         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 839
 840         *pprog = prog;
 841         return 0;
 842 }
 843
 844 static bool ex_handler_bpf(const struct exception_table_entry *x,
 845                            struct pt_regs *regs, int trapnr,
 846                            unsigned long error_code, unsigned long fault_addr)
 847 {
 848         u32 reg = x->fixup >> 8;
 849
 850         /* jump over faulting load and clear dest register */
 851         *(unsigned long *)((void *)regs + reg) = 0;
 852         regs->ip += x->fixup & 0xff;
 853         return true;
 854 }
 855
 856 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
 857                              bool *regs_used, bool *tail_call_seen)
 858 {
 859         int i;
 860
 861         for (i = 1; i <= insn_cnt; i++, insn++) {
 862                 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
 863                         *tail_call_seen = true;
 864                 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
 865                         regs_used[0] = true;
 866                 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
 867                         regs_used[1] = true;
 868                 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
 869                         regs_used[2] = true;
 870                 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
 871                         regs_used[3] = true;
 872         }
 873 }
 874
 875 static void emit_nops(u8 **pprog, int len)
 876 {
 877         u8 *prog = *pprog;
 878         int i, noplen;
 879
 880         while (len > 0) {
 881                 noplen = len;
 882
 883                 if (noplen > ASM_NOP_MAX)
 884                         noplen = ASM_NOP_MAX;
 885
 886                 for (i = 0; i < noplen; i++)
 887                         EMIT1(x86_nops[noplen][i]);
 888                 len -= noplen;
 889         }
 890
 891         *pprog = prog;
 892 }
 893
 894 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
 895
 896 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
 897                   int oldproglen, struct jit_context *ctx, bool jmp_padding)
 898 {
 899         bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
 900         struct bpf_insn *insn = bpf_prog->insnsi;
 901         bool callee_regs_used[4] = {};
 902         int insn_cnt = bpf_prog->len;
 903         bool tail_call_seen = false;
 904         bool seen_exit = false;
 905         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
 906         int i, excnt = 0;
 907         int ilen, proglen = 0;
 908         u8 *prog = temp;
 909         int err;
 910
 911         detect_reg_usage(insn, insn_cnt, callee_regs_used,
 912                          &tail_call_seen);
 913
 914         /* tail call's presence in current prog implies it is reachable */
 915         tail_call_reachable |= tail_call_seen;
 916
 917         emit_prologue(&prog, bpf_prog->aux->stack_depth,
 918                       bpf_prog_was_classic(bpf_prog), tail_call_reachable,
 919                       bpf_prog->aux->func_idx != 0);
 920         push_callee_regs(&prog, callee_regs_used);
 921
 922         ilen = prog - temp;
 923         if (image)
 924                 memcpy(image + proglen, temp, ilen);
 925         proglen += ilen;
 926         addrs[0] = proglen;
 927         prog = temp;
 928
 929         for (i = 1; i <= insn_cnt; i++, insn++) {
 930                 const s32 imm32 = insn->imm;
 931                 u32 dst_reg = insn->dst_reg;
 932                 u32 src_reg = insn->src_reg;
 933                 u8 b2 = 0, b3 = 0;
 934                 u8 *start_of_ldx;
 935                 s64 jmp_offset;
 936                 u8 jmp_cond;
 937                 u8 *func;
 938                 int nops;
 939
 940                 switch (insn->code) {
 941                         /* ALU */
 942                 case BPF_ALU | BPF_ADD | BPF_X:
 943                 case BPF_ALU | BPF_SUB | BPF_X:
 944                 case BPF_ALU | BPF_AND | BPF_X:
 945                 case BPF_ALU | BPF_OR | BPF_X:
 946                 case BPF_ALU | BPF_XOR | BPF_X:
 947                 case BPF_ALU64 | BPF_ADD | BPF_X:
 948                 case BPF_ALU64 | BPF_SUB | BPF_X:
 949                 case BPF_ALU64 | BPF_AND | BPF_X:
 950                 case BPF_ALU64 | BPF_OR | BPF_X:
 951                 case BPF_ALU64 | BPF_XOR | BPF_X:
 952                         maybe_emit_mod(&prog, dst_reg, src_reg,
 953                                        BPF_CLASS(insn->code) == BPF_ALU64);
 954                         b2 = simple_alu_opcodes[BPF_OP(insn->code)];
 955                         EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
 956                         break;
 957
 958                 case BPF_ALU64 | BPF_MOV | BPF_X:
 959                 case BPF_ALU | BPF_MOV | BPF_X:
 960                         emit_mov_reg(&prog,
 961                                      BPF_CLASS(insn->code) == BPF_ALU64,
 962                                      dst_reg, src_reg);
 963                         break;
 964
 965                         /* neg dst */
 966                 case BPF_ALU | BPF_NEG:
 967                 case BPF_ALU64 | BPF_NEG:
 968                         maybe_emit_1mod(&prog, dst_reg,
 969                                         BPF_CLASS(insn->code) == BPF_ALU64);
 970                         EMIT2(0xF7, add_1reg(0xD8, dst_reg));
 971                         break;
 972
 973                 case BPF_ALU | BPF_ADD | BPF_K:
 974                 case BPF_ALU | BPF_SUB | BPF_K:
 975                 case BPF_ALU | BPF_AND | BPF_K:
 976                 case BPF_ALU | BPF_OR | BPF_K:
 977                 case BPF_ALU | BPF_XOR | BPF_K:
 978                 case BPF_ALU64 | BPF_ADD | BPF_K:
 979                 case BPF_ALU64 | BPF_SUB | BPF_K:
 980                 case BPF_ALU64 | BPF_AND | BPF_K:
 981                 case BPF_ALU64 | BPF_OR | BPF_K:
 982                 case BPF_ALU64 | BPF_XOR | BPF_K:
 983                         maybe_emit_1mod(&prog, dst_reg,
 984                                         BPF_CLASS(insn->code) == BPF_ALU64);
 985
 986                         /*
 987                          * b3 holds 'normal' opcode, b2 short form only valid
 988                          * in case dst is eax/rax.
 989                          */
 990                         switch (BPF_OP(insn->code)) {
 991                         case BPF_ADD:
 992                                 b3 = 0xC0;
 993                                 b2 = 0x05;
 994                                 break;
 995                         case BPF_SUB:
 996                                 b3 = 0xE8;
 997                                 b2 = 0x2D;
 998                                 break;
 999                         case BPF_AND:
1000                                 b3 = 0xE0;
1001                                 b2 = 0x25;
1002                                 break;
1003                         case BPF_OR:
1004                                 b3 = 0xC8;
1005                                 b2 = 0x0D;
1006                                 break;
1007                         case BPF_XOR:
1008                                 b3 = 0xF0;
1009                                 b2 = 0x35;
1010                                 break;
1011                         }
1012
1013                         if (is_imm8(imm32))
1014                                 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1015                         else if (is_axreg(dst_reg))
1016                                 EMIT1_off32(b2, imm32);
1017                         else
1018                                 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1019                         break;
1020
1021                 case BPF_ALU64 | BPF_MOV | BPF_K:
1022                 case BPF_ALU | BPF_MOV | BPF_K:
1023                         emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1024                                        dst_reg, imm32);
1025                         break;
1026
1027                 case BPF_LD | BPF_IMM | BPF_DW:
1028                         emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1029                         insn++;
1030                         i++;
1031                         break;
1032
1033                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1034                 case BPF_ALU | BPF_MOD | BPF_X:
1035                 case BPF_ALU | BPF_DIV | BPF_X:
1036                 case BPF_ALU | BPF_MOD | BPF_K:
1037                 case BPF_ALU | BPF_DIV | BPF_K:
1038                 case BPF_ALU64 | BPF_MOD | BPF_X:
1039                 case BPF_ALU64 | BPF_DIV | BPF_X:
1040                 case BPF_ALU64 | BPF_MOD | BPF_K:
1041                 case BPF_ALU64 | BPF_DIV | BPF_K:
1042                         EMIT1(0x50); /* push rax */
1043                         EMIT1(0x52); /* push rdx */
1044
1045                         if (BPF_SRC(insn->code) == BPF_X)
1046                                 /* mov r11, src_reg */
1047                                 EMIT_mov(AUX_REG, src_reg);
1048                         else
1049                                 /* mov r11, imm32 */
1050                                 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1051
1052                         /* mov rax, dst_reg */
1053                         EMIT_mov(BPF_REG_0, dst_reg);
1054
1055                         /*
1056                          * xor edx, edx
1057                          * equivalent to 'xor rdx, rdx', but one byte less
1058                          */
1059                         EMIT2(0x31, 0xd2);
1060
1061                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1062                                 /* div r11 */
1063                                 EMIT3(0x49, 0xF7, 0xF3);
1064                         else
1065                                 /* div r11d */
1066                                 EMIT3(0x41, 0xF7, 0xF3);
1067
1068                         if (BPF_OP(insn->code) == BPF_MOD)
1069                                 /* mov r11, rdx */
1070                                 EMIT3(0x49, 0x89, 0xD3);
1071                         else
1072                                 /* mov r11, rax */
1073                                 EMIT3(0x49, 0x89, 0xC3);
1074
1075                         EMIT1(0x5A); /* pop rdx */
1076                         EMIT1(0x58); /* pop rax */
1077
1078                         /* mov dst_reg, r11 */
1079                         EMIT_mov(dst_reg, AUX_REG);
1080                         break;
1081
1082                 case BPF_ALU | BPF_MUL | BPF_K:
1083                 case BPF_ALU | BPF_MUL | BPF_X:
1084                 case BPF_ALU64 | BPF_MUL | BPF_K:
1085                 case BPF_ALU64 | BPF_MUL | BPF_X:
1086                 {
1087                         bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1088
1089                         if (dst_reg != BPF_REG_0)
1090                                 EMIT1(0x50); /* push rax */
1091                         if (dst_reg != BPF_REG_3)
1092                                 EMIT1(0x52); /* push rdx */
1093
1094                         /* mov r11, dst_reg */
1095                         EMIT_mov(AUX_REG, dst_reg);
1096
1097                         if (BPF_SRC(insn->code) == BPF_X)
1098                                 emit_mov_reg(&prog, is64, BPF_REG_0, src_reg);
1099                         else
1100                                 emit_mov_imm32(&prog, is64, BPF_REG_0, imm32);
1101
1102                         if (is64)
1103                                 EMIT1(add_1mod(0x48, AUX_REG));
1104                         else if (is_ereg(AUX_REG))
1105                                 EMIT1(add_1mod(0x40, AUX_REG));
1106                         /* mul(q) r11 */
1107                         EMIT2(0xF7, add_1reg(0xE0, AUX_REG));
1108
1109                         if (dst_reg != BPF_REG_3)
1110                                 EMIT1(0x5A); /* pop rdx */
1111                         if (dst_reg != BPF_REG_0) {
1112                                 /* mov dst_reg, rax */
1113                                 EMIT_mov(dst_reg, BPF_REG_0);
1114                                 EMIT1(0x58); /* pop rax */
1115                         }
1116                         break;
1117                 }
1118                         /* Shifts */
1119                 case BPF_ALU | BPF_LSH | BPF_K:
1120                 case BPF_ALU | BPF_RSH | BPF_K:
1121                 case BPF_ALU | BPF_ARSH | BPF_K:
1122                 case BPF_ALU64 | BPF_LSH | BPF_K:
1123                 case BPF_ALU64 | BPF_RSH | BPF_K:
1124                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1125                         maybe_emit_1mod(&prog, dst_reg,
1126                                         BPF_CLASS(insn->code) == BPF_ALU64);
1127
1128                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1129                         if (imm32 == 1)
1130                                 EMIT2(0xD1, add_1reg(b3, dst_reg));
1131                         else
1132                                 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1133                         break;
1134
1135                 case BPF_ALU | BPF_LSH | BPF_X:
1136                 case BPF_ALU | BPF_RSH | BPF_X:
1137                 case BPF_ALU | BPF_ARSH | BPF_X:
1138                 case BPF_ALU64 | BPF_LSH | BPF_X:
1139                 case BPF_ALU64 | BPF_RSH | BPF_X:
1140                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1141
1142                         /* Check for bad case when dst_reg == rcx */
1143                         if (dst_reg == BPF_REG_4) {
1144                                 /* mov r11, dst_reg */
1145                                 EMIT_mov(AUX_REG, dst_reg);
1146                                 dst_reg = AUX_REG;
1147                         }
1148
1149                         if (src_reg != BPF_REG_4) { /* common case */
1150                                 EMIT1(0x51); /* push rcx */
1151
1152                                 /* mov rcx, src_reg */
1153                                 EMIT_mov(BPF_REG_4, src_reg);
1154                         }
1155
1156                         /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1157                         maybe_emit_1mod(&prog, dst_reg,
1158                                         BPF_CLASS(insn->code) == BPF_ALU64);
1159
1160                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1161                         EMIT2(0xD3, add_1reg(b3, dst_reg));
1162
1163                         if (src_reg != BPF_REG_4)
1164                                 EMIT1(0x59); /* pop rcx */
1165
1166                         if (insn->dst_reg == BPF_REG_4)
1167                                 /* mov dst_reg, r11 */
1168                                 EMIT_mov(insn->dst_reg, AUX_REG);
1169                         break;
1170
1171                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1172                         switch (imm32) {
1173                         case 16:
1174                                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1175                                 EMIT1(0x66);
1176                                 if (is_ereg(dst_reg))
1177                                         EMIT1(0x41);
1178                                 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1179
1180                                 /* Emit 'movzwl eax, ax' */
1181                                 if (is_ereg(dst_reg))
1182                                         EMIT3(0x45, 0x0F, 0xB7);
1183                                 else
1184                                         EMIT2(0x0F, 0xB7);
1185                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1186                                 break;
1187                         case 32:
1188                                 /* Emit 'bswap eax' to swap lower 4 bytes */
1189                                 if (is_ereg(dst_reg))
1190                                         EMIT2(0x41, 0x0F);
1191                                 else
1192                                         EMIT1(0x0F);
1193                                 EMIT1(add_1reg(0xC8, dst_reg));
1194                                 break;
1195                         case 64:
1196                                 /* Emit 'bswap rax' to swap 8 bytes */
1197                                 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1198                                       add_1reg(0xC8, dst_reg));
1199                                 break;
1200                         }
1201                         break;
1202
1203                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1204                         switch (imm32) {
1205                         case 16:
1206                                 /*
1207                                  * Emit 'movzwl eax, ax' to zero extend 16-bit
1208                                  * into 64 bit
1209                                  */
1210                                 if (is_ereg(dst_reg))
1211                                         EMIT3(0x45, 0x0F, 0xB7);
1212                                 else
1213                                         EMIT2(0x0F, 0xB7);
1214                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1215                                 break;
1216                         case 32:
1217                                 /* Emit 'mov eax, eax' to clear upper 32-bits */
1218                                 if (is_ereg(dst_reg))
1219                                         EMIT1(0x45);
1220                                 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1221                                 break;
1222                         case 64:
1223                                 /* nop */
1224                                 break;
1225                         }
1226                         break;
1227
1228                         /* speculation barrier */
1229                 case BPF_ST | BPF_NOSPEC:
1230                         if (boot_cpu_has(X86_FEATURE_XMM2))
1231                                 /* Emit 'lfence' */
1232                                 EMIT3(0x0F, 0xAE, 0xE8);
1233                         break;
1234
1235                         /* ST: *(u8*)(dst_reg + off) = imm */
1236                 case BPF_ST | BPF_MEM | BPF_B:
1237                         if (is_ereg(dst_reg))
1238                                 EMIT2(0x41, 0xC6);
1239                         else
1240                                 EMIT1(0xC6);
1241                         goto st;
1242                 case BPF_ST | BPF_MEM | BPF_H:
1243                         if (is_ereg(dst_reg))
1244                                 EMIT3(0x66, 0x41, 0xC7);
1245                         else
1246                                 EMIT2(0x66, 0xC7);
1247                         goto st;
1248                 case BPF_ST | BPF_MEM | BPF_W:
1249                         if (is_ereg(dst_reg))
1250                                 EMIT2(0x41, 0xC7);
1251                         else
1252                                 EMIT1(0xC7);
1253                         goto st;
1254                 case BPF_ST | BPF_MEM | BPF_DW:
1255                         EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1256
1257 st:                     if (is_imm8(insn->off))
1258                                 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1259                         else
1260                                 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1261
1262                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1263                         break;
1264
1265                         /* STX: *(u8*)(dst_reg + off) = src_reg */
1266                 case BPF_STX | BPF_MEM | BPF_B:
1267                 case BPF_STX | BPF_MEM | BPF_H:
1268                 case BPF_STX | BPF_MEM | BPF_W:
1269                 case BPF_STX | BPF_MEM | BPF_DW:
1270                         emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1271                         break;
1272
1273                         /* LDX: dst_reg = *(u8*)(src_reg + off) */
1274                 case BPF_LDX | BPF_MEM | BPF_B:
1275                 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1276                 case BPF_LDX | BPF_MEM | BPF_H:
1277                 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1278                 case BPF_LDX | BPF_MEM | BPF_W:
1279                 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1280                 case BPF_LDX | BPF_MEM | BPF_DW:
1281                 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1282                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1283                                 /* Though the verifier prevents negative insn->off in BPF_PROBE_MEM
1284                                  * add abs(insn->off) to the limit to make sure that negative
1285                                  * offset won't be an issue.
1286                                  * insn->off is s16, so it won't affect valid pointers.
1287                                  */
1288                                 u64 limit = TASK_SIZE_MAX + PAGE_SIZE + abs(insn->off);
1289                                 u8 *end_of_jmp1, *end_of_jmp2;
1290
1291                                 /* Conservatively check that src_reg + insn->off is a kernel address:
1292                                  * 1. src_reg + insn->off >= limit
1293                                  * 2. src_reg + insn->off doesn't become small positive.
1294                                  * Cannot do src_reg + insn->off >= limit in one branch,
1295                                  * since it needs two spare registers, but JIT has only one.
1296                                  */
1297
1298                                 /* movabsq r11, limit */
1299                                 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1300                                 EMIT((u32)limit, 4);
1301                                 EMIT(limit >> 32, 4);
1302                                 /* cmp src_reg, r11 */
1303                                 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1304                                 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1305                                 /* if unsigned '<' goto end_of_jmp2 */
1306                                 EMIT2(X86_JB, 0);
1307                                 end_of_jmp1 = prog;
1308
1309                                 /* mov r11, src_reg */
1310                                 emit_mov_reg(&prog, true, AUX_REG, src_reg);
1311                                 /* add r11, insn->off */
1312                                 maybe_emit_1mod(&prog, AUX_REG, true);
1313                                 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1314                                 /* jmp if not carry to start_of_ldx
1315                                  * Otherwise ERR_PTR(-EINVAL) + 128 will be the user addr
1316                                  * that has to be rejected.
1317                                  */
1318                                 EMIT2(0x73 /* JNC */, 0);
1319                                 end_of_jmp2 = prog;
1320
1321                                 /* xor dst_reg, dst_reg */
1322                                 emit_mov_imm32(&prog, false, dst_reg, 0);
1323                                 /* jmp byte_after_ldx */
1324                                 EMIT2(0xEB, 0);
1325
1326                                 /* populate jmp_offset for JB above to jump to xor dst_reg */
1327                                 end_of_jmp1[-1] = end_of_jmp2 - end_of_jmp1;
1328                                 /* populate jmp_offset for JNC above to jump to start_of_ldx */
1329                                 start_of_ldx = prog;
1330                                 end_of_jmp2[-1] = start_of_ldx - end_of_jmp2;
1331                         }
1332                         emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1333                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1334                                 struct exception_table_entry *ex;
1335                                 u8 *_insn = image + proglen + (start_of_ldx - temp);
1336                                 s64 delta;
1337
1338                                 /* populate jmp_offset for JMP above */
1339                                 start_of_ldx[-1] = prog - start_of_ldx;
1340
1341                                 if (!bpf_prog->aux->extable)
1342                                         break;
1343
1344                                 if (excnt >= bpf_prog->aux->num_exentries) {
1345                                         pr_err("ex gen bug\n");
1346                                         return -EFAULT;
1347                                 }
1348                                 ex = &bpf_prog->aux->extable[excnt++];
1349
1350                                 delta = _insn - (u8 *)&ex->insn;
1351                                 if (!is_simm32(delta)) {
1352                                         pr_err("extable->insn doesn't fit into 32-bit\n");
1353                                         return -EFAULT;
1354                                 }
1355                                 ex->insn = delta;
1356
1357                                 delta = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
1358                                 if (!is_simm32(delta)) {
1359                                         pr_err("extable->handler doesn't fit into 32-bit\n");
1360                                         return -EFAULT;
1361                                 }
1362                                 ex->handler = delta;
1363
1364                                 if (dst_reg > BPF_REG_9) {
1365                                         pr_err("verifier error\n");
1366                                         return -EFAULT;
1367                                 }
1368                                 /*
1369                                  * Compute size of x86 insn and its target dest x86 register.
1370                                  * ex_handler_bpf() will use lower 8 bits to adjust
1371                                  * pt_regs->ip to jump over this x86 instruction
1372                                  * and upper bits to figure out which pt_regs to zero out.
1373                                  * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1374                                  * of 4 bytes will be ignored and rbx will be zero inited.
1375                                  */
1376                                 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1377                         }
1378                         break;
1379
1380                 case BPF_STX | BPF_ATOMIC | BPF_W:
1381                 case BPF_STX | BPF_ATOMIC | BPF_DW:
1382                         if (insn->imm == (BPF_AND | BPF_FETCH) ||
1383                             insn->imm == (BPF_OR | BPF_FETCH) ||
1384                             insn->imm == (BPF_XOR | BPF_FETCH)) {
1385                                 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1386                                 u32 real_src_reg = src_reg;
1387                                 u32 real_dst_reg = dst_reg;
1388                                 u8 *branch_target;
1389
1390                                 /*
1391                                  * Can't be implemented with a single x86 insn.
1392                                  * Need to do a CMPXCHG loop.
1393                                  */
1394
1395                                 /* Will need RAX as a CMPXCHG operand so save R0 */
1396                                 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1397                                 if (src_reg == BPF_REG_0)
1398                                         real_src_reg = BPF_REG_AX;
1399                                 if (dst_reg == BPF_REG_0)
1400                                         real_dst_reg = BPF_REG_AX;
1401
1402                                 branch_target = prog;
1403                                 /* Load old value */
1404                                 emit_ldx(&prog, BPF_SIZE(insn->code),
1405                                          BPF_REG_0, real_dst_reg, insn->off);
1406                                 /*
1407                                  * Perform the (commutative) operation locally,
1408                                  * put the result in the AUX_REG.
1409                                  */
1410                                 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1411                                 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1412                                 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1413                                       add_2reg(0xC0, AUX_REG, real_src_reg));
1414                                 /* Attempt to swap in new value */
1415                                 err = emit_atomic(&prog, BPF_CMPXCHG,
1416                                                   real_dst_reg, AUX_REG,
1417                                                   insn->off,
1418                                                   BPF_SIZE(insn->code));
1419                                 if (WARN_ON(err))
1420                                         return err;
1421                                 /*
1422                                  * ZF tells us whether we won the race. If it's
1423                                  * cleared we need to try again.
1424                                  */
1425                                 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1426                                 /* Return the pre-modification value */
1427                                 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1428                                 /* Restore R0 after clobbering RAX */
1429                                 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1430                                 break;
1431                         }
1432
1433                         err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1434                                           insn->off, BPF_SIZE(insn->code));
1435                         if (err)
1436                                 return err;
1437                         break;
1438
1439                         /* call */
1440                 case BPF_JMP | BPF_CALL:
1441                         func = (u8 *) __bpf_call_base + imm32;
1442                         if (tail_call_reachable) {
1443                                 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1444                                 EMIT3_off32(0x48, 0x8B, 0x85,
1445                                             -round_up(bpf_prog->aux->stack_depth, 8) - 8);
1446                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
1447                                         return -EINVAL;
1448                         } else {
1449                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1]))
1450                                         return -EINVAL;
1451                         }
1452                         break;
1453
1454                 case BPF_JMP | BPF_TAIL_CALL:
1455                         if (imm32)
1456                                 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1457                                                           &prog, addrs[i], image,
1458                                                           callee_regs_used,
1459                                                           bpf_prog->aux->stack_depth);
1460                         else
1461                                 emit_bpf_tail_call_indirect(&prog,
1462                                                             callee_regs_used,
1463                                                             bpf_prog->aux->stack_depth);
1464                         break;
1465
1466                         /* cond jump */
1467                 case BPF_JMP | BPF_JEQ | BPF_X:
1468                 case BPF_JMP | BPF_JNE | BPF_X:
1469                 case BPF_JMP | BPF_JGT | BPF_X:
1470                 case BPF_JMP | BPF_JLT | BPF_X:
1471                 case BPF_JMP | BPF_JGE | BPF_X:
1472                 case BPF_JMP | BPF_JLE | BPF_X:
1473                 case BPF_JMP | BPF_JSGT | BPF_X:
1474                 case BPF_JMP | BPF_JSLT | BPF_X:
1475                 case BPF_JMP | BPF_JSGE | BPF_X:
1476                 case BPF_JMP | BPF_JSLE | BPF_X:
1477                 case BPF_JMP32 | BPF_JEQ | BPF_X:
1478                 case BPF_JMP32 | BPF_JNE | BPF_X:
1479                 case BPF_JMP32 | BPF_JGT | BPF_X:
1480                 case BPF_JMP32 | BPF_JLT | BPF_X:
1481                 case BPF_JMP32 | BPF_JGE | BPF_X:
1482                 case BPF_JMP32 | BPF_JLE | BPF_X:
1483                 case BPF_JMP32 | BPF_JSGT | BPF_X:
1484                 case BPF_JMP32 | BPF_JSLT | BPF_X:
1485                 case BPF_JMP32 | BPF_JSGE | BPF_X:
1486                 case BPF_JMP32 | BPF_JSLE | BPF_X:
1487                         /* cmp dst_reg, src_reg */
1488                         maybe_emit_mod(&prog, dst_reg, src_reg,
1489                                        BPF_CLASS(insn->code) == BPF_JMP);
1490                         EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1491                         goto emit_cond_jmp;
1492
1493                 case BPF_JMP | BPF_JSET | BPF_X:
1494                 case BPF_JMP32 | BPF_JSET | BPF_X:
1495                         /* test dst_reg, src_reg */
1496                         maybe_emit_mod(&prog, dst_reg, src_reg,
1497                                        BPF_CLASS(insn->code) == BPF_JMP);
1498                         EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1499                         goto emit_cond_jmp;
1500
1501                 case BPF_JMP | BPF_JSET | BPF_K:
1502                 case BPF_JMP32 | BPF_JSET | BPF_K:
1503                         /* test dst_reg, imm32 */
1504                         maybe_emit_1mod(&prog, dst_reg,
1505                                         BPF_CLASS(insn->code) == BPF_JMP);
1506                         EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1507                         goto emit_cond_jmp;
1508
1509                 case BPF_JMP | BPF_JEQ | BPF_K:
1510                 case BPF_JMP | BPF_JNE | BPF_K:
1511                 case BPF_JMP | BPF_JGT | BPF_K:
1512                 case BPF_JMP | BPF_JLT | BPF_K:
1513                 case BPF_JMP | BPF_JGE | BPF_K:
1514                 case BPF_JMP | BPF_JLE | BPF_K:
1515                 case BPF_JMP | BPF_JSGT | BPF_K:
1516                 case BPF_JMP | BPF_JSLT | BPF_K:
1517                 case BPF_JMP | BPF_JSGE | BPF_K:
1518                 case BPF_JMP | BPF_JSLE | BPF_K:
1519                 case BPF_JMP32 | BPF_JEQ | BPF_K:
1520                 case BPF_JMP32 | BPF_JNE | BPF_K:
1521                 case BPF_JMP32 | BPF_JGT | BPF_K:
1522                 case BPF_JMP32 | BPF_JLT | BPF_K:
1523                 case BPF_JMP32 | BPF_JGE | BPF_K:
1524                 case BPF_JMP32 | BPF_JLE | BPF_K:
1525                 case BPF_JMP32 | BPF_JSGT | BPF_K:
1526                 case BPF_JMP32 | BPF_JSLT | BPF_K:
1527                 case BPF_JMP32 | BPF_JSGE | BPF_K:
1528                 case BPF_JMP32 | BPF_JSLE | BPF_K:
1529                         /* test dst_reg, dst_reg to save one extra byte */
1530                         if (imm32 == 0) {
1531                                 maybe_emit_mod(&prog, dst_reg, dst_reg,
1532                                                BPF_CLASS(insn->code) == BPF_JMP);
1533                                 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1534                                 goto emit_cond_jmp;
1535                         }
1536
1537                         /* cmp dst_reg, imm8/32 */
1538                         maybe_emit_1mod(&prog, dst_reg,
1539                                         BPF_CLASS(insn->code) == BPF_JMP);
1540
1541                         if (is_imm8(imm32))
1542                                 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1543                         else
1544                                 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1545
1546 emit_cond_jmp:          /* Convert BPF opcode to x86 */
1547                         switch (BPF_OP(insn->code)) {
1548                         case BPF_JEQ:
1549                                 jmp_cond = X86_JE;
1550                                 break;
1551                         case BPF_JSET:
1552                         case BPF_JNE:
1553                                 jmp_cond = X86_JNE;
1554                                 break;
1555                         case BPF_JGT:
1556                                 /* GT is unsigned '>', JA in x86 */
1557                                 jmp_cond = X86_JA;
1558                                 break;
1559                         case BPF_JLT:
1560                                 /* LT is unsigned '<', JB in x86 */
1561                                 jmp_cond = X86_JB;
1562                                 break;
1563                         case BPF_JGE:
1564                                 /* GE is unsigned '>=', JAE in x86 */
1565                                 jmp_cond = X86_JAE;
1566                                 break;
1567                         case BPF_JLE:
1568                                 /* LE is unsigned '<=', JBE in x86 */
1569                                 jmp_cond = X86_JBE;
1570                                 break;
1571                         case BPF_JSGT:
1572                                 /* Signed '>', GT in x86 */
1573                                 jmp_cond = X86_JG;
1574                                 break;
1575                         case BPF_JSLT:
1576                                 /* Signed '<', LT in x86 */
1577                                 jmp_cond = X86_JL;
1578                                 break;
1579                         case BPF_JSGE:
1580                                 /* Signed '>=', GE in x86 */
1581                                 jmp_cond = X86_JGE;
1582                                 break;
1583                         case BPF_JSLE:
1584                                 /* Signed '<=', LE in x86 */
1585                                 jmp_cond = X86_JLE;
1586                                 break;
1587                         default: /* to silence GCC warning */
1588                                 return -EFAULT;
1589                         }
1590                         jmp_offset = addrs[i + insn->off] - addrs[i];
1591                         if (is_imm8(jmp_offset)) {
1592                                 if (jmp_padding) {
1593                                         /* To keep the jmp_offset valid, the extra bytes are
1594                                          * padded before the jump insn, so we subtract the
1595                                          * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1596                                          *
1597                                          * If the previous pass already emits an imm8
1598                                          * jmp_cond, then this BPF insn won't shrink, so
1599                                          * "nops" is 0.
1600                                          *
1601                                          * On the other hand, if the previous pass emits an
1602                                          * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1603                                          * keep the image from shrinking further.
1604                                          *
1605                                          * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1606                                          *     is 2 bytes, so the size difference is 4 bytes.
1607                                          */
1608                                         nops = INSN_SZ_DIFF - 2;
1609                                         if (nops != 0 && nops != 4) {
1610                                                 pr_err("unexpected jmp_cond padding: %d bytes\n",
1611                                                        nops);
1612                                                 return -EFAULT;
1613                                         }
1614                                         emit_nops(&prog, nops);
1615                                 }
1616                                 EMIT2(jmp_cond, jmp_offset);
1617                         } else if (is_simm32(jmp_offset)) {
1618                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1619                         } else {
1620                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1621                                 return -EFAULT;
1622                         }
1623
1624                         break;
1625
1626                 case BPF_JMP | BPF_JA:
1627                         if (insn->off == -1)
1628                                 /* -1 jmp instructions will always jump
1629                                  * backwards two bytes. Explicitly handling
1630                                  * this case avoids wasting too many passes
1631                                  * when there are long sequences of replaced
1632                                  * dead code.
1633                                  */
1634                                 jmp_offset = -2;
1635                         else
1636                                 jmp_offset = addrs[i + insn->off] - addrs[i];
1637
1638                         if (!jmp_offset) {
1639                                 /*
1640                                  * If jmp_padding is enabled, the extra nops will
1641                                  * be inserted. Otherwise, optimize out nop jumps.
1642                                  */
1643                                 if (jmp_padding) {
1644                                         /* There are 3 possible conditions.
1645                                          * (1) This BPF_JA is already optimized out in
1646                                          *     the previous run, so there is no need
1647                                          *     to pad any extra byte (0 byte).
1648                                          * (2) The previous pass emits an imm8 jmp,
1649                                          *     so we pad 2 bytes to match the previous
1650                                          *     insn size.
1651                                          * (3) Similarly, the previous pass emits an
1652                                          *     imm32 jmp, and 5 bytes is padded.
1653                                          */
1654                                         nops = INSN_SZ_DIFF;
1655                                         if (nops != 0 && nops != 2 && nops != 5) {
1656                                                 pr_err("unexpected nop jump padding: %d bytes\n",
1657                                                        nops);
1658                                                 return -EFAULT;
1659                                         }
1660                                         emit_nops(&prog, nops);
1661                                 }
1662                                 break;
1663                         }
1664 emit_jmp:
1665                         if (is_imm8(jmp_offset)) {
1666                                 if (jmp_padding) {
1667                                         /* To avoid breaking jmp_offset, the extra bytes
1668                                          * are padded before the actual jmp insn, so
1669                                          * 2 bytes is subtracted from INSN_SZ_DIFF.
1670                                          *
1671                                          * If the previous pass already emits an imm8
1672                                          * jmp, there is nothing to pad (0 byte).
1673                                          *
1674                                          * If it emits an imm32 jmp (5 bytes) previously
1675                                          * and now an imm8 jmp (2 bytes), then we pad
1676                                          * (5 - 2 = 3) bytes to stop the image from
1677                                          * shrinking further.
1678                                          */
1679                                         nops = INSN_SZ_DIFF - 2;
1680                                         if (nops != 0 && nops != 3) {
1681                                                 pr_err("unexpected jump padding: %d bytes\n",
1682                                                        nops);
1683                                                 return -EFAULT;
1684                                         }
1685                                         emit_nops(&prog, INSN_SZ_DIFF - 2);
1686                                 }
1687                                 EMIT2(0xEB, jmp_offset);
1688                         } else if (is_simm32(jmp_offset)) {
1689                                 EMIT1_off32(0xE9, jmp_offset);
1690                         } else {
1691                                 pr_err("jmp gen bug %llx\n", jmp_offset);
1692                                 return -EFAULT;
1693                         }
1694                         break;
1695
1696                 case BPF_JMP | BPF_EXIT:
1697                         if (seen_exit) {
1698                                 jmp_offset = ctx->cleanup_addr - addrs[i];
1699                                 goto emit_jmp;
1700                         }
1701                         seen_exit = true;
1702                         /* Update cleanup_addr */
1703                         ctx->cleanup_addr = proglen;
1704                         pop_callee_regs(&prog, callee_regs_used);
1705                         EMIT1(0xC9);         /* leave */
1706                         EMIT1(0xC3);         /* ret */
1707                         break;
1708
1709                 default:
1710                         /*
1711                          * By design x86-64 JIT should support all BPF instructions.
1712                          * This error will be seen if new instruction was added
1713                          * to the interpreter, but not to the JIT, or if there is
1714                          * junk in bpf_prog.
1715                          */
1716                         pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1717                         return -EINVAL;
1718                 }
1719
1720                 ilen = prog - temp;
1721                 if (ilen > BPF_MAX_INSN_SIZE) {
1722                         pr_err("bpf_jit: fatal insn size error\n");
1723                         return -EFAULT;
1724                 }
1725
1726                 if (image) {
1727                         /*
1728                          * When populating the image, assert that:
1729                          *
1730                          *  i) We do not write beyond the allocated space, and
1731                          * ii) addrs[i] did not change from the prior run, in order
1732                          *     to validate assumptions made for computing branch
1733                          *     displacements.
1734                          */
1735                         if (unlikely(proglen + ilen > oldproglen ||
1736                                      proglen + ilen != addrs[i])) {
1737                                 pr_err("bpf_jit: fatal error\n");
1738                                 return -EFAULT;
1739                         }
1740                         memcpy(image + proglen, temp, ilen);
1741                 }
1742                 proglen += ilen;
1743                 addrs[i] = proglen;
1744                 prog = temp;
1745         }
1746
1747         if (image && excnt != bpf_prog->aux->num_exentries) {
1748                 pr_err("extable is not populated\n");
1749                 return -EFAULT;
1750         }
1751         return proglen;
1752 }
1753
1754 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1755                       int stack_size)
1756 {
1757         int i;
1758         /* Store function arguments to stack.
1759          * For a function that accepts two pointers the sequence will be:
1760          * mov QWORD PTR [rbp-0x10],rdi
1761          * mov QWORD PTR [rbp-0x8],rsi
1762          */
1763         for (i = 0; i < min(nr_args, 6); i++)
1764                 emit_stx(prog, bytes_to_bpf_size(m->arg_size[i]),
1765                          BPF_REG_FP,
1766                          i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1767                          -(stack_size - i * 8));
1768 }
1769
1770 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1771                          int stack_size)
1772 {
1773         int i;
1774
1775         /* Restore function arguments from stack.
1776          * For a function that accepts two pointers the sequence will be:
1777          * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1778          * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1779          */
1780         for (i = 0; i < min(nr_args, 6); i++)
1781                 emit_ldx(prog, bytes_to_bpf_size(m->arg_size[i]),
1782                          i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1783                          BPF_REG_FP,
1784                          -(stack_size - i * 8));
1785 }
1786
1787 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1788                            struct bpf_prog *p, int stack_size, bool save_ret)
1789 {
1790         u8 *prog = *pprog;
1791         u8 *jmp_insn;
1792
1793         /* arg1: mov rdi, progs[i] */
1794         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1795         if (emit_call(&prog,
1796                       p->aux->sleepable ? __bpf_prog_enter_sleepable :
1797                       __bpf_prog_enter, prog))
1798                         return -EINVAL;
1799         /* remember prog start time returned by __bpf_prog_enter */
1800         emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1801
1802         /* if (__bpf_prog_enter*(prog) == 0)
1803          *      goto skip_exec_of_prog;
1804          */
1805         EMIT3(0x48, 0x85, 0xC0);  /* test rax,rax */
1806         /* emit 2 nops that will be replaced with JE insn */
1807         jmp_insn = prog;
1808         emit_nops(&prog, 2);
1809
1810         /* arg1: lea rdi, [rbp - stack_size] */
1811         EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1812         /* arg2: progs[i]->insnsi for interpreter */
1813         if (!p->jited)
1814                 emit_mov_imm64(&prog, BPF_REG_2,
1815                                (long) p->insnsi >> 32,
1816                                (u32) (long) p->insnsi);
1817         /* call JITed bpf program or interpreter */
1818         if (emit_call(&prog, p->bpf_func, prog))
1819                 return -EINVAL;
1820
1821         /*
1822          * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1823          * of the previous call which is then passed on the stack to
1824          * the next BPF program.
1825          *
1826          * BPF_TRAMP_FENTRY trampoline may need to return the return
1827          * value of BPF_PROG_TYPE_STRUCT_OPS prog.
1828          */
1829         if (save_ret)
1830                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1831
1832         /* replace 2 nops with JE insn, since jmp target is known */
1833         jmp_insn[0] = X86_JE;
1834         jmp_insn[1] = prog - jmp_insn - 2;
1835
1836         /* arg1: mov rdi, progs[i] */
1837         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1838         /* arg2: mov rsi, rbx <- start time in nsec */
1839         emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1840         if (emit_call(&prog,
1841                       p->aux->sleepable ? __bpf_prog_exit_sleepable :
1842                       __bpf_prog_exit, prog))
1843                         return -EINVAL;
1844
1845         *pprog = prog;
1846         return 0;
1847 }
1848
1849 static void emit_align(u8 **pprog, u32 align)
1850 {
1851         u8 *target, *prog = *pprog;
1852
1853         target = PTR_ALIGN(prog, align);
1854         if (target != prog)
1855                 emit_nops(&prog, target - prog);
1856
1857         *pprog = prog;
1858 }
1859
1860 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
1861 {
1862         u8 *prog = *pprog;
1863         s64 offset;
1864
1865         offset = func - (ip + 2 + 4);
1866         if (!is_simm32(offset)) {
1867                 pr_err("Target %p is out of range\n", func);
1868                 return -EINVAL;
1869         }
1870         EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
1871         *pprog = prog;
1872         return 0;
1873 }
1874
1875 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
1876                       struct bpf_tramp_progs *tp, int stack_size,
1877                       bool save_ret)
1878 {
1879         int i;
1880         u8 *prog = *pprog;
1881
1882         for (i = 0; i < tp->nr_progs; i++) {
1883                 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size,
1884                                     save_ret))
1885                         return -EINVAL;
1886         }
1887         *pprog = prog;
1888         return 0;
1889 }
1890
1891 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
1892                               struct bpf_tramp_progs *tp, int stack_size,
1893                               u8 **branches)
1894 {
1895         u8 *prog = *pprog;
1896         int i;
1897
1898         /* The first fmod_ret program will receive a garbage return value.
1899          * Set this to 0 to avoid confusing the program.
1900          */
1901         emit_mov_imm32(&prog, false, BPF_REG_0, 0);
1902         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1903         for (i = 0; i < tp->nr_progs; i++) {
1904                 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, true))
1905                         return -EINVAL;
1906
1907                 /* mod_ret prog stored return value into [rbp - 8]. Emit:
1908                  * if (*(u64 *)(rbp - 8) !=  0)
1909                  *      goto do_fexit;
1910                  */
1911                 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
1912                 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
1913
1914                 /* Save the location of the branch and Generate 6 nops
1915                  * (4 bytes for an offset and 2 bytes for the jump) These nops
1916                  * are replaced with a conditional jump once do_fexit (i.e. the
1917                  * start of the fexit invocation) is finalized.
1918                  */
1919                 branches[i] = prog;
1920                 emit_nops(&prog, 4 + 2);
1921         }
1922
1923         *pprog = prog;
1924         return 0;
1925 }
1926
1927 static bool is_valid_bpf_tramp_flags(unsigned int flags)
1928 {
1929         if ((flags & BPF_TRAMP_F_RESTORE_REGS) &&
1930             (flags & BPF_TRAMP_F_SKIP_FRAME))
1931                 return false;
1932
1933         /*
1934          * BPF_TRAMP_F_RET_FENTRY_RET is only used by bpf_struct_ops,
1935          * and it must be used alone.
1936          */
1937         if ((flags & BPF_TRAMP_F_RET_FENTRY_RET) &&
1938             (flags & ~BPF_TRAMP_F_RET_FENTRY_RET))
1939                 return false;
1940
1941         return true;
1942 }
1943
1944 /* Example:
1945  * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
1946  * its 'struct btf_func_model' will be nr_args=2
1947  * The assembly code when eth_type_trans is executing after trampoline:
1948  *
1949  * push rbp
1950  * mov rbp, rsp
1951  * sub rsp, 16                     // space for skb and dev
1952  * push rbx                        // temp regs to pass start time
1953  * mov qword ptr [rbp - 16], rdi   // save skb pointer to stack
1954  * mov qword ptr [rbp - 8], rsi    // save dev pointer to stack
1955  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1956  * mov rbx, rax                    // remember start time in bpf stats are enabled
1957  * lea rdi, [rbp - 16]             // R1==ctx of bpf prog
1958  * call addr_of_jited_FENTRY_prog
1959  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1960  * mov rsi, rbx                    // prog start time
1961  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1962  * mov rdi, qword ptr [rbp - 16]   // restore skb pointer from stack
1963  * mov rsi, qword ptr [rbp - 8]    // restore dev pointer from stack
1964  * pop rbx
1965  * leave
1966  * ret
1967  *
1968  * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
1969  * replaced with 'call generated_bpf_trampoline'. When it returns
1970  * eth_type_trans will continue executing with original skb and dev pointers.
1971  *
1972  * The assembly code when eth_type_trans is called from trampoline:
1973  *
1974  * push rbp
1975  * mov rbp, rsp
1976  * sub rsp, 24                     // space for skb, dev, return value
1977  * push rbx                        // temp regs to pass start time
1978  * mov qword ptr [rbp - 24], rdi   // save skb pointer to stack
1979  * mov qword ptr [rbp - 16], rsi   // save dev pointer to stack
1980  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1981  * mov rbx, rax                    // remember start time if bpf stats are enabled
1982  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
1983  * call addr_of_jited_FENTRY_prog  // bpf prog can access skb and dev
1984  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1985  * mov rsi, rbx                    // prog start time
1986  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1987  * mov rdi, qword ptr [rbp - 24]   // restore skb pointer from stack
1988  * mov rsi, qword ptr [rbp - 16]   // restore dev pointer from stack
1989  * call eth_type_trans+5           // execute body of eth_type_trans
1990  * mov qword ptr [rbp - 8], rax    // save return value
1991  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1992  * mov rbx, rax                    // remember start time in bpf stats are enabled
1993  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
1994  * call addr_of_jited_FEXIT_prog   // bpf prog can access skb, dev, return value
1995  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1996  * mov rsi, rbx                    // prog start time
1997  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1998  * mov rax, qword ptr [rbp - 8]    // restore eth_type_trans's return value
1999  * pop rbx
2000  * leave
2001  * add rsp, 8                      // skip eth_type_trans's frame
2002  * ret                             // return to its caller
2003  */
2004 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2005                                 const struct btf_func_model *m, u32 flags,
2006                                 struct bpf_tramp_progs *tprogs,
2007                                 void *orig_call)
2008 {
2009         int ret, i, nr_args = m->nr_args;
2010         int stack_size = nr_args * 8;
2011         struct bpf_tramp_progs *fentry = &tprogs[BPF_TRAMP_FENTRY];
2012         struct bpf_tramp_progs *fexit = &tprogs[BPF_TRAMP_FEXIT];
2013         struct bpf_tramp_progs *fmod_ret = &tprogs[BPF_TRAMP_MODIFY_RETURN];
2014         u8 **branches = NULL;
2015         u8 *prog;
2016         bool save_ret;
2017
2018         /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
2019         if (nr_args > 6)
2020                 return -ENOTSUPP;
2021
2022         if (!is_valid_bpf_tramp_flags(flags))
2023                 return -EINVAL;
2024
2025         /* room for return value of orig_call or fentry prog */
2026         save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2027         if (save_ret)
2028                 stack_size += 8;
2029
2030         if (flags & BPF_TRAMP_F_IP_ARG)
2031                 stack_size += 8; /* room for IP address argument */
2032
2033         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2034                 /* skip patched call instruction and point orig_call to actual
2035                  * body of the kernel function.
2036                  */
2037                 orig_call += X86_PATCH_SIZE;
2038
2039         prog = image;
2040
2041         EMIT1(0x55);             /* push rbp */
2042         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2043         EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
2044         EMIT1(0x53);             /* push rbx */
2045
2046         if (flags & BPF_TRAMP_F_IP_ARG) {
2047                 /* Store IP address of the traced function:
2048                  * mov rax, QWORD PTR [rbp + 8]
2049                  * sub rax, X86_PATCH_SIZE
2050                  * mov QWORD PTR [rbp - stack_size], rax
2051                  */
2052                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
2053                 EMIT4(0x48, 0x83, 0xe8, X86_PATCH_SIZE);
2054                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -stack_size);
2055
2056                 /* Continue with stack_size for regs storage, stack will
2057                  * be correctly restored with 'leave' instruction.
2058                  */
2059                 stack_size -= 8;
2060         }
2061
2062         save_regs(m, &prog, nr_args, stack_size);
2063
2064         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2065                 /* arg1: mov rdi, im */
2066                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2067                 if (emit_call(&prog, __bpf_tramp_enter, prog)) {
2068                         ret = -EINVAL;
2069                         goto cleanup;
2070                 }
2071         }
2072
2073         if (fentry->nr_progs)
2074                 if (invoke_bpf(m, &prog, fentry, stack_size,
2075                                flags & BPF_TRAMP_F_RET_FENTRY_RET))
2076                         return -EINVAL;
2077
2078         if (fmod_ret->nr_progs) {
2079                 branches = kcalloc(fmod_ret->nr_progs, sizeof(u8 *),
2080                                    GFP_KERNEL);
2081                 if (!branches)
2082                         return -ENOMEM;
2083
2084                 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, stack_size,
2085                                        branches)) {
2086                         ret = -EINVAL;
2087                         goto cleanup;
2088                 }
2089         }
2090
2091         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2092                 restore_regs(m, &prog, nr_args, stack_size);
2093
2094                 /* call original function */
2095                 if (emit_call(&prog, orig_call, prog)) {
2096                         ret = -EINVAL;
2097                         goto cleanup;
2098                 }
2099                 /* remember return value in a stack for bpf prog to access */
2100                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2101                 im->ip_after_call = prog;
2102                 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2103                 prog += X86_PATCH_SIZE;
2104         }
2105
2106         if (fmod_ret->nr_progs) {
2107                 /* From Intel 64 and IA-32 Architectures Optimization
2108                  * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2109                  * Coding Rule 11: All branch targets should be 16-byte
2110                  * aligned.
2111                  */
2112                 emit_align(&prog, 16);
2113                 /* Update the branches saved in invoke_bpf_mod_ret with the
2114                  * aligned address of do_fexit.
2115                  */
2116                 for (i = 0; i < fmod_ret->nr_progs; i++)
2117                         emit_cond_near_jump(&branches[i], prog, branches[i],
2118                                             X86_JNE);
2119         }
2120
2121         if (fexit->nr_progs)
2122                 if (invoke_bpf(m, &prog, fexit, stack_size, false)) {
2123                         ret = -EINVAL;
2124                         goto cleanup;
2125                 }
2126
2127         if (flags & BPF_TRAMP_F_RESTORE_REGS)
2128                 restore_regs(m, &prog, nr_args, stack_size);
2129
2130         /* This needs to be done regardless. If there were fmod_ret programs,
2131          * the return value is only updated on the stack and still needs to be
2132          * restored to R0.
2133          */
2134         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2135                 im->ip_epilogue = prog;
2136                 /* arg1: mov rdi, im */
2137                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2138                 if (emit_call(&prog, __bpf_tramp_exit, prog)) {
2139                         ret = -EINVAL;
2140                         goto cleanup;
2141                 }
2142         }
2143         /* restore return value of orig_call or fentry prog back into RAX */
2144         if (save_ret)
2145                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2146
2147         EMIT1(0x5B); /* pop rbx */
2148         EMIT1(0xC9); /* leave */
2149         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2150                 /* skip our return address and return to parent */
2151                 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2152         EMIT1(0xC3); /* ret */
2153         /* Make sure the trampoline generation logic doesn't overflow */
2154         if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2155                 ret = -EFAULT;
2156                 goto cleanup;
2157         }
2158         ret = prog - (u8 *)image;
2159
2160 cleanup:
2161         kfree(branches);
2162         return ret;
2163 }
2164
2165 static int emit_fallback_jump(u8 **pprog)
2166 {
2167         u8 *prog = *pprog;
2168         int err = 0;
2169
2170 #ifdef CONFIG_RETPOLINE
2171         /* Note that this assumes the the compiler uses external
2172          * thunks for indirect calls. Both clang and GCC use the same
2173          * naming convention for external thunks.
2174          */
2175         err = emit_jump(&prog, __x86_indirect_thunk_rdx, prog);
2176 #else
2177         EMIT2(0xFF, 0xE2);      /* jmp rdx */
2178 #endif
2179         *pprog = prog;
2180         return err;
2181 }
2182
2183 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs)
2184 {
2185         u8 *jg_reloc, *prog = *pprog;
2186         int pivot, err, jg_bytes = 1;
2187         s64 jg_offset;
2188
2189         if (a == b) {
2190                 /* Leaf node of recursion, i.e. not a range of indices
2191                  * anymore.
2192                  */
2193                 EMIT1(add_1mod(0x48, BPF_REG_3));       /* cmp rdx,func */
2194                 if (!is_simm32(progs[a]))
2195                         return -1;
2196                 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2197                             progs[a]);
2198                 err = emit_cond_near_jump(&prog,        /* je func */
2199                                           (void *)progs[a], prog,
2200                                           X86_JE);
2201                 if (err)
2202                         return err;
2203
2204                 err = emit_fallback_jump(&prog);        /* jmp thunk/indirect */
2205                 if (err)
2206                         return err;
2207
2208                 *pprog = prog;
2209                 return 0;
2210         }
2211
2212         /* Not a leaf node, so we pivot, and recursively descend into
2213          * the lower and upper ranges.
2214          */
2215         pivot = (b - a) / 2;
2216         EMIT1(add_1mod(0x48, BPF_REG_3));               /* cmp rdx,func */
2217         if (!is_simm32(progs[a + pivot]))
2218                 return -1;
2219         EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2220
2221         if (pivot > 2) {                                /* jg upper_part */
2222                 /* Require near jump. */
2223                 jg_bytes = 4;
2224                 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2225         } else {
2226                 EMIT2(X86_JG, 0);
2227         }
2228         jg_reloc = prog;
2229
2230         err = emit_bpf_dispatcher(&prog, a, a + pivot,  /* emit lower_part */
2231                                   progs);
2232         if (err)
2233                 return err;
2234
2235         /* From Intel 64 and IA-32 Architectures Optimization
2236          * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2237          * Coding Rule 11: All branch targets should be 16-byte
2238          * aligned.
2239          */
2240         emit_align(&prog, 16);
2241         jg_offset = prog - jg_reloc;
2242         emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2243
2244         err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2245                                   b, progs);
2246         if (err)
2247                 return err;
2248
2249         *pprog = prog;
2250         return 0;
2251 }
2252
2253 static int cmp_ips(const void *a, const void *b)
2254 {
2255         const s64 *ipa = a;
2256         const s64 *ipb = b;
2257
2258         if (*ipa > *ipb)
2259                 return 1;
2260         if (*ipa < *ipb)
2261                 return -1;
2262         return 0;
2263 }
2264
2265 int arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs)
2266 {
2267         u8 *prog = image;
2268
2269         sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2270         return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs);
2271 }
2272
2273 struct x64_jit_data {
2274         struct bpf_binary_header *header;
2275         int *addrs;
2276         u8 *image;
2277         int proglen;
2278         struct jit_context ctx;
2279 };
2280
2281 #define MAX_PASSES 20
2282 #define PADDING_PASSES (MAX_PASSES - 5)
2283
2284 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2285 {
2286         struct bpf_binary_header *header = NULL;
2287         struct bpf_prog *tmp, *orig_prog = prog;
2288         struct x64_jit_data *jit_data;
2289         int proglen, oldproglen = 0;
2290         struct jit_context ctx = {};
2291         bool tmp_blinded = false;
2292         bool extra_pass = false;
2293         bool padding = false;
2294         u8 *image = NULL;
2295         int *addrs;
2296         int pass;
2297         int i;
2298
2299         if (!prog->jit_requested)
2300                 return orig_prog;
2301
2302         tmp = bpf_jit_blind_constants(prog);
2303         /*
2304          * If blinding was requested and we failed during blinding,
2305          * we must fall back to the interpreter.
2306          */
2307         if (IS_ERR(tmp))
2308                 return orig_prog;
2309         if (tmp != prog) {
2310                 tmp_blinded = true;
2311                 prog = tmp;
2312         }
2313
2314         jit_data = prog->aux->jit_data;
2315         if (!jit_data) {
2316                 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2317                 if (!jit_data) {
2318                         prog = orig_prog;
2319                         goto out;
2320                 }
2321                 prog->aux->jit_data = jit_data;
2322         }
2323         addrs = jit_data->addrs;
2324         if (addrs) {
2325                 ctx = jit_data->ctx;
2326                 oldproglen = jit_data->proglen;
2327                 image = jit_data->image;
2328                 header = jit_data->header;
2329                 extra_pass = true;
2330                 padding = true;
2331                 goto skip_init_addrs;
2332         }
2333         addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2334         if (!addrs) {
2335                 prog = orig_prog;
2336                 goto out_addrs;
2337         }
2338
2339         /*
2340          * Before first pass, make a rough estimation of addrs[]
2341          * each BPF instruction is translated to less than 64 bytes
2342          */
2343         for (proglen = 0, i = 0; i <= prog->len; i++) {
2344                 proglen += 64;
2345                 addrs[i] = proglen;
2346         }
2347         ctx.cleanup_addr = proglen;
2348 skip_init_addrs:
2349
2350         /*
2351          * JITed image shrinks with every pass and the loop iterates
2352          * until the image stops shrinking. Very large BPF programs
2353          * may converge on the last pass. In such case do one more
2354          * pass to emit the final image.
2355          */
2356         for (pass = 0; pass < MAX_PASSES || image; pass++) {
2357                 if (!padding && pass >= PADDING_PASSES)
2358                         padding = true;
2359                 proglen = do_jit(prog, addrs, image, oldproglen, &ctx, padding);
2360                 if (proglen <= 0) {
2361 out_image:
2362                         image = NULL;
2363                         if (header)
2364                                 bpf_jit_binary_free(header);
2365                         prog = orig_prog;
2366                         goto out_addrs;
2367                 }
2368                 if (image) {
2369                         if (proglen != oldproglen) {
2370                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2371                                        proglen, oldproglen);
2372                                 goto out_image;
2373                         }
2374                         break;
2375                 }
2376                 if (proglen == oldproglen) {
2377                         /*
2378                          * The number of entries in extable is the number of BPF_LDX
2379                          * insns that access kernel memory via "pointer to BTF type".
2380                          * The verifier changed their opcode from LDX|MEM|size
2381                          * to LDX|PROBE_MEM|size to make JITing easier.
2382                          */
2383                         u32 align = __alignof__(struct exception_table_entry);
2384                         u32 extable_size = prog->aux->num_exentries *
2385                                 sizeof(struct exception_table_entry);
2386
2387                         /* allocate module memory for x86 insns and extable */
2388                         header = bpf_jit_binary_alloc(roundup(proglen, align) + extable_size,
2389                                                       &image, align, jit_fill_hole);
2390                         if (!header) {
2391                                 prog = orig_prog;
2392                                 goto out_addrs;
2393                         }
2394                         prog->aux->extable = (void *) image + roundup(proglen, align);
2395                 }
2396                 oldproglen = proglen;
2397                 cond_resched();
2398         }
2399
2400         if (bpf_jit_enable > 1)
2401                 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2402
2403         if (image) {
2404                 if (!prog->is_func || extra_pass) {
2405                         bpf_tail_call_direct_fixup(prog);
2406                         bpf_jit_binary_lock_ro(header);
2407                 } else {
2408                         jit_data->addrs = addrs;
2409                         jit_data->ctx = ctx;
2410                         jit_data->proglen = proglen;
2411                         jit_data->image = image;
2412                         jit_data->header = header;
2413                 }
2414                 prog->bpf_func = (void *)image;
2415                 prog->jited = 1;
2416                 prog->jited_len = proglen;
2417         } else {
2418                 prog = orig_prog;
2419         }
2420
2421         if (!image || !prog->is_func || extra_pass) {
2422                 if (image)
2423                         bpf_prog_fill_jited_linfo(prog, addrs + 1);
2424 out_addrs:
2425                 kvfree(addrs);
2426                 kfree(jit_data);
2427                 prog->aux->jit_data = NULL;
2428         }
2429 out:
2430         if (tmp_blinded)
2431                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2432                                            tmp : orig_prog);
2433         return prog;
2434 }
2435
2436 bool bpf_jit_supports_kfunc_call(void)
2437 {
2438         return true;
2439 }