2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/sched.h>
9 #include <linux/interrupt.h>
10 #include <linux/seq_file.h>
11 #include <linux/debugfs.h>
12 #include <linux/pfn.h>
13 #include <linux/percpu.h>
14 #include <linux/gfp.h>
15 #include <linux/pci.h>
16 #include <linux/vmalloc.h>
18 #include <asm/e820/api.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <linux/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
27 #include <asm/set_memory.h>
30 * The current flushing context - we pass it instead of 5 arguments:
37 unsigned long numpages;
40 unsigned force_split : 1;
46 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
47 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
48 * entries change the page attribute in parallel to some other cpu
49 * splitting a large page entry along with changing the attribute.
51 static DEFINE_SPINLOCK(cpa_lock);
53 #define CPA_FLUSHTLB 1
55 #define CPA_PAGES_ARRAY 4
58 static unsigned long direct_pages_count[PG_LEVEL_NUM];
60 void update_page_count(int level, unsigned long pages)
62 /* Protect against CPA */
64 direct_pages_count[level] += pages;
65 spin_unlock(&pgd_lock);
68 static void split_page_count(int level)
70 if (direct_pages_count[level] == 0)
73 direct_pages_count[level]--;
74 direct_pages_count[level - 1] += PTRS_PER_PTE;
77 void arch_report_meminfo(struct seq_file *m)
79 seq_printf(m, "DirectMap4k: %8lu kB\n",
80 direct_pages_count[PG_LEVEL_4K] << 2);
81 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
82 seq_printf(m, "DirectMap2M: %8lu kB\n",
83 direct_pages_count[PG_LEVEL_2M] << 11);
85 seq_printf(m, "DirectMap4M: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_2M] << 12);
89 seq_printf(m, "DirectMap1G: %8lu kB\n",
90 direct_pages_count[PG_LEVEL_1G] << 20);
93 static inline void split_page_count(int level) { }
98 static inline unsigned long highmap_start_pfn(void)
100 return __pa_symbol(_text) >> PAGE_SHIFT;
103 static inline unsigned long highmap_end_pfn(void)
105 /* Do not reference physical address outside the kernel. */
106 return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT;
112 within(unsigned long addr, unsigned long start, unsigned long end)
114 return addr >= start && addr < end;
118 within_inclusive(unsigned long addr, unsigned long start, unsigned long end)
120 return addr >= start && addr <= end;
128 * clflush_cache_range - flush a cache range with clflush
129 * @vaddr: virtual start address
130 * @size: number of bytes to flush
132 * clflushopt is an unordered instruction which needs fencing with mfence or
133 * sfence to avoid ordering issues.
135 void clflush_cache_range(void *vaddr, unsigned int size)
137 const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
138 void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1));
139 void *vend = vaddr + size;
146 for (; p < vend; p += clflush_size)
151 EXPORT_SYMBOL_GPL(clflush_cache_range);
153 void arch_invalidate_pmem(void *addr, size_t size)
155 clflush_cache_range(addr, size);
157 EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
159 static void __cpa_flush_all(void *arg)
161 unsigned long cache = (unsigned long)arg;
164 * Flush all to work around Errata in early athlons regarding
165 * large page flushing.
169 if (cache && boot_cpu_data.x86 >= 4)
173 static void cpa_flush_all(unsigned long cache)
175 BUG_ON(irqs_disabled());
177 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
180 static void __cpa_flush_range(void *arg)
183 * We could optimize that further and do individual per page
184 * tlb invalidates for a low number of pages. Caveat: we must
185 * flush the high aliases on 64bit as well.
190 static void cpa_flush_range(unsigned long start, int numpages, int cache)
192 unsigned int i, level;
195 BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
196 WARN_ON(PAGE_ALIGN(start) != start);
198 on_each_cpu(__cpa_flush_range, NULL, 1);
204 * We only need to flush on one CPU,
205 * clflush is a MESI-coherent instruction that
206 * will cause all other CPUs to flush the same
209 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
210 pte_t *pte = lookup_address(addr, &level);
213 * Only flush present addresses:
215 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
216 clflush_cache_range((void *) addr, PAGE_SIZE);
220 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
221 int in_flags, struct page **pages)
223 unsigned int i, level;
224 #ifdef CONFIG_PREEMPT
226 * Avoid wbinvd() because it causes latencies on all CPUs,
227 * regardless of any CPU isolation that may be in effect.
229 * This should be extended for CAT enabled systems independent of
230 * PREEMPT because wbinvd() does not respect the CAT partitions and
231 * this is exposed to unpriviledged users through the graphics
234 unsigned long do_wbinvd = 0;
236 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
239 BUG_ON(irqs_disabled());
241 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
243 if (!cache || do_wbinvd)
247 * We only need to flush on one CPU,
248 * clflush is a MESI-coherent instruction that
249 * will cause all other CPUs to flush the same
252 for (i = 0; i < numpages; i++) {
256 if (in_flags & CPA_PAGES_ARRAY)
257 addr = (unsigned long)page_address(pages[i]);
261 pte = lookup_address(addr, &level);
264 * Only flush present addresses:
266 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
267 clflush_cache_range((void *)addr, PAGE_SIZE);
272 * Certain areas of memory on x86 require very specific protection flags,
273 * for example the BIOS area or kernel text. Callers don't always get this
274 * right (again, ioremap() on BIOS memory is not uncommon) so this function
275 * checks and fixes these known static required protection bits.
277 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
280 pgprot_t forbidden = __pgprot(0);
283 * The BIOS area between 640k and 1Mb needs to be executable for
284 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
286 #ifdef CONFIG_PCI_BIOS
287 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
288 pgprot_val(forbidden) |= _PAGE_NX;
292 * The kernel text needs to be executable for obvious reasons
293 * Does not cover __inittext since that is gone later on. On
294 * 64bit we do not enforce !NX on the low mapping
296 if (within(address, (unsigned long)_text, (unsigned long)_etext))
297 pgprot_val(forbidden) |= _PAGE_NX;
300 * The .rodata section needs to be read-only. Using the pfn
301 * catches all aliases. This also includes __ro_after_init,
302 * so do not enforce until kernel_set_to_readonly is true.
304 if (kernel_set_to_readonly &&
305 within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
306 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
307 pgprot_val(forbidden) |= _PAGE_RW;
309 #if defined(CONFIG_X86_64)
311 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
312 * kernel text mappings for the large page aligned text, rodata sections
313 * will be always read-only. For the kernel identity mappings covering
314 * the holes caused by this alignment can be anything that user asks.
316 * This will preserve the large page mappings for kernel text/data
319 if (kernel_set_to_readonly &&
320 within(address, (unsigned long)_text,
321 (unsigned long)__end_rodata_hpage_align)) {
325 * Don't enforce the !RW mapping for the kernel text mapping,
326 * if the current mapping is already using small page mapping.
327 * No need to work hard to preserve large page mappings in this
330 * This also fixes the Linux Xen paravirt guest boot failure
331 * (because of unexpected read-only mappings for kernel identity
332 * mappings). In this paravirt guest case, the kernel text
333 * mapping and the kernel identity mapping share the same
334 * page-table pages. Thus we can't really use different
335 * protections for the kernel text and identity mappings. Also,
336 * these shared mappings are made of small page mappings.
337 * Thus this don't enforce !RW mapping for small page kernel
338 * text mapping logic will help Linux Xen parvirt guest boot
341 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
342 pgprot_val(forbidden) |= _PAGE_RW;
346 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
352 * Lookup the page table entry for a virtual address in a specific pgd.
353 * Return a pointer to the entry and the level of the mapping.
355 pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
362 *level = PG_LEVEL_NONE;
367 p4d = p4d_offset(pgd, address);
371 *level = PG_LEVEL_512G;
372 if (p4d_large(*p4d) || !p4d_present(*p4d))
375 pud = pud_offset(p4d, address);
379 *level = PG_LEVEL_1G;
380 if (pud_large(*pud) || !pud_present(*pud))
383 pmd = pmd_offset(pud, address);
387 *level = PG_LEVEL_2M;
388 if (pmd_large(*pmd) || !pmd_present(*pmd))
391 *level = PG_LEVEL_4K;
393 return pte_offset_kernel(pmd, address);
397 * Lookup the page table entry for a virtual address. Return a pointer
398 * to the entry and the level of the mapping.
400 * Note: We return pud and pmd either when the entry is marked large
401 * or when the present bit is not set. Otherwise we would return a
402 * pointer to a nonexisting mapping.
404 pte_t *lookup_address(unsigned long address, unsigned int *level)
406 return lookup_address_in_pgd(pgd_offset_k(address), address, level);
408 EXPORT_SYMBOL_GPL(lookup_address);
410 static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address,
414 return lookup_address_in_pgd(cpa->pgd + pgd_index(address),
417 return lookup_address(address, level);
421 * Lookup the PMD entry for a virtual address. Return a pointer to the entry
422 * or NULL if not present.
424 pmd_t *lookup_pmd_address(unsigned long address)
430 pgd = pgd_offset_k(address);
434 p4d = p4d_offset(pgd, address);
435 if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d))
438 pud = pud_offset(p4d, address);
439 if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud))
442 return pmd_offset(pud, address);
446 * This is necessary because __pa() does not work on some
447 * kinds of memory, like vmalloc() or the alloc_remap()
448 * areas on 32-bit NUMA systems. The percpu areas can
449 * end up in this kind of memory, for instance.
451 * This could be optimized, but it is only intended to be
452 * used at inititalization time, and keeping it
453 * unoptimized should increase the testing coverage for
454 * the more obscure platforms.
456 phys_addr_t slow_virt_to_phys(void *__virt_addr)
458 unsigned long virt_addr = (unsigned long)__virt_addr;
459 phys_addr_t phys_addr;
460 unsigned long offset;
464 pte = lookup_address(virt_addr, &level);
468 * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t
469 * before being left-shifted PAGE_SHIFT bits -- this trick is to
470 * make 32-PAE kernel work correctly.
474 phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT;
475 offset = virt_addr & ~PUD_PAGE_MASK;
478 phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT;
479 offset = virt_addr & ~PMD_PAGE_MASK;
482 phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
483 offset = virt_addr & ~PAGE_MASK;
486 return (phys_addr_t)(phys_addr | offset);
488 EXPORT_SYMBOL_GPL(slow_virt_to_phys);
491 * Set the new pmd in all the pgds we know about:
493 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
496 set_pte_atomic(kpte, pte);
498 if (!SHARED_KERNEL_PMD) {
501 list_for_each_entry(page, &pgd_list, lru) {
507 pgd = (pgd_t *)page_address(page) + pgd_index(address);
508 p4d = p4d_offset(pgd, address);
509 pud = pud_offset(p4d, address);
510 pmd = pmd_offset(pud, address);
511 set_pte_atomic((pte_t *)pmd, pte);
518 try_preserve_large_page(pte_t *kpte, unsigned long address,
519 struct cpa_data *cpa)
521 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn;
522 pte_t new_pte, old_pte, *tmp;
523 pgprot_t old_prot, new_prot, req_prot;
527 if (cpa->force_split)
530 spin_lock(&pgd_lock);
532 * Check for races, another CPU might have split this page
535 tmp = _lookup_address_cpa(cpa, address, &level);
541 old_prot = pmd_pgprot(*(pmd_t *)kpte);
542 old_pfn = pmd_pfn(*(pmd_t *)kpte);
545 old_prot = pud_pgprot(*(pud_t *)kpte);
546 old_pfn = pud_pfn(*(pud_t *)kpte);
553 psize = page_level_size(level);
554 pmask = page_level_mask(level);
557 * Calculate the number of pages, which fit into this large
558 * page starting at address:
560 nextpage_addr = (address + psize) & pmask;
561 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
562 if (numpages < cpa->numpages)
563 cpa->numpages = numpages;
566 * We are safe now. Check whether the new pgprot is the same:
567 * Convert protection attributes to 4k-format, as cpa->mask* are set
571 req_prot = pgprot_large_2_4k(old_prot);
573 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
574 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
577 * req_prot is in format of 4k pages. It must be converted to large
578 * page format: the caching mode includes the PAT bit located at
579 * different bit positions in the two formats.
581 req_prot = pgprot_4k_2_large(req_prot);
584 * Set the PSE and GLOBAL flags only if the PRESENT flag is
585 * set otherwise pmd_present/pmd_huge will return true even on
586 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
587 * for the ancient hardware that doesn't support it.
589 if (pgprot_val(req_prot) & _PAGE_PRESENT)
590 pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
592 pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
594 req_prot = canon_pgprot(req_prot);
597 * old_pfn points to the large page base pfn. So we need
598 * to add the offset of the virtual address:
600 pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT);
603 new_prot = static_protections(req_prot, address, pfn);
606 * We need to check the full range, whether
607 * static_protection() requires a different pgprot for one of
608 * the pages in the range we try to preserve:
610 addr = address & pmask;
612 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
613 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
615 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
620 * If there are no changes, return. maxpages has been updated
623 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
629 * We need to change the attributes. Check, whether we can
630 * change the large page in one go. We request a split, when
631 * the address is not aligned and the number of pages is
632 * smaller than the number of pages in the large page. Note
633 * that we limited the number of possible pages already to
634 * the number of pages in the large page.
636 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
638 * The address is aligned and the number of pages
639 * covers the full page.
641 new_pte = pfn_pte(old_pfn, new_prot);
642 __set_pmd_pte(kpte, address, new_pte);
643 cpa->flags |= CPA_FLUSHTLB;
648 spin_unlock(&pgd_lock);
654 __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
657 pte_t *pbase = (pte_t *)page_address(base);
658 unsigned long ref_pfn, pfn, pfninc = 1;
659 unsigned int i, level;
663 spin_lock(&pgd_lock);
665 * Check for races, another CPU might have split this page
668 tmp = _lookup_address_cpa(cpa, address, &level);
670 spin_unlock(&pgd_lock);
674 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
678 ref_prot = pmd_pgprot(*(pmd_t *)kpte);
679 /* clear PSE and promote PAT bit to correct position */
680 ref_prot = pgprot_large_2_4k(ref_prot);
681 ref_pfn = pmd_pfn(*(pmd_t *)kpte);
685 ref_prot = pud_pgprot(*(pud_t *)kpte);
686 ref_pfn = pud_pfn(*(pud_t *)kpte);
687 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
690 * Clear the PSE flags if the PRESENT flag is not set
691 * otherwise pmd_present/pmd_huge will return true
692 * even on a non present pmd.
694 if (!(pgprot_val(ref_prot) & _PAGE_PRESENT))
695 pgprot_val(ref_prot) &= ~_PAGE_PSE;
699 spin_unlock(&pgd_lock);
704 * Set the GLOBAL flags only if the PRESENT flag is set
705 * otherwise pmd/pte_present will return true even on a non
706 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
707 * for the ancient hardware that doesn't support it.
709 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
710 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
712 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
715 * Get the target pfn from the original entry:
718 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
719 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
721 if (virt_addr_valid(address)) {
722 unsigned long pfn = PFN_DOWN(__pa(address));
724 if (pfn_range_is_mapped(pfn, pfn + 1))
725 split_page_count(level);
729 * Install the new, split up pagetable.
731 * We use the standard kernel pagetable protections for the new
732 * pagetable protections, the actual ptes set above control the
733 * primary protection behavior:
735 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
738 * Intel Atom errata AAH41 workaround.
740 * The real fix should be in hw or in a microcode update, but
741 * we also probabilistically try to reduce the window of having
742 * a large TLB mixed with 4K TLBs while instruction fetches are
746 spin_unlock(&pgd_lock);
751 static int split_large_page(struct cpa_data *cpa, pte_t *kpte,
752 unsigned long address)
756 if (!debug_pagealloc_enabled())
757 spin_unlock(&cpa_lock);
758 base = alloc_pages(GFP_KERNEL, 0);
759 if (!debug_pagealloc_enabled())
760 spin_lock(&cpa_lock);
764 if (__split_large_page(cpa, kpte, address, base))
770 static bool try_to_free_pte_page(pte_t *pte)
774 for (i = 0; i < PTRS_PER_PTE; i++)
775 if (!pte_none(pte[i]))
778 free_page((unsigned long)pte);
782 static bool try_to_free_pmd_page(pmd_t *pmd)
786 for (i = 0; i < PTRS_PER_PMD; i++)
787 if (!pmd_none(pmd[i]))
790 free_page((unsigned long)pmd);
794 static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end)
796 pte_t *pte = pte_offset_kernel(pmd, start);
798 while (start < end) {
799 set_pte(pte, __pte(0));
805 if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) {
812 static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd,
813 unsigned long start, unsigned long end)
815 if (unmap_pte_range(pmd, start, end))
816 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
820 static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end)
822 pmd_t *pmd = pmd_offset(pud, start);
825 * Not on a 2MB page boundary?
827 if (start & (PMD_SIZE - 1)) {
828 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
829 unsigned long pre_end = min_t(unsigned long, end, next_page);
831 __unmap_pmd_range(pud, pmd, start, pre_end);
838 * Try to unmap in 2M chunks.
840 while (end - start >= PMD_SIZE) {
844 __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE);
854 return __unmap_pmd_range(pud, pmd, start, end);
857 * Try again to free the PMD page if haven't succeeded above.
860 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
864 static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end)
866 pud_t *pud = pud_offset(p4d, start);
869 * Not on a GB page boundary?
871 if (start & (PUD_SIZE - 1)) {
872 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
873 unsigned long pre_end = min_t(unsigned long, end, next_page);
875 unmap_pmd_range(pud, start, pre_end);
882 * Try to unmap in 1G chunks?
884 while (end - start >= PUD_SIZE) {
889 unmap_pmd_range(pud, start, start + PUD_SIZE);
899 unmap_pmd_range(pud, start, end);
902 * No need to try to free the PUD page because we'll free it in
903 * populate_pgd's error path
907 static int alloc_pte_page(pmd_t *pmd)
909 pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL);
913 set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE));
917 static int alloc_pmd_page(pud_t *pud)
919 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL);
923 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
927 static void populate_pte(struct cpa_data *cpa,
928 unsigned long start, unsigned long end,
929 unsigned num_pages, pmd_t *pmd, pgprot_t pgprot)
933 pte = pte_offset_kernel(pmd, start);
936 * Set the GLOBAL flags only if the PRESENT flag is
937 * set otherwise pte_present will return true even on
938 * a non present pte. The canon_pgprot will clear
939 * _PAGE_GLOBAL for the ancient hardware that doesn't
942 if (pgprot_val(pgprot) & _PAGE_PRESENT)
943 pgprot_val(pgprot) |= _PAGE_GLOBAL;
945 pgprot_val(pgprot) &= ~_PAGE_GLOBAL;
947 pgprot = canon_pgprot(pgprot);
949 while (num_pages-- && start < end) {
950 set_pte(pte, pfn_pte(cpa->pfn, pgprot));
958 static long populate_pmd(struct cpa_data *cpa,
959 unsigned long start, unsigned long end,
960 unsigned num_pages, pud_t *pud, pgprot_t pgprot)
967 * Not on a 2M boundary?
969 if (start & (PMD_SIZE - 1)) {
970 unsigned long pre_end = start + (num_pages << PAGE_SHIFT);
971 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
973 pre_end = min_t(unsigned long, pre_end, next_page);
974 cur_pages = (pre_end - start) >> PAGE_SHIFT;
975 cur_pages = min_t(unsigned int, num_pages, cur_pages);
980 pmd = pmd_offset(pud, start);
982 if (alloc_pte_page(pmd))
985 populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot);
991 * We mapped them all?
993 if (num_pages == cur_pages)
996 pmd_pgprot = pgprot_4k_2_large(pgprot);
998 while (end - start >= PMD_SIZE) {
1001 * We cannot use a 1G page so allocate a PMD page if needed.
1004 if (alloc_pmd_page(pud))
1007 pmd = pmd_offset(pud, start);
1009 set_pmd(pmd, pmd_mkhuge(pfn_pmd(cpa->pfn,
1010 canon_pgprot(pmd_pgprot))));
1013 cpa->pfn += PMD_SIZE >> PAGE_SHIFT;
1014 cur_pages += PMD_SIZE >> PAGE_SHIFT;
1018 * Map trailing 4K pages.
1021 pmd = pmd_offset(pud, start);
1023 if (alloc_pte_page(pmd))
1026 populate_pte(cpa, start, end, num_pages - cur_pages,
1032 static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d,
1038 pgprot_t pud_pgprot;
1040 end = start + (cpa->numpages << PAGE_SHIFT);
1043 * Not on a Gb page boundary? => map everything up to it with
1046 if (start & (PUD_SIZE - 1)) {
1047 unsigned long pre_end;
1048 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
1050 pre_end = min_t(unsigned long, end, next_page);
1051 cur_pages = (pre_end - start) >> PAGE_SHIFT;
1052 cur_pages = min_t(int, (int)cpa->numpages, cur_pages);
1054 pud = pud_offset(p4d, start);
1060 if (alloc_pmd_page(pud))
1063 cur_pages = populate_pmd(cpa, start, pre_end, cur_pages,
1071 /* We mapped them all? */
1072 if (cpa->numpages == cur_pages)
1075 pud = pud_offset(p4d, start);
1076 pud_pgprot = pgprot_4k_2_large(pgprot);
1079 * Map everything starting from the Gb boundary, possibly with 1G pages
1081 while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) {
1082 set_pud(pud, pud_mkhuge(pfn_pud(cpa->pfn,
1083 canon_pgprot(pud_pgprot))));
1086 cpa->pfn += PUD_SIZE >> PAGE_SHIFT;
1087 cur_pages += PUD_SIZE >> PAGE_SHIFT;
1091 /* Map trailing leftover */
1095 pud = pud_offset(p4d, start);
1097 if (alloc_pmd_page(pud))
1100 tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages,
1111 * Restrictions for kernel page table do not necessarily apply when mapping in
1114 static int populate_pgd(struct cpa_data *cpa, unsigned long addr)
1116 pgprot_t pgprot = __pgprot(_KERNPG_TABLE);
1117 pud_t *pud = NULL; /* shut up gcc */
1122 pgd_entry = cpa->pgd + pgd_index(addr);
1124 if (pgd_none(*pgd_entry)) {
1125 p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL);
1129 set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE));
1133 * Allocate a PUD page and hand it down for mapping.
1135 p4d = p4d_offset(pgd_entry, addr);
1136 if (p4d_none(*p4d)) {
1137 pud = (pud_t *)get_zeroed_page(GFP_KERNEL);
1141 set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE));
1144 pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr);
1145 pgprot_val(pgprot) |= pgprot_val(cpa->mask_set);
1147 ret = populate_pud(cpa, addr, p4d, pgprot);
1150 * Leave the PUD page in place in case some other CPU or thread
1151 * already found it, but remove any useless entries we just
1154 unmap_pud_range(p4d, addr,
1155 addr + (cpa->numpages << PAGE_SHIFT));
1159 cpa->numpages = ret;
1163 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
1168 * Right now, we only execute this code path when mapping
1169 * the EFI virtual memory map regions, no other users
1170 * provide a ->pgd value. This may change in the future.
1172 return populate_pgd(cpa, vaddr);
1176 * Ignore all non primary paths.
1184 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1186 * Also set numpages to '1' indicating that we processed cpa req for
1187 * one virtual address page and its pfn. TBD: numpages can be set based
1188 * on the initial value and the level returned by lookup_address().
1190 if (within(vaddr, PAGE_OFFSET,
1191 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
1193 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
1196 WARN(1, KERN_WARNING "CPA: called for zero pte. "
1197 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
1204 static int __change_page_attr(struct cpa_data *cpa, int primary)
1206 unsigned long address;
1209 pte_t *kpte, old_pte;
1211 if (cpa->flags & CPA_PAGES_ARRAY) {
1212 struct page *page = cpa->pages[cpa->curpage];
1213 if (unlikely(PageHighMem(page)))
1215 address = (unsigned long)page_address(page);
1216 } else if (cpa->flags & CPA_ARRAY)
1217 address = cpa->vaddr[cpa->curpage];
1219 address = *cpa->vaddr;
1221 kpte = _lookup_address_cpa(cpa, address, &level);
1223 return __cpa_process_fault(cpa, address, primary);
1226 if (pte_none(old_pte))
1227 return __cpa_process_fault(cpa, address, primary);
1229 if (level == PG_LEVEL_4K) {
1231 pgprot_t new_prot = pte_pgprot(old_pte);
1232 unsigned long pfn = pte_pfn(old_pte);
1234 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
1235 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
1237 new_prot = static_protections(new_prot, address, pfn);
1240 * Set the GLOBAL flags only if the PRESENT flag is
1241 * set otherwise pte_present will return true even on
1242 * a non present pte. The canon_pgprot will clear
1243 * _PAGE_GLOBAL for the ancient hardware that doesn't
1246 if (pgprot_val(new_prot) & _PAGE_PRESENT)
1247 pgprot_val(new_prot) |= _PAGE_GLOBAL;
1249 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
1252 * We need to keep the pfn from the existing PTE,
1253 * after all we're only going to change it's attributes
1254 * not the memory it points to
1256 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
1259 * Do we really change anything ?
1261 if (pte_val(old_pte) != pte_val(new_pte)) {
1262 set_pte_atomic(kpte, new_pte);
1263 cpa->flags |= CPA_FLUSHTLB;
1270 * Check, whether we can keep the large page intact
1271 * and just change the pte:
1273 do_split = try_preserve_large_page(kpte, address, cpa);
1275 * When the range fits into the existing large page,
1276 * return. cp->numpages and cpa->tlbflush have been updated in
1283 * We have to split the large page:
1285 err = split_large_page(cpa, kpte, address);
1288 * Do a global flush tlb after splitting the large page
1289 * and before we do the actual change page attribute in the PTE.
1291 * With out this, we violate the TLB application note, that says
1292 * "The TLBs may contain both ordinary and large-page
1293 * translations for a 4-KByte range of linear addresses. This
1294 * may occur if software modifies the paging structures so that
1295 * the page size used for the address range changes. If the two
1296 * translations differ with respect to page frame or attributes
1297 * (e.g., permissions), processor behavior is undefined and may
1298 * be implementation-specific."
1300 * We do this global tlb flush inside the cpa_lock, so that we
1301 * don't allow any other cpu, with stale tlb entries change the
1302 * page attribute in parallel, that also falls into the
1303 * just split large page entry.
1312 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
1314 static int cpa_process_alias(struct cpa_data *cpa)
1316 struct cpa_data alias_cpa;
1317 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
1318 unsigned long vaddr;
1321 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
1325 * No need to redo, when the primary call touched the direct
1328 if (cpa->flags & CPA_PAGES_ARRAY) {
1329 struct page *page = cpa->pages[cpa->curpage];
1330 if (unlikely(PageHighMem(page)))
1332 vaddr = (unsigned long)page_address(page);
1333 } else if (cpa->flags & CPA_ARRAY)
1334 vaddr = cpa->vaddr[cpa->curpage];
1336 vaddr = *cpa->vaddr;
1338 if (!(within(vaddr, PAGE_OFFSET,
1339 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
1342 alias_cpa.vaddr = &laddr;
1343 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1345 ret = __change_page_attr_set_clr(&alias_cpa, 0);
1350 #ifdef CONFIG_X86_64
1352 * If the primary call didn't touch the high mapping already
1353 * and the physical address is inside the kernel map, we need
1354 * to touch the high mapped kernel as well:
1356 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
1357 within_inclusive(cpa->pfn, highmap_start_pfn(),
1358 highmap_end_pfn())) {
1359 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
1360 __START_KERNEL_map - phys_base;
1362 alias_cpa.vaddr = &temp_cpa_vaddr;
1363 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1366 * The high mapping range is imprecise, so ignore the
1369 __change_page_attr_set_clr(&alias_cpa, 0);
1376 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
1378 unsigned long numpages = cpa->numpages;
1383 * Store the remaining nr of pages for the large page
1384 * preservation check.
1386 cpa->numpages = numpages;
1387 /* for array changes, we can't use large page */
1388 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
1391 if (!debug_pagealloc_enabled())
1392 spin_lock(&cpa_lock);
1393 ret = __change_page_attr(cpa, checkalias);
1394 if (!debug_pagealloc_enabled())
1395 spin_unlock(&cpa_lock);
1400 ret = cpa_process_alias(cpa);
1406 * Adjust the number of pages with the result of the
1407 * CPA operation. Either a large page has been
1408 * preserved or a single page update happened.
1410 BUG_ON(cpa->numpages > numpages || !cpa->numpages);
1411 numpages -= cpa->numpages;
1412 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
1415 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
1421 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
1422 pgprot_t mask_set, pgprot_t mask_clr,
1423 int force_split, int in_flag,
1424 struct page **pages)
1426 struct cpa_data cpa;
1427 int ret, cache, checkalias;
1428 unsigned long baddr = 0;
1430 memset(&cpa, 0, sizeof(cpa));
1433 * Check, if we are requested to change a not supported
1436 mask_set = canon_pgprot(mask_set);
1437 mask_clr = canon_pgprot(mask_clr);
1438 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
1441 /* Ensure we are PAGE_SIZE aligned */
1442 if (in_flag & CPA_ARRAY) {
1444 for (i = 0; i < numpages; i++) {
1445 if (addr[i] & ~PAGE_MASK) {
1446 addr[i] &= PAGE_MASK;
1450 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
1452 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
1453 * No need to cehck in that case
1455 if (*addr & ~PAGE_MASK) {
1458 * People should not be passing in unaligned addresses:
1463 * Save address for cache flush. *addr is modified in the call
1464 * to __change_page_attr_set_clr() below.
1469 /* Must avoid aliasing mappings in the highmem code */
1470 kmap_flush_unused();
1476 cpa.numpages = numpages;
1477 cpa.mask_set = mask_set;
1478 cpa.mask_clr = mask_clr;
1481 cpa.force_split = force_split;
1483 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
1484 cpa.flags |= in_flag;
1486 /* No alias checking for _NX bit modifications */
1487 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
1489 ret = __change_page_attr_set_clr(&cpa, checkalias);
1492 * Check whether we really changed something:
1494 if (!(cpa.flags & CPA_FLUSHTLB))
1498 * No need to flush, when we did not set any of the caching
1501 cache = !!pgprot2cachemode(mask_set);
1504 * On success we use CLFLUSH, when the CPU supports it to
1505 * avoid the WBINVD. If the CPU does not support it and in the
1506 * error case we fall back to cpa_flush_all (which uses
1509 if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) {
1510 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
1511 cpa_flush_array(addr, numpages, cache,
1514 cpa_flush_range(baddr, numpages, cache);
1516 cpa_flush_all(cache);
1522 static inline int change_page_attr_set(unsigned long *addr, int numpages,
1523 pgprot_t mask, int array)
1525 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
1526 (array ? CPA_ARRAY : 0), NULL);
1529 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1530 pgprot_t mask, int array)
1532 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
1533 (array ? CPA_ARRAY : 0), NULL);
1536 static inline int cpa_set_pages_array(struct page **pages, int numpages,
1539 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1540 CPA_PAGES_ARRAY, pages);
1543 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1546 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1547 CPA_PAGES_ARRAY, pages);
1550 int _set_memory_uc(unsigned long addr, int numpages)
1553 * for now UC MINUS. see comments in ioremap_nocache()
1554 * If you really need strong UC use ioremap_uc(), but note
1555 * that you cannot override IO areas with set_memory_*() as
1556 * these helpers cannot work with IO memory.
1558 return change_page_attr_set(&addr, numpages,
1559 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1563 int set_memory_uc(unsigned long addr, int numpages)
1568 * for now UC MINUS. see comments in ioremap_nocache()
1570 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1571 _PAGE_CACHE_MODE_UC_MINUS, NULL);
1575 ret = _set_memory_uc(addr, numpages);
1582 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1586 EXPORT_SYMBOL(set_memory_uc);
1588 static int _set_memory_array(unsigned long *addr, int addrinarray,
1589 enum page_cache_mode new_type)
1591 enum page_cache_mode set_type;
1595 for (i = 0; i < addrinarray; i++) {
1596 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1602 /* If WC, set to UC- first and then WC */
1603 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
1604 _PAGE_CACHE_MODE_UC_MINUS : new_type;
1606 ret = change_page_attr_set(addr, addrinarray,
1607 cachemode2pgprot(set_type), 1);
1609 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1610 ret = change_page_attr_set_clr(addr, addrinarray,
1612 _PAGE_CACHE_MODE_WC),
1613 __pgprot(_PAGE_CACHE_MASK),
1614 0, CPA_ARRAY, NULL);
1621 for (j = 0; j < i; j++)
1622 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1627 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1629 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1631 EXPORT_SYMBOL(set_memory_array_uc);
1633 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1635 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC);
1637 EXPORT_SYMBOL(set_memory_array_wc);
1639 int set_memory_array_wt(unsigned long *addr, int addrinarray)
1641 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT);
1643 EXPORT_SYMBOL_GPL(set_memory_array_wt);
1645 int _set_memory_wc(unsigned long addr, int numpages)
1648 unsigned long addr_copy = addr;
1650 ret = change_page_attr_set(&addr, numpages,
1651 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1654 ret = change_page_attr_set_clr(&addr_copy, numpages,
1656 _PAGE_CACHE_MODE_WC),
1657 __pgprot(_PAGE_CACHE_MASK),
1663 int set_memory_wc(unsigned long addr, int numpages)
1667 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1668 _PAGE_CACHE_MODE_WC, NULL);
1672 ret = _set_memory_wc(addr, numpages);
1674 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1678 EXPORT_SYMBOL(set_memory_wc);
1680 int _set_memory_wt(unsigned long addr, int numpages)
1682 return change_page_attr_set(&addr, numpages,
1683 cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0);
1686 int set_memory_wt(unsigned long addr, int numpages)
1690 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1691 _PAGE_CACHE_MODE_WT, NULL);
1695 ret = _set_memory_wt(addr, numpages);
1697 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1701 EXPORT_SYMBOL_GPL(set_memory_wt);
1703 int _set_memory_wb(unsigned long addr, int numpages)
1705 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1706 return change_page_attr_clear(&addr, numpages,
1707 __pgprot(_PAGE_CACHE_MASK), 0);
1710 int set_memory_wb(unsigned long addr, int numpages)
1714 ret = _set_memory_wb(addr, numpages);
1718 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1721 EXPORT_SYMBOL(set_memory_wb);
1723 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1728 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1729 ret = change_page_attr_clear(addr, addrinarray,
1730 __pgprot(_PAGE_CACHE_MASK), 1);
1734 for (i = 0; i < addrinarray; i++)
1735 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1739 EXPORT_SYMBOL(set_memory_array_wb);
1741 int set_memory_x(unsigned long addr, int numpages)
1743 if (!(__supported_pte_mask & _PAGE_NX))
1746 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1748 EXPORT_SYMBOL(set_memory_x);
1750 int set_memory_nx(unsigned long addr, int numpages)
1752 if (!(__supported_pte_mask & _PAGE_NX))
1755 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1757 EXPORT_SYMBOL(set_memory_nx);
1759 int set_memory_ro(unsigned long addr, int numpages)
1761 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1764 int set_memory_rw(unsigned long addr, int numpages)
1766 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1769 int set_memory_np(unsigned long addr, int numpages)
1771 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1774 int set_memory_4k(unsigned long addr, int numpages)
1776 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1777 __pgprot(0), 1, 0, NULL);
1780 static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
1782 struct cpa_data cpa;
1783 unsigned long start;
1786 /* Nothing to do if the SME is not active */
1790 /* Should not be working on unaligned addresses */
1791 if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr))
1796 memset(&cpa, 0, sizeof(cpa));
1798 cpa.numpages = numpages;
1799 cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0);
1800 cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC);
1801 cpa.pgd = init_mm.pgd;
1803 /* Must avoid aliasing mappings in the highmem code */
1804 kmap_flush_unused();
1808 * Before changing the encryption attribute, we need to flush caches.
1810 if (static_cpu_has(X86_FEATURE_CLFLUSH))
1811 cpa_flush_range(start, numpages, 1);
1815 ret = __change_page_attr_set_clr(&cpa, 1);
1818 * After changing the encryption attribute, we need to flush TLBs
1819 * again in case any speculative TLB caching occurred (but no need
1820 * to flush caches again). We could just use cpa_flush_all(), but
1821 * in case TLB flushing gets optimized in the cpa_flush_range()
1822 * path use the same logic as above.
1824 if (static_cpu_has(X86_FEATURE_CLFLUSH))
1825 cpa_flush_range(start, numpages, 0);
1832 int set_memory_encrypted(unsigned long addr, int numpages)
1834 return __set_memory_enc_dec(addr, numpages, true);
1836 EXPORT_SYMBOL_GPL(set_memory_encrypted);
1838 int set_memory_decrypted(unsigned long addr, int numpages)
1840 return __set_memory_enc_dec(addr, numpages, false);
1842 EXPORT_SYMBOL_GPL(set_memory_decrypted);
1844 int set_pages_uc(struct page *page, int numpages)
1846 unsigned long addr = (unsigned long)page_address(page);
1848 return set_memory_uc(addr, numpages);
1850 EXPORT_SYMBOL(set_pages_uc);
1852 static int _set_pages_array(struct page **pages, int addrinarray,
1853 enum page_cache_mode new_type)
1855 unsigned long start;
1857 enum page_cache_mode set_type;
1862 for (i = 0; i < addrinarray; i++) {
1863 if (PageHighMem(pages[i]))
1865 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1866 end = start + PAGE_SIZE;
1867 if (reserve_memtype(start, end, new_type, NULL))
1871 /* If WC, set to UC- first and then WC */
1872 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
1873 _PAGE_CACHE_MODE_UC_MINUS : new_type;
1875 ret = cpa_set_pages_array(pages, addrinarray,
1876 cachemode2pgprot(set_type));
1877 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1878 ret = change_page_attr_set_clr(NULL, addrinarray,
1880 _PAGE_CACHE_MODE_WC),
1881 __pgprot(_PAGE_CACHE_MASK),
1882 0, CPA_PAGES_ARRAY, pages);
1885 return 0; /* Success */
1888 for (i = 0; i < free_idx; i++) {
1889 if (PageHighMem(pages[i]))
1891 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1892 end = start + PAGE_SIZE;
1893 free_memtype(start, end);
1898 int set_pages_array_uc(struct page **pages, int addrinarray)
1900 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1902 EXPORT_SYMBOL(set_pages_array_uc);
1904 int set_pages_array_wc(struct page **pages, int addrinarray)
1906 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC);
1908 EXPORT_SYMBOL(set_pages_array_wc);
1910 int set_pages_array_wt(struct page **pages, int addrinarray)
1912 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT);
1914 EXPORT_SYMBOL_GPL(set_pages_array_wt);
1916 int set_pages_wb(struct page *page, int numpages)
1918 unsigned long addr = (unsigned long)page_address(page);
1920 return set_memory_wb(addr, numpages);
1922 EXPORT_SYMBOL(set_pages_wb);
1924 int set_pages_array_wb(struct page **pages, int addrinarray)
1927 unsigned long start;
1931 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1932 retval = cpa_clear_pages_array(pages, addrinarray,
1933 __pgprot(_PAGE_CACHE_MASK));
1937 for (i = 0; i < addrinarray; i++) {
1938 if (PageHighMem(pages[i]))
1940 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1941 end = start + PAGE_SIZE;
1942 free_memtype(start, end);
1947 EXPORT_SYMBOL(set_pages_array_wb);
1949 int set_pages_x(struct page *page, int numpages)
1951 unsigned long addr = (unsigned long)page_address(page);
1953 return set_memory_x(addr, numpages);
1955 EXPORT_SYMBOL(set_pages_x);
1957 int set_pages_nx(struct page *page, int numpages)
1959 unsigned long addr = (unsigned long)page_address(page);
1961 return set_memory_nx(addr, numpages);
1963 EXPORT_SYMBOL(set_pages_nx);
1965 int set_pages_ro(struct page *page, int numpages)
1967 unsigned long addr = (unsigned long)page_address(page);
1969 return set_memory_ro(addr, numpages);
1972 int set_pages_rw(struct page *page, int numpages)
1974 unsigned long addr = (unsigned long)page_address(page);
1976 return set_memory_rw(addr, numpages);
1979 #ifdef CONFIG_DEBUG_PAGEALLOC
1981 static int __set_pages_p(struct page *page, int numpages)
1983 unsigned long tempaddr = (unsigned long) page_address(page);
1984 struct cpa_data cpa = { .vaddr = &tempaddr,
1986 .numpages = numpages,
1987 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1988 .mask_clr = __pgprot(0),
1992 * No alias checking needed for setting present flag. otherwise,
1993 * we may need to break large pages for 64-bit kernel text
1994 * mappings (this adds to complexity if we want to do this from
1995 * atomic context especially). Let's keep it simple!
1997 return __change_page_attr_set_clr(&cpa, 0);
2000 static int __set_pages_np(struct page *page, int numpages)
2002 unsigned long tempaddr = (unsigned long) page_address(page);
2003 struct cpa_data cpa = { .vaddr = &tempaddr,
2005 .numpages = numpages,
2006 .mask_set = __pgprot(0),
2007 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
2011 * No alias checking needed for setting not present flag. otherwise,
2012 * we may need to break large pages for 64-bit kernel text
2013 * mappings (this adds to complexity if we want to do this from
2014 * atomic context especially). Let's keep it simple!
2016 return __change_page_attr_set_clr(&cpa, 0);
2019 void __kernel_map_pages(struct page *page, int numpages, int enable)
2021 if (PageHighMem(page))
2024 debug_check_no_locks_freed(page_address(page),
2025 numpages * PAGE_SIZE);
2029 * The return value is ignored as the calls cannot fail.
2030 * Large pages for identity mappings are not used at boot time
2031 * and hence no memory allocations during large page split.
2034 __set_pages_p(page, numpages);
2036 __set_pages_np(page, numpages);
2039 * We should perform an IPI and flush all tlbs,
2040 * but that can deadlock->flush only current cpu.
2041 * Preemption needs to be disabled around __flush_tlb_all() due to
2042 * CR3 reload in __native_flush_tlb().
2048 arch_flush_lazy_mmu_mode();
2051 #ifdef CONFIG_HIBERNATION
2053 bool kernel_page_present(struct page *page)
2058 if (PageHighMem(page))
2061 pte = lookup_address((unsigned long)page_address(page), &level);
2062 return (pte_val(*pte) & _PAGE_PRESENT);
2065 #endif /* CONFIG_HIBERNATION */
2067 #endif /* CONFIG_DEBUG_PAGEALLOC */
2069 int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
2070 unsigned numpages, unsigned long page_flags)
2072 int retval = -EINVAL;
2074 struct cpa_data cpa = {
2078 .numpages = numpages,
2079 .mask_set = __pgprot(0),
2080 .mask_clr = __pgprot(~page_flags & (_PAGE_NX|_PAGE_RW)),
2084 if (!(__supported_pte_mask & _PAGE_NX))
2087 if (!(page_flags & _PAGE_ENC))
2088 cpa.mask_clr = pgprot_encrypted(cpa.mask_clr);
2090 cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags);
2092 retval = __change_page_attr_set_clr(&cpa, 0);
2100 * The testcases use internal knowledge of the implementation that shouldn't
2101 * be exposed to the rest of the kernel. Include these directly here.
2103 #ifdef CONFIG_CPA_DEBUG
2104 #include "pageattr-test.c"