1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Memory Encryption Support
5 * Copyright (C) 2016 Advanced Micro Devices, Inc.
7 * Author: Tom Lendacky <thomas.lendacky@amd.com>
10 #define DISABLE_BRANCH_PROFILING
13 * Since we're dealing with identity mappings, physical and virtual
14 * addresses are the same, so override these defines which are ultimately
15 * used by the headers in misc.h.
17 #define __pa(x) ((unsigned long)(x))
18 #define __va(x) ((void *)((unsigned long)(x)))
21 * Special hack: we have to be careful, because no indirections are
22 * allowed here, and paravirt_ops is a kind of one. As it will only run in
23 * baremetal anyway, we just keep it from happening. (This list needs to
24 * be extended when new paravirt and debugging variants are added.)
26 #undef CONFIG_PARAVIRT
27 #undef CONFIG_PARAVIRT_XXL
28 #undef CONFIG_PARAVIRT_SPINLOCKS
31 * This code runs before CPU feature bits are set. By default, the
32 * pgtable_l5_enabled() function uses bit X86_FEATURE_LA57 to determine if
33 * 5-level paging is active, so that won't work here. USE_EARLY_PGTABLE_L5
34 * is provided to handle this situation and, instead, use a variable that
35 * has been set by the early boot code.
37 #define USE_EARLY_PGTABLE_L5
39 #include <linux/kernel.h>
41 #include <linux/mem_encrypt.h>
43 #include <asm/setup.h>
44 #include <asm/sections.h>
45 #include <asm/cmdline.h>
47 #include "mm_internal.h"
49 #define PGD_FLAGS _KERNPG_TABLE_NOENC
50 #define P4D_FLAGS _KERNPG_TABLE_NOENC
51 #define PUD_FLAGS _KERNPG_TABLE_NOENC
52 #define PMD_FLAGS _KERNPG_TABLE_NOENC
54 #define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
56 #define PMD_FLAGS_DEC PMD_FLAGS_LARGE
57 #define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_LARGE_CACHE_MASK) | \
58 (_PAGE_PAT_LARGE | _PAGE_PWT))
60 #define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC)
62 #define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
64 #define PTE_FLAGS_DEC PTE_FLAGS
65 #define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
66 (_PAGE_PAT | _PAGE_PWT))
68 #define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC)
70 struct sme_populate_pgd_data {
79 unsigned long vaddr_end;
83 * This work area lives in the .init.scratch section, which lives outside of
84 * the kernel proper. It is sized to hold the intermediate copy buffer and
85 * more than enough pagetable pages.
87 * By using this section, the kernel can be encrypted in place and it
88 * avoids any possibility of boot parameters or initramfs images being
89 * placed such that the in-place encryption logic overwrites them. This
90 * section is 2MB aligned to allow for simple pagetable setup using only
91 * PMD entries (see vmlinux.lds.S).
93 static char sme_workarea[2 * PMD_PAGE_SIZE] __section(".init.scratch");
95 static char sme_cmdline_arg[] __initdata = "mem_encrypt";
96 static char sme_cmdline_on[] __initdata = "on";
97 static char sme_cmdline_off[] __initdata = "off";
99 static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
101 unsigned long pgd_start, pgd_end, pgd_size;
104 pgd_start = ppd->vaddr & PGDIR_MASK;
105 pgd_end = ppd->vaddr_end & PGDIR_MASK;
107 pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
109 pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
111 memset(pgd_p, 0, pgd_size);
114 static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
121 pgd = ppd->pgd + pgd_index(ppd->vaddr);
122 if (pgd_none(*pgd)) {
123 p4d = ppd->pgtable_area;
124 memset(p4d, 0, sizeof(*p4d) * PTRS_PER_P4D);
125 ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D;
126 set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d)));
129 p4d = p4d_offset(pgd, ppd->vaddr);
130 if (p4d_none(*p4d)) {
131 pud = ppd->pgtable_area;
132 memset(pud, 0, sizeof(*pud) * PTRS_PER_PUD);
133 ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD;
134 set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud)));
137 pud = pud_offset(p4d, ppd->vaddr);
138 if (pud_none(*pud)) {
139 pmd = ppd->pgtable_area;
140 memset(pmd, 0, sizeof(*pmd) * PTRS_PER_PMD);
141 ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD;
142 set_pud(pud, __pud(PUD_FLAGS | __pa(pmd)));
151 static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
156 pud = sme_prepare_pgd(ppd);
160 pmd = pmd_offset(pud, ppd->vaddr);
164 set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags));
167 static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
173 pud = sme_prepare_pgd(ppd);
177 pmd = pmd_offset(pud, ppd->vaddr);
178 if (pmd_none(*pmd)) {
179 pte = ppd->pgtable_area;
180 memset(pte, 0, sizeof(*pte) * PTRS_PER_PTE);
181 ppd->pgtable_area += sizeof(*pte) * PTRS_PER_PTE;
182 set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte)));
188 pte = pte_offset_map(pmd, ppd->vaddr);
190 set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
193 static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
195 while (ppd->vaddr < ppd->vaddr_end) {
196 sme_populate_pgd_large(ppd);
198 ppd->vaddr += PMD_PAGE_SIZE;
199 ppd->paddr += PMD_PAGE_SIZE;
203 static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
205 while (ppd->vaddr < ppd->vaddr_end) {
206 sme_populate_pgd(ppd);
208 ppd->vaddr += PAGE_SIZE;
209 ppd->paddr += PAGE_SIZE;
213 static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
214 pmdval_t pmd_flags, pteval_t pte_flags)
216 unsigned long vaddr_end;
218 ppd->pmd_flags = pmd_flags;
219 ppd->pte_flags = pte_flags;
221 /* Save original end value since we modify the struct value */
222 vaddr_end = ppd->vaddr_end;
224 /* If start is not 2MB aligned, create PTE entries */
225 ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
226 __sme_map_range_pte(ppd);
228 /* Create PMD entries */
229 ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
230 __sme_map_range_pmd(ppd);
232 /* If end is not 2MB aligned, create PTE entries */
233 ppd->vaddr_end = vaddr_end;
234 __sme_map_range_pte(ppd);
237 static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
239 __sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
242 static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
244 __sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
247 static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
249 __sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
252 static unsigned long __init sme_pgtable_calc(unsigned long len)
254 unsigned long entries = 0, tables = 0;
257 * Perform a relatively simplistic calculation of the pagetable
258 * entries that are needed. Those mappings will be covered mostly
259 * by 2MB PMD entries so we can conservatively calculate the required
260 * number of P4D, PUD and PMD structures needed to perform the
261 * mappings. For mappings that are not 2MB aligned, PTE mappings
262 * would be needed for the start and end portion of the address range
263 * that fall outside of the 2MB alignment. This results in, at most,
264 * two extra pages to hold PTE entries for each range that is mapped.
265 * Incrementing the count for each covers the case where the addresses
269 /* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */
270 if (PTRS_PER_P4D > 1)
271 entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D;
272 entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD;
273 entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD;
274 entries += 2 * sizeof(pte_t) * PTRS_PER_PTE;
277 * Now calculate the added pagetable structures needed to populate
278 * the new pagetables.
281 if (PTRS_PER_P4D > 1)
282 tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D;
283 tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD;
284 tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD;
286 return entries + tables;
289 void __init sme_encrypt_kernel(struct boot_params *bp)
291 unsigned long workarea_start, workarea_end, workarea_len;
292 unsigned long execute_start, execute_end, execute_len;
293 unsigned long kernel_start, kernel_end, kernel_len;
294 unsigned long initrd_start, initrd_end, initrd_len;
295 struct sme_populate_pgd_data ppd;
296 unsigned long pgtable_area_len;
297 unsigned long decrypted_base;
303 * Prepare for encrypting the kernel and initrd by building new
304 * pagetables with the necessary attributes needed to encrypt the
307 * One range of virtual addresses will map the memory occupied
308 * by the kernel and initrd as encrypted.
310 * Another range of virtual addresses will map the memory occupied
311 * by the kernel and initrd as decrypted and write-protected.
313 * The use of write-protect attribute will prevent any of the
314 * memory from being cached.
317 /* Physical addresses gives us the identity mapped virtual addresses */
318 kernel_start = __pa_symbol(_text);
319 kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
320 kernel_len = kernel_end - kernel_start;
325 #ifdef CONFIG_BLK_DEV_INITRD
326 initrd_len = (unsigned long)bp->hdr.ramdisk_size |
327 ((unsigned long)bp->ext_ramdisk_size << 32);
329 initrd_start = (unsigned long)bp->hdr.ramdisk_image |
330 ((unsigned long)bp->ext_ramdisk_image << 32);
331 initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
332 initrd_len = initrd_end - initrd_start;
337 * We're running identity mapped, so we must obtain the address to the
338 * SME encryption workarea using rip-relative addressing.
340 asm ("lea sme_workarea(%%rip), %0"
341 : "=r" (workarea_start)
342 : "p" (sme_workarea));
345 * Calculate required number of workarea bytes needed:
346 * executable encryption area size:
347 * stack page (PAGE_SIZE)
348 * encryption routine page (PAGE_SIZE)
349 * intermediate copy buffer (PMD_PAGE_SIZE)
350 * pagetable structures for the encryption of the kernel
351 * pagetable structures for workarea (in case not currently mapped)
353 execute_start = workarea_start;
354 execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE;
355 execute_len = execute_end - execute_start;
358 * One PGD for both encrypted and decrypted mappings and a set of
359 * PUDs and PMDs for each of the encrypted and decrypted mappings.
361 pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
362 pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
364 pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
366 /* PUDs and PMDs needed in the current pagetables for the workarea */
367 pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
370 * The total workarea includes the executable encryption area and
371 * the pagetable area. The start of the workarea is already 2MB
372 * aligned, align the end of the workarea on a 2MB boundary so that
373 * we don't try to create/allocate PTE entries from the workarea
374 * before it is mapped.
376 workarea_len = execute_len + pgtable_area_len;
377 workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
380 * Set the address to the start of where newly created pagetable
381 * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
382 * structures are created when the workarea is added to the current
383 * pagetables and when the new encrypted and decrypted kernel
384 * mappings are populated.
386 ppd.pgtable_area = (void *)execute_end;
389 * Make sure the current pagetable structure has entries for
390 * addressing the workarea.
392 ppd.pgd = (pgd_t *)native_read_cr3_pa();
393 ppd.paddr = workarea_start;
394 ppd.vaddr = workarea_start;
395 ppd.vaddr_end = workarea_end;
396 sme_map_range_decrypted(&ppd);
398 /* Flush the TLB - no globals so cr3 is enough */
399 native_write_cr3(__native_read_cr3());
402 * A new pagetable structure is being built to allow for the kernel
403 * and initrd to be encrypted. It starts with an empty PGD that will
404 * then be populated with new PUDs and PMDs as the encrypted and
405 * decrypted kernel mappings are created.
407 ppd.pgd = ppd.pgtable_area;
408 memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
409 ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
412 * A different PGD index/entry must be used to get different
413 * pagetable entries for the decrypted mapping. Choose the next
414 * PGD index and convert it to a virtual address to be used as
415 * the base of the mapping.
417 decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
419 unsigned long check_base;
421 check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
422 decrypted_base = max(decrypted_base, check_base);
424 decrypted_base <<= PGDIR_SHIFT;
426 /* Add encrypted kernel (identity) mappings */
427 ppd.paddr = kernel_start;
428 ppd.vaddr = kernel_start;
429 ppd.vaddr_end = kernel_end;
430 sme_map_range_encrypted(&ppd);
432 /* Add decrypted, write-protected kernel (non-identity) mappings */
433 ppd.paddr = kernel_start;
434 ppd.vaddr = kernel_start + decrypted_base;
435 ppd.vaddr_end = kernel_end + decrypted_base;
436 sme_map_range_decrypted_wp(&ppd);
439 /* Add encrypted initrd (identity) mappings */
440 ppd.paddr = initrd_start;
441 ppd.vaddr = initrd_start;
442 ppd.vaddr_end = initrd_end;
443 sme_map_range_encrypted(&ppd);
445 * Add decrypted, write-protected initrd (non-identity) mappings
447 ppd.paddr = initrd_start;
448 ppd.vaddr = initrd_start + decrypted_base;
449 ppd.vaddr_end = initrd_end + decrypted_base;
450 sme_map_range_decrypted_wp(&ppd);
453 /* Add decrypted workarea mappings to both kernel mappings */
454 ppd.paddr = workarea_start;
455 ppd.vaddr = workarea_start;
456 ppd.vaddr_end = workarea_end;
457 sme_map_range_decrypted(&ppd);
459 ppd.paddr = workarea_start;
460 ppd.vaddr = workarea_start + decrypted_base;
461 ppd.vaddr_end = workarea_end + decrypted_base;
462 sme_map_range_decrypted(&ppd);
464 /* Perform the encryption */
465 sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
466 kernel_len, workarea_start, (unsigned long)ppd.pgd);
469 sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
470 initrd_len, workarea_start,
471 (unsigned long)ppd.pgd);
474 * At this point we are running encrypted. Remove the mappings for
475 * the decrypted areas - all that is needed for this is to remove
476 * the PGD entry/entries.
478 ppd.vaddr = kernel_start + decrypted_base;
479 ppd.vaddr_end = kernel_end + decrypted_base;
483 ppd.vaddr = initrd_start + decrypted_base;
484 ppd.vaddr_end = initrd_end + decrypted_base;
488 ppd.vaddr = workarea_start + decrypted_base;
489 ppd.vaddr_end = workarea_end + decrypted_base;
492 /* Flush the TLB - no globals so cr3 is enough */
493 native_write_cr3(__native_read_cr3());
496 void __init sme_enable(struct boot_params *bp)
498 const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
499 unsigned int eax, ebx, ecx, edx;
500 unsigned long feature_mask;
501 bool active_by_default;
502 unsigned long me_mask;
506 /* Check for the SME/SEV support leaf */
509 native_cpuid(&eax, &ebx, &ecx, &edx);
510 if (eax < 0x8000001f)
513 #define AMD_SME_BIT BIT(0)
514 #define AMD_SEV_BIT BIT(1)
517 * Check for the SME/SEV feature:
518 * CPUID Fn8000_001F[EAX]
519 * - Bit 0 - Secure Memory Encryption support
520 * - Bit 1 - Secure Encrypted Virtualization support
521 * CPUID Fn8000_001F[EBX]
522 * - Bits 5:0 - Pagetable bit position used to indicate encryption
526 native_cpuid(&eax, &ebx, &ecx, &edx);
527 /* Check whether SEV or SME is supported */
528 if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT)))
531 me_mask = 1UL << (ebx & 0x3f);
533 /* Check the SEV MSR whether SEV or SME is enabled */
534 sev_status = __rdmsr(MSR_AMD64_SEV);
535 feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT;
537 /* Check if memory encryption is enabled */
538 if (feature_mask == AMD_SME_BIT) {
540 * No SME if Hypervisor bit is set. This check is here to
541 * prevent a guest from trying to enable SME. For running as a
542 * KVM guest the MSR_AMD64_SYSCFG will be sufficient, but there
543 * might be other hypervisors which emulate that MSR as non-zero
544 * or even pass it through to the guest.
545 * A malicious hypervisor can still trick a guest into this
546 * path, but there is no way to protect against that.
550 native_cpuid(&eax, &ebx, &ecx, &edx);
554 /* For SME, check the SYSCFG MSR */
555 msr = __rdmsr(MSR_AMD64_SYSCFG);
556 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
559 /* SEV state cannot be controlled by a command line option */
560 sme_me_mask = me_mask;
561 physical_mask &= ~sme_me_mask;
566 * Fixups have not been applied to phys_base yet and we're running
567 * identity mapped, so we must obtain the address to the SME command
568 * line argument data using rip-relative addressing.
570 asm ("lea sme_cmdline_arg(%%rip), %0"
572 : "p" (sme_cmdline_arg));
573 asm ("lea sme_cmdline_on(%%rip), %0"
575 : "p" (sme_cmdline_on));
576 asm ("lea sme_cmdline_off(%%rip), %0"
578 : "p" (sme_cmdline_off));
580 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
581 active_by_default = true;
583 active_by_default = false;
585 cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
586 ((u64)bp->ext_cmd_line_ptr << 32));
588 if (cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)) < 0)
591 if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
592 sme_me_mask = me_mask;
593 else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
596 sme_me_mask = active_by_default ? me_mask : 0;
598 physical_mask &= ~sme_me_mask;