2 #include <linux/initrd.h>
3 #include <linux/ioport.h>
4 #include <linux/swap.h>
5 #include <linux/memblock.h>
6 #include <linux/bootmem.h> /* for max_low_pfn */
7 #include <linux/swapfile.h>
8 #include <linux/swapops.h>
10 #include <asm/set_memory.h>
11 #include <asm/e820/api.h>
14 #include <asm/page_types.h>
15 #include <asm/sections.h>
16 #include <asm/setup.h>
17 #include <asm/tlbflush.h>
19 #include <asm/proto.h>
20 #include <asm/dma.h> /* for MAX_DMA_PFN */
21 #include <asm/microcode.h>
22 #include <asm/kaslr.h>
23 #include <asm/hypervisor.h>
24 #include <asm/cpufeature.h>
28 * We need to define the tracepoints somewhere, and tlb.c
29 * is only compied when SMP=y.
31 #define CREATE_TRACE_POINTS
32 #include <trace/events/tlb.h>
34 #include "mm_internal.h"
37 * Tables translating between page_cache_type_t and pte encoding.
39 * The default values are defined statically as minimal supported mode;
40 * WC and WT fall back to UC-. pat_init() updates these values to support
41 * more cache modes, WC and WT, when it is safe to do so. See pat_init()
42 * for the details. Note, __early_ioremap() used during early boot-time
43 * takes pgprot_t (pte encoding) and does not use these tables.
45 * Index into __cachemode2pte_tbl[] is the cachemode.
47 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
48 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
50 uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
51 [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
52 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
53 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
54 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
55 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
56 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
58 EXPORT_SYMBOL(__cachemode2pte_tbl);
60 uint8_t __pte2cachemode_tbl[8] = {
61 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
62 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
63 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
64 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
65 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
66 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
67 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
68 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
70 EXPORT_SYMBOL(__pte2cachemode_tbl);
72 static unsigned long __initdata pgt_buf_start;
73 static unsigned long __initdata pgt_buf_end;
74 static unsigned long __initdata pgt_buf_top;
76 static unsigned long min_pfn_mapped;
78 static bool __initdata can_use_brk_pgt = true;
81 * Pages returned are already directly mapped.
83 * Changing that is likely to break Xen, see commit:
85 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
87 * for detailed information.
89 __ref void *alloc_low_pages(unsigned int num)
97 order = get_order((unsigned long)num << PAGE_SHIFT);
98 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
101 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
103 if (min_pfn_mapped >= max_pfn_mapped)
104 panic("alloc_low_pages: ran out of memory");
105 ret = memblock_find_in_range(min_pfn_mapped << PAGE_SHIFT,
106 max_pfn_mapped << PAGE_SHIFT,
107 PAGE_SIZE * num , PAGE_SIZE);
109 panic("alloc_low_pages: can not alloc memory");
110 memblock_reserve(ret, PAGE_SIZE * num);
111 pfn = ret >> PAGE_SHIFT;
117 for (i = 0; i < num; i++) {
120 adr = __va((pfn + i) << PAGE_SHIFT);
124 return __va(pfn << PAGE_SHIFT);
128 * By default need 3 4k for initial PMD_SIZE, 3 4k for 0-ISA_END_ADDRESS.
129 * With KASLR memory randomization, depending on the machine e820 memory
130 * and the PUD alignment. We may need twice more pages when KASLR memory
131 * randomization is enabled.
133 #ifndef CONFIG_RANDOMIZE_MEMORY
134 #define INIT_PGD_PAGE_COUNT 6
136 #define INIT_PGD_PAGE_COUNT 12
138 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE)
139 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
140 void __init early_alloc_pgt_buf(void)
142 unsigned long tables = INIT_PGT_BUF_SIZE;
145 base = __pa(extend_brk(tables, PAGE_SIZE));
147 pgt_buf_start = base >> PAGE_SHIFT;
148 pgt_buf_end = pgt_buf_start;
149 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
154 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
159 unsigned page_size_mask;
162 static int page_size_mask;
164 static void enable_global_pages(void)
166 if (!static_cpu_has(X86_FEATURE_PTI))
167 __supported_pte_mask |= _PAGE_GLOBAL;
170 static void __init probe_page_size_mask(void)
173 * For pagealloc debugging, identity mapping will use small pages.
174 * This will simplify cpa(), which otherwise needs to support splitting
175 * large pages into small in interrupt context, etc.
177 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
178 page_size_mask |= 1 << PG_LEVEL_2M;
182 /* Enable PSE if available */
183 if (boot_cpu_has(X86_FEATURE_PSE))
184 cr4_set_bits_and_update_boot(X86_CR4_PSE);
186 /* Enable PGE if available */
187 __supported_pte_mask &= ~_PAGE_GLOBAL;
188 if (boot_cpu_has(X86_FEATURE_PGE)) {
189 cr4_set_bits_and_update_boot(X86_CR4_PGE);
190 enable_global_pages();
193 /* Enable 1 GB linear kernel mappings if available: */
194 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
195 printk(KERN_INFO "Using GB pages for direct mapping\n");
196 page_size_mask |= 1 << PG_LEVEL_1G;
202 static void setup_pcid(void)
204 if (!IS_ENABLED(CONFIG_X86_64))
207 if (!boot_cpu_has(X86_FEATURE_PCID))
210 if (boot_cpu_has(X86_FEATURE_PGE)) {
212 * This can't be cr4_set_bits_and_update_boot() -- the
213 * trampoline code can't handle CR4.PCIDE and it wouldn't
214 * do any good anyway. Despite the name,
215 * cr4_set_bits_and_update_boot() doesn't actually cause
216 * the bits in question to remain set all the way through
217 * the secondary boot asm.
219 * Instead, we brute-force it and set CR4.PCIDE manually in
222 cr4_set_bits(X86_CR4_PCIDE);
225 * INVPCID's single-context modes (2/3) only work if we set
226 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
227 * on systems that have X86_CR4_PCIDE clear, or that have
228 * no INVPCID support at all.
230 if (boot_cpu_has(X86_FEATURE_INVPCID))
231 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
234 * flush_tlb_all(), as currently implemented, won't work if
235 * PCID is on but PGE is not. Since that combination
236 * doesn't exist on real hardware, there's no reason to try
237 * to fully support it, but it's polite to avoid corrupting
238 * data if we're on an improperly configured VM.
240 setup_clear_cpu_cap(X86_FEATURE_PCID);
245 #define NR_RANGE_MR 3
246 #else /* CONFIG_X86_64 */
247 #define NR_RANGE_MR 5
250 static int __meminit save_mr(struct map_range *mr, int nr_range,
251 unsigned long start_pfn, unsigned long end_pfn,
252 unsigned long page_size_mask)
254 if (start_pfn < end_pfn) {
255 if (nr_range >= NR_RANGE_MR)
256 panic("run out of range for init_memory_mapping\n");
257 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
258 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
259 mr[nr_range].page_size_mask = page_size_mask;
267 * adjust the page_size_mask for small range to go with
268 * big page size instead small one if nearby are ram too.
270 static void __ref adjust_range_page_size_mask(struct map_range *mr,
275 for (i = 0; i < nr_range; i++) {
276 if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
277 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
278 unsigned long start = round_down(mr[i].start, PMD_SIZE);
279 unsigned long end = round_up(mr[i].end, PMD_SIZE);
282 if ((end >> PAGE_SHIFT) > max_low_pfn)
286 if (memblock_is_region_memory(start, end - start))
287 mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
289 if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
290 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
291 unsigned long start = round_down(mr[i].start, PUD_SIZE);
292 unsigned long end = round_up(mr[i].end, PUD_SIZE);
294 if (memblock_is_region_memory(start, end - start))
295 mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
300 static const char *page_size_string(struct map_range *mr)
302 static const char str_1g[] = "1G";
303 static const char str_2m[] = "2M";
304 static const char str_4m[] = "4M";
305 static const char str_4k[] = "4k";
307 if (mr->page_size_mask & (1<<PG_LEVEL_1G))
310 * 32-bit without PAE has a 4M large page size.
311 * PG_LEVEL_2M is misnamed, but we can at least
312 * print out the right size in the string.
314 if (IS_ENABLED(CONFIG_X86_32) &&
315 !IS_ENABLED(CONFIG_X86_PAE) &&
316 mr->page_size_mask & (1<<PG_LEVEL_2M))
319 if (mr->page_size_mask & (1<<PG_LEVEL_2M))
325 static int __meminit split_mem_range(struct map_range *mr, int nr_range,
329 unsigned long start_pfn, end_pfn, limit_pfn;
333 limit_pfn = PFN_DOWN(end);
335 /* head if not big page alignment ? */
336 pfn = start_pfn = PFN_DOWN(start);
339 * Don't use a large page for the first 2/4MB of memory
340 * because there are often fixed size MTRRs in there
341 * and overlapping MTRRs into large pages can cause
345 end_pfn = PFN_DOWN(PMD_SIZE);
347 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
348 #else /* CONFIG_X86_64 */
349 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
351 if (end_pfn > limit_pfn)
353 if (start_pfn < end_pfn) {
354 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
358 /* big page (2M) range */
359 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
361 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
362 #else /* CONFIG_X86_64 */
363 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
364 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
365 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
368 if (start_pfn < end_pfn) {
369 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
370 page_size_mask & (1<<PG_LEVEL_2M));
375 /* big page (1G) range */
376 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
377 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
378 if (start_pfn < end_pfn) {
379 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
381 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
385 /* tail is not big page (1G) alignment */
386 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
387 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
388 if (start_pfn < end_pfn) {
389 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
390 page_size_mask & (1<<PG_LEVEL_2M));
395 /* tail is not big page (2M) alignment */
398 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
401 adjust_range_page_size_mask(mr, nr_range);
403 /* try to merge same page size and continuous */
404 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
405 unsigned long old_start;
406 if (mr[i].end != mr[i+1].start ||
407 mr[i].page_size_mask != mr[i+1].page_size_mask)
410 old_start = mr[i].start;
411 memmove(&mr[i], &mr[i+1],
412 (nr_range - 1 - i) * sizeof(struct map_range));
413 mr[i--].start = old_start;
417 for (i = 0; i < nr_range; i++)
418 pr_debug(" [mem %#010lx-%#010lx] page %s\n",
419 mr[i].start, mr[i].end - 1,
420 page_size_string(&mr[i]));
425 struct range pfn_mapped[E820_MAX_ENTRIES];
428 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
430 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
431 nr_pfn_mapped, start_pfn, end_pfn);
432 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
434 max_pfn_mapped = max(max_pfn_mapped, end_pfn);
436 if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
437 max_low_pfn_mapped = max(max_low_pfn_mapped,
438 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
441 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
445 for (i = 0; i < nr_pfn_mapped; i++)
446 if ((start_pfn >= pfn_mapped[i].start) &&
447 (end_pfn <= pfn_mapped[i].end))
454 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
455 * This runs before bootmem is initialized and gets pages directly from
456 * the physical memory. To access them they are temporarily mapped.
458 unsigned long __ref init_memory_mapping(unsigned long start,
461 struct map_range mr[NR_RANGE_MR];
462 unsigned long ret = 0;
465 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
468 memset(mr, 0, sizeof(mr));
469 nr_range = split_mem_range(mr, 0, start, end);
471 for (i = 0; i < nr_range; i++)
472 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
473 mr[i].page_size_mask);
475 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
477 return ret >> PAGE_SHIFT;
481 * We need to iterate through the E820 memory map and create direct mappings
482 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
483 * create direct mappings for all pfns from [0 to max_low_pfn) and
484 * [4GB to max_pfn) because of possible memory holes in high addresses
485 * that cannot be marked as UC by fixed/variable range MTRRs.
486 * Depending on the alignment of E820 ranges, this may possibly result
487 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
489 * init_mem_mapping() calls init_range_memory_mapping() with big range.
490 * That range would have hole in the middle or ends, and only ram parts
491 * will be mapped in init_range_memory_mapping().
493 static unsigned long __init init_range_memory_mapping(
494 unsigned long r_start,
497 unsigned long start_pfn, end_pfn;
498 unsigned long mapped_ram_size = 0;
501 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
502 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
503 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
508 * if it is overlapping with brk pgt, we need to
509 * alloc pgt buf from memblock instead.
511 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
512 min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
513 init_memory_mapping(start, end);
514 mapped_ram_size += end - start;
515 can_use_brk_pgt = true;
518 return mapped_ram_size;
521 static unsigned long __init get_new_step_size(unsigned long step_size)
524 * Initial mapped size is PMD_SIZE (2M).
525 * We can not set step_size to be PUD_SIZE (1G) yet.
526 * In worse case, when we cross the 1G boundary, and
527 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
528 * to map 1G range with PTE. Hence we use one less than the
529 * difference of page table level shifts.
531 * Don't need to worry about overflow in the top-down case, on 32bit,
532 * when step_size is 0, round_down() returns 0 for start, and that
533 * turns it into 0x100000000ULL.
534 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
535 * needs to be taken into consideration by the code below.
537 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
541 * memory_map_top_down - Map [map_start, map_end) top down
542 * @map_start: start address of the target memory range
543 * @map_end: end address of the target memory range
545 * This function will setup direct mapping for memory range
546 * [map_start, map_end) in top-down. That said, the page tables
547 * will be allocated at the end of the memory, and we map the
548 * memory in top-down.
550 static void __init memory_map_top_down(unsigned long map_start,
551 unsigned long map_end)
553 unsigned long real_end, start, last_start;
554 unsigned long step_size;
556 unsigned long mapped_ram_size = 0;
558 /* xen has big range in reserved near end of ram, skip it at first.*/
559 addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE);
560 real_end = addr + PMD_SIZE;
562 /* step_size need to be small so pgt_buf from BRK could cover it */
563 step_size = PMD_SIZE;
564 max_pfn_mapped = 0; /* will get exact value next */
565 min_pfn_mapped = real_end >> PAGE_SHIFT;
566 last_start = start = real_end;
569 * We start from the top (end of memory) and go to the bottom.
570 * The memblock_find_in_range() gets us a block of RAM from the
571 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
574 while (last_start > map_start) {
575 if (last_start > step_size) {
576 start = round_down(last_start - 1, step_size);
577 if (start < map_start)
581 mapped_ram_size += init_range_memory_mapping(start,
584 min_pfn_mapped = last_start >> PAGE_SHIFT;
585 if (mapped_ram_size >= step_size)
586 step_size = get_new_step_size(step_size);
589 if (real_end < map_end)
590 init_range_memory_mapping(real_end, map_end);
594 * memory_map_bottom_up - Map [map_start, map_end) bottom up
595 * @map_start: start address of the target memory range
596 * @map_end: end address of the target memory range
598 * This function will setup direct mapping for memory range
599 * [map_start, map_end) in bottom-up. Since we have limited the
600 * bottom-up allocation above the kernel, the page tables will
601 * be allocated just above the kernel and we map the memory
602 * in [map_start, map_end) in bottom-up.
604 static void __init memory_map_bottom_up(unsigned long map_start,
605 unsigned long map_end)
607 unsigned long next, start;
608 unsigned long mapped_ram_size = 0;
609 /* step_size need to be small so pgt_buf from BRK could cover it */
610 unsigned long step_size = PMD_SIZE;
613 min_pfn_mapped = start >> PAGE_SHIFT;
616 * We start from the bottom (@map_start) and go to the top (@map_end).
617 * The memblock_find_in_range() gets us a block of RAM from the
618 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
621 while (start < map_end) {
622 if (step_size && map_end - start > step_size) {
623 next = round_up(start + 1, step_size);
630 mapped_ram_size += init_range_memory_mapping(start, next);
633 if (mapped_ram_size >= step_size)
634 step_size = get_new_step_size(step_size);
638 void __init init_mem_mapping(void)
642 pti_check_boottime_disable();
643 probe_page_size_mask();
647 end = max_pfn << PAGE_SHIFT;
649 end = max_low_pfn << PAGE_SHIFT;
652 /* the ISA range is always mapped regardless of memory holes */
653 init_memory_mapping(0, ISA_END_ADDRESS);
655 /* Init the trampoline, possibly with KASLR memory offset */
659 * If the allocation is in bottom-up direction, we setup direct mapping
660 * in bottom-up, otherwise we setup direct mapping in top-down.
662 if (memblock_bottom_up()) {
663 unsigned long kernel_end = __pa_symbol(_end);
666 * we need two separate calls here. This is because we want to
667 * allocate page tables above the kernel. So we first map
668 * [kernel_end, end) to make memory above the kernel be mapped
669 * as soon as possible. And then use page tables allocated above
670 * the kernel to map [ISA_END_ADDRESS, kernel_end).
672 memory_map_bottom_up(kernel_end, end);
673 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
675 memory_map_top_down(ISA_END_ADDRESS, end);
679 if (max_pfn > max_low_pfn) {
680 /* can we preseve max_low_pfn ?*/
681 max_low_pfn = max_pfn;
684 early_ioremap_page_table_range_init();
687 load_cr3(swapper_pg_dir);
690 x86_init.hyper.init_mem_mapping();
692 early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
696 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
697 * is valid. The argument is a physical page number.
699 * On x86, access has to be given to the first megabyte of RAM because that
700 * area traditionally contains BIOS code and data regions used by X, dosemu,
701 * and similar apps. Since they map the entire memory range, the whole range
702 * must be allowed (for mapping), but any areas that would otherwise be
703 * disallowed are flagged as being "zero filled" instead of rejected.
704 * Access has to be given to non-kernel-ram areas as well, these contain the
705 * PCI mmio resources as well as potential bios/acpi data regions.
707 int devmem_is_allowed(unsigned long pagenr)
709 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
710 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
711 != REGION_DISJOINT) {
713 * For disallowed memory regions in the low 1MB range,
714 * request that the page be shown as all zeros.
723 * This must follow RAM test, since System RAM is considered a
724 * restricted resource under CONFIG_STRICT_IOMEM.
726 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
727 /* Low 1MB bypasses iomem restrictions. */
737 void free_init_pages(char *what, unsigned long begin, unsigned long end)
739 unsigned long begin_aligned, end_aligned;
741 /* Make sure boundaries are page aligned */
742 begin_aligned = PAGE_ALIGN(begin);
743 end_aligned = end & PAGE_MASK;
745 if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
746 begin = begin_aligned;
754 * If debugging page accesses then do not free this memory but
755 * mark them not present - any buggy init-section access will
756 * create a kernel page fault:
758 if (debug_pagealloc_enabled()) {
759 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
761 set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
764 * We just marked the kernel text read only above, now that
765 * we are going to free part of that, we need to make that
766 * writeable and non-executable first.
768 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
769 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
771 free_reserved_area((void *)begin, (void *)end,
772 POISON_FREE_INITMEM, what);
776 void __ref free_initmem(void)
778 e820__reallocate_tables();
780 free_init_pages("unused kernel",
781 (unsigned long)(&__init_begin),
782 (unsigned long)(&__init_end));
785 #ifdef CONFIG_BLK_DEV_INITRD
786 void __init free_initrd_mem(unsigned long start, unsigned long end)
789 * end could be not aligned, and We can not align that,
790 * decompresser could be confused by aligned initrd_end
791 * We already reserve the end partial page before in
792 * - i386_start_kernel()
793 * - x86_64_start_kernel()
794 * - relocate_initrd()
795 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
797 free_init_pages("initrd", start, PAGE_ALIGN(end));
802 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
803 * and pass it to the MM layer - to help it set zone watermarks more
806 * Done on 64-bit systems only for the time being, although 32-bit systems
807 * might benefit from this as well.
809 void __init memblock_find_dma_reserve(void)
812 u64 nr_pages = 0, nr_free_pages = 0;
813 unsigned long start_pfn, end_pfn;
814 phys_addr_t start_addr, end_addr;
819 * Iterate over all memory ranges (free and reserved ones alike),
820 * to calculate the total number of pages in the first 16 MB of RAM:
823 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
824 start_pfn = min(start_pfn, MAX_DMA_PFN);
825 end_pfn = min(end_pfn, MAX_DMA_PFN);
827 nr_pages += end_pfn - start_pfn;
831 * Iterate over free memory ranges to calculate the number of free
832 * pages in the DMA zone, while not counting potential partial
833 * pages at the beginning or the end of the range:
836 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
837 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
838 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
840 if (start_pfn < end_pfn)
841 nr_free_pages += end_pfn - start_pfn;
844 set_dma_reserve(nr_pages - nr_free_pages);
848 void __init zone_sizes_init(void)
850 unsigned long max_zone_pfns[MAX_NR_ZONES];
852 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
854 #ifdef CONFIG_ZONE_DMA
855 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
857 #ifdef CONFIG_ZONE_DMA32
858 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn);
860 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
861 #ifdef CONFIG_HIGHMEM
862 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
865 free_area_init_nodes(max_zone_pfns);
868 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
869 .loaded_mm = &init_mm,
871 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
873 EXPORT_PER_CPU_SYMBOL(cpu_tlbstate);
875 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
877 /* entry 0 MUST be WB (hardwired to speed up translations) */
878 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
880 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
881 __pte2cachemode_tbl[entry] = cache;
885 unsigned long max_swapfile_size(void)
889 pages = generic_max_swapfile_size();
891 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
892 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */
893 unsigned long long l1tf_limit = l1tf_pfn_limit();
895 * We encode swap offsets also with 3 bits below those for pfn
896 * which makes the usable limit higher.
898 #if CONFIG_PGTABLE_LEVELS > 2
899 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
901 pages = min_t(unsigned long long, l1tf_limit, pages);