1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 instruction analysis
5 * Copyright (C) IBM Corporation, 2002, 2004, 2009
9 #include <linux/string.h>
13 #include <asm/inat.h> /*__ignore_sync_check__ */
14 #include <asm/insn.h> /* __ignore_sync_check__ */
16 #include <linux/errno.h>
17 #include <linux/kconfig.h>
19 #include <asm/emulate_prefix.h> /* __ignore_sync_check__ */
21 /* Verify next sizeof(t) bytes can be on the same instruction */
22 #define validate_next(t, insn, n) \
23 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
25 #define __get_next(t, insn) \
26 ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
28 #define __peek_nbyte_next(t, insn, n) \
29 ({ t r = *(t*)((insn)->next_byte + n); r; })
31 #define get_next(t, insn) \
32 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
34 #define peek_nbyte_next(t, insn, n) \
35 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
37 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
40 * insn_init() - initialize struct insn
41 * @insn: &struct insn to be initialized
42 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
43 * @x86_64: !0 for 64-bit kernel or 64-bit app
45 void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64)
48 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid
49 * even if the input buffer is long enough to hold them.
51 if (buf_len > MAX_INSN_SIZE)
52 buf_len = MAX_INSN_SIZE;
54 memset(insn, 0, sizeof(*insn));
56 insn->end_kaddr = kaddr + buf_len;
57 insn->next_byte = kaddr;
58 insn->x86_64 = x86_64 ? 1 : 0;
66 static const insn_byte_t xen_prefix[] = { __XEN_EMULATE_PREFIX };
67 static const insn_byte_t kvm_prefix[] = { __KVM_EMULATE_PREFIX };
69 static int __insn_get_emulate_prefix(struct insn *insn,
70 const insn_byte_t *prefix, size_t len)
74 for (i = 0; i < len; i++) {
75 if (peek_nbyte_next(insn_byte_t, insn, i) != prefix[i])
79 insn->emulate_prefix_size = len;
80 insn->next_byte += len;
88 static void insn_get_emulate_prefix(struct insn *insn)
90 if (__insn_get_emulate_prefix(insn, xen_prefix, sizeof(xen_prefix)))
93 __insn_get_emulate_prefix(insn, kvm_prefix, sizeof(kvm_prefix));
97 * insn_get_prefixes - scan x86 instruction prefix bytes
98 * @insn: &struct insn containing instruction
100 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
101 * to point to the (first) opcode. No effect if @insn->prefixes.got
108 int insn_get_prefixes(struct insn *insn)
110 struct insn_field *prefixes = &insn->prefixes;
118 insn_get_emulate_prefix(insn);
122 b = peek_next(insn_byte_t, insn);
123 attr = inat_get_opcode_attribute(b);
124 while (inat_is_legacy_prefix(attr)) {
125 /* Skip if same prefix */
126 for (i = 0; i < nb; i++)
127 if (prefixes->bytes[i] == b)
130 /* Invalid instruction */
132 prefixes->bytes[nb++] = b;
133 if (inat_is_address_size_prefix(attr)) {
134 /* address size switches 2/4 or 4/8 */
136 insn->addr_bytes ^= 12;
138 insn->addr_bytes ^= 6;
139 } else if (inat_is_operand_size_prefix(attr)) {
140 /* oprand size switches 2/4 */
141 insn->opnd_bytes ^= 6;
147 b = peek_next(insn_byte_t, insn);
148 attr = inat_get_opcode_attribute(b);
150 /* Set the last prefix */
151 if (lb && lb != insn->prefixes.bytes[3]) {
152 if (unlikely(insn->prefixes.bytes[3])) {
153 /* Swap the last prefix */
154 b = insn->prefixes.bytes[3];
155 for (i = 0; i < nb; i++)
156 if (prefixes->bytes[i] == lb)
157 prefixes->bytes[i] = b;
159 insn->prefixes.bytes[3] = lb;
162 /* Decode REX prefix */
164 b = peek_next(insn_byte_t, insn);
165 attr = inat_get_opcode_attribute(b);
166 if (inat_is_rex_prefix(attr)) {
167 insn->rex_prefix.value = b;
168 insn->rex_prefix.nbytes = 1;
171 /* REX.W overrides opnd_size */
172 insn->opnd_bytes = 8;
175 insn->rex_prefix.got = 1;
177 /* Decode VEX prefix */
178 b = peek_next(insn_byte_t, insn);
179 attr = inat_get_opcode_attribute(b);
180 if (inat_is_vex_prefix(attr)) {
181 insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1);
184 * In 32-bits mode, if the [7:6] bits (mod bits of
185 * ModRM) on the second byte are not 11b, it is
186 * LDS or LES or BOUND.
188 if (X86_MODRM_MOD(b2) != 3)
191 insn->vex_prefix.bytes[0] = b;
192 insn->vex_prefix.bytes[1] = b2;
193 if (inat_is_evex_prefix(attr)) {
194 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
195 insn->vex_prefix.bytes[2] = b2;
196 b2 = peek_nbyte_next(insn_byte_t, insn, 3);
197 insn->vex_prefix.bytes[3] = b2;
198 insn->vex_prefix.nbytes = 4;
199 insn->next_byte += 4;
200 if (insn->x86_64 && X86_VEX_W(b2))
201 /* VEX.W overrides opnd_size */
202 insn->opnd_bytes = 8;
203 } else if (inat_is_vex3_prefix(attr)) {
204 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
205 insn->vex_prefix.bytes[2] = b2;
206 insn->vex_prefix.nbytes = 3;
207 insn->next_byte += 3;
208 if (insn->x86_64 && X86_VEX_W(b2))
209 /* VEX.W overrides opnd_size */
210 insn->opnd_bytes = 8;
213 * For VEX2, fake VEX3-like byte#2.
214 * Makes it easier to decode vex.W, vex.vvvv,
215 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
217 insn->vex_prefix.bytes[2] = b2 & 0x7f;
218 insn->vex_prefix.nbytes = 2;
219 insn->next_byte += 2;
223 insn->vex_prefix.got = 1;
234 * insn_get_opcode - collect opcode(s)
235 * @insn: &struct insn containing instruction
237 * Populates @insn->opcode, updates @insn->next_byte to point past the
238 * opcode byte(s), and set @insn->attr (except for groups).
239 * If necessary, first collects any preceding (prefix) bytes.
240 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
247 int insn_get_opcode(struct insn *insn)
249 struct insn_field *opcode = &insn->opcode;
256 if (!insn->prefixes.got) {
257 ret = insn_get_prefixes(insn);
262 /* Get first opcode */
263 op = get_next(insn_byte_t, insn);
264 opcode->bytes[0] = op;
267 /* Check if there is VEX prefix or not */
268 if (insn_is_avx(insn)) {
270 m = insn_vex_m_bits(insn);
271 p = insn_vex_p_bits(insn);
272 insn->attr = inat_get_avx_attribute(op, m, p);
273 if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) ||
274 (!inat_accept_vex(insn->attr) &&
275 !inat_is_group(insn->attr))) {
276 /* This instruction is bad */
280 /* VEX has only 1 byte for opcode */
284 insn->attr = inat_get_opcode_attribute(op);
285 while (inat_is_escape(insn->attr)) {
286 /* Get escaped opcode */
287 op = get_next(insn_byte_t, insn);
288 opcode->bytes[opcode->nbytes++] = op;
289 pfx_id = insn_last_prefix_id(insn);
290 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr);
293 if (inat_must_vex(insn->attr)) {
294 /* This instruction is bad */
307 * insn_get_modrm - collect ModRM byte, if any
308 * @insn: &struct insn containing instruction
310 * Populates @insn->modrm and updates @insn->next_byte to point past the
311 * ModRM byte, if any. If necessary, first collects the preceding bytes
312 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
318 int insn_get_modrm(struct insn *insn)
320 struct insn_field *modrm = &insn->modrm;
321 insn_byte_t pfx_id, mod;
327 if (!insn->opcode.got) {
328 ret = insn_get_opcode(insn);
333 if (inat_has_modrm(insn->attr)) {
334 mod = get_next(insn_byte_t, insn);
337 if (inat_is_group(insn->attr)) {
338 pfx_id = insn_last_prefix_id(insn);
339 insn->attr = inat_get_group_attribute(mod, pfx_id,
341 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr)) {
349 if (insn->x86_64 && inat_is_force64(insn->attr))
350 insn->opnd_bytes = 8;
361 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
362 * @insn: &struct insn containing instruction
364 * If necessary, first collects the instruction up to and including the
365 * ModRM byte. No effect if @insn->x86_64 is 0.
367 int insn_rip_relative(struct insn *insn)
369 struct insn_field *modrm = &insn->modrm;
376 ret = insn_get_modrm(insn);
381 * For rip-relative instructions, the mod field (top 2 bits)
382 * is zero and the r/m field (bottom 3 bits) is 0x5.
384 return (modrm->nbytes && (modrm->value & 0xc7) == 0x5);
388 * insn_get_sib() - Get the SIB byte of instruction
389 * @insn: &struct insn containing instruction
391 * If necessary, first collects the instruction up to and including the
395 * 0: if decoding succeeded
398 int insn_get_sib(struct insn *insn)
406 if (!insn->modrm.got) {
407 ret = insn_get_modrm(insn);
412 if (insn->modrm.nbytes) {
413 modrm = (insn_byte_t)insn->modrm.value;
414 if (insn->addr_bytes != 2 &&
415 X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) {
416 insn->sib.value = get_next(insn_byte_t, insn);
417 insn->sib.nbytes = 1;
430 * insn_get_displacement() - Get the displacement of instruction
431 * @insn: &struct insn containing instruction
433 * If necessary, first collects the instruction up to and including the
435 * Displacement value is sign-expanded.
438 * 0: if decoding succeeded
441 int insn_get_displacement(struct insn *insn)
443 insn_byte_t mod, rm, base;
446 if (insn->displacement.got)
449 if (!insn->sib.got) {
450 ret = insn_get_sib(insn);
455 if (insn->modrm.nbytes) {
457 * Interpreting the modrm byte:
458 * mod = 00 - no displacement fields (exceptions below)
459 * mod = 01 - 1-byte displacement field
460 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
461 * address size = 2 (0x67 prefix in 32-bit mode)
462 * mod = 11 - no memory operand
464 * If address size = 2...
465 * mod = 00, r/m = 110 - displacement field is 2 bytes
467 * If address size != 2...
468 * mod != 11, r/m = 100 - SIB byte exists
469 * mod = 00, SIB base = 101 - displacement field is 4 bytes
470 * mod = 00, r/m = 101 - rip-relative addressing, displacement
473 mod = X86_MODRM_MOD(insn->modrm.value);
474 rm = X86_MODRM_RM(insn->modrm.value);
475 base = X86_SIB_BASE(insn->sib.value);
479 insn->displacement.value = get_next(signed char, insn);
480 insn->displacement.nbytes = 1;
481 } else if (insn->addr_bytes == 2) {
482 if ((mod == 0 && rm == 6) || mod == 2) {
483 insn->displacement.value =
484 get_next(short, insn);
485 insn->displacement.nbytes = 2;
488 if ((mod == 0 && rm == 5) || mod == 2 ||
489 (mod == 0 && base == 5)) {
490 insn->displacement.value = get_next(int, insn);
491 insn->displacement.nbytes = 4;
496 insn->displacement.got = 1;
503 /* Decode moffset16/32/64. Return 0 if failed */
504 static int __get_moffset(struct insn *insn)
506 switch (insn->addr_bytes) {
508 insn->moffset1.value = get_next(short, insn);
509 insn->moffset1.nbytes = 2;
512 insn->moffset1.value = get_next(int, insn);
513 insn->moffset1.nbytes = 4;
516 insn->moffset1.value = get_next(int, insn);
517 insn->moffset1.nbytes = 4;
518 insn->moffset2.value = get_next(int, insn);
519 insn->moffset2.nbytes = 4;
521 default: /* opnd_bytes must be modified manually */
524 insn->moffset1.got = insn->moffset2.got = 1;
532 /* Decode imm v32(Iz). Return 0 if failed */
533 static int __get_immv32(struct insn *insn)
535 switch (insn->opnd_bytes) {
537 insn->immediate.value = get_next(short, insn);
538 insn->immediate.nbytes = 2;
542 insn->immediate.value = get_next(int, insn);
543 insn->immediate.nbytes = 4;
545 default: /* opnd_bytes must be modified manually */
555 /* Decode imm v64(Iv/Ov), Return 0 if failed */
556 static int __get_immv(struct insn *insn)
558 switch (insn->opnd_bytes) {
560 insn->immediate1.value = get_next(short, insn);
561 insn->immediate1.nbytes = 2;
564 insn->immediate1.value = get_next(int, insn);
565 insn->immediate1.nbytes = 4;
568 insn->immediate1.value = get_next(int, insn);
569 insn->immediate1.nbytes = 4;
570 insn->immediate2.value = get_next(int, insn);
571 insn->immediate2.nbytes = 4;
573 default: /* opnd_bytes must be modified manually */
576 insn->immediate1.got = insn->immediate2.got = 1;
583 /* Decode ptr16:16/32(Ap) */
584 static int __get_immptr(struct insn *insn)
586 switch (insn->opnd_bytes) {
588 insn->immediate1.value = get_next(short, insn);
589 insn->immediate1.nbytes = 2;
592 insn->immediate1.value = get_next(int, insn);
593 insn->immediate1.nbytes = 4;
596 /* ptr16:64 is not exist (no segment) */
598 default: /* opnd_bytes must be modified manually */
601 insn->immediate2.value = get_next(unsigned short, insn);
602 insn->immediate2.nbytes = 2;
603 insn->immediate1.got = insn->immediate2.got = 1;
611 * insn_get_immediate() - Get the immediate in an instruction
612 * @insn: &struct insn containing instruction
614 * If necessary, first collects the instruction up to and including the
615 * displacement bytes.
616 * Basically, most of immediates are sign-expanded. Unsigned-value can be
617 * computed by bit masking with ((1 << (nbytes * 8)) - 1)
623 int insn_get_immediate(struct insn *insn)
627 if (insn->immediate.got)
630 if (!insn->displacement.got) {
631 ret = insn_get_displacement(insn);
636 if (inat_has_moffset(insn->attr)) {
637 if (!__get_moffset(insn))
642 if (!inat_has_immediate(insn->attr))
646 switch (inat_immediate_size(insn->attr)) {
648 insn->immediate.value = get_next(signed char, insn);
649 insn->immediate.nbytes = 1;
652 insn->immediate.value = get_next(short, insn);
653 insn->immediate.nbytes = 2;
656 insn->immediate.value = get_next(int, insn);
657 insn->immediate.nbytes = 4;
660 insn->immediate1.value = get_next(int, insn);
661 insn->immediate1.nbytes = 4;
662 insn->immediate2.value = get_next(int, insn);
663 insn->immediate2.nbytes = 4;
666 if (!__get_immptr(insn))
669 case INAT_IMM_VWORD32:
670 if (!__get_immv32(insn))
674 if (!__get_immv(insn))
678 /* Here, insn must have an immediate, but failed */
681 if (inat_has_second_immediate(insn->attr)) {
682 insn->immediate2.value = get_next(signed char, insn);
683 insn->immediate2.nbytes = 1;
686 insn->immediate.got = 1;
694 * insn_get_length() - Get the length of instruction
695 * @insn: &struct insn containing instruction
697 * If necessary, first collects the instruction up to and including the
704 int insn_get_length(struct insn *insn)
711 if (!insn->immediate.got) {
712 ret = insn_get_immediate(insn);
717 insn->length = (unsigned char)((unsigned long)insn->next_byte
718 - (unsigned long)insn->kaddr);
724 * insn_decode() - Decode an x86 instruction
725 * @insn: &struct insn to be initialized
726 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
727 * @buf_len: length of the insn buffer at @kaddr
728 * @m: insn mode, see enum insn_mode
731 * 0: if decoding succeeded
734 int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m)
738 /* #define INSN_MODE_KERN -1 __ignore_sync_check__ mode is only valid in the kernel */
740 if (m == INSN_MODE_KERN)
741 insn_init(insn, kaddr, buf_len, IS_ENABLED(CONFIG_X86_64));
743 insn_init(insn, kaddr, buf_len, m == INSN_MODE_64);
745 ret = insn_get_length(insn);
749 if (insn_complete(insn))