2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define CREATE_TRACE_POINTS
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
93 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
94 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void process_smi(struct kvm_vcpu *vcpu);
102 static void enter_smm(struct kvm_vcpu *vcpu);
103 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
106 EXPORT_SYMBOL_GPL(kvm_x86_ops);
108 static bool __read_mostly ignore_msrs = 0;
109 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
111 unsigned int min_timer_period_us = 500;
112 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
114 static bool __read_mostly kvmclock_periodic_sync = true;
115 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
117 bool __read_mostly kvm_has_tsc_control;
118 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
119 u32 __read_mostly kvm_max_guest_tsc_khz;
120 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
121 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
122 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
123 u64 __read_mostly kvm_max_tsc_scaling_ratio;
124 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
125 u64 __read_mostly kvm_default_tsc_scaling_ratio;
126 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
128 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
129 static u32 __read_mostly tsc_tolerance_ppm = 250;
130 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
132 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
133 unsigned int __read_mostly lapic_timer_advance_ns = 0;
134 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
136 static bool __read_mostly vector_hashing = true;
137 module_param(vector_hashing, bool, S_IRUGO);
139 #define KVM_NR_SHARED_MSRS 16
141 struct kvm_shared_msrs_global {
143 u32 msrs[KVM_NR_SHARED_MSRS];
146 struct kvm_shared_msrs {
147 struct user_return_notifier urn;
149 struct kvm_shared_msr_values {
152 } values[KVM_NR_SHARED_MSRS];
155 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
156 static struct kvm_shared_msrs __percpu *shared_msrs;
158 struct kvm_stats_debugfs_item debugfs_entries[] = {
159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
169 { "halt_exits", VCPU_STAT(halt_exits) },
170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
174 { "hypercalls", VCPU_STAT(hypercalls) },
175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
182 { "irq_injections", VCPU_STAT(irq_injections) },
183 { "nmi_injections", VCPU_STAT(nmi_injections) },
184 { "req_event", VCPU_STAT(req_event) },
185 { "l1d_flush", VCPU_STAT(l1d_flush) },
186 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
187 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
188 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
189 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
190 { "mmu_flooded", VM_STAT(mmu_flooded) },
191 { "mmu_recycled", VM_STAT(mmu_recycled) },
192 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
193 { "mmu_unsync", VM_STAT(mmu_unsync) },
194 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
195 { "largepages", VM_STAT(lpages, .mode = 0444) },
196 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
202 u64 __read_mostly host_xcr0;
204 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
206 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
213 static void kvm_on_user_return(struct user_return_notifier *urn)
216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
218 struct kvm_shared_msr_values *values;
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
230 local_irq_restore(flags);
231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
240 static void shared_msr_update(unsigned slot, u32 msr)
243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
257 void kvm_define_shared_msr(unsigned slot, u32 msr)
259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
260 shared_msrs_global.msrs[slot] = msr;
261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
264 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266 static void kvm_shared_msr_cpu_online(void)
270 for (i = 0; i < shared_msrs_global.nr; ++i)
271 shared_msr_update(i, shared_msrs_global.msrs[i]);
274 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
280 value = (value & mask) | (smsr->values[slot].host & ~mask);
281 if (value == smsr->values[slot].curr)
283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
287 smsr->values[slot].curr = value;
288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
295 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
297 static void drop_user_return_notifiers(void)
299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
306 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
308 return vcpu->arch.apic_base;
310 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
312 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
314 return kvm_apic_mode(kvm_get_apic_base(vcpu));
316 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
318 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
320 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
321 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
322 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
323 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
325 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
327 if (!msr_info->host_initiated) {
328 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
330 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
334 kvm_lapic_set_base(vcpu, msr_info->data);
337 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
339 asmlinkage __visible void kvm_spurious_fault(void)
341 /* Fault while not rebooting. We want the trace. */
344 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
346 #define EXCPT_BENIGN 0
347 #define EXCPT_CONTRIBUTORY 1
350 static int exception_class(int vector)
360 return EXCPT_CONTRIBUTORY;
367 #define EXCPT_FAULT 0
369 #define EXCPT_ABORT 2
370 #define EXCPT_INTERRUPT 3
372 static int exception_type(int vector)
376 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
377 return EXCPT_INTERRUPT;
381 /* #DB is trap, as instruction watchpoints are handled elsewhere */
382 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
385 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
388 /* Reserved exceptions will result in fault */
392 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
393 unsigned nr, bool has_error, u32 error_code,
399 kvm_make_request(KVM_REQ_EVENT, vcpu);
401 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
405 * On vmentry, vcpu->arch.exception.pending is only
406 * true if an event injection was blocked by
407 * nested_run_pending. In that case, however,
408 * vcpu_enter_guest requests an immediate exit,
409 * and the guest shouldn't proceed far enough to
412 WARN_ON_ONCE(vcpu->arch.exception.pending);
413 vcpu->arch.exception.injected = true;
415 vcpu->arch.exception.pending = true;
416 vcpu->arch.exception.injected = false;
418 vcpu->arch.exception.has_error_code = has_error;
419 vcpu->arch.exception.nr = nr;
420 vcpu->arch.exception.error_code = error_code;
424 /* to check exception */
425 prev_nr = vcpu->arch.exception.nr;
426 if (prev_nr == DF_VECTOR) {
427 /* triple fault -> shutdown */
428 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
431 class1 = exception_class(prev_nr);
432 class2 = exception_class(nr);
433 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
434 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
436 * Generate double fault per SDM Table 5-5. Set
437 * exception.pending = true so that the double fault
438 * can trigger a nested vmexit.
440 vcpu->arch.exception.pending = true;
441 vcpu->arch.exception.injected = false;
442 vcpu->arch.exception.has_error_code = true;
443 vcpu->arch.exception.nr = DF_VECTOR;
444 vcpu->arch.exception.error_code = 0;
446 /* replace previous exception with a new one in a hope
447 that instruction re-execution will regenerate lost
452 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
454 kvm_multiple_exception(vcpu, nr, false, 0, false);
456 EXPORT_SYMBOL_GPL(kvm_queue_exception);
458 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
460 kvm_multiple_exception(vcpu, nr, false, 0, true);
462 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
464 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
467 kvm_inject_gp(vcpu, 0);
469 return kvm_skip_emulated_instruction(vcpu);
473 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
475 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
477 ++vcpu->stat.pf_guest;
478 vcpu->arch.exception.nested_apf =
479 is_guest_mode(vcpu) && fault->async_page_fault;
480 if (vcpu->arch.exception.nested_apf)
481 vcpu->arch.apf.nested_apf_token = fault->address;
483 vcpu->arch.cr2 = fault->address;
484 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
486 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
488 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
490 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
491 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
493 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
495 return fault->nested_page_fault;
498 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
500 atomic_inc(&vcpu->arch.nmi_queued);
501 kvm_make_request(KVM_REQ_NMI, vcpu);
503 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
505 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
507 kvm_multiple_exception(vcpu, nr, true, error_code, false);
509 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
511 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
513 kvm_multiple_exception(vcpu, nr, true, error_code, true);
515 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
518 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
519 * a #GP and return false.
521 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
523 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
525 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
528 EXPORT_SYMBOL_GPL(kvm_require_cpl);
530 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
532 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
535 kvm_queue_exception(vcpu, UD_VECTOR);
538 EXPORT_SYMBOL_GPL(kvm_require_dr);
541 * This function will be used to read from the physical memory of the currently
542 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
543 * can read from guest physical or from the guest's guest physical memory.
545 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
546 gfn_t ngfn, void *data, int offset, int len,
549 struct x86_exception exception;
553 ngpa = gfn_to_gpa(ngfn);
554 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
555 if (real_gfn == UNMAPPED_GVA)
558 real_gfn = gpa_to_gfn(real_gfn);
560 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
562 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
564 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
565 void *data, int offset, int len, u32 access)
567 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
568 data, offset, len, access);
571 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
573 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
578 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
580 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
582 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
583 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
586 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
588 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
589 offset * sizeof(u64), sizeof(pdpte),
590 PFERR_USER_MASK|PFERR_WRITE_MASK);
595 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
596 if ((pdpte[i] & PT_PRESENT_MASK) &&
597 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
604 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
605 __set_bit(VCPU_EXREG_PDPTR,
606 (unsigned long *)&vcpu->arch.regs_avail);
607 __set_bit(VCPU_EXREG_PDPTR,
608 (unsigned long *)&vcpu->arch.regs_dirty);
613 EXPORT_SYMBOL_GPL(load_pdptrs);
615 bool pdptrs_changed(struct kvm_vcpu *vcpu)
617 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
623 if (!is_pae_paging(vcpu))
626 if (!test_bit(VCPU_EXREG_PDPTR,
627 (unsigned long *)&vcpu->arch.regs_avail))
630 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
631 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
632 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
633 PFERR_USER_MASK | PFERR_WRITE_MASK);
636 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
641 EXPORT_SYMBOL_GPL(pdptrs_changed);
643 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
645 unsigned long old_cr0 = kvm_read_cr0(vcpu);
646 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
651 if (cr0 & 0xffffffff00000000UL)
655 cr0 &= ~CR0_RESERVED_BITS;
657 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
660 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
663 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
665 if ((vcpu->arch.efer & EFER_LME)) {
670 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
675 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
680 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
683 kvm_x86_ops->set_cr0(vcpu, cr0);
685 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
686 kvm_clear_async_pf_completion_queue(vcpu);
687 kvm_async_pf_hash_reset(vcpu);
690 if ((cr0 ^ old_cr0) & update_bits)
691 kvm_mmu_reset_context(vcpu);
693 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
694 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
695 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
696 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
700 EXPORT_SYMBOL_GPL(kvm_set_cr0);
702 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
704 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
706 EXPORT_SYMBOL_GPL(kvm_lmsw);
708 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
710 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
711 !vcpu->guest_xcr0_loaded) {
712 /* kvm_set_xcr() also depends on this */
713 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
714 vcpu->guest_xcr0_loaded = 1;
718 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
720 if (vcpu->guest_xcr0_loaded) {
721 if (vcpu->arch.xcr0 != host_xcr0)
722 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
723 vcpu->guest_xcr0_loaded = 0;
727 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
730 u64 old_xcr0 = vcpu->arch.xcr0;
733 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
734 if (index != XCR_XFEATURE_ENABLED_MASK)
736 if (!(xcr0 & XFEATURE_MASK_FP))
738 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
742 * Do not allow the guest to set bits that we do not support
743 * saving. However, xcr0 bit 0 is always set, even if the
744 * emulated CPU does not support XSAVE (see fx_init).
746 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
747 if (xcr0 & ~valid_bits)
750 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
751 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
754 if (xcr0 & XFEATURE_MASK_AVX512) {
755 if (!(xcr0 & XFEATURE_MASK_YMM))
757 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
760 vcpu->arch.xcr0 = xcr0;
762 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
763 kvm_update_cpuid(vcpu);
767 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
769 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
770 __kvm_set_xcr(vcpu, index, xcr)) {
771 kvm_inject_gp(vcpu, 0);
776 EXPORT_SYMBOL_GPL(kvm_set_xcr);
778 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
780 unsigned long old_cr4 = kvm_read_cr4(vcpu);
781 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
782 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
784 if (cr4 & CR4_RESERVED_BITS)
787 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
790 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
796 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
799 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
802 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
805 if (is_long_mode(vcpu)) {
806 if (!(cr4 & X86_CR4_PAE))
808 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
810 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
811 && ((cr4 ^ old_cr4) & pdptr_bits)
812 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
816 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
817 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
820 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
821 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
825 if (kvm_x86_ops->set_cr4(vcpu, cr4))
828 if (((cr4 ^ old_cr4) & pdptr_bits) ||
829 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
830 kvm_mmu_reset_context(vcpu);
832 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
833 kvm_update_cpuid(vcpu);
837 EXPORT_SYMBOL_GPL(kvm_set_cr4);
839 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
842 cr3 &= ~CR3_PCID_INVD;
845 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
846 kvm_mmu_sync_roots(vcpu);
847 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
851 if (is_long_mode(vcpu) &&
852 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
854 else if (is_pae_paging(vcpu) &&
855 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
858 vcpu->arch.cr3 = cr3;
859 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
860 kvm_mmu_new_cr3(vcpu);
863 EXPORT_SYMBOL_GPL(kvm_set_cr3);
865 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
867 if (cr8 & CR8_RESERVED_BITS)
869 if (lapic_in_kernel(vcpu))
870 kvm_lapic_set_tpr(vcpu, cr8);
872 vcpu->arch.cr8 = cr8;
875 EXPORT_SYMBOL_GPL(kvm_set_cr8);
877 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
879 if (lapic_in_kernel(vcpu))
880 return kvm_lapic_get_cr8(vcpu);
882 return vcpu->arch.cr8;
884 EXPORT_SYMBOL_GPL(kvm_get_cr8);
886 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
890 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
891 for (i = 0; i < KVM_NR_DB_REGS; i++)
892 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
893 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
897 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
899 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
900 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
903 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 dr7 = vcpu->arch.guest_debug_dr7;
910 dr7 = vcpu->arch.dr7;
911 kvm_x86_ops->set_dr7(vcpu, dr7);
912 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
913 if (dr7 & DR7_BP_EN_MASK)
914 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
917 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
919 u64 fixed = DR6_FIXED_1;
921 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
926 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
928 size_t size = ARRAY_SIZE(vcpu->arch.db);
932 vcpu->arch.db[array_index_nospec(dr, size)] = val;
933 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
934 vcpu->arch.eff_db[dr] = val;
939 if (val & 0xffffffff00000000ULL)
941 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
942 kvm_update_dr6(vcpu);
947 if (val & 0xffffffff00000000ULL)
949 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
950 kvm_update_dr7(vcpu);
957 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
959 if (__kvm_set_dr(vcpu, dr, val)) {
960 kvm_inject_gp(vcpu, 0);
965 EXPORT_SYMBOL_GPL(kvm_set_dr);
967 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
969 size_t size = ARRAY_SIZE(vcpu->arch.db);
973 *val = vcpu->arch.db[array_index_nospec(dr, size)];
978 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
979 *val = vcpu->arch.dr6;
981 *val = kvm_x86_ops->get_dr6(vcpu);
986 *val = vcpu->arch.dr7;
991 EXPORT_SYMBOL_GPL(kvm_get_dr);
993 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
995 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
999 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1002 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1003 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1006 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1009 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1010 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1012 * This list is modified at module load time to reflect the
1013 * capabilities of the host cpu. This capabilities test skips MSRs that are
1014 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1015 * may depend on host virtualization features rather than host cpu features.
1018 static u32 msrs_to_save[] = {
1019 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1021 #ifdef CONFIG_X86_64
1022 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1024 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1025 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1026 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1029 static unsigned num_msrs_to_save;
1031 static u32 emulated_msrs[] = {
1032 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1033 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1034 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1035 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1036 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1037 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1038 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1040 HV_X64_MSR_VP_INDEX,
1041 HV_X64_MSR_VP_RUNTIME,
1042 HV_X64_MSR_SCONTROL,
1043 HV_X64_MSR_STIMER0_CONFIG,
1044 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1047 MSR_IA32_TSC_ADJUST,
1048 MSR_IA32_TSCDEADLINE,
1049 MSR_IA32_MISC_ENABLE,
1050 MSR_IA32_MCG_STATUS,
1052 MSR_IA32_MCG_EXT_CTL,
1055 MSR_MISC_FEATURES_ENABLES,
1056 MSR_AMD64_VIRT_SPEC_CTRL,
1059 static unsigned num_emulated_msrs;
1062 * List of msr numbers which are used to expose MSR-based features that
1063 * can be used by a hypervisor to validate requested CPU features.
1065 static u32 msr_based_features[] = {
1068 MSR_IA32_ARCH_CAPABILITIES,
1071 static unsigned int num_msr_based_features;
1073 u64 kvm_get_arch_capabilities(void)
1077 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1080 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1081 * the nested hypervisor runs with NX huge pages. If it is not,
1082 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1083 * L1 guests, so it need not worry about its own (L2) guests.
1085 data |= ARCH_CAP_PSCHANGE_MC_NO;
1088 * If we're doing cache flushes (either "always" or "cond")
1089 * we will do one whenever the guest does a vmlaunch/vmresume.
1090 * If an outer hypervisor is doing the cache flush for us
1091 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1092 * capability to the guest too, and if EPT is disabled we're not
1093 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1094 * require a nested hypervisor to do a flush of its own.
1096 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1097 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1099 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1100 data |= ARCH_CAP_RDCL_NO;
1101 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1102 data |= ARCH_CAP_SSB_NO;
1103 if (!boot_cpu_has_bug(X86_BUG_MDS))
1104 data |= ARCH_CAP_MDS_NO;
1107 * On TAA affected systems, export MDS_NO=0 when:
1108 * - TSX is enabled on the host, i.e. X86_FEATURE_RTM=1.
1109 * - Updated microcode is present. This is detected by
1110 * the presence of ARCH_CAP_TSX_CTRL_MSR and ensures
1111 * that VERW clears CPU buffers.
1113 * When MDS_NO=0 is exported, guests deploy clear CPU buffer
1114 * mitigation and don't complain:
1116 * "Vulnerable: Clear CPU buffers attempted, no microcode"
1118 * If TSX is disabled on the system, guests are also mitigated against
1119 * TAA and clear CPU buffer mitigation is not required for guests.
1121 if (!boot_cpu_has(X86_FEATURE_RTM))
1122 data &= ~ARCH_CAP_TAA_NO;
1123 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1124 data |= ARCH_CAP_TAA_NO;
1125 else if (data & ARCH_CAP_TSX_CTRL_MSR)
1126 data &= ~ARCH_CAP_MDS_NO;
1128 /* KVM does not emulate MSR_IA32_TSX_CTRL. */
1129 data &= ~ARCH_CAP_TSX_CTRL_MSR;
1133 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1135 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1137 switch (msr->index) {
1138 case MSR_IA32_ARCH_CAPABILITIES:
1139 msr->data = kvm_get_arch_capabilities();
1141 case MSR_IA32_UCODE_REV:
1142 rdmsrl_safe(msr->index, &msr->data);
1145 if (kvm_x86_ops->get_msr_feature(msr))
1151 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1153 struct kvm_msr_entry msr;
1157 r = kvm_get_msr_feature(&msr);
1166 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1168 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1171 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1177 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1179 if (efer & efer_reserved_bits)
1182 return __kvm_valid_efer(vcpu, efer);
1184 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1186 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1188 u64 old_efer = vcpu->arch.efer;
1189 u64 efer = msr_info->data;
1191 if (efer & efer_reserved_bits)
1194 if (!msr_info->host_initiated) {
1195 if (!__kvm_valid_efer(vcpu, efer))
1198 if (is_paging(vcpu) &&
1199 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1204 efer |= vcpu->arch.efer & EFER_LMA;
1206 kvm_x86_ops->set_efer(vcpu, efer);
1208 /* Update reserved bits */
1209 if ((efer ^ old_efer) & EFER_NX)
1210 kvm_mmu_reset_context(vcpu);
1215 void kvm_enable_efer_bits(u64 mask)
1217 efer_reserved_bits &= ~mask;
1219 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1222 * Writes msr value into into the appropriate "register".
1223 * Returns 0 on success, non-0 otherwise.
1224 * Assumes vcpu_load() was already called.
1226 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1228 switch (msr->index) {
1231 case MSR_KERNEL_GS_BASE:
1234 if (is_noncanonical_address(msr->data, vcpu))
1237 case MSR_IA32_SYSENTER_EIP:
1238 case MSR_IA32_SYSENTER_ESP:
1240 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1241 * non-canonical address is written on Intel but not on
1242 * AMD (which ignores the top 32-bits, because it does
1243 * not implement 64-bit SYSENTER).
1245 * 64-bit code should hence be able to write a non-canonical
1246 * value on AMD. Making the address canonical ensures that
1247 * vmentry does not fail on Intel after writing a non-canonical
1248 * value, and that something deterministic happens if the guest
1249 * invokes 64-bit SYSENTER.
1251 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1253 return kvm_x86_ops->set_msr(vcpu, msr);
1255 EXPORT_SYMBOL_GPL(kvm_set_msr);
1258 * Adapt set_msr() to msr_io()'s calling convention
1260 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1262 struct msr_data msr;
1266 msr.host_initiated = true;
1267 r = kvm_get_msr(vcpu, &msr);
1275 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1277 struct msr_data msr;
1281 msr.host_initiated = true;
1282 return kvm_set_msr(vcpu, &msr);
1285 #ifdef CONFIG_X86_64
1286 struct pvclock_gtod_data {
1289 struct { /* extract of a clocksource struct */
1302 static struct pvclock_gtod_data pvclock_gtod_data;
1304 static void update_pvclock_gtod(struct timekeeper *tk)
1306 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1309 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1311 write_seqcount_begin(&vdata->seq);
1313 /* copy pvclock gtod data */
1314 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1315 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1316 vdata->clock.mask = tk->tkr_mono.mask;
1317 vdata->clock.mult = tk->tkr_mono.mult;
1318 vdata->clock.shift = tk->tkr_mono.shift;
1320 vdata->boot_ns = boot_ns;
1321 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1323 vdata->wall_time_sec = tk->xtime_sec;
1325 write_seqcount_end(&vdata->seq);
1329 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1332 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1333 * vcpu_enter_guest. This function is only called from
1334 * the physical CPU that is running vcpu.
1336 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1339 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1343 struct pvclock_wall_clock wc;
1344 struct timespec64 boot;
1349 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1354 ++version; /* first time write, random junk */
1358 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1362 * The guest calculates current wall clock time by adding
1363 * system time (updated by kvm_guest_time_update below) to the
1364 * wall clock specified here. guest system time equals host
1365 * system time for us, thus we must fill in host boot time here.
1367 getboottime64(&boot);
1369 if (kvm->arch.kvmclock_offset) {
1370 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1371 boot = timespec64_sub(boot, ts);
1373 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1374 wc.nsec = boot.tv_nsec;
1375 wc.version = version;
1377 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1380 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1383 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1385 do_shl32_div32(dividend, divisor);
1389 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1390 s8 *pshift, u32 *pmultiplier)
1398 scaled64 = scaled_hz;
1399 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1404 tps32 = (uint32_t)tps64;
1405 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1406 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1414 *pmultiplier = div_frac(scaled64, tps32);
1416 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1417 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1420 #ifdef CONFIG_X86_64
1421 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1424 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1425 static unsigned long max_tsc_khz;
1427 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1429 u64 v = (u64)khz * (1000000 + ppm);
1434 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1438 /* Guest TSC same frequency as host TSC? */
1440 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1444 /* TSC scaling supported? */
1445 if (!kvm_has_tsc_control) {
1446 if (user_tsc_khz > tsc_khz) {
1447 vcpu->arch.tsc_catchup = 1;
1448 vcpu->arch.tsc_always_catchup = 1;
1451 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1456 /* TSC scaling required - calculate ratio */
1457 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1458 user_tsc_khz, tsc_khz);
1460 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1461 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1466 vcpu->arch.tsc_scaling_ratio = ratio;
1470 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1472 u32 thresh_lo, thresh_hi;
1473 int use_scaling = 0;
1475 /* tsc_khz can be zero if TSC calibration fails */
1476 if (user_tsc_khz == 0) {
1477 /* set tsc_scaling_ratio to a safe value */
1478 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1482 /* Compute a scale to convert nanoseconds in TSC cycles */
1483 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1484 &vcpu->arch.virtual_tsc_shift,
1485 &vcpu->arch.virtual_tsc_mult);
1486 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1489 * Compute the variation in TSC rate which is acceptable
1490 * within the range of tolerance and decide if the
1491 * rate being applied is within that bounds of the hardware
1492 * rate. If so, no scaling or compensation need be done.
1494 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1495 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1496 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1497 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1500 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1503 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1505 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1506 vcpu->arch.virtual_tsc_mult,
1507 vcpu->arch.virtual_tsc_shift);
1508 tsc += vcpu->arch.this_tsc_write;
1512 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1514 #ifdef CONFIG_X86_64
1516 struct kvm_arch *ka = &vcpu->kvm->arch;
1517 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1519 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1520 atomic_read(&vcpu->kvm->online_vcpus));
1523 * Once the masterclock is enabled, always perform request in
1524 * order to update it.
1526 * In order to enable masterclock, the host clocksource must be TSC
1527 * and the vcpus need to have matched TSCs. When that happens,
1528 * perform request to enable masterclock.
1530 if (ka->use_master_clock ||
1531 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1532 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1534 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1535 atomic_read(&vcpu->kvm->online_vcpus),
1536 ka->use_master_clock, gtod->clock.vclock_mode);
1540 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1542 u64 curr_offset = vcpu->arch.tsc_offset;
1543 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1547 * Multiply tsc by a fixed point number represented by ratio.
1549 * The most significant 64-N bits (mult) of ratio represent the
1550 * integral part of the fixed point number; the remaining N bits
1551 * (frac) represent the fractional part, ie. ratio represents a fixed
1552 * point number (mult + frac * 2^(-N)).
1554 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1556 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1558 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1561 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1564 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1566 if (ratio != kvm_default_tsc_scaling_ratio)
1567 _tsc = __scale_tsc(ratio, tsc);
1571 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1573 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1577 tsc = kvm_scale_tsc(vcpu, rdtsc());
1579 return target_tsc - tsc;
1582 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1584 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1586 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1588 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1590 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1591 vcpu->arch.tsc_offset = offset;
1594 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1596 struct kvm *kvm = vcpu->kvm;
1597 u64 offset, ns, elapsed;
1598 unsigned long flags;
1600 bool already_matched;
1601 u64 data = msr->data;
1602 bool synchronizing = false;
1604 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1605 offset = kvm_compute_tsc_offset(vcpu, data);
1606 ns = ktime_get_boot_ns();
1607 elapsed = ns - kvm->arch.last_tsc_nsec;
1609 if (vcpu->arch.virtual_tsc_khz) {
1610 if (data == 0 && msr->host_initiated) {
1612 * detection of vcpu initialization -- need to sync
1613 * with other vCPUs. This particularly helps to keep
1614 * kvm_clock stable after CPU hotplug
1616 synchronizing = true;
1618 u64 tsc_exp = kvm->arch.last_tsc_write +
1619 nsec_to_cycles(vcpu, elapsed);
1620 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1622 * Special case: TSC write with a small delta (1 second)
1623 * of virtual cycle time against real time is
1624 * interpreted as an attempt to synchronize the CPU.
1626 synchronizing = data < tsc_exp + tsc_hz &&
1627 data + tsc_hz > tsc_exp;
1632 * For a reliable TSC, we can match TSC offsets, and for an unstable
1633 * TSC, we add elapsed time in this computation. We could let the
1634 * compensation code attempt to catch up if we fall behind, but
1635 * it's better to try to match offsets from the beginning.
1637 if (synchronizing &&
1638 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1639 if (!check_tsc_unstable()) {
1640 offset = kvm->arch.cur_tsc_offset;
1641 pr_debug("kvm: matched tsc offset for %llu\n", data);
1643 u64 delta = nsec_to_cycles(vcpu, elapsed);
1645 offset = kvm_compute_tsc_offset(vcpu, data);
1646 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1649 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1652 * We split periods of matched TSC writes into generations.
1653 * For each generation, we track the original measured
1654 * nanosecond time, offset, and write, so if TSCs are in
1655 * sync, we can match exact offset, and if not, we can match
1656 * exact software computation in compute_guest_tsc()
1658 * These values are tracked in kvm->arch.cur_xxx variables.
1660 kvm->arch.cur_tsc_generation++;
1661 kvm->arch.cur_tsc_nsec = ns;
1662 kvm->arch.cur_tsc_write = data;
1663 kvm->arch.cur_tsc_offset = offset;
1665 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1666 kvm->arch.cur_tsc_generation, data);
1670 * We also track th most recent recorded KHZ, write and time to
1671 * allow the matching interval to be extended at each write.
1673 kvm->arch.last_tsc_nsec = ns;
1674 kvm->arch.last_tsc_write = data;
1675 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1677 vcpu->arch.last_guest_tsc = data;
1679 /* Keep track of which generation this VCPU has synchronized to */
1680 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1681 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1682 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1684 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1685 update_ia32_tsc_adjust_msr(vcpu, offset);
1687 kvm_vcpu_write_tsc_offset(vcpu, offset);
1688 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1690 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1692 kvm->arch.nr_vcpus_matched_tsc = 0;
1693 } else if (!already_matched) {
1694 kvm->arch.nr_vcpus_matched_tsc++;
1697 kvm_track_tsc_matching(vcpu);
1698 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1701 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1703 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1706 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1709 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1711 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1712 WARN_ON(adjustment < 0);
1713 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1714 adjust_tsc_offset_guest(vcpu, adjustment);
1717 #ifdef CONFIG_X86_64
1719 static u64 read_tsc(void)
1721 u64 ret = (u64)rdtsc_ordered();
1722 u64 last = pvclock_gtod_data.clock.cycle_last;
1724 if (likely(ret >= last))
1728 * GCC likes to generate cmov here, but this branch is extremely
1729 * predictable (it's just a function of time and the likely is
1730 * very likely) and there's a data dependence, so force GCC
1731 * to generate a branch instead. I don't barrier() because
1732 * we don't actually need a barrier, and if this function
1733 * ever gets inlined it will generate worse code.
1739 static inline u64 vgettsc(u64 *cycle_now)
1742 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1744 *cycle_now = read_tsc();
1746 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1747 return v * gtod->clock.mult;
1750 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1752 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1758 seq = read_seqcount_begin(>od->seq);
1759 mode = gtod->clock.vclock_mode;
1760 ns = gtod->nsec_base;
1761 ns += vgettsc(cycle_now);
1762 ns >>= gtod->clock.shift;
1763 ns += gtod->boot_ns;
1764 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1770 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1772 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1778 seq = read_seqcount_begin(>od->seq);
1779 mode = gtod->clock.vclock_mode;
1780 ts->tv_sec = gtod->wall_time_sec;
1781 ns = gtod->nsec_base;
1782 ns += vgettsc(cycle_now);
1783 ns >>= gtod->clock.shift;
1784 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1786 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1792 /* returns true if host is using tsc clocksource */
1793 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1795 /* checked again under seqlock below */
1796 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1799 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1802 /* returns true if host is using tsc clocksource */
1803 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1806 /* checked again under seqlock below */
1807 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1810 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1816 * Assuming a stable TSC across physical CPUS, and a stable TSC
1817 * across virtual CPUs, the following condition is possible.
1818 * Each numbered line represents an event visible to both
1819 * CPUs at the next numbered event.
1821 * "timespecX" represents host monotonic time. "tscX" represents
1824 * VCPU0 on CPU0 | VCPU1 on CPU1
1826 * 1. read timespec0,tsc0
1827 * 2. | timespec1 = timespec0 + N
1829 * 3. transition to guest | transition to guest
1830 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1831 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1832 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1834 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1837 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1839 * - 0 < N - M => M < N
1841 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1842 * always the case (the difference between two distinct xtime instances
1843 * might be smaller then the difference between corresponding TSC reads,
1844 * when updating guest vcpus pvclock areas).
1846 * To avoid that problem, do not allow visibility of distinct
1847 * system_timestamp/tsc_timestamp values simultaneously: use a master
1848 * copy of host monotonic time values. Update that master copy
1851 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1855 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1857 #ifdef CONFIG_X86_64
1858 struct kvm_arch *ka = &kvm->arch;
1860 bool host_tsc_clocksource, vcpus_matched;
1862 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1863 atomic_read(&kvm->online_vcpus));
1866 * If the host uses TSC clock, then passthrough TSC as stable
1869 host_tsc_clocksource = kvm_get_time_and_clockread(
1870 &ka->master_kernel_ns,
1871 &ka->master_cycle_now);
1873 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1874 && !ka->backwards_tsc_observed
1875 && !ka->boot_vcpu_runs_old_kvmclock;
1877 if (ka->use_master_clock)
1878 atomic_set(&kvm_guest_has_master_clock, 1);
1880 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1881 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1886 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1888 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1891 static void kvm_gen_update_masterclock(struct kvm *kvm)
1893 #ifdef CONFIG_X86_64
1895 struct kvm_vcpu *vcpu;
1896 struct kvm_arch *ka = &kvm->arch;
1898 spin_lock(&ka->pvclock_gtod_sync_lock);
1899 kvm_make_mclock_inprogress_request(kvm);
1900 /* no guest entries from this point */
1901 pvclock_update_vm_gtod_copy(kvm);
1903 kvm_for_each_vcpu(i, vcpu, kvm)
1904 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1906 /* guest entries allowed */
1907 kvm_for_each_vcpu(i, vcpu, kvm)
1908 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1910 spin_unlock(&ka->pvclock_gtod_sync_lock);
1914 u64 get_kvmclock_ns(struct kvm *kvm)
1916 struct kvm_arch *ka = &kvm->arch;
1917 struct pvclock_vcpu_time_info hv_clock;
1920 spin_lock(&ka->pvclock_gtod_sync_lock);
1921 if (!ka->use_master_clock) {
1922 spin_unlock(&ka->pvclock_gtod_sync_lock);
1923 return ktime_get_boot_ns() + ka->kvmclock_offset;
1926 hv_clock.tsc_timestamp = ka->master_cycle_now;
1927 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1928 spin_unlock(&ka->pvclock_gtod_sync_lock);
1930 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1933 if (__this_cpu_read(cpu_tsc_khz)) {
1934 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1935 &hv_clock.tsc_shift,
1936 &hv_clock.tsc_to_system_mul);
1937 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1939 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1946 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1948 struct kvm_vcpu_arch *vcpu = &v->arch;
1949 struct pvclock_vcpu_time_info guest_hv_clock;
1951 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1952 &guest_hv_clock, sizeof(guest_hv_clock))))
1955 /* This VCPU is paused, but it's legal for a guest to read another
1956 * VCPU's kvmclock, so we really have to follow the specification where
1957 * it says that version is odd if data is being modified, and even after
1960 * Version field updates must be kept separate. This is because
1961 * kvm_write_guest_cached might use a "rep movs" instruction, and
1962 * writes within a string instruction are weakly ordered. So there
1963 * are three writes overall.
1965 * As a small optimization, only write the version field in the first
1966 * and third write. The vcpu->pv_time cache is still valid, because the
1967 * version field is the first in the struct.
1969 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1971 if (guest_hv_clock.version & 1)
1972 ++guest_hv_clock.version; /* first time write, random junk */
1974 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1975 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1977 sizeof(vcpu->hv_clock.version));
1981 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1982 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1984 if (vcpu->pvclock_set_guest_stopped_request) {
1985 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1986 vcpu->pvclock_set_guest_stopped_request = false;
1989 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1991 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1993 sizeof(vcpu->hv_clock));
1997 vcpu->hv_clock.version++;
1998 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2000 sizeof(vcpu->hv_clock.version));
2003 static int kvm_guest_time_update(struct kvm_vcpu *v)
2005 unsigned long flags, tgt_tsc_khz;
2006 struct kvm_vcpu_arch *vcpu = &v->arch;
2007 struct kvm_arch *ka = &v->kvm->arch;
2009 u64 tsc_timestamp, host_tsc;
2011 bool use_master_clock;
2017 * If the host uses TSC clock, then passthrough TSC as stable
2020 spin_lock(&ka->pvclock_gtod_sync_lock);
2021 use_master_clock = ka->use_master_clock;
2022 if (use_master_clock) {
2023 host_tsc = ka->master_cycle_now;
2024 kernel_ns = ka->master_kernel_ns;
2026 spin_unlock(&ka->pvclock_gtod_sync_lock);
2028 /* Keep irq disabled to prevent changes to the clock */
2029 local_irq_save(flags);
2030 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2031 if (unlikely(tgt_tsc_khz == 0)) {
2032 local_irq_restore(flags);
2033 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2036 if (!use_master_clock) {
2038 kernel_ns = ktime_get_boot_ns();
2041 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2044 * We may have to catch up the TSC to match elapsed wall clock
2045 * time for two reasons, even if kvmclock is used.
2046 * 1) CPU could have been running below the maximum TSC rate
2047 * 2) Broken TSC compensation resets the base at each VCPU
2048 * entry to avoid unknown leaps of TSC even when running
2049 * again on the same CPU. This may cause apparent elapsed
2050 * time to disappear, and the guest to stand still or run
2053 if (vcpu->tsc_catchup) {
2054 u64 tsc = compute_guest_tsc(v, kernel_ns);
2055 if (tsc > tsc_timestamp) {
2056 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2057 tsc_timestamp = tsc;
2061 local_irq_restore(flags);
2063 /* With all the info we got, fill in the values */
2065 if (kvm_has_tsc_control)
2066 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2068 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2069 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2070 &vcpu->hv_clock.tsc_shift,
2071 &vcpu->hv_clock.tsc_to_system_mul);
2072 vcpu->hw_tsc_khz = tgt_tsc_khz;
2075 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2076 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2077 vcpu->last_guest_tsc = tsc_timestamp;
2079 /* If the host uses TSC clocksource, then it is stable */
2081 if (use_master_clock)
2082 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2084 vcpu->hv_clock.flags = pvclock_flags;
2086 if (vcpu->pv_time_enabled)
2087 kvm_setup_pvclock_page(v);
2088 if (v == kvm_get_vcpu(v->kvm, 0))
2089 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2094 * kvmclock updates which are isolated to a given vcpu, such as
2095 * vcpu->cpu migration, should not allow system_timestamp from
2096 * the rest of the vcpus to remain static. Otherwise ntp frequency
2097 * correction applies to one vcpu's system_timestamp but not
2100 * So in those cases, request a kvmclock update for all vcpus.
2101 * We need to rate-limit these requests though, as they can
2102 * considerably slow guests that have a large number of vcpus.
2103 * The time for a remote vcpu to update its kvmclock is bound
2104 * by the delay we use to rate-limit the updates.
2107 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2109 static void kvmclock_update_fn(struct work_struct *work)
2112 struct delayed_work *dwork = to_delayed_work(work);
2113 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2114 kvmclock_update_work);
2115 struct kvm *kvm = container_of(ka, struct kvm, arch);
2116 struct kvm_vcpu *vcpu;
2118 kvm_for_each_vcpu(i, vcpu, kvm) {
2119 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2120 kvm_vcpu_kick(vcpu);
2124 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2126 struct kvm *kvm = v->kvm;
2128 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2129 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2130 KVMCLOCK_UPDATE_DELAY);
2133 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2135 static void kvmclock_sync_fn(struct work_struct *work)
2137 struct delayed_work *dwork = to_delayed_work(work);
2138 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2139 kvmclock_sync_work);
2140 struct kvm *kvm = container_of(ka, struct kvm, arch);
2142 if (!kvmclock_periodic_sync)
2145 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2146 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2147 KVMCLOCK_SYNC_PERIOD);
2150 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2152 u64 mcg_cap = vcpu->arch.mcg_cap;
2153 unsigned bank_num = mcg_cap & 0xff;
2156 case MSR_IA32_MCG_STATUS:
2157 vcpu->arch.mcg_status = data;
2159 case MSR_IA32_MCG_CTL:
2160 if (!(mcg_cap & MCG_CTL_P))
2162 if (data != 0 && data != ~(u64)0)
2164 vcpu->arch.mcg_ctl = data;
2167 if (msr >= MSR_IA32_MC0_CTL &&
2168 msr < MSR_IA32_MCx_CTL(bank_num)) {
2169 u32 offset = array_index_nospec(
2170 msr - MSR_IA32_MC0_CTL,
2171 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2173 /* only 0 or all 1s can be written to IA32_MCi_CTL
2174 * some Linux kernels though clear bit 10 in bank 4 to
2175 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2176 * this to avoid an uncatched #GP in the guest
2178 if ((offset & 0x3) == 0 &&
2179 data != 0 && (data | (1 << 10)) != ~(u64)0)
2181 vcpu->arch.mce_banks[offset] = data;
2189 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2191 struct kvm *kvm = vcpu->kvm;
2192 int lm = is_long_mode(vcpu);
2193 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2194 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2195 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2196 : kvm->arch.xen_hvm_config.blob_size_32;
2197 u32 page_num = data & ~PAGE_MASK;
2198 u64 page_addr = data & PAGE_MASK;
2203 if (page_num >= blob_size)
2206 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2211 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2220 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2222 gpa_t gpa = data & ~0x3f;
2224 /* Bits 3:5 are reserved, Should be zero */
2228 vcpu->arch.apf.msr_val = data;
2230 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2231 kvm_clear_async_pf_completion_queue(vcpu);
2232 kvm_async_pf_hash_reset(vcpu);
2236 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2240 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2241 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2242 kvm_async_pf_wakeup_all(vcpu);
2246 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2248 vcpu->arch.pv_time_enabled = false;
2251 static void record_steal_time(struct kvm_vcpu *vcpu)
2253 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2256 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2257 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2260 vcpu->arch.st.steal.preempted = 0;
2262 if (vcpu->arch.st.steal.version & 1)
2263 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2265 vcpu->arch.st.steal.version += 1;
2267 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2268 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2272 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2273 vcpu->arch.st.last_steal;
2274 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2276 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2277 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2281 vcpu->arch.st.steal.version += 1;
2283 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2284 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2287 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2290 u32 msr = msr_info->index;
2291 u64 data = msr_info->data;
2294 case MSR_AMD64_NB_CFG:
2295 case MSR_IA32_UCODE_WRITE:
2296 case MSR_VM_HSAVE_PA:
2297 case MSR_AMD64_PATCH_LOADER:
2298 case MSR_AMD64_BU_CFG2:
2299 case MSR_AMD64_DC_CFG:
2300 case MSR_F15H_EX_CFG:
2303 case MSR_IA32_UCODE_REV:
2304 if (msr_info->host_initiated)
2305 vcpu->arch.microcode_version = data;
2307 case MSR_IA32_ARCH_CAPABILITIES:
2308 if (!msr_info->host_initiated)
2310 vcpu->arch.arch_capabilities = data;
2313 return set_efer(vcpu, msr_info);
2315 data &= ~(u64)0x40; /* ignore flush filter disable */
2316 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2317 data &= ~(u64)0x8; /* ignore TLB cache disable */
2318 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2320 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2325 case MSR_FAM10H_MMIO_CONF_BASE:
2327 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2332 case MSR_IA32_DEBUGCTLMSR:
2334 /* We support the non-activated case already */
2336 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2337 /* Values other than LBR and BTF are vendor-specific,
2338 thus reserved and should throw a #GP */
2341 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2344 case 0x200 ... 0x2ff:
2345 return kvm_mtrr_set_msr(vcpu, msr, data);
2346 case MSR_IA32_APICBASE:
2347 return kvm_set_apic_base(vcpu, msr_info);
2348 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
2349 return kvm_x2apic_msr_write(vcpu, msr, data);
2350 case MSR_IA32_TSCDEADLINE:
2351 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2353 case MSR_IA32_TSC_ADJUST:
2354 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2355 if (!msr_info->host_initiated) {
2356 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2357 adjust_tsc_offset_guest(vcpu, adj);
2358 /* Before back to guest, tsc_timestamp must be adjusted
2359 * as well, otherwise guest's percpu pvclock time could jump.
2361 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2363 vcpu->arch.ia32_tsc_adjust_msr = data;
2366 case MSR_IA32_MISC_ENABLE:
2367 vcpu->arch.ia32_misc_enable_msr = data;
2369 case MSR_IA32_SMBASE:
2370 if (!msr_info->host_initiated)
2372 vcpu->arch.smbase = data;
2374 case MSR_KVM_WALL_CLOCK_NEW:
2375 case MSR_KVM_WALL_CLOCK:
2376 vcpu->kvm->arch.wall_clock = data;
2377 kvm_write_wall_clock(vcpu->kvm, data);
2379 case MSR_KVM_SYSTEM_TIME_NEW:
2380 case MSR_KVM_SYSTEM_TIME: {
2381 struct kvm_arch *ka = &vcpu->kvm->arch;
2383 kvmclock_reset(vcpu);
2385 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2386 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2388 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2389 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2391 ka->boot_vcpu_runs_old_kvmclock = tmp;
2394 vcpu->arch.time = data;
2395 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2397 /* we verify if the enable bit is set... */
2401 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2402 &vcpu->arch.pv_time, data & ~1ULL,
2403 sizeof(struct pvclock_vcpu_time_info)))
2404 vcpu->arch.pv_time_enabled = false;
2406 vcpu->arch.pv_time_enabled = true;
2410 case MSR_KVM_ASYNC_PF_EN:
2411 if (kvm_pv_enable_async_pf(vcpu, data))
2414 case MSR_KVM_STEAL_TIME:
2416 if (unlikely(!sched_info_on()))
2419 if (data & KVM_STEAL_RESERVED_MASK)
2422 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2423 data & KVM_STEAL_VALID_BITS,
2424 sizeof(struct kvm_steal_time)))
2427 vcpu->arch.st.msr_val = data;
2429 if (!(data & KVM_MSR_ENABLED))
2432 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2435 case MSR_KVM_PV_EOI_EN:
2436 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2440 case MSR_IA32_MCG_CTL:
2441 case MSR_IA32_MCG_STATUS:
2442 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2443 return set_msr_mce(vcpu, msr, data);
2445 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2446 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2447 pr = true; /* fall through */
2448 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2449 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2450 if (kvm_pmu_is_valid_msr(vcpu, msr))
2451 return kvm_pmu_set_msr(vcpu, msr_info);
2453 if (pr || data != 0)
2454 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2455 "0x%x data 0x%llx\n", msr, data);
2457 case MSR_K7_CLK_CTL:
2459 * Ignore all writes to this no longer documented MSR.
2460 * Writes are only relevant for old K7 processors,
2461 * all pre-dating SVM, but a recommended workaround from
2462 * AMD for these chips. It is possible to specify the
2463 * affected processor models on the command line, hence
2464 * the need to ignore the workaround.
2467 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2468 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2469 case HV_X64_MSR_CRASH_CTL:
2470 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2471 return kvm_hv_set_msr_common(vcpu, msr, data,
2472 msr_info->host_initiated);
2473 case MSR_IA32_BBL_CR_CTL3:
2474 /* Drop writes to this legacy MSR -- see rdmsr
2475 * counterpart for further detail.
2477 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2479 case MSR_AMD64_OSVW_ID_LENGTH:
2480 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2482 vcpu->arch.osvw.length = data;
2484 case MSR_AMD64_OSVW_STATUS:
2485 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2487 vcpu->arch.osvw.status = data;
2489 case MSR_PLATFORM_INFO:
2490 if (!msr_info->host_initiated ||
2491 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2492 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2493 cpuid_fault_enabled(vcpu)))
2495 vcpu->arch.msr_platform_info = data;
2497 case MSR_MISC_FEATURES_ENABLES:
2498 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2499 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2500 !supports_cpuid_fault(vcpu)))
2502 vcpu->arch.msr_misc_features_enables = data;
2505 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2506 return xen_hvm_config(vcpu, data);
2507 if (kvm_pmu_is_valid_msr(vcpu, msr))
2508 return kvm_pmu_set_msr(vcpu, msr_info);
2510 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2514 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2521 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2525 * Reads an msr value (of 'msr_index') into 'pdata'.
2526 * Returns 0 on success, non-0 otherwise.
2527 * Assumes vcpu_load() was already called.
2529 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2531 return kvm_x86_ops->get_msr(vcpu, msr);
2533 EXPORT_SYMBOL_GPL(kvm_get_msr);
2535 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2538 u64 mcg_cap = vcpu->arch.mcg_cap;
2539 unsigned bank_num = mcg_cap & 0xff;
2542 case MSR_IA32_P5_MC_ADDR:
2543 case MSR_IA32_P5_MC_TYPE:
2546 case MSR_IA32_MCG_CAP:
2547 data = vcpu->arch.mcg_cap;
2549 case MSR_IA32_MCG_CTL:
2550 if (!(mcg_cap & MCG_CTL_P))
2552 data = vcpu->arch.mcg_ctl;
2554 case MSR_IA32_MCG_STATUS:
2555 data = vcpu->arch.mcg_status;
2558 if (msr >= MSR_IA32_MC0_CTL &&
2559 msr < MSR_IA32_MCx_CTL(bank_num)) {
2560 u32 offset = array_index_nospec(
2561 msr - MSR_IA32_MC0_CTL,
2562 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2564 data = vcpu->arch.mce_banks[offset];
2573 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2575 switch (msr_info->index) {
2576 case MSR_IA32_PLATFORM_ID:
2577 case MSR_IA32_EBL_CR_POWERON:
2578 case MSR_IA32_DEBUGCTLMSR:
2579 case MSR_IA32_LASTBRANCHFROMIP:
2580 case MSR_IA32_LASTBRANCHTOIP:
2581 case MSR_IA32_LASTINTFROMIP:
2582 case MSR_IA32_LASTINTTOIP:
2584 case MSR_K8_TSEG_ADDR:
2585 case MSR_K8_TSEG_MASK:
2587 case MSR_VM_HSAVE_PA:
2588 case MSR_K8_INT_PENDING_MSG:
2589 case MSR_AMD64_NB_CFG:
2590 case MSR_FAM10H_MMIO_CONF_BASE:
2591 case MSR_AMD64_BU_CFG2:
2592 case MSR_IA32_PERF_CTL:
2593 case MSR_AMD64_DC_CFG:
2594 case MSR_F15H_EX_CFG:
2597 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2598 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2599 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2600 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2601 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2602 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2605 case MSR_IA32_UCODE_REV:
2606 msr_info->data = vcpu->arch.microcode_version;
2608 case MSR_IA32_ARCH_CAPABILITIES:
2609 if (!msr_info->host_initiated &&
2610 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2612 msr_info->data = vcpu->arch.arch_capabilities;
2615 case 0x200 ... 0x2ff:
2616 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2617 case 0xcd: /* fsb frequency */
2621 * MSR_EBC_FREQUENCY_ID
2622 * Conservative value valid for even the basic CPU models.
2623 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2624 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2625 * and 266MHz for model 3, or 4. Set Core Clock
2626 * Frequency to System Bus Frequency Ratio to 1 (bits
2627 * 31:24) even though these are only valid for CPU
2628 * models > 2, however guests may end up dividing or
2629 * multiplying by zero otherwise.
2631 case MSR_EBC_FREQUENCY_ID:
2632 msr_info->data = 1 << 24;
2634 case MSR_IA32_APICBASE:
2635 msr_info->data = kvm_get_apic_base(vcpu);
2637 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
2638 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2640 case MSR_IA32_TSCDEADLINE:
2641 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2643 case MSR_IA32_TSC_ADJUST:
2644 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2646 case MSR_IA32_MISC_ENABLE:
2647 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2649 case MSR_IA32_SMBASE:
2650 if (!msr_info->host_initiated)
2652 msr_info->data = vcpu->arch.smbase;
2654 case MSR_IA32_PERF_STATUS:
2655 /* TSC increment by tick */
2656 msr_info->data = 1000ULL;
2657 /* CPU multiplier */
2658 msr_info->data |= (((uint64_t)4ULL) << 40);
2661 msr_info->data = vcpu->arch.efer;
2663 case MSR_KVM_WALL_CLOCK:
2664 case MSR_KVM_WALL_CLOCK_NEW:
2665 msr_info->data = vcpu->kvm->arch.wall_clock;
2667 case MSR_KVM_SYSTEM_TIME:
2668 case MSR_KVM_SYSTEM_TIME_NEW:
2669 msr_info->data = vcpu->arch.time;
2671 case MSR_KVM_ASYNC_PF_EN:
2672 msr_info->data = vcpu->arch.apf.msr_val;
2674 case MSR_KVM_STEAL_TIME:
2675 msr_info->data = vcpu->arch.st.msr_val;
2677 case MSR_KVM_PV_EOI_EN:
2678 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2680 case MSR_IA32_P5_MC_ADDR:
2681 case MSR_IA32_P5_MC_TYPE:
2682 case MSR_IA32_MCG_CAP:
2683 case MSR_IA32_MCG_CTL:
2684 case MSR_IA32_MCG_STATUS:
2685 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2686 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2687 case MSR_K7_CLK_CTL:
2689 * Provide expected ramp-up count for K7. All other
2690 * are set to zero, indicating minimum divisors for
2693 * This prevents guest kernels on AMD host with CPU
2694 * type 6, model 8 and higher from exploding due to
2695 * the rdmsr failing.
2697 msr_info->data = 0x20000000;
2699 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2700 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2701 case HV_X64_MSR_CRASH_CTL:
2702 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2703 return kvm_hv_get_msr_common(vcpu,
2704 msr_info->index, &msr_info->data);
2706 case MSR_IA32_BBL_CR_CTL3:
2707 /* This legacy MSR exists but isn't fully documented in current
2708 * silicon. It is however accessed by winxp in very narrow
2709 * scenarios where it sets bit #19, itself documented as
2710 * a "reserved" bit. Best effort attempt to source coherent
2711 * read data here should the balance of the register be
2712 * interpreted by the guest:
2714 * L2 cache control register 3: 64GB range, 256KB size,
2715 * enabled, latency 0x1, configured
2717 msr_info->data = 0xbe702111;
2719 case MSR_AMD64_OSVW_ID_LENGTH:
2720 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2722 msr_info->data = vcpu->arch.osvw.length;
2724 case MSR_AMD64_OSVW_STATUS:
2725 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2727 msr_info->data = vcpu->arch.osvw.status;
2729 case MSR_PLATFORM_INFO:
2730 msr_info->data = vcpu->arch.msr_platform_info;
2732 case MSR_MISC_FEATURES_ENABLES:
2733 msr_info->data = vcpu->arch.msr_misc_features_enables;
2736 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2737 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2739 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2743 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2750 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2753 * Read or write a bunch of msrs. All parameters are kernel addresses.
2755 * @return number of msrs set successfully.
2757 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2758 struct kvm_msr_entry *entries,
2759 int (*do_msr)(struct kvm_vcpu *vcpu,
2760 unsigned index, u64 *data))
2764 for (i = 0; i < msrs->nmsrs; ++i)
2765 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2772 * Read or write a bunch of msrs. Parameters are user addresses.
2774 * @return number of msrs set successfully.
2776 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2777 int (*do_msr)(struct kvm_vcpu *vcpu,
2778 unsigned index, u64 *data),
2781 struct kvm_msrs msrs;
2782 struct kvm_msr_entry *entries;
2787 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2791 if (msrs.nmsrs >= MAX_IO_MSRS)
2794 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2795 entries = memdup_user(user_msrs->entries, size);
2796 if (IS_ERR(entries)) {
2797 r = PTR_ERR(entries);
2801 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2806 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2817 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2822 case KVM_CAP_IRQCHIP:
2824 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2825 case KVM_CAP_SET_TSS_ADDR:
2826 case KVM_CAP_EXT_CPUID:
2827 case KVM_CAP_EXT_EMUL_CPUID:
2828 case KVM_CAP_CLOCKSOURCE:
2830 case KVM_CAP_NOP_IO_DELAY:
2831 case KVM_CAP_MP_STATE:
2832 case KVM_CAP_SYNC_MMU:
2833 case KVM_CAP_USER_NMI:
2834 case KVM_CAP_REINJECT_CONTROL:
2835 case KVM_CAP_IRQ_INJECT_STATUS:
2836 case KVM_CAP_IOEVENTFD:
2837 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2839 case KVM_CAP_PIT_STATE2:
2840 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2841 case KVM_CAP_XEN_HVM:
2842 case KVM_CAP_VCPU_EVENTS:
2843 case KVM_CAP_HYPERV:
2844 case KVM_CAP_HYPERV_VAPIC:
2845 case KVM_CAP_HYPERV_SPIN:
2846 case KVM_CAP_HYPERV_SYNIC:
2847 case KVM_CAP_HYPERV_SYNIC2:
2848 case KVM_CAP_HYPERV_VP_INDEX:
2849 case KVM_CAP_PCI_SEGMENT:
2850 case KVM_CAP_DEBUGREGS:
2851 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2853 case KVM_CAP_ASYNC_PF:
2854 case KVM_CAP_GET_TSC_KHZ:
2855 case KVM_CAP_KVMCLOCK_CTRL:
2856 case KVM_CAP_READONLY_MEM:
2857 case KVM_CAP_HYPERV_TIME:
2858 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2859 case KVM_CAP_TSC_DEADLINE_TIMER:
2860 case KVM_CAP_ENABLE_CAP_VM:
2861 case KVM_CAP_DISABLE_QUIRKS:
2862 case KVM_CAP_SET_BOOT_CPU_ID:
2863 case KVM_CAP_SPLIT_IRQCHIP:
2864 case KVM_CAP_IMMEDIATE_EXIT:
2865 case KVM_CAP_GET_MSR_FEATURES:
2868 case KVM_CAP_ADJUST_CLOCK:
2869 r = KVM_CLOCK_TSC_STABLE;
2871 case KVM_CAP_X86_GUEST_MWAIT:
2872 r = kvm_mwait_in_guest();
2874 case KVM_CAP_X86_SMM:
2875 /* SMBASE is usually relocated above 1M on modern chipsets,
2876 * and SMM handlers might indeed rely on 4G segment limits,
2877 * so do not report SMM to be available if real mode is
2878 * emulated via vm86 mode. Still, do not go to great lengths
2879 * to avoid userspace's usage of the feature, because it is a
2880 * fringe case that is not enabled except via specific settings
2881 * of the module parameters.
2883 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2886 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2888 case KVM_CAP_NR_VCPUS:
2889 r = KVM_SOFT_MAX_VCPUS;
2891 case KVM_CAP_MAX_VCPUS:
2894 case KVM_CAP_MAX_VCPU_ID:
2895 r = KVM_MAX_VCPU_ID;
2897 case KVM_CAP_NR_MEMSLOTS:
2898 r = KVM_USER_MEM_SLOTS;
2900 case KVM_CAP_PV_MMU: /* obsolete */
2904 r = KVM_MAX_MCE_BANKS;
2907 r = boot_cpu_has(X86_FEATURE_XSAVE);
2909 case KVM_CAP_TSC_CONTROL:
2910 r = kvm_has_tsc_control;
2912 case KVM_CAP_X2APIC_API:
2913 r = KVM_X2APIC_API_VALID_FLAGS;
2923 long kvm_arch_dev_ioctl(struct file *filp,
2924 unsigned int ioctl, unsigned long arg)
2926 void __user *argp = (void __user *)arg;
2930 case KVM_GET_MSR_INDEX_LIST: {
2931 struct kvm_msr_list __user *user_msr_list = argp;
2932 struct kvm_msr_list msr_list;
2936 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2939 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2940 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2943 if (n < msr_list.nmsrs)
2946 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2947 num_msrs_to_save * sizeof(u32)))
2949 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2951 num_emulated_msrs * sizeof(u32)))
2956 case KVM_GET_SUPPORTED_CPUID:
2957 case KVM_GET_EMULATED_CPUID: {
2958 struct kvm_cpuid2 __user *cpuid_arg = argp;
2959 struct kvm_cpuid2 cpuid;
2962 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2965 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2971 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2976 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2978 if (copy_to_user(argp, &kvm_mce_cap_supported,
2979 sizeof(kvm_mce_cap_supported)))
2983 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2984 struct kvm_msr_list __user *user_msr_list = argp;
2985 struct kvm_msr_list msr_list;
2989 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2992 msr_list.nmsrs = num_msr_based_features;
2993 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2996 if (n < msr_list.nmsrs)
2999 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3000 num_msr_based_features * sizeof(u32)))
3006 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3016 static void wbinvd_ipi(void *garbage)
3021 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3023 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3026 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3028 /* Address WBINVD may be executed by guest */
3029 if (need_emulate_wbinvd(vcpu)) {
3030 if (kvm_x86_ops->has_wbinvd_exit())
3031 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3032 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3033 smp_call_function_single(vcpu->cpu,
3034 wbinvd_ipi, NULL, 1);
3037 kvm_x86_ops->vcpu_load(vcpu, cpu);
3039 /* Apply any externally detected TSC adjustments (due to suspend) */
3040 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3041 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3042 vcpu->arch.tsc_offset_adjustment = 0;
3043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3046 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
3047 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3048 rdtsc() - vcpu->arch.last_host_tsc;
3050 mark_tsc_unstable("KVM discovered backwards TSC");
3052 if (check_tsc_unstable()) {
3053 u64 offset = kvm_compute_tsc_offset(vcpu,
3054 vcpu->arch.last_guest_tsc);
3055 kvm_vcpu_write_tsc_offset(vcpu, offset);
3056 vcpu->arch.tsc_catchup = 1;
3059 if (kvm_lapic_hv_timer_in_use(vcpu))
3060 kvm_lapic_restart_hv_timer(vcpu);
3063 * On a host with synchronized TSC, there is no need to update
3064 * kvmclock on vcpu->cpu migration
3066 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3067 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3068 if (vcpu->cpu != cpu)
3069 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3073 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3076 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3078 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3081 if (vcpu->arch.st.steal.preempted)
3084 vcpu->arch.st.steal.preempted = 1;
3086 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3087 &vcpu->arch.st.steal.preempted,
3088 offsetof(struct kvm_steal_time, preempted),
3089 sizeof(vcpu->arch.st.steal.preempted));
3092 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3096 if (vcpu->preempted)
3097 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3100 * Disable page faults because we're in atomic context here.
3101 * kvm_write_guest_offset_cached() would call might_fault()
3102 * that relies on pagefault_disable() to tell if there's a
3103 * bug. NOTE: the write to guest memory may not go through if
3104 * during postcopy live migration or if there's heavy guest
3107 pagefault_disable();
3109 * kvm_memslots() will be called by
3110 * kvm_write_guest_offset_cached() so take the srcu lock.
3112 idx = srcu_read_lock(&vcpu->kvm->srcu);
3113 kvm_steal_time_set_preempted(vcpu);
3114 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3116 kvm_x86_ops->vcpu_put(vcpu);
3117 vcpu->arch.last_host_tsc = rdtsc();
3119 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3120 * on every vmexit, but if not, we might have a stale dr6 from the
3121 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3126 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3127 struct kvm_lapic_state *s)
3129 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
3130 kvm_x86_ops->sync_pir_to_irr(vcpu);
3132 return kvm_apic_get_state(vcpu, s);
3135 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3136 struct kvm_lapic_state *s)
3140 r = kvm_apic_set_state(vcpu, s);
3143 update_cr8_intercept(vcpu);
3148 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3150 return (!lapic_in_kernel(vcpu) ||
3151 kvm_apic_accept_pic_intr(vcpu));
3155 * if userspace requested an interrupt window, check that the
3156 * interrupt window is open.
3158 * No need to exit to userspace if we already have an interrupt queued.
3160 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3162 return kvm_arch_interrupt_allowed(vcpu) &&
3163 !kvm_cpu_has_interrupt(vcpu) &&
3164 !kvm_event_needs_reinjection(vcpu) &&
3165 kvm_cpu_accept_dm_intr(vcpu);
3168 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3169 struct kvm_interrupt *irq)
3171 if (irq->irq >= KVM_NR_INTERRUPTS)
3174 if (!irqchip_in_kernel(vcpu->kvm)) {
3175 kvm_queue_interrupt(vcpu, irq->irq, false);
3176 kvm_make_request(KVM_REQ_EVENT, vcpu);
3181 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3182 * fail for in-kernel 8259.
3184 if (pic_in_kernel(vcpu->kvm))
3187 if (vcpu->arch.pending_external_vector != -1)
3190 vcpu->arch.pending_external_vector = irq->irq;
3191 kvm_make_request(KVM_REQ_EVENT, vcpu);
3195 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3197 kvm_inject_nmi(vcpu);
3202 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3204 kvm_make_request(KVM_REQ_SMI, vcpu);
3209 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3210 struct kvm_tpr_access_ctl *tac)
3214 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3218 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3222 unsigned bank_num = mcg_cap & 0xff, bank;
3225 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
3227 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3230 vcpu->arch.mcg_cap = mcg_cap;
3231 /* Init IA32_MCG_CTL to all 1s */
3232 if (mcg_cap & MCG_CTL_P)
3233 vcpu->arch.mcg_ctl = ~(u64)0;
3234 /* Init IA32_MCi_CTL to all 1s */
3235 for (bank = 0; bank < bank_num; bank++)
3236 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3238 if (kvm_x86_ops->setup_mce)
3239 kvm_x86_ops->setup_mce(vcpu);
3244 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3245 struct kvm_x86_mce *mce)
3247 u64 mcg_cap = vcpu->arch.mcg_cap;
3248 unsigned bank_num = mcg_cap & 0xff;
3249 u64 *banks = vcpu->arch.mce_banks;
3251 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3254 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3255 * reporting is disabled
3257 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3258 vcpu->arch.mcg_ctl != ~(u64)0)
3260 banks += 4 * mce->bank;
3262 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3263 * reporting is disabled for the bank
3265 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3267 if (mce->status & MCI_STATUS_UC) {
3268 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3269 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3270 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3273 if (banks[1] & MCI_STATUS_VAL)
3274 mce->status |= MCI_STATUS_OVER;
3275 banks[2] = mce->addr;
3276 banks[3] = mce->misc;
3277 vcpu->arch.mcg_status = mce->mcg_status;
3278 banks[1] = mce->status;
3279 kvm_queue_exception(vcpu, MC_VECTOR);
3280 } else if (!(banks[1] & MCI_STATUS_VAL)
3281 || !(banks[1] & MCI_STATUS_UC)) {
3282 if (banks[1] & MCI_STATUS_VAL)
3283 mce->status |= MCI_STATUS_OVER;
3284 banks[2] = mce->addr;
3285 banks[3] = mce->misc;
3286 banks[1] = mce->status;
3288 banks[1] |= MCI_STATUS_OVER;
3292 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3293 struct kvm_vcpu_events *events)
3297 if (kvm_check_request(KVM_REQ_SMI, vcpu))
3301 * FIXME: pass injected and pending separately. This is only
3302 * needed for nested virtualization, whose state cannot be
3303 * migrated yet. For now we can combine them.
3305 events->exception.injected =
3306 (vcpu->arch.exception.pending ||
3307 vcpu->arch.exception.injected) &&
3308 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3309 events->exception.nr = vcpu->arch.exception.nr;
3310 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3311 events->exception.pad = 0;
3312 events->exception.error_code = vcpu->arch.exception.error_code;
3314 events->interrupt.injected =
3315 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3316 events->interrupt.nr = vcpu->arch.interrupt.nr;
3317 events->interrupt.soft = 0;
3318 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3320 events->nmi.injected = vcpu->arch.nmi_injected;
3321 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3322 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3323 events->nmi.pad = 0;
3325 events->sipi_vector = 0; /* never valid when reporting to user space */
3327 events->smi.smm = is_smm(vcpu);
3328 events->smi.pending = vcpu->arch.smi_pending;
3329 events->smi.smm_inside_nmi =
3330 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3331 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3333 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3334 | KVM_VCPUEVENT_VALID_SHADOW
3335 | KVM_VCPUEVENT_VALID_SMM);
3336 memset(&events->reserved, 0, sizeof(events->reserved));
3339 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3341 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3342 struct kvm_vcpu_events *events)
3344 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3345 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3346 | KVM_VCPUEVENT_VALID_SHADOW
3347 | KVM_VCPUEVENT_VALID_SMM))
3350 if (events->exception.injected &&
3351 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3352 is_guest_mode(vcpu)))
3355 /* INITs are latched while in SMM */
3356 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3357 (events->smi.smm || events->smi.pending) &&
3358 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3362 vcpu->arch.exception.injected = false;
3363 vcpu->arch.exception.pending = events->exception.injected;
3364 vcpu->arch.exception.nr = events->exception.nr;
3365 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3366 vcpu->arch.exception.error_code = events->exception.error_code;
3368 vcpu->arch.interrupt.pending = events->interrupt.injected;
3369 vcpu->arch.interrupt.nr = events->interrupt.nr;
3370 vcpu->arch.interrupt.soft = events->interrupt.soft;
3371 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3372 kvm_x86_ops->set_interrupt_shadow(vcpu,
3373 events->interrupt.shadow);
3375 vcpu->arch.nmi_injected = events->nmi.injected;
3376 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3377 vcpu->arch.nmi_pending = events->nmi.pending;
3378 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3380 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3381 lapic_in_kernel(vcpu))
3382 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3384 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3385 u32 hflags = vcpu->arch.hflags;
3386 if (events->smi.smm)
3387 hflags |= HF_SMM_MASK;
3389 hflags &= ~HF_SMM_MASK;
3390 kvm_set_hflags(vcpu, hflags);
3392 vcpu->arch.smi_pending = events->smi.pending;
3394 if (events->smi.smm) {
3395 if (events->smi.smm_inside_nmi)
3396 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3398 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3399 if (lapic_in_kernel(vcpu)) {
3400 if (events->smi.latched_init)
3401 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3403 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3408 kvm_make_request(KVM_REQ_EVENT, vcpu);
3413 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3414 struct kvm_debugregs *dbgregs)
3418 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3419 kvm_get_dr(vcpu, 6, &val);
3421 dbgregs->dr7 = vcpu->arch.dr7;
3423 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3426 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3427 struct kvm_debugregs *dbgregs)
3432 if (dbgregs->dr6 & ~0xffffffffull)
3434 if (dbgregs->dr7 & ~0xffffffffull)
3437 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3438 kvm_update_dr0123(vcpu);
3439 vcpu->arch.dr6 = dbgregs->dr6;
3440 kvm_update_dr6(vcpu);
3441 vcpu->arch.dr7 = dbgregs->dr7;
3442 kvm_update_dr7(vcpu);
3447 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3449 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3451 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3452 u64 xstate_bv = xsave->header.xfeatures;
3456 * Copy legacy XSAVE area, to avoid complications with CPUID
3457 * leaves 0 and 1 in the loop below.
3459 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3462 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3463 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3466 * Copy each region from the possibly compacted offset to the
3467 * non-compacted offset.
3469 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3471 u64 feature = valid & -valid;
3472 int index = fls64(feature) - 1;
3473 void *src = get_xsave_addr(xsave, feature);
3476 u32 size, offset, ecx, edx;
3477 cpuid_count(XSTATE_CPUID, index,
3478 &size, &offset, &ecx, &edx);
3479 if (feature == XFEATURE_MASK_PKRU)
3480 memcpy(dest + offset, &vcpu->arch.pkru,
3481 sizeof(vcpu->arch.pkru));
3483 memcpy(dest + offset, src, size);
3491 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3493 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3494 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3498 * Copy legacy XSAVE area, to avoid complications with CPUID
3499 * leaves 0 and 1 in the loop below.
3501 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3503 /* Set XSTATE_BV and possibly XCOMP_BV. */
3504 xsave->header.xfeatures = xstate_bv;
3505 if (boot_cpu_has(X86_FEATURE_XSAVES))
3506 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3509 * Copy each region from the non-compacted offset to the
3510 * possibly compacted offset.
3512 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3514 u64 feature = valid & -valid;
3515 int index = fls64(feature) - 1;
3516 void *dest = get_xsave_addr(xsave, feature);
3519 u32 size, offset, ecx, edx;
3520 cpuid_count(XSTATE_CPUID, index,
3521 &size, &offset, &ecx, &edx);
3522 if (feature == XFEATURE_MASK_PKRU)
3523 memcpy(&vcpu->arch.pkru, src + offset,
3524 sizeof(vcpu->arch.pkru));
3526 memcpy(dest, src + offset, size);
3533 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3534 struct kvm_xsave *guest_xsave)
3536 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3537 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3538 fill_xsave((u8 *) guest_xsave->region, vcpu);
3540 memcpy(guest_xsave->region,
3541 &vcpu->arch.guest_fpu.state.fxsave,
3542 sizeof(struct fxregs_state));
3543 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3544 XFEATURE_MASK_FPSSE;
3548 #define XSAVE_MXCSR_OFFSET 24
3550 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3551 struct kvm_xsave *guest_xsave)
3554 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3555 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3557 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3559 * Here we allow setting states that are not present in
3560 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3561 * with old userspace.
3563 if (xstate_bv & ~kvm_supported_xcr0() ||
3564 mxcsr & ~mxcsr_feature_mask)
3566 load_xsave(vcpu, (u8 *)guest_xsave->region);
3568 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3569 mxcsr & ~mxcsr_feature_mask)
3571 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3572 guest_xsave->region, sizeof(struct fxregs_state));
3577 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3578 struct kvm_xcrs *guest_xcrs)
3580 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3581 guest_xcrs->nr_xcrs = 0;
3585 guest_xcrs->nr_xcrs = 1;
3586 guest_xcrs->flags = 0;
3587 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3588 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3591 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3592 struct kvm_xcrs *guest_xcrs)
3596 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3599 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3602 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3603 /* Only support XCR0 currently */
3604 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3605 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3606 guest_xcrs->xcrs[i].value);
3615 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3616 * stopped by the hypervisor. This function will be called from the host only.
3617 * EINVAL is returned when the host attempts to set the flag for a guest that
3618 * does not support pv clocks.
3620 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3622 if (!vcpu->arch.pv_time_enabled)
3624 vcpu->arch.pvclock_set_guest_stopped_request = true;
3625 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3629 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3630 struct kvm_enable_cap *cap)
3636 case KVM_CAP_HYPERV_SYNIC2:
3639 case KVM_CAP_HYPERV_SYNIC:
3640 if (!irqchip_in_kernel(vcpu->kvm))
3642 return kvm_hv_activate_synic(vcpu, cap->cap ==
3643 KVM_CAP_HYPERV_SYNIC2);
3649 long kvm_arch_vcpu_ioctl(struct file *filp,
3650 unsigned int ioctl, unsigned long arg)
3652 struct kvm_vcpu *vcpu = filp->private_data;
3653 void __user *argp = (void __user *)arg;
3656 struct kvm_lapic_state *lapic;
3657 struct kvm_xsave *xsave;
3658 struct kvm_xcrs *xcrs;
3664 case KVM_GET_LAPIC: {
3666 if (!lapic_in_kernel(vcpu))
3668 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3673 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3677 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3682 case KVM_SET_LAPIC: {
3684 if (!lapic_in_kernel(vcpu))
3686 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3687 if (IS_ERR(u.lapic))
3688 return PTR_ERR(u.lapic);
3690 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3693 case KVM_INTERRUPT: {
3694 struct kvm_interrupt irq;
3697 if (copy_from_user(&irq, argp, sizeof irq))
3699 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3703 r = kvm_vcpu_ioctl_nmi(vcpu);
3707 r = kvm_vcpu_ioctl_smi(vcpu);
3710 case KVM_SET_CPUID: {
3711 struct kvm_cpuid __user *cpuid_arg = argp;
3712 struct kvm_cpuid cpuid;
3715 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3717 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3720 case KVM_SET_CPUID2: {
3721 struct kvm_cpuid2 __user *cpuid_arg = argp;
3722 struct kvm_cpuid2 cpuid;
3725 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3727 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3728 cpuid_arg->entries);
3731 case KVM_GET_CPUID2: {
3732 struct kvm_cpuid2 __user *cpuid_arg = argp;
3733 struct kvm_cpuid2 cpuid;
3736 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3738 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3739 cpuid_arg->entries);
3743 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3748 case KVM_GET_MSRS: {
3749 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3750 r = msr_io(vcpu, argp, do_get_msr, 1);
3751 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3754 case KVM_SET_MSRS: {
3755 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3756 r = msr_io(vcpu, argp, do_set_msr, 0);
3757 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3760 case KVM_TPR_ACCESS_REPORTING: {
3761 struct kvm_tpr_access_ctl tac;
3764 if (copy_from_user(&tac, argp, sizeof tac))
3766 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3770 if (copy_to_user(argp, &tac, sizeof tac))
3775 case KVM_SET_VAPIC_ADDR: {
3776 struct kvm_vapic_addr va;
3780 if (!lapic_in_kernel(vcpu))
3783 if (copy_from_user(&va, argp, sizeof va))
3785 idx = srcu_read_lock(&vcpu->kvm->srcu);
3786 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3787 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3790 case KVM_X86_SETUP_MCE: {
3794 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3796 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3799 case KVM_X86_SET_MCE: {
3800 struct kvm_x86_mce mce;
3803 if (copy_from_user(&mce, argp, sizeof mce))
3805 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3808 case KVM_GET_VCPU_EVENTS: {
3809 struct kvm_vcpu_events events;
3811 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3814 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3819 case KVM_SET_VCPU_EVENTS: {
3820 struct kvm_vcpu_events events;
3823 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3826 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3829 case KVM_GET_DEBUGREGS: {
3830 struct kvm_debugregs dbgregs;
3832 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3835 if (copy_to_user(argp, &dbgregs,
3836 sizeof(struct kvm_debugregs)))
3841 case KVM_SET_DEBUGREGS: {
3842 struct kvm_debugregs dbgregs;
3845 if (copy_from_user(&dbgregs, argp,
3846 sizeof(struct kvm_debugregs)))
3849 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3852 case KVM_GET_XSAVE: {
3853 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3858 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3861 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3866 case KVM_SET_XSAVE: {
3867 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3868 if (IS_ERR(u.xsave))
3869 return PTR_ERR(u.xsave);
3871 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3874 case KVM_GET_XCRS: {
3875 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3880 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3883 if (copy_to_user(argp, u.xcrs,
3884 sizeof(struct kvm_xcrs)))
3889 case KVM_SET_XCRS: {
3890 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3892 return PTR_ERR(u.xcrs);
3894 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3897 case KVM_SET_TSC_KHZ: {
3901 user_tsc_khz = (u32)arg;
3903 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3906 if (user_tsc_khz == 0)
3907 user_tsc_khz = tsc_khz;
3909 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3914 case KVM_GET_TSC_KHZ: {
3915 r = vcpu->arch.virtual_tsc_khz;
3918 case KVM_KVMCLOCK_CTRL: {
3919 r = kvm_set_guest_paused(vcpu);
3922 case KVM_ENABLE_CAP: {
3923 struct kvm_enable_cap cap;
3926 if (copy_from_user(&cap, argp, sizeof(cap)))
3928 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3939 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3941 return VM_FAULT_SIGBUS;
3944 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3948 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3950 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3954 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3957 kvm->arch.ept_identity_map_addr = ident_addr;
3961 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3962 u32 kvm_nr_mmu_pages)
3964 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3967 mutex_lock(&kvm->slots_lock);
3969 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3970 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3972 mutex_unlock(&kvm->slots_lock);
3976 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3978 return kvm->arch.n_max_mmu_pages;
3981 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3983 struct kvm_pic *pic = kvm->arch.vpic;
3987 switch (chip->chip_id) {
3988 case KVM_IRQCHIP_PIC_MASTER:
3989 memcpy(&chip->chip.pic, &pic->pics[0],
3990 sizeof(struct kvm_pic_state));
3992 case KVM_IRQCHIP_PIC_SLAVE:
3993 memcpy(&chip->chip.pic, &pic->pics[1],
3994 sizeof(struct kvm_pic_state));
3996 case KVM_IRQCHIP_IOAPIC:
3997 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4006 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4008 struct kvm_pic *pic = kvm->arch.vpic;
4012 switch (chip->chip_id) {
4013 case KVM_IRQCHIP_PIC_MASTER:
4014 spin_lock(&pic->lock);
4015 memcpy(&pic->pics[0], &chip->chip.pic,
4016 sizeof(struct kvm_pic_state));
4017 spin_unlock(&pic->lock);
4019 case KVM_IRQCHIP_PIC_SLAVE:
4020 spin_lock(&pic->lock);
4021 memcpy(&pic->pics[1], &chip->chip.pic,
4022 sizeof(struct kvm_pic_state));
4023 spin_unlock(&pic->lock);
4025 case KVM_IRQCHIP_IOAPIC:
4026 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4032 kvm_pic_update_irq(pic);
4036 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4038 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4040 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4042 mutex_lock(&kps->lock);
4043 memcpy(ps, &kps->channels, sizeof(*ps));
4044 mutex_unlock(&kps->lock);
4048 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4051 struct kvm_pit *pit = kvm->arch.vpit;
4053 mutex_lock(&pit->pit_state.lock);
4054 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4055 for (i = 0; i < 3; i++)
4056 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4057 mutex_unlock(&pit->pit_state.lock);
4061 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4064 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4065 sizeof(ps->channels));
4066 ps->flags = kvm->arch.vpit->pit_state.flags;
4067 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4068 memset(&ps->reserved, 0, sizeof(ps->reserved));
4072 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4076 u32 prev_legacy, cur_legacy;
4077 struct kvm_pit *pit = kvm->arch.vpit;
4079 mutex_lock(&pit->pit_state.lock);
4080 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4081 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4082 if (!prev_legacy && cur_legacy)
4084 memcpy(&pit->pit_state.channels, &ps->channels,
4085 sizeof(pit->pit_state.channels));
4086 pit->pit_state.flags = ps->flags;
4087 for (i = 0; i < 3; i++)
4088 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4090 mutex_unlock(&pit->pit_state.lock);
4094 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4095 struct kvm_reinject_control *control)
4097 struct kvm_pit *pit = kvm->arch.vpit;
4102 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4103 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4104 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4106 mutex_lock(&pit->pit_state.lock);
4107 kvm_pit_set_reinject(pit, control->pit_reinject);
4108 mutex_unlock(&pit->pit_state.lock);
4114 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4115 * @kvm: kvm instance
4116 * @log: slot id and address to which we copy the log
4118 * Steps 1-4 below provide general overview of dirty page logging. See
4119 * kvm_get_dirty_log_protect() function description for additional details.
4121 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4122 * always flush the TLB (step 4) even if previous step failed and the dirty
4123 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4124 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4125 * writes will be marked dirty for next log read.
4127 * 1. Take a snapshot of the bit and clear it if needed.
4128 * 2. Write protect the corresponding page.
4129 * 3. Copy the snapshot to the userspace.
4130 * 4. Flush TLB's if needed.
4132 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4134 bool is_dirty = false;
4137 mutex_lock(&kvm->slots_lock);
4140 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4142 if (kvm_x86_ops->flush_log_dirty)
4143 kvm_x86_ops->flush_log_dirty(kvm);
4145 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4148 * All the TLBs can be flushed out of mmu lock, see the comments in
4149 * kvm_mmu_slot_remove_write_access().
4151 lockdep_assert_held(&kvm->slots_lock);
4153 kvm_flush_remote_tlbs(kvm);
4155 mutex_unlock(&kvm->slots_lock);
4159 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4162 if (!irqchip_in_kernel(kvm))
4165 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4166 irq_event->irq, irq_event->level,
4171 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4172 struct kvm_enable_cap *cap)
4180 case KVM_CAP_DISABLE_QUIRKS:
4181 kvm->arch.disabled_quirks = cap->args[0];
4184 case KVM_CAP_SPLIT_IRQCHIP: {
4185 mutex_lock(&kvm->lock);
4187 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4188 goto split_irqchip_unlock;
4190 if (irqchip_in_kernel(kvm))
4191 goto split_irqchip_unlock;
4192 if (kvm->created_vcpus)
4193 goto split_irqchip_unlock;
4194 r = kvm_setup_empty_irq_routing(kvm);
4196 goto split_irqchip_unlock;
4197 /* Pairs with irqchip_in_kernel. */
4199 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4200 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4202 split_irqchip_unlock:
4203 mutex_unlock(&kvm->lock);
4206 case KVM_CAP_X2APIC_API:
4208 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4211 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4212 kvm->arch.x2apic_format = true;
4213 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4214 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4225 long kvm_arch_vm_ioctl(struct file *filp,
4226 unsigned int ioctl, unsigned long arg)
4228 struct kvm *kvm = filp->private_data;
4229 void __user *argp = (void __user *)arg;
4232 * This union makes it completely explicit to gcc-3.x
4233 * that these two variables' stack usage should be
4234 * combined, not added together.
4237 struct kvm_pit_state ps;
4238 struct kvm_pit_state2 ps2;
4239 struct kvm_pit_config pit_config;
4243 case KVM_SET_TSS_ADDR:
4244 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4246 case KVM_SET_IDENTITY_MAP_ADDR: {
4250 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4252 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4255 case KVM_SET_NR_MMU_PAGES:
4256 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4258 case KVM_GET_NR_MMU_PAGES:
4259 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4261 case KVM_CREATE_IRQCHIP: {
4262 mutex_lock(&kvm->lock);
4265 if (irqchip_in_kernel(kvm))
4266 goto create_irqchip_unlock;
4269 if (kvm->created_vcpus)
4270 goto create_irqchip_unlock;
4272 r = kvm_pic_init(kvm);
4274 goto create_irqchip_unlock;
4276 r = kvm_ioapic_init(kvm);
4278 kvm_pic_destroy(kvm);
4279 goto create_irqchip_unlock;
4282 r = kvm_setup_default_irq_routing(kvm);
4284 kvm_ioapic_destroy(kvm);
4285 kvm_pic_destroy(kvm);
4286 goto create_irqchip_unlock;
4288 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4290 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4291 create_irqchip_unlock:
4292 mutex_unlock(&kvm->lock);
4295 case KVM_CREATE_PIT:
4296 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4298 case KVM_CREATE_PIT2:
4300 if (copy_from_user(&u.pit_config, argp,
4301 sizeof(struct kvm_pit_config)))
4304 mutex_lock(&kvm->lock);
4307 goto create_pit_unlock;
4309 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4313 mutex_unlock(&kvm->lock);
4315 case KVM_GET_IRQCHIP: {
4316 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4317 struct kvm_irqchip *chip;
4319 chip = memdup_user(argp, sizeof(*chip));
4326 if (!irqchip_kernel(kvm))
4327 goto get_irqchip_out;
4328 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4330 goto get_irqchip_out;
4332 if (copy_to_user(argp, chip, sizeof *chip))
4333 goto get_irqchip_out;
4339 case KVM_SET_IRQCHIP: {
4340 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4341 struct kvm_irqchip *chip;
4343 chip = memdup_user(argp, sizeof(*chip));
4350 if (!irqchip_kernel(kvm))
4351 goto set_irqchip_out;
4352 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4354 goto set_irqchip_out;
4362 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4365 if (!kvm->arch.vpit)
4367 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4371 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4378 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4380 mutex_lock(&kvm->lock);
4382 if (!kvm->arch.vpit)
4384 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4386 mutex_unlock(&kvm->lock);
4389 case KVM_GET_PIT2: {
4391 if (!kvm->arch.vpit)
4393 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4397 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4402 case KVM_SET_PIT2: {
4404 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4406 mutex_lock(&kvm->lock);
4408 if (!kvm->arch.vpit)
4410 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4412 mutex_unlock(&kvm->lock);
4415 case KVM_REINJECT_CONTROL: {
4416 struct kvm_reinject_control control;
4418 if (copy_from_user(&control, argp, sizeof(control)))
4420 r = kvm_vm_ioctl_reinject(kvm, &control);
4423 case KVM_SET_BOOT_CPU_ID:
4425 mutex_lock(&kvm->lock);
4426 if (kvm->created_vcpus)
4429 kvm->arch.bsp_vcpu_id = arg;
4430 mutex_unlock(&kvm->lock);
4432 case KVM_XEN_HVM_CONFIG: {
4433 struct kvm_xen_hvm_config xhc;
4435 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4440 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4444 case KVM_SET_CLOCK: {
4445 struct kvm_clock_data user_ns;
4449 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4458 * TODO: userspace has to take care of races with VCPU_RUN, so
4459 * kvm_gen_update_masterclock() can be cut down to locked
4460 * pvclock_update_vm_gtod_copy().
4462 kvm_gen_update_masterclock(kvm);
4463 now_ns = get_kvmclock_ns(kvm);
4464 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4465 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4468 case KVM_GET_CLOCK: {
4469 struct kvm_clock_data user_ns;
4472 now_ns = get_kvmclock_ns(kvm);
4473 user_ns.clock = now_ns;
4474 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4475 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4478 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4483 case KVM_ENABLE_CAP: {
4484 struct kvm_enable_cap cap;
4487 if (copy_from_user(&cap, argp, sizeof(cap)))
4489 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4499 static void kvm_init_msr_list(void)
4504 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4505 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4509 * Even MSRs that are valid in the host may not be exposed
4510 * to the guests in some cases.
4512 switch (msrs_to_save[i]) {
4513 case MSR_IA32_BNDCFGS:
4514 if (!kvm_x86_ops->mpx_supported())
4518 if (!kvm_x86_ops->rdtscp_supported())
4526 msrs_to_save[j] = msrs_to_save[i];
4529 num_msrs_to_save = j;
4531 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4532 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4536 emulated_msrs[j] = emulated_msrs[i];
4539 num_emulated_msrs = j;
4541 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4542 struct kvm_msr_entry msr;
4544 msr.index = msr_based_features[i];
4545 if (kvm_get_msr_feature(&msr))
4549 msr_based_features[j] = msr_based_features[i];
4552 num_msr_based_features = j;
4555 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4563 if (!(lapic_in_kernel(vcpu) &&
4564 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4565 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4576 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4583 if (!(lapic_in_kernel(vcpu) &&
4584 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4586 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4588 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4598 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4599 struct kvm_segment *var, int seg)
4601 kvm_x86_ops->set_segment(vcpu, var, seg);
4604 void kvm_get_segment(struct kvm_vcpu *vcpu,
4605 struct kvm_segment *var, int seg)
4607 kvm_x86_ops->get_segment(vcpu, var, seg);
4610 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4611 struct x86_exception *exception)
4615 BUG_ON(!mmu_is_nested(vcpu));
4617 /* NPT walks are always user-walks */
4618 access |= PFERR_USER_MASK;
4619 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4624 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4625 struct x86_exception *exception)
4627 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4628 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4631 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4632 struct x86_exception *exception)
4634 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4635 access |= PFERR_FETCH_MASK;
4636 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4639 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4640 struct x86_exception *exception)
4642 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4643 access |= PFERR_WRITE_MASK;
4644 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4647 /* uses this to access any guest's mapped memory without checking CPL */
4648 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4649 struct x86_exception *exception)
4651 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4654 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4655 struct kvm_vcpu *vcpu, u32 access,
4656 struct x86_exception *exception)
4659 int r = X86EMUL_CONTINUE;
4662 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4664 unsigned offset = addr & (PAGE_SIZE-1);
4665 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4668 if (gpa == UNMAPPED_GVA)
4669 return X86EMUL_PROPAGATE_FAULT;
4670 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4673 r = X86EMUL_IO_NEEDED;
4685 /* used for instruction fetching */
4686 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4687 gva_t addr, void *val, unsigned int bytes,
4688 struct x86_exception *exception)
4690 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4691 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4695 /* Inline kvm_read_guest_virt_helper for speed. */
4696 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4698 if (unlikely(gpa == UNMAPPED_GVA))
4699 return X86EMUL_PROPAGATE_FAULT;
4701 offset = addr & (PAGE_SIZE-1);
4702 if (WARN_ON(offset + bytes > PAGE_SIZE))
4703 bytes = (unsigned)PAGE_SIZE - offset;
4704 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4706 if (unlikely(ret < 0))
4707 return X86EMUL_IO_NEEDED;
4709 return X86EMUL_CONTINUE;
4712 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
4713 gva_t addr, void *val, unsigned int bytes,
4714 struct x86_exception *exception)
4716 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4719 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
4720 * is returned, but our callers are not ready for that and they blindly
4721 * call kvm_inject_page_fault. Ensure that they at least do not leak
4722 * uninitialized kernel stack memory into cr2 and error code.
4724 memset(exception, 0, sizeof(*exception));
4725 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4728 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4730 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4731 gva_t addr, void *val, unsigned int bytes,
4732 struct x86_exception *exception, bool system)
4734 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4737 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4738 access |= PFERR_USER_MASK;
4740 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
4743 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4744 unsigned long addr, void *val, unsigned int bytes)
4746 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4747 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4749 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4752 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4753 struct kvm_vcpu *vcpu, u32 access,
4754 struct x86_exception *exception)
4757 int r = X86EMUL_CONTINUE;
4760 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4763 unsigned offset = addr & (PAGE_SIZE-1);
4764 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4767 if (gpa == UNMAPPED_GVA)
4768 return X86EMUL_PROPAGATE_FAULT;
4769 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4771 r = X86EMUL_IO_NEEDED;
4783 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
4784 unsigned int bytes, struct x86_exception *exception,
4787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4788 u32 access = PFERR_WRITE_MASK;
4790 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4791 access |= PFERR_USER_MASK;
4793 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4797 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4798 unsigned int bytes, struct x86_exception *exception)
4800 /* kvm_write_guest_virt_system can pull in tons of pages. */
4801 vcpu->arch.l1tf_flush_l1d = true;
4804 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
4805 * is returned, but our callers are not ready for that and they blindly
4806 * call kvm_inject_page_fault. Ensure that they at least do not leak
4807 * uninitialized kernel stack memory into cr2 and error code.
4809 memset(exception, 0, sizeof(*exception));
4810 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4811 PFERR_WRITE_MASK, exception);
4813 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4815 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4816 gpa_t gpa, bool write)
4818 /* For APIC access vmexit */
4819 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4822 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4823 trace_vcpu_match_mmio(gva, gpa, write, true);
4830 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4831 gpa_t *gpa, struct x86_exception *exception,
4834 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4835 | (write ? PFERR_WRITE_MASK : 0);
4838 * currently PKRU is only applied to ept enabled guest so
4839 * there is no pkey in EPT page table for L1 guest or EPT
4840 * shadow page table for L2 guest.
4842 if (vcpu_match_mmio_gva(vcpu, gva)
4843 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4844 vcpu->arch.access, 0, access)) {
4845 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4846 (gva & (PAGE_SIZE - 1));
4847 trace_vcpu_match_mmio(gva, *gpa, write, false);
4851 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4853 if (*gpa == UNMAPPED_GVA)
4856 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4859 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4860 const void *val, int bytes)
4864 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4867 kvm_page_track_write(vcpu, gpa, val, bytes);
4871 struct read_write_emulator_ops {
4872 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4874 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4875 void *val, int bytes);
4876 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4877 int bytes, void *val);
4878 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4879 void *val, int bytes);
4883 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4885 if (vcpu->mmio_read_completed) {
4886 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4887 vcpu->mmio_fragments[0].gpa, val);
4888 vcpu->mmio_read_completed = 0;
4895 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4896 void *val, int bytes)
4898 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4901 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4902 void *val, int bytes)
4904 return emulator_write_phys(vcpu, gpa, val, bytes);
4907 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4909 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4910 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4913 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4914 void *val, int bytes)
4916 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4917 return X86EMUL_IO_NEEDED;
4920 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4921 void *val, int bytes)
4923 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4925 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4926 return X86EMUL_CONTINUE;
4929 static const struct read_write_emulator_ops read_emultor = {
4930 .read_write_prepare = read_prepare,
4931 .read_write_emulate = read_emulate,
4932 .read_write_mmio = vcpu_mmio_read,
4933 .read_write_exit_mmio = read_exit_mmio,
4936 static const struct read_write_emulator_ops write_emultor = {
4937 .read_write_emulate = write_emulate,
4938 .read_write_mmio = write_mmio,
4939 .read_write_exit_mmio = write_exit_mmio,
4943 static int emulator_read_write_onepage(unsigned long addr, void *val,
4945 struct x86_exception *exception,
4946 struct kvm_vcpu *vcpu,
4947 const struct read_write_emulator_ops *ops)
4951 bool write = ops->write;
4952 struct kvm_mmio_fragment *frag;
4953 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4956 * If the exit was due to a NPF we may already have a GPA.
4957 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4958 * Note, this cannot be used on string operations since string
4959 * operation using rep will only have the initial GPA from the NPF
4962 if (vcpu->arch.gpa_available &&
4963 emulator_can_use_gpa(ctxt) &&
4964 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4965 gpa = vcpu->arch.gpa_val;
4966 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4968 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4970 return X86EMUL_PROPAGATE_FAULT;
4973 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
4974 return X86EMUL_CONTINUE;
4977 * Is this MMIO handled locally?
4979 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4980 if (handled == bytes)
4981 return X86EMUL_CONTINUE;
4987 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4988 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4992 return X86EMUL_CONTINUE;
4995 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4997 void *val, unsigned int bytes,
4998 struct x86_exception *exception,
4999 const struct read_write_emulator_ops *ops)
5001 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5005 if (ops->read_write_prepare &&
5006 ops->read_write_prepare(vcpu, val, bytes))
5007 return X86EMUL_CONTINUE;
5009 vcpu->mmio_nr_fragments = 0;
5011 /* Crossing a page boundary? */
5012 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5015 now = -addr & ~PAGE_MASK;
5016 rc = emulator_read_write_onepage(addr, val, now, exception,
5019 if (rc != X86EMUL_CONTINUE)
5022 if (ctxt->mode != X86EMUL_MODE_PROT64)
5028 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5030 if (rc != X86EMUL_CONTINUE)
5033 if (!vcpu->mmio_nr_fragments)
5036 gpa = vcpu->mmio_fragments[0].gpa;
5038 vcpu->mmio_needed = 1;
5039 vcpu->mmio_cur_fragment = 0;
5041 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5042 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5043 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5044 vcpu->run->mmio.phys_addr = gpa;
5046 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5049 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5053 struct x86_exception *exception)
5055 return emulator_read_write(ctxt, addr, val, bytes,
5056 exception, &read_emultor);
5059 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5063 struct x86_exception *exception)
5065 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5066 exception, &write_emultor);
5069 #define CMPXCHG_TYPE(t, ptr, old, new) \
5070 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5072 #ifdef CONFIG_X86_64
5073 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5075 # define CMPXCHG64(ptr, old, new) \
5076 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5079 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5084 struct x86_exception *exception)
5086 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5092 /* guests cmpxchg8b have to be emulated atomically */
5093 if (bytes > 8 || (bytes & (bytes - 1)))
5096 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5098 if (gpa == UNMAPPED_GVA ||
5099 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5102 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5105 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5106 if (is_error_page(page))
5109 kaddr = kmap_atomic(page);
5110 kaddr += offset_in_page(gpa);
5113 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5116 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5119 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5122 exchanged = CMPXCHG64(kaddr, old, new);
5127 kunmap_atomic(kaddr);
5128 kvm_release_page_dirty(page);
5131 return X86EMUL_CMPXCHG_FAILED;
5133 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5134 kvm_page_track_write(vcpu, gpa, new, bytes);
5136 return X86EMUL_CONTINUE;
5139 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5141 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5144 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5148 for (i = 0; i < vcpu->arch.pio.count; i++) {
5149 if (vcpu->arch.pio.in)
5150 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5151 vcpu->arch.pio.size, pd);
5153 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5154 vcpu->arch.pio.port, vcpu->arch.pio.size,
5158 pd += vcpu->arch.pio.size;
5163 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5164 unsigned short port, void *val,
5165 unsigned int count, bool in)
5167 vcpu->arch.pio.port = port;
5168 vcpu->arch.pio.in = in;
5169 vcpu->arch.pio.count = count;
5170 vcpu->arch.pio.size = size;
5172 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5173 vcpu->arch.pio.count = 0;
5177 vcpu->run->exit_reason = KVM_EXIT_IO;
5178 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5179 vcpu->run->io.size = size;
5180 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5181 vcpu->run->io.count = count;
5182 vcpu->run->io.port = port;
5187 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5188 int size, unsigned short port, void *val,
5191 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5194 if (vcpu->arch.pio.count)
5197 memset(vcpu->arch.pio_data, 0, size * count);
5199 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5202 memcpy(val, vcpu->arch.pio_data, size * count);
5203 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5204 vcpu->arch.pio.count = 0;
5211 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5212 int size, unsigned short port,
5213 const void *val, unsigned int count)
5215 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5217 memcpy(vcpu->arch.pio_data, val, size * count);
5218 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5219 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5222 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5224 return kvm_x86_ops->get_segment_base(vcpu, seg);
5227 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5229 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5232 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5234 if (!need_emulate_wbinvd(vcpu))
5235 return X86EMUL_CONTINUE;
5237 if (kvm_x86_ops->has_wbinvd_exit()) {
5238 int cpu = get_cpu();
5240 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5241 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5242 wbinvd_ipi, NULL, 1);
5244 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5247 return X86EMUL_CONTINUE;
5250 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5252 kvm_emulate_wbinvd_noskip(vcpu);
5253 return kvm_skip_emulated_instruction(vcpu);
5255 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5259 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5261 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5264 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5265 unsigned long *dest)
5267 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5270 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5271 unsigned long value)
5274 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5277 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5279 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5282 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5285 unsigned long value;
5289 value = kvm_read_cr0(vcpu);
5292 value = vcpu->arch.cr2;
5295 value = kvm_read_cr3(vcpu);
5298 value = kvm_read_cr4(vcpu);
5301 value = kvm_get_cr8(vcpu);
5304 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5311 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5313 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5318 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5321 vcpu->arch.cr2 = val;
5324 res = kvm_set_cr3(vcpu, val);
5327 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5330 res = kvm_set_cr8(vcpu, val);
5333 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5340 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5342 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5345 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5347 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5350 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5352 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5355 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5357 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5360 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5362 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5365 static unsigned long emulator_get_cached_segment_base(
5366 struct x86_emulate_ctxt *ctxt, int seg)
5368 return get_segment_base(emul_to_vcpu(ctxt), seg);
5371 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5372 struct desc_struct *desc, u32 *base3,
5375 struct kvm_segment var;
5377 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5378 *selector = var.selector;
5381 memset(desc, 0, sizeof(*desc));
5389 set_desc_limit(desc, var.limit);
5390 set_desc_base(desc, (unsigned long)var.base);
5391 #ifdef CONFIG_X86_64
5393 *base3 = var.base >> 32;
5395 desc->type = var.type;
5397 desc->dpl = var.dpl;
5398 desc->p = var.present;
5399 desc->avl = var.avl;
5407 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5408 struct desc_struct *desc, u32 base3,
5411 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5412 struct kvm_segment var;
5414 var.selector = selector;
5415 var.base = get_desc_base(desc);
5416 #ifdef CONFIG_X86_64
5417 var.base |= ((u64)base3) << 32;
5419 var.limit = get_desc_limit(desc);
5421 var.limit = (var.limit << 12) | 0xfff;
5422 var.type = desc->type;
5423 var.dpl = desc->dpl;
5428 var.avl = desc->avl;
5429 var.present = desc->p;
5430 var.unusable = !var.present;
5433 kvm_set_segment(vcpu, &var, seg);
5437 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5438 u32 msr_index, u64 *pdata)
5440 struct msr_data msr;
5443 msr.index = msr_index;
5444 msr.host_initiated = false;
5445 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5453 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5454 u32 msr_index, u64 data)
5456 struct msr_data msr;
5459 msr.index = msr_index;
5460 msr.host_initiated = false;
5461 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5464 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5466 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5468 return vcpu->arch.smbase;
5471 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5473 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5475 vcpu->arch.smbase = smbase;
5478 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5481 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5484 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5485 u32 pmc, u64 *pdata)
5487 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5490 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5492 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5495 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5499 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5503 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5504 struct x86_instruction_info *info,
5505 enum x86_intercept_stage stage)
5507 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5510 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5511 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5513 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5516 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5518 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5521 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5523 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5526 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5528 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5531 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5533 return emul_to_vcpu(ctxt)->arch.hflags;
5536 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5538 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5541 static const struct x86_emulate_ops emulate_ops = {
5542 .read_gpr = emulator_read_gpr,
5543 .write_gpr = emulator_write_gpr,
5544 .read_std = emulator_read_std,
5545 .write_std = emulator_write_std,
5546 .read_phys = kvm_read_guest_phys_system,
5547 .fetch = kvm_fetch_guest_virt,
5548 .read_emulated = emulator_read_emulated,
5549 .write_emulated = emulator_write_emulated,
5550 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5551 .invlpg = emulator_invlpg,
5552 .pio_in_emulated = emulator_pio_in_emulated,
5553 .pio_out_emulated = emulator_pio_out_emulated,
5554 .get_segment = emulator_get_segment,
5555 .set_segment = emulator_set_segment,
5556 .get_cached_segment_base = emulator_get_cached_segment_base,
5557 .get_gdt = emulator_get_gdt,
5558 .get_idt = emulator_get_idt,
5559 .set_gdt = emulator_set_gdt,
5560 .set_idt = emulator_set_idt,
5561 .get_cr = emulator_get_cr,
5562 .set_cr = emulator_set_cr,
5563 .cpl = emulator_get_cpl,
5564 .get_dr = emulator_get_dr,
5565 .set_dr = emulator_set_dr,
5566 .get_smbase = emulator_get_smbase,
5567 .set_smbase = emulator_set_smbase,
5568 .set_msr = emulator_set_msr,
5569 .get_msr = emulator_get_msr,
5570 .check_pmc = emulator_check_pmc,
5571 .read_pmc = emulator_read_pmc,
5572 .halt = emulator_halt,
5573 .wbinvd = emulator_wbinvd,
5574 .fix_hypercall = emulator_fix_hypercall,
5575 .get_fpu = emulator_get_fpu,
5576 .put_fpu = emulator_put_fpu,
5577 .intercept = emulator_intercept,
5578 .get_cpuid = emulator_get_cpuid,
5579 .set_nmi_mask = emulator_set_nmi_mask,
5580 .get_hflags = emulator_get_hflags,
5581 .set_hflags = emulator_set_hflags,
5584 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5586 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5588 * an sti; sti; sequence only disable interrupts for the first
5589 * instruction. So, if the last instruction, be it emulated or
5590 * not, left the system with the INT_STI flag enabled, it
5591 * means that the last instruction is an sti. We should not
5592 * leave the flag on in this case. The same goes for mov ss
5594 if (int_shadow & mask)
5596 if (unlikely(int_shadow || mask)) {
5597 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5599 kvm_make_request(KVM_REQ_EVENT, vcpu);
5603 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5605 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5606 if (ctxt->exception.vector == PF_VECTOR)
5607 return kvm_propagate_fault(vcpu, &ctxt->exception);
5609 if (ctxt->exception.error_code_valid)
5610 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5611 ctxt->exception.error_code);
5613 kvm_queue_exception(vcpu, ctxt->exception.vector);
5617 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5619 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5622 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5624 ctxt->eflags = kvm_get_rflags(vcpu);
5625 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5627 ctxt->eip = kvm_rip_read(vcpu);
5628 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5629 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5630 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5631 cs_db ? X86EMUL_MODE_PROT32 :
5632 X86EMUL_MODE_PROT16;
5633 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5634 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5635 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5637 init_decode_cache(ctxt);
5638 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5641 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5643 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5646 init_emulate_ctxt(vcpu);
5650 ctxt->_eip = ctxt->eip + inc_eip;
5651 ret = emulate_int_real(ctxt, irq);
5653 if (ret != X86EMUL_CONTINUE)
5654 return EMULATE_FAIL;
5656 ctxt->eip = ctxt->_eip;
5657 kvm_rip_write(vcpu, ctxt->eip);
5658 kvm_set_rflags(vcpu, ctxt->eflags);
5660 if (irq == NMI_VECTOR)
5661 vcpu->arch.nmi_pending = 0;
5663 vcpu->arch.interrupt.pending = false;
5665 return EMULATE_DONE;
5667 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5669 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5671 int r = EMULATE_DONE;
5673 ++vcpu->stat.insn_emulation_fail;
5674 trace_kvm_emulate_insn_failed(vcpu);
5675 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5676 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5677 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5678 vcpu->run->internal.ndata = 0;
5679 r = EMULATE_USER_EXIT;
5681 kvm_queue_exception(vcpu, UD_VECTOR);
5686 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5687 bool write_fault_to_shadow_pgtable,
5693 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5696 if (!vcpu->arch.mmu.direct_map) {
5698 * Write permission should be allowed since only
5699 * write access need to be emulated.
5701 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5704 * If the mapping is invalid in guest, let cpu retry
5705 * it to generate fault.
5707 if (gpa == UNMAPPED_GVA)
5712 * Do not retry the unhandleable instruction if it faults on the
5713 * readonly host memory, otherwise it will goto a infinite loop:
5714 * retry instruction -> write #PF -> emulation fail -> retry
5715 * instruction -> ...
5717 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5720 * If the instruction failed on the error pfn, it can not be fixed,
5721 * report the error to userspace.
5723 if (is_error_noslot_pfn(pfn))
5726 kvm_release_pfn_clean(pfn);
5728 /* The instructions are well-emulated on direct mmu. */
5729 if (vcpu->arch.mmu.direct_map) {
5730 unsigned int indirect_shadow_pages;
5732 spin_lock(&vcpu->kvm->mmu_lock);
5733 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5734 spin_unlock(&vcpu->kvm->mmu_lock);
5736 if (indirect_shadow_pages)
5737 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5743 * if emulation was due to access to shadowed page table
5744 * and it failed try to unshadow page and re-enter the
5745 * guest to let CPU execute the instruction.
5747 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5750 * If the access faults on its page table, it can not
5751 * be fixed by unprotecting shadow page and it should
5752 * be reported to userspace.
5754 return !write_fault_to_shadow_pgtable;
5757 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5758 unsigned long cr2, int emulation_type)
5760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5761 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5763 last_retry_eip = vcpu->arch.last_retry_eip;
5764 last_retry_addr = vcpu->arch.last_retry_addr;
5767 * If the emulation is caused by #PF and it is non-page_table
5768 * writing instruction, it means the VM-EXIT is caused by shadow
5769 * page protected, we can zap the shadow page and retry this
5770 * instruction directly.
5772 * Note: if the guest uses a non-page-table modifying instruction
5773 * on the PDE that points to the instruction, then we will unmap
5774 * the instruction and go to an infinite loop. So, we cache the
5775 * last retried eip and the last fault address, if we meet the eip
5776 * and the address again, we can break out of the potential infinite
5779 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5781 if (!(emulation_type & EMULTYPE_RETRY))
5784 if (x86_page_table_writing_insn(ctxt))
5787 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5790 vcpu->arch.last_retry_eip = ctxt->eip;
5791 vcpu->arch.last_retry_addr = cr2;
5793 if (!vcpu->arch.mmu.direct_map)
5794 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5796 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5801 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5802 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5804 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5806 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5807 /* This is a good place to trace that we are exiting SMM. */
5808 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5810 /* Process a latched INIT or SMI, if any. */
5811 kvm_make_request(KVM_REQ_EVENT, vcpu);
5814 kvm_mmu_reset_context(vcpu);
5817 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5819 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5821 vcpu->arch.hflags = emul_flags;
5823 if (changed & HF_SMM_MASK)
5824 kvm_smm_changed(vcpu);
5827 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5836 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5837 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5842 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5844 struct kvm_run *kvm_run = vcpu->run;
5846 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5847 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5848 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5849 kvm_run->debug.arch.exception = DB_VECTOR;
5850 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5851 *r = EMULATE_USER_EXIT;
5854 * "Certain debug exceptions may clear bit 0-3. The
5855 * remaining contents of the DR6 register are never
5856 * cleared by the processor".
5858 vcpu->arch.dr6 &= ~15;
5859 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5860 kvm_queue_exception(vcpu, DB_VECTOR);
5864 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5866 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5867 int r = EMULATE_DONE;
5869 kvm_x86_ops->skip_emulated_instruction(vcpu);
5872 * rflags is the old, "raw" value of the flags. The new value has
5873 * not been saved yet.
5875 * This is correct even for TF set by the guest, because "the
5876 * processor will not generate this exception after the instruction
5877 * that sets the TF flag".
5879 if (unlikely(rflags & X86_EFLAGS_TF))
5880 kvm_vcpu_do_singlestep(vcpu, &r);
5881 return r == EMULATE_DONE;
5883 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5885 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5887 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5888 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5889 struct kvm_run *kvm_run = vcpu->run;
5890 unsigned long eip = kvm_get_linear_rip(vcpu);
5891 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5892 vcpu->arch.guest_debug_dr7,
5896 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5897 kvm_run->debug.arch.pc = eip;
5898 kvm_run->debug.arch.exception = DB_VECTOR;
5899 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5900 *r = EMULATE_USER_EXIT;
5905 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5906 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5907 unsigned long eip = kvm_get_linear_rip(vcpu);
5908 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5913 vcpu->arch.dr6 &= ~15;
5914 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5915 kvm_queue_exception(vcpu, DB_VECTOR);
5924 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5931 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5932 bool writeback = true;
5933 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5935 vcpu->arch.l1tf_flush_l1d = true;
5938 * Clear write_fault_to_shadow_pgtable here to ensure it is
5941 vcpu->arch.write_fault_to_shadow_pgtable = false;
5942 kvm_clear_exception_queue(vcpu);
5944 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5945 init_emulate_ctxt(vcpu);
5948 * We will reenter on the same instruction since
5949 * we do not set complete_userspace_io. This does not
5950 * handle watchpoints yet, those would be handled in
5953 if (!(emulation_type & EMULTYPE_SKIP) &&
5954 kvm_vcpu_check_breakpoint(vcpu, &r))
5957 ctxt->interruptibility = 0;
5958 ctxt->have_exception = false;
5959 ctxt->exception.vector = -1;
5960 ctxt->perm_ok = false;
5962 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5964 r = x86_decode_insn(ctxt, insn, insn_len);
5966 trace_kvm_emulate_insn_start(vcpu);
5967 ++vcpu->stat.insn_emulation;
5968 if (r != EMULATION_OK) {
5969 if (emulation_type & EMULTYPE_TRAP_UD)
5970 return EMULATE_FAIL;
5971 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5973 return EMULATE_DONE;
5974 if (ctxt->have_exception) {
5976 * #UD should result in just EMULATION_FAILED, and trap-like
5977 * exception should not be encountered during decode.
5979 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
5980 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
5981 inject_emulated_exception(vcpu);
5982 return EMULATE_DONE;
5984 if (emulation_type & EMULTYPE_SKIP)
5985 return EMULATE_FAIL;
5986 return handle_emulation_failure(vcpu);
5990 if (emulation_type & EMULTYPE_SKIP) {
5991 kvm_rip_write(vcpu, ctxt->_eip);
5992 if (ctxt->eflags & X86_EFLAGS_RF)
5993 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5994 return EMULATE_DONE;
5997 if (retry_instruction(ctxt, cr2, emulation_type))
5998 return EMULATE_DONE;
6000 /* this is needed for vmware backdoor interface to work since it
6001 changes registers values during IO operation */
6002 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6003 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6004 emulator_invalidate_register_cache(ctxt);
6008 /* Save the faulting GPA (cr2) in the address field */
6009 ctxt->exception.address = cr2;
6011 r = x86_emulate_insn(ctxt);
6013 if (r == EMULATION_INTERCEPTED)
6014 return EMULATE_DONE;
6016 if (r == EMULATION_FAILED) {
6017 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6019 return EMULATE_DONE;
6021 return handle_emulation_failure(vcpu);
6024 if (ctxt->have_exception) {
6026 if (inject_emulated_exception(vcpu))
6028 } else if (vcpu->arch.pio.count) {
6029 if (!vcpu->arch.pio.in) {
6030 /* FIXME: return into emulator if single-stepping. */
6031 vcpu->arch.pio.count = 0;
6034 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6036 r = EMULATE_USER_EXIT;
6037 } else if (vcpu->mmio_needed) {
6038 if (!vcpu->mmio_is_write)
6040 r = EMULATE_USER_EXIT;
6041 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6042 } else if (r == EMULATION_RESTART)
6048 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6049 toggle_interruptibility(vcpu, ctxt->interruptibility);
6050 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6051 if (!ctxt->have_exception ||
6052 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6053 kvm_rip_write(vcpu, ctxt->eip);
6054 if (r == EMULATE_DONE && ctxt->tf)
6055 kvm_vcpu_do_singlestep(vcpu, &r);
6056 __kvm_set_rflags(vcpu, ctxt->eflags);
6060 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6061 * do nothing, and it will be requested again as soon as
6062 * the shadow expires. But we still need to check here,
6063 * because POPF has no interrupt shadow.
6065 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6066 kvm_make_request(KVM_REQ_EVENT, vcpu);
6068 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6072 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
6074 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
6076 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
6077 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6078 size, port, &val, 1);
6079 /* do not return to emulator after return from userspace */
6080 vcpu->arch.pio.count = 0;
6083 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
6085 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6089 /* We should only ever be called with arch.pio.count equal to 1 */
6090 BUG_ON(vcpu->arch.pio.count != 1);
6092 /* For size less than 4 we merge, else we zero extend */
6093 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6097 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6098 * the copy and tracing
6100 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6101 vcpu->arch.pio.port, &val, 1);
6102 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6107 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6112 /* For size less than 4 we merge, else we zero extend */
6113 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6115 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6118 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6122 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6126 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6128 static int kvmclock_cpu_down_prep(unsigned int cpu)
6130 __this_cpu_write(cpu_tsc_khz, 0);
6134 static void tsc_khz_changed(void *data)
6136 struct cpufreq_freqs *freq = data;
6137 unsigned long khz = 0;
6141 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6142 khz = cpufreq_quick_get(raw_smp_processor_id());
6145 __this_cpu_write(cpu_tsc_khz, khz);
6148 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6151 struct cpufreq_freqs *freq = data;
6153 struct kvm_vcpu *vcpu;
6154 int i, send_ipi = 0;
6157 * We allow guests to temporarily run on slowing clocks,
6158 * provided we notify them after, or to run on accelerating
6159 * clocks, provided we notify them before. Thus time never
6162 * However, we have a problem. We can't atomically update
6163 * the frequency of a given CPU from this function; it is
6164 * merely a notifier, which can be called from any CPU.
6165 * Changing the TSC frequency at arbitrary points in time
6166 * requires a recomputation of local variables related to
6167 * the TSC for each VCPU. We must flag these local variables
6168 * to be updated and be sure the update takes place with the
6169 * new frequency before any guests proceed.
6171 * Unfortunately, the combination of hotplug CPU and frequency
6172 * change creates an intractable locking scenario; the order
6173 * of when these callouts happen is undefined with respect to
6174 * CPU hotplug, and they can race with each other. As such,
6175 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6176 * undefined; you can actually have a CPU frequency change take
6177 * place in between the computation of X and the setting of the
6178 * variable. To protect against this problem, all updates of
6179 * the per_cpu tsc_khz variable are done in an interrupt
6180 * protected IPI, and all callers wishing to update the value
6181 * must wait for a synchronous IPI to complete (which is trivial
6182 * if the caller is on the CPU already). This establishes the
6183 * necessary total order on variable updates.
6185 * Note that because a guest time update may take place
6186 * anytime after the setting of the VCPU's request bit, the
6187 * correct TSC value must be set before the request. However,
6188 * to ensure the update actually makes it to any guest which
6189 * starts running in hardware virtualization between the set
6190 * and the acquisition of the spinlock, we must also ping the
6191 * CPU after setting the request bit.
6195 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6197 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6200 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6202 mutex_lock(&kvm_lock);
6203 list_for_each_entry(kvm, &vm_list, vm_list) {
6204 kvm_for_each_vcpu(i, vcpu, kvm) {
6205 if (vcpu->cpu != freq->cpu)
6207 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6208 if (vcpu->cpu != raw_smp_processor_id())
6212 mutex_unlock(&kvm_lock);
6214 if (freq->old < freq->new && send_ipi) {
6216 * We upscale the frequency. Must make the guest
6217 * doesn't see old kvmclock values while running with
6218 * the new frequency, otherwise we risk the guest sees
6219 * time go backwards.
6221 * In case we update the frequency for another cpu
6222 * (which might be in guest context) send an interrupt
6223 * to kick the cpu out of guest context. Next time
6224 * guest context is entered kvmclock will be updated,
6225 * so the guest will not see stale values.
6227 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6232 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6233 .notifier_call = kvmclock_cpufreq_notifier
6236 static int kvmclock_cpu_online(unsigned int cpu)
6238 tsc_khz_changed(NULL);
6242 static void kvm_timer_init(void)
6244 max_tsc_khz = tsc_khz;
6246 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6247 #ifdef CONFIG_CPU_FREQ
6248 struct cpufreq_policy policy;
6251 memset(&policy, 0, sizeof(policy));
6253 cpufreq_get_policy(&policy, cpu);
6254 if (policy.cpuinfo.max_freq)
6255 max_tsc_khz = policy.cpuinfo.max_freq;
6258 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6259 CPUFREQ_TRANSITION_NOTIFIER);
6261 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6263 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6264 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6267 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6269 int kvm_is_in_guest(void)
6271 return __this_cpu_read(current_vcpu) != NULL;
6274 static int kvm_is_user_mode(void)
6278 if (__this_cpu_read(current_vcpu))
6279 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6281 return user_mode != 0;
6284 static unsigned long kvm_get_guest_ip(void)
6286 unsigned long ip = 0;
6288 if (__this_cpu_read(current_vcpu))
6289 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6294 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6295 .is_in_guest = kvm_is_in_guest,
6296 .is_user_mode = kvm_is_user_mode,
6297 .get_guest_ip = kvm_get_guest_ip,
6300 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6302 __this_cpu_write(current_vcpu, vcpu);
6304 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6306 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6308 __this_cpu_write(current_vcpu, NULL);
6310 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6312 #ifdef CONFIG_X86_64
6313 static void pvclock_gtod_update_fn(struct work_struct *work)
6317 struct kvm_vcpu *vcpu;
6320 mutex_lock(&kvm_lock);
6321 list_for_each_entry(kvm, &vm_list, vm_list)
6322 kvm_for_each_vcpu(i, vcpu, kvm)
6323 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6324 atomic_set(&kvm_guest_has_master_clock, 0);
6325 mutex_unlock(&kvm_lock);
6328 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6331 * Notification about pvclock gtod data update.
6333 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6336 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6337 struct timekeeper *tk = priv;
6339 update_pvclock_gtod(tk);
6341 /* disable master clock if host does not trust, or does not
6342 * use, TSC clocksource
6344 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6345 atomic_read(&kvm_guest_has_master_clock) != 0)
6346 queue_work(system_long_wq, &pvclock_gtod_work);
6351 static struct notifier_block pvclock_gtod_notifier = {
6352 .notifier_call = pvclock_gtod_notify,
6356 int kvm_arch_init(void *opaque)
6359 struct kvm_x86_ops *ops = opaque;
6362 printk(KERN_ERR "kvm: already loaded the other module\n");
6367 if (!ops->cpu_has_kvm_support()) {
6368 printk(KERN_ERR "kvm: no hardware support\n");
6372 if (ops->disabled_by_bios()) {
6373 printk(KERN_ERR "kvm: disabled by bios\n");
6379 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6381 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6385 r = kvm_mmu_module_init();
6387 goto out_free_percpu;
6391 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6392 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6393 PT_PRESENT_MASK, 0, sme_me_mask);
6396 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6398 if (boot_cpu_has(X86_FEATURE_XSAVE))
6399 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6402 #ifdef CONFIG_X86_64
6403 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6409 free_percpu(shared_msrs);
6414 void kvm_arch_exit(void)
6417 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6419 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6420 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6421 CPUFREQ_TRANSITION_NOTIFIER);
6422 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6423 #ifdef CONFIG_X86_64
6424 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6425 cancel_work_sync(&pvclock_gtod_work);
6428 kvm_mmu_module_exit();
6429 free_percpu(shared_msrs);
6432 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6434 ++vcpu->stat.halt_exits;
6435 if (lapic_in_kernel(vcpu)) {
6436 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6439 vcpu->run->exit_reason = KVM_EXIT_HLT;
6443 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6445 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6447 int ret = kvm_skip_emulated_instruction(vcpu);
6449 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6450 * KVM_EXIT_DEBUG here.
6452 return kvm_vcpu_halt(vcpu) && ret;
6454 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6456 #ifdef CONFIG_X86_64
6457 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6458 unsigned long clock_type)
6460 struct kvm_clock_pairing clock_pairing;
6465 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6466 return -KVM_EOPNOTSUPP;
6468 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6469 return -KVM_EOPNOTSUPP;
6471 clock_pairing.sec = ts.tv_sec;
6472 clock_pairing.nsec = ts.tv_nsec;
6473 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6474 clock_pairing.flags = 0;
6475 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
6478 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6479 sizeof(struct kvm_clock_pairing)))
6487 * kvm_pv_kick_cpu_op: Kick a vcpu.
6489 * @apicid - apicid of vcpu to be kicked.
6491 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6493 struct kvm_lapic_irq lapic_irq;
6495 lapic_irq.shorthand = 0;
6496 lapic_irq.dest_mode = 0;
6497 lapic_irq.level = 0;
6498 lapic_irq.dest_id = apicid;
6499 lapic_irq.msi_redir_hint = false;
6501 lapic_irq.delivery_mode = APIC_DM_REMRD;
6502 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6505 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6507 vcpu->arch.apicv_active = false;
6508 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6511 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6513 unsigned long nr, a0, a1, a2, a3, ret;
6516 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6517 if (!kvm_hv_hypercall(vcpu))
6522 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6523 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6524 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6525 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6526 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6528 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6530 op_64_bit = is_64_bit_mode(vcpu);
6539 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6545 case KVM_HC_VAPIC_POLL_IRQ:
6548 case KVM_HC_KICK_CPU:
6549 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6552 #ifdef CONFIG_X86_64
6553 case KVM_HC_CLOCK_PAIRING:
6554 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6564 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6567 ++vcpu->stat.hypercalls;
6568 return kvm_skip_emulated_instruction(vcpu);
6570 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6572 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6574 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6575 char instruction[3];
6576 unsigned long rip = kvm_rip_read(vcpu);
6578 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6580 return emulator_write_emulated(ctxt, rip, instruction, 3,
6584 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6586 return vcpu->run->request_interrupt_window &&
6587 likely(!pic_in_kernel(vcpu->kvm));
6590 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6592 struct kvm_run *kvm_run = vcpu->run;
6594 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6595 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6596 kvm_run->cr8 = kvm_get_cr8(vcpu);
6597 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6598 kvm_run->ready_for_interrupt_injection =
6599 pic_in_kernel(vcpu->kvm) ||
6600 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6603 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6607 if (!kvm_x86_ops->update_cr8_intercept)
6610 if (!lapic_in_kernel(vcpu))
6613 if (vcpu->arch.apicv_active)
6616 if (!vcpu->arch.apic->vapic_addr)
6617 max_irr = kvm_lapic_find_highest_irr(vcpu);
6624 tpr = kvm_lapic_get_cr8(vcpu);
6626 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6629 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
6631 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
6632 vcpu->arch.exception.error_code = false;
6633 kvm_x86_ops->queue_exception(vcpu);
6636 static int inject_pending_event(struct kvm_vcpu *vcpu)
6640 /* try to reinject previous events if any */
6641 if (vcpu->arch.exception.injected) {
6642 kvm_inject_exception(vcpu);
6647 * Exceptions must be injected immediately, or the exception
6648 * frame will have the address of the NMI or interrupt handler.
6650 if (!vcpu->arch.exception.pending) {
6651 if (vcpu->arch.nmi_injected) {
6652 kvm_x86_ops->set_nmi(vcpu);
6656 if (vcpu->arch.interrupt.pending) {
6657 kvm_x86_ops->set_irq(vcpu);
6662 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6663 r = kvm_x86_ops->check_nested_events(vcpu);
6668 /* try to inject new event if pending */
6669 if (vcpu->arch.exception.pending) {
6670 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6671 vcpu->arch.exception.has_error_code,
6672 vcpu->arch.exception.error_code);
6674 vcpu->arch.exception.pending = false;
6675 vcpu->arch.exception.injected = true;
6677 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6678 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6681 if (vcpu->arch.exception.nr == DB_VECTOR &&
6682 (vcpu->arch.dr7 & DR7_GD)) {
6683 vcpu->arch.dr7 &= ~DR7_GD;
6684 kvm_update_dr7(vcpu);
6687 kvm_inject_exception(vcpu);
6688 } else if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6689 vcpu->arch.smi_pending = false;
6691 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6692 --vcpu->arch.nmi_pending;
6693 vcpu->arch.nmi_injected = true;
6694 kvm_x86_ops->set_nmi(vcpu);
6695 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6697 * Because interrupts can be injected asynchronously, we are
6698 * calling check_nested_events again here to avoid a race condition.
6699 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6700 * proposal and current concerns. Perhaps we should be setting
6701 * KVM_REQ_EVENT only on certain events and not unconditionally?
6703 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6704 r = kvm_x86_ops->check_nested_events(vcpu);
6708 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6709 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6711 kvm_x86_ops->set_irq(vcpu);
6718 static void process_nmi(struct kvm_vcpu *vcpu)
6723 * x86 is limited to one NMI running, and one NMI pending after it.
6724 * If an NMI is already in progress, limit further NMIs to just one.
6725 * Otherwise, allow two (and we'll inject the first one immediately).
6727 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6730 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6731 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6732 kvm_make_request(KVM_REQ_EVENT, vcpu);
6735 #define put_smstate(type, buf, offset, val) \
6736 *(type *)((buf) + (offset) - 0x7e00) = val
6738 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6741 flags |= seg->g << 23;
6742 flags |= seg->db << 22;
6743 flags |= seg->l << 21;
6744 flags |= seg->avl << 20;
6745 flags |= seg->present << 15;
6746 flags |= seg->dpl << 13;
6747 flags |= seg->s << 12;
6748 flags |= seg->type << 8;
6752 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6754 struct kvm_segment seg;
6757 kvm_get_segment(vcpu, &seg, n);
6758 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6761 offset = 0x7f84 + n * 12;
6763 offset = 0x7f2c + (n - 3) * 12;
6765 put_smstate(u32, buf, offset + 8, seg.base);
6766 put_smstate(u32, buf, offset + 4, seg.limit);
6767 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6770 #ifdef CONFIG_X86_64
6771 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6773 struct kvm_segment seg;
6777 kvm_get_segment(vcpu, &seg, n);
6778 offset = 0x7e00 + n * 16;
6780 flags = enter_smm_get_segment_flags(&seg) >> 8;
6781 put_smstate(u16, buf, offset, seg.selector);
6782 put_smstate(u16, buf, offset + 2, flags);
6783 put_smstate(u32, buf, offset + 4, seg.limit);
6784 put_smstate(u64, buf, offset + 8, seg.base);
6788 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6791 struct kvm_segment seg;
6795 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6796 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6797 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6798 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6800 for (i = 0; i < 8; i++)
6801 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6803 kvm_get_dr(vcpu, 6, &val);
6804 put_smstate(u32, buf, 0x7fcc, (u32)val);
6805 kvm_get_dr(vcpu, 7, &val);
6806 put_smstate(u32, buf, 0x7fc8, (u32)val);
6808 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6809 put_smstate(u32, buf, 0x7fc4, seg.selector);
6810 put_smstate(u32, buf, 0x7f64, seg.base);
6811 put_smstate(u32, buf, 0x7f60, seg.limit);
6812 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6814 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6815 put_smstate(u32, buf, 0x7fc0, seg.selector);
6816 put_smstate(u32, buf, 0x7f80, seg.base);
6817 put_smstate(u32, buf, 0x7f7c, seg.limit);
6818 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6820 kvm_x86_ops->get_gdt(vcpu, &dt);
6821 put_smstate(u32, buf, 0x7f74, dt.address);
6822 put_smstate(u32, buf, 0x7f70, dt.size);
6824 kvm_x86_ops->get_idt(vcpu, &dt);
6825 put_smstate(u32, buf, 0x7f58, dt.address);
6826 put_smstate(u32, buf, 0x7f54, dt.size);
6828 for (i = 0; i < 6; i++)
6829 enter_smm_save_seg_32(vcpu, buf, i);
6831 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6834 put_smstate(u32, buf, 0x7efc, 0x00020000);
6835 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6838 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6840 #ifdef CONFIG_X86_64
6842 struct kvm_segment seg;
6846 for (i = 0; i < 16; i++)
6847 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6849 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6850 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6852 kvm_get_dr(vcpu, 6, &val);
6853 put_smstate(u64, buf, 0x7f68, val);
6854 kvm_get_dr(vcpu, 7, &val);
6855 put_smstate(u64, buf, 0x7f60, val);
6857 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6858 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6859 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6861 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6864 put_smstate(u32, buf, 0x7efc, 0x00020064);
6866 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6868 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6869 put_smstate(u16, buf, 0x7e90, seg.selector);
6870 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6871 put_smstate(u32, buf, 0x7e94, seg.limit);
6872 put_smstate(u64, buf, 0x7e98, seg.base);
6874 kvm_x86_ops->get_idt(vcpu, &dt);
6875 put_smstate(u32, buf, 0x7e84, dt.size);
6876 put_smstate(u64, buf, 0x7e88, dt.address);
6878 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6879 put_smstate(u16, buf, 0x7e70, seg.selector);
6880 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6881 put_smstate(u32, buf, 0x7e74, seg.limit);
6882 put_smstate(u64, buf, 0x7e78, seg.base);
6884 kvm_x86_ops->get_gdt(vcpu, &dt);
6885 put_smstate(u32, buf, 0x7e64, dt.size);
6886 put_smstate(u64, buf, 0x7e68, dt.address);
6888 for (i = 0; i < 6; i++)
6889 enter_smm_save_seg_64(vcpu, buf, i);
6895 static void enter_smm(struct kvm_vcpu *vcpu)
6897 struct kvm_segment cs, ds;
6902 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6903 vcpu->arch.hflags |= HF_SMM_MASK;
6904 memset(buf, 0, 512);
6905 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6906 enter_smm_save_state_64(vcpu, buf);
6908 enter_smm_save_state_32(vcpu, buf);
6910 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6912 if (kvm_x86_ops->get_nmi_mask(vcpu))
6913 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6915 kvm_x86_ops->set_nmi_mask(vcpu, true);
6917 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6918 kvm_rip_write(vcpu, 0x8000);
6920 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6921 kvm_x86_ops->set_cr0(vcpu, cr0);
6922 vcpu->arch.cr0 = cr0;
6924 kvm_x86_ops->set_cr4(vcpu, 0);
6926 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6927 dt.address = dt.size = 0;
6928 kvm_x86_ops->set_idt(vcpu, &dt);
6930 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6932 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6933 cs.base = vcpu->arch.smbase;
6938 cs.limit = ds.limit = 0xffffffff;
6939 cs.type = ds.type = 0x3;
6940 cs.dpl = ds.dpl = 0;
6945 cs.avl = ds.avl = 0;
6946 cs.present = ds.present = 1;
6947 cs.unusable = ds.unusable = 0;
6948 cs.padding = ds.padding = 0;
6950 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6951 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6952 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6953 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6954 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6955 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6957 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6958 kvm_x86_ops->set_efer(vcpu, 0);
6960 kvm_update_cpuid(vcpu);
6961 kvm_mmu_reset_context(vcpu);
6964 static void process_smi(struct kvm_vcpu *vcpu)
6966 vcpu->arch.smi_pending = true;
6967 kvm_make_request(KVM_REQ_EVENT, vcpu);
6970 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6972 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6975 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6977 u64 eoi_exit_bitmap[4];
6979 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6982 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6984 if (irqchip_split(vcpu->kvm))
6985 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6987 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6988 kvm_x86_ops->sync_pir_to_irr(vcpu);
6989 if (ioapic_in_kernel(vcpu->kvm))
6990 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6992 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6993 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6994 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6997 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
6999 ++vcpu->stat.tlb_flush;
7000 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
7003 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7004 unsigned long start, unsigned long end)
7006 unsigned long apic_address;
7009 * The physical address of apic access page is stored in the VMCS.
7010 * Update it when it becomes invalid.
7012 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7013 if (start <= apic_address && apic_address < end)
7014 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7017 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7019 struct page *page = NULL;
7021 if (!lapic_in_kernel(vcpu))
7024 if (!kvm_x86_ops->set_apic_access_page_addr)
7027 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7028 if (is_error_page(page))
7030 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7033 * Do not pin apic access page in memory, the MMU notifier
7034 * will call us again if it is migrated or swapped out.
7038 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7041 * Returns 1 to let vcpu_run() continue the guest execution loop without
7042 * exiting to the userspace. Otherwise, the value will be returned to the
7045 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7049 dm_request_for_irq_injection(vcpu) &&
7050 kvm_cpu_accept_dm_intr(vcpu);
7052 bool req_immediate_exit = false;
7054 if (kvm_request_pending(vcpu)) {
7055 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7056 kvm_mmu_unload(vcpu);
7057 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7058 __kvm_migrate_timers(vcpu);
7059 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7060 kvm_gen_update_masterclock(vcpu->kvm);
7061 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7062 kvm_gen_kvmclock_update(vcpu);
7063 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7064 r = kvm_guest_time_update(vcpu);
7068 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7069 kvm_mmu_sync_roots(vcpu);
7070 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7071 kvm_vcpu_flush_tlb(vcpu, true);
7072 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7073 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7077 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7078 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7079 vcpu->mmio_needed = 0;
7083 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7084 /* Page is swapped out. Do synthetic halt */
7085 vcpu->arch.apf.halted = true;
7089 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7090 record_steal_time(vcpu);
7091 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7093 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7095 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7096 kvm_pmu_handle_event(vcpu);
7097 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7098 kvm_pmu_deliver_pmi(vcpu);
7099 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7100 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7101 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7102 vcpu->arch.ioapic_handled_vectors)) {
7103 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7104 vcpu->run->eoi.vector =
7105 vcpu->arch.pending_ioapic_eoi;
7110 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7111 vcpu_scan_ioapic(vcpu);
7112 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7113 kvm_vcpu_reload_apic_access_page(vcpu);
7114 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7115 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7116 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7120 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7121 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7122 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7126 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7127 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7128 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7134 * KVM_REQ_HV_STIMER has to be processed after
7135 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7136 * depend on the guest clock being up-to-date
7138 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7139 kvm_hv_process_stimers(vcpu);
7142 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7143 ++vcpu->stat.req_event;
7144 kvm_apic_accept_events(vcpu);
7145 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7150 if (inject_pending_event(vcpu) != 0)
7151 req_immediate_exit = true;
7153 /* Enable NMI/IRQ window open exits if needed.
7155 * SMIs have two cases: 1) they can be nested, and
7156 * then there is nothing to do here because RSM will
7157 * cause a vmexit anyway; 2) or the SMI can be pending
7158 * because inject_pending_event has completed the
7159 * injection of an IRQ or NMI from the previous vmexit,
7160 * and then we request an immediate exit to inject the SMI.
7162 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7163 req_immediate_exit = true;
7164 if (vcpu->arch.nmi_pending)
7165 kvm_x86_ops->enable_nmi_window(vcpu);
7166 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7167 kvm_x86_ops->enable_irq_window(vcpu);
7168 WARN_ON(vcpu->arch.exception.pending);
7171 if (kvm_lapic_enabled(vcpu)) {
7172 update_cr8_intercept(vcpu);
7173 kvm_lapic_sync_to_vapic(vcpu);
7177 r = kvm_mmu_reload(vcpu);
7179 goto cancel_injection;
7184 kvm_x86_ops->prepare_guest_switch(vcpu);
7187 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7188 * IPI are then delayed after guest entry, which ensures that they
7189 * result in virtual interrupt delivery.
7191 local_irq_disable();
7192 vcpu->mode = IN_GUEST_MODE;
7194 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7197 * 1) We should set ->mode before checking ->requests. Please see
7198 * the comment in kvm_vcpu_exiting_guest_mode().
7200 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7201 * pairs with the memory barrier implicit in pi_test_and_set_on
7202 * (see vmx_deliver_posted_interrupt).
7204 * 3) This also orders the write to mode from any reads to the page
7205 * tables done while the VCPU is running. Please see the comment
7206 * in kvm_flush_remote_tlbs.
7208 smp_mb__after_srcu_read_unlock();
7211 * This handles the case where a posted interrupt was
7212 * notified with kvm_vcpu_kick.
7214 if (kvm_lapic_enabled(vcpu)) {
7215 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7216 kvm_x86_ops->sync_pir_to_irr(vcpu);
7219 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7220 || need_resched() || signal_pending(current)) {
7221 vcpu->mode = OUTSIDE_GUEST_MODE;
7225 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7227 goto cancel_injection;
7230 kvm_load_guest_xcr0(vcpu);
7232 if (req_immediate_exit) {
7233 kvm_make_request(KVM_REQ_EVENT, vcpu);
7234 smp_send_reschedule(vcpu->cpu);
7237 trace_kvm_entry(vcpu->vcpu_id);
7238 wait_lapic_expire(vcpu);
7239 guest_enter_irqoff();
7241 if (unlikely(vcpu->arch.switch_db_regs)) {
7243 set_debugreg(vcpu->arch.eff_db[0], 0);
7244 set_debugreg(vcpu->arch.eff_db[1], 1);
7245 set_debugreg(vcpu->arch.eff_db[2], 2);
7246 set_debugreg(vcpu->arch.eff_db[3], 3);
7247 set_debugreg(vcpu->arch.dr6, 6);
7248 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7249 } else if (unlikely(hw_breakpoint_active())) {
7253 kvm_x86_ops->run(vcpu);
7256 * Do this here before restoring debug registers on the host. And
7257 * since we do this before handling the vmexit, a DR access vmexit
7258 * can (a) read the correct value of the debug registers, (b) set
7259 * KVM_DEBUGREG_WONT_EXIT again.
7261 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7262 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7263 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7264 kvm_update_dr0123(vcpu);
7265 kvm_update_dr6(vcpu);
7266 kvm_update_dr7(vcpu);
7267 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7271 * If the guest has used debug registers, at least dr7
7272 * will be disabled while returning to the host.
7273 * If we don't have active breakpoints in the host, we don't
7274 * care about the messed up debug address registers. But if
7275 * we have some of them active, restore the old state.
7277 if (hw_breakpoint_active())
7278 hw_breakpoint_restore();
7280 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7282 vcpu->mode = OUTSIDE_GUEST_MODE;
7285 kvm_put_guest_xcr0(vcpu);
7287 kvm_x86_ops->handle_external_intr(vcpu);
7291 guest_exit_irqoff();
7296 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7299 * Profile KVM exit RIPs:
7301 if (unlikely(prof_on == KVM_PROFILING)) {
7302 unsigned long rip = kvm_rip_read(vcpu);
7303 profile_hit(KVM_PROFILING, (void *)rip);
7306 if (unlikely(vcpu->arch.tsc_always_catchup))
7307 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7309 if (vcpu->arch.apic_attention)
7310 kvm_lapic_sync_from_vapic(vcpu);
7312 vcpu->arch.gpa_available = false;
7313 r = kvm_x86_ops->handle_exit(vcpu);
7317 kvm_x86_ops->cancel_injection(vcpu);
7318 if (unlikely(vcpu->arch.apic_attention))
7319 kvm_lapic_sync_from_vapic(vcpu);
7324 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7326 if (!kvm_arch_vcpu_runnable(vcpu) &&
7327 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7328 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7329 kvm_vcpu_block(vcpu);
7330 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7332 if (kvm_x86_ops->post_block)
7333 kvm_x86_ops->post_block(vcpu);
7335 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7339 kvm_apic_accept_events(vcpu);
7340 switch(vcpu->arch.mp_state) {
7341 case KVM_MP_STATE_HALTED:
7342 vcpu->arch.pv.pv_unhalted = false;
7343 vcpu->arch.mp_state =
7344 KVM_MP_STATE_RUNNABLE;
7345 case KVM_MP_STATE_RUNNABLE:
7346 vcpu->arch.apf.halted = false;
7348 case KVM_MP_STATE_INIT_RECEIVED:
7357 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7359 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7360 kvm_x86_ops->check_nested_events(vcpu);
7362 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7363 !vcpu->arch.apf.halted);
7366 static int vcpu_run(struct kvm_vcpu *vcpu)
7369 struct kvm *kvm = vcpu->kvm;
7371 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7372 vcpu->arch.l1tf_flush_l1d = true;
7375 if (kvm_vcpu_running(vcpu)) {
7376 r = vcpu_enter_guest(vcpu);
7378 r = vcpu_block(kvm, vcpu);
7384 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7385 if (kvm_cpu_has_pending_timer(vcpu))
7386 kvm_inject_pending_timer_irqs(vcpu);
7388 if (dm_request_for_irq_injection(vcpu) &&
7389 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7391 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7392 ++vcpu->stat.request_irq_exits;
7396 kvm_check_async_pf_completion(vcpu);
7398 if (signal_pending(current)) {
7400 vcpu->run->exit_reason = KVM_EXIT_INTR;
7401 ++vcpu->stat.signal_exits;
7404 if (need_resched()) {
7405 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7407 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7411 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7416 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7419 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7420 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7421 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7422 if (r != EMULATE_DONE)
7427 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7429 BUG_ON(!vcpu->arch.pio.count);
7431 return complete_emulated_io(vcpu);
7435 * Implements the following, as a state machine:
7439 * for each mmio piece in the fragment
7447 * for each mmio piece in the fragment
7452 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7454 struct kvm_run *run = vcpu->run;
7455 struct kvm_mmio_fragment *frag;
7458 BUG_ON(!vcpu->mmio_needed);
7460 /* Complete previous fragment */
7461 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7462 len = min(8u, frag->len);
7463 if (!vcpu->mmio_is_write)
7464 memcpy(frag->data, run->mmio.data, len);
7466 if (frag->len <= 8) {
7467 /* Switch to the next fragment. */
7469 vcpu->mmio_cur_fragment++;
7471 /* Go forward to the next mmio piece. */
7477 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7478 vcpu->mmio_needed = 0;
7480 /* FIXME: return into emulator if single-stepping. */
7481 if (vcpu->mmio_is_write)
7483 vcpu->mmio_read_completed = 1;
7484 return complete_emulated_io(vcpu);
7487 run->exit_reason = KVM_EXIT_MMIO;
7488 run->mmio.phys_addr = frag->gpa;
7489 if (vcpu->mmio_is_write)
7490 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7491 run->mmio.len = min(8u, frag->len);
7492 run->mmio.is_write = vcpu->mmio_is_write;
7493 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7498 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7502 kvm_sigset_activate(vcpu);
7504 kvm_load_guest_fpu(vcpu);
7506 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7507 if (kvm_run->immediate_exit) {
7511 kvm_vcpu_block(vcpu);
7512 kvm_apic_accept_events(vcpu);
7513 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7515 if (signal_pending(current)) {
7517 vcpu->run->exit_reason = KVM_EXIT_INTR;
7518 ++vcpu->stat.signal_exits;
7523 /* re-sync apic's tpr */
7524 if (!lapic_in_kernel(vcpu)) {
7525 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7531 if (unlikely(vcpu->arch.complete_userspace_io)) {
7532 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7533 vcpu->arch.complete_userspace_io = NULL;
7538 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7540 if (kvm_run->immediate_exit)
7546 kvm_put_guest_fpu(vcpu);
7547 post_kvm_run_save(vcpu);
7548 kvm_sigset_deactivate(vcpu);
7553 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7555 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7557 * We are here if userspace calls get_regs() in the middle of
7558 * instruction emulation. Registers state needs to be copied
7559 * back from emulation context to vcpu. Userspace shouldn't do
7560 * that usually, but some bad designed PV devices (vmware
7561 * backdoor interface) need this to work
7563 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7564 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7566 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7567 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7568 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7569 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7570 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7571 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7572 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7573 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7574 #ifdef CONFIG_X86_64
7575 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7576 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7577 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7578 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7579 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7580 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7581 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7582 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7585 regs->rip = kvm_rip_read(vcpu);
7586 regs->rflags = kvm_get_rflags(vcpu);
7591 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7593 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7594 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7596 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7597 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7598 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7599 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7600 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7601 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7602 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7603 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7604 #ifdef CONFIG_X86_64
7605 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7606 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7607 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7608 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7609 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7610 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7611 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7612 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7615 kvm_rip_write(vcpu, regs->rip);
7616 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7618 vcpu->arch.exception.pending = false;
7620 kvm_make_request(KVM_REQ_EVENT, vcpu);
7625 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7627 struct kvm_segment cs;
7629 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7633 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7635 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7636 struct kvm_sregs *sregs)
7640 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7641 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7642 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7643 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7644 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7645 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7647 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7648 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7650 kvm_x86_ops->get_idt(vcpu, &dt);
7651 sregs->idt.limit = dt.size;
7652 sregs->idt.base = dt.address;
7653 kvm_x86_ops->get_gdt(vcpu, &dt);
7654 sregs->gdt.limit = dt.size;
7655 sregs->gdt.base = dt.address;
7657 sregs->cr0 = kvm_read_cr0(vcpu);
7658 sregs->cr2 = vcpu->arch.cr2;
7659 sregs->cr3 = kvm_read_cr3(vcpu);
7660 sregs->cr4 = kvm_read_cr4(vcpu);
7661 sregs->cr8 = kvm_get_cr8(vcpu);
7662 sregs->efer = vcpu->arch.efer;
7663 sregs->apic_base = kvm_get_apic_base(vcpu);
7665 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7667 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7668 set_bit(vcpu->arch.interrupt.nr,
7669 (unsigned long *)sregs->interrupt_bitmap);
7674 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7675 struct kvm_mp_state *mp_state)
7677 if (kvm_mpx_supported())
7678 kvm_load_guest_fpu(vcpu);
7680 kvm_apic_accept_events(vcpu);
7681 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7682 vcpu->arch.pv.pv_unhalted)
7683 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7685 mp_state->mp_state = vcpu->arch.mp_state;
7687 if (kvm_mpx_supported())
7688 kvm_put_guest_fpu(vcpu);
7692 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7693 struct kvm_mp_state *mp_state)
7695 if (!lapic_in_kernel(vcpu) &&
7696 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7699 /* INITs are latched while in SMM */
7700 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7701 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7702 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7705 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7706 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7707 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7709 vcpu->arch.mp_state = mp_state->mp_state;
7710 kvm_make_request(KVM_REQ_EVENT, vcpu);
7714 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7715 int reason, bool has_error_code, u32 error_code)
7717 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7720 init_emulate_ctxt(vcpu);
7722 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7723 has_error_code, error_code);
7726 return EMULATE_FAIL;
7728 kvm_rip_write(vcpu, ctxt->eip);
7729 kvm_set_rflags(vcpu, ctxt->eflags);
7730 kvm_make_request(KVM_REQ_EVENT, vcpu);
7731 return EMULATE_DONE;
7733 EXPORT_SYMBOL_GPL(kvm_task_switch);
7735 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7737 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7739 * When EFER.LME and CR0.PG are set, the processor is in
7740 * 64-bit mode (though maybe in a 32-bit code segment).
7741 * CR4.PAE and EFER.LMA must be set.
7743 if (!(sregs->cr4 & X86_CR4_PAE)
7744 || !(sregs->efer & EFER_LMA))
7748 * Not in 64-bit mode: EFER.LMA is clear and the code
7749 * segment cannot be 64-bit.
7751 if (sregs->efer & EFER_LMA || sregs->cs.l)
7758 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7759 struct kvm_sregs *sregs)
7761 struct msr_data apic_base_msr;
7762 int mmu_reset_needed = 0;
7763 int cpuid_update_needed = 0;
7764 int pending_vec, max_bits, idx;
7767 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7768 (sregs->cr4 & X86_CR4_OSXSAVE))
7771 if (kvm_valid_sregs(vcpu, sregs))
7774 apic_base_msr.data = sregs->apic_base;
7775 apic_base_msr.host_initiated = true;
7776 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7779 dt.size = sregs->idt.limit;
7780 dt.address = sregs->idt.base;
7781 kvm_x86_ops->set_idt(vcpu, &dt);
7782 dt.size = sregs->gdt.limit;
7783 dt.address = sregs->gdt.base;
7784 kvm_x86_ops->set_gdt(vcpu, &dt);
7786 vcpu->arch.cr2 = sregs->cr2;
7787 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7788 vcpu->arch.cr3 = sregs->cr3;
7789 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7791 kvm_set_cr8(vcpu, sregs->cr8);
7793 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7794 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7796 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7797 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7798 vcpu->arch.cr0 = sregs->cr0;
7800 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7801 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
7802 (X86_CR4_OSXSAVE | X86_CR4_PKE));
7803 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7804 if (cpuid_update_needed)
7805 kvm_update_cpuid(vcpu);
7807 idx = srcu_read_lock(&vcpu->kvm->srcu);
7808 if (is_pae_paging(vcpu)) {
7809 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7810 mmu_reset_needed = 1;
7812 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7814 if (mmu_reset_needed)
7815 kvm_mmu_reset_context(vcpu);
7817 max_bits = KVM_NR_INTERRUPTS;
7818 pending_vec = find_first_bit(
7819 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7820 if (pending_vec < max_bits) {
7821 kvm_queue_interrupt(vcpu, pending_vec, false);
7822 pr_debug("Set back pending irq %d\n", pending_vec);
7825 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7826 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7827 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7828 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7829 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7830 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7832 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7833 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7835 update_cr8_intercept(vcpu);
7837 /* Older userspace won't unhalt the vcpu on reset. */
7838 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7839 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7841 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7843 kvm_make_request(KVM_REQ_EVENT, vcpu);
7848 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7849 struct kvm_guest_debug *dbg)
7851 unsigned long rflags;
7854 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7856 if (vcpu->arch.exception.pending)
7858 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7859 kvm_queue_exception(vcpu, DB_VECTOR);
7861 kvm_queue_exception(vcpu, BP_VECTOR);
7865 * Read rflags as long as potentially injected trace flags are still
7868 rflags = kvm_get_rflags(vcpu);
7870 vcpu->guest_debug = dbg->control;
7871 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7872 vcpu->guest_debug = 0;
7874 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7875 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7876 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7877 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7879 for (i = 0; i < KVM_NR_DB_REGS; i++)
7880 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7882 kvm_update_dr7(vcpu);
7884 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7885 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7886 get_segment_base(vcpu, VCPU_SREG_CS);
7889 * Trigger an rflags update that will inject or remove the trace
7892 kvm_set_rflags(vcpu, rflags);
7894 kvm_x86_ops->update_bp_intercept(vcpu);
7904 * Translate a guest virtual address to a guest physical address.
7906 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7907 struct kvm_translation *tr)
7909 unsigned long vaddr = tr->linear_address;
7913 idx = srcu_read_lock(&vcpu->kvm->srcu);
7914 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7915 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7916 tr->physical_address = gpa;
7917 tr->valid = gpa != UNMAPPED_GVA;
7924 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7926 struct fxregs_state *fxsave =
7927 &vcpu->arch.guest_fpu.state.fxsave;
7929 memcpy(fpu->fpr, fxsave->st_space, 128);
7930 fpu->fcw = fxsave->cwd;
7931 fpu->fsw = fxsave->swd;
7932 fpu->ftwx = fxsave->twd;
7933 fpu->last_opcode = fxsave->fop;
7934 fpu->last_ip = fxsave->rip;
7935 fpu->last_dp = fxsave->rdp;
7936 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7941 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7943 struct fxregs_state *fxsave =
7944 &vcpu->arch.guest_fpu.state.fxsave;
7946 memcpy(fxsave->st_space, fpu->fpr, 128);
7947 fxsave->cwd = fpu->fcw;
7948 fxsave->swd = fpu->fsw;
7949 fxsave->twd = fpu->ftwx;
7950 fxsave->fop = fpu->last_opcode;
7951 fxsave->rip = fpu->last_ip;
7952 fxsave->rdp = fpu->last_dp;
7953 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7958 static void fx_init(struct kvm_vcpu *vcpu)
7960 fpstate_init(&vcpu->arch.guest_fpu.state);
7961 if (boot_cpu_has(X86_FEATURE_XSAVES))
7962 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7963 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7966 * Ensure guest xcr0 is valid for loading
7968 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7970 vcpu->arch.cr0 |= X86_CR0_ET;
7973 /* Swap (qemu) user FPU context for the guest FPU context. */
7974 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7977 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7978 /* PKRU is separately restored in kvm_x86_ops->run. */
7979 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7980 ~XFEATURE_MASK_PKRU);
7985 /* When vcpu_run ends, restore user space FPU context. */
7986 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7989 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7990 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7992 ++vcpu->stat.fpu_reload;
7996 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7998 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8000 kvmclock_reset(vcpu);
8002 kvm_x86_ops->vcpu_free(vcpu);
8003 free_cpumask_var(wbinvd_dirty_mask);
8006 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8009 struct kvm_vcpu *vcpu;
8011 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8012 printk_once(KERN_WARNING
8013 "kvm: SMP vm created on host with unstable TSC; "
8014 "guest TSC will not be reliable\n");
8016 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8021 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8025 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8026 kvm_vcpu_mtrr_init(vcpu);
8027 r = vcpu_load(vcpu);
8030 kvm_vcpu_reset(vcpu, false);
8031 kvm_mmu_setup(vcpu);
8036 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8038 struct msr_data msr;
8039 struct kvm *kvm = vcpu->kvm;
8041 kvm_hv_vcpu_postcreate(vcpu);
8043 if (vcpu_load(vcpu))
8046 msr.index = MSR_IA32_TSC;
8047 msr.host_initiated = true;
8048 kvm_write_tsc(vcpu, &msr);
8051 if (!kvmclock_periodic_sync)
8054 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8055 KVMCLOCK_SYNC_PERIOD);
8058 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8061 vcpu->arch.apf.msr_val = 0;
8063 r = vcpu_load(vcpu);
8065 kvm_mmu_unload(vcpu);
8068 kvm_arch_vcpu_free(vcpu);
8071 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8073 kvm_lapic_reset(vcpu, init_event);
8075 vcpu->arch.hflags = 0;
8077 vcpu->arch.smi_pending = 0;
8078 atomic_set(&vcpu->arch.nmi_queued, 0);
8079 vcpu->arch.nmi_pending = 0;
8080 vcpu->arch.nmi_injected = false;
8081 kvm_clear_interrupt_queue(vcpu);
8082 kvm_clear_exception_queue(vcpu);
8083 vcpu->arch.exception.pending = false;
8085 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8086 kvm_update_dr0123(vcpu);
8087 vcpu->arch.dr6 = DR6_INIT;
8088 kvm_update_dr6(vcpu);
8089 vcpu->arch.dr7 = DR7_FIXED_1;
8090 kvm_update_dr7(vcpu);
8094 kvm_make_request(KVM_REQ_EVENT, vcpu);
8095 vcpu->arch.apf.msr_val = 0;
8096 vcpu->arch.st.msr_val = 0;
8098 kvmclock_reset(vcpu);
8100 kvm_clear_async_pf_completion_queue(vcpu);
8101 kvm_async_pf_hash_reset(vcpu);
8102 vcpu->arch.apf.halted = false;
8105 kvm_pmu_reset(vcpu);
8106 vcpu->arch.smbase = 0x30000;
8108 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8109 vcpu->arch.msr_misc_features_enables = 0;
8112 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8113 vcpu->arch.regs_avail = ~0;
8114 vcpu->arch.regs_dirty = ~0;
8116 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8119 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8121 struct kvm_segment cs;
8123 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8124 cs.selector = vector << 8;
8125 cs.base = vector << 12;
8126 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8127 kvm_rip_write(vcpu, 0);
8130 int kvm_arch_hardware_enable(void)
8133 struct kvm_vcpu *vcpu;
8138 bool stable, backwards_tsc = false;
8140 kvm_shared_msr_cpu_online();
8141 ret = kvm_x86_ops->hardware_enable();
8145 local_tsc = rdtsc();
8146 stable = !check_tsc_unstable();
8147 list_for_each_entry(kvm, &vm_list, vm_list) {
8148 kvm_for_each_vcpu(i, vcpu, kvm) {
8149 if (!stable && vcpu->cpu == smp_processor_id())
8150 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8151 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8152 backwards_tsc = true;
8153 if (vcpu->arch.last_host_tsc > max_tsc)
8154 max_tsc = vcpu->arch.last_host_tsc;
8160 * Sometimes, even reliable TSCs go backwards. This happens on
8161 * platforms that reset TSC during suspend or hibernate actions, but
8162 * maintain synchronization. We must compensate. Fortunately, we can
8163 * detect that condition here, which happens early in CPU bringup,
8164 * before any KVM threads can be running. Unfortunately, we can't
8165 * bring the TSCs fully up to date with real time, as we aren't yet far
8166 * enough into CPU bringup that we know how much real time has actually
8167 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8168 * variables that haven't been updated yet.
8170 * So we simply find the maximum observed TSC above, then record the
8171 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8172 * the adjustment will be applied. Note that we accumulate
8173 * adjustments, in case multiple suspend cycles happen before some VCPU
8174 * gets a chance to run again. In the event that no KVM threads get a
8175 * chance to run, we will miss the entire elapsed period, as we'll have
8176 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8177 * loose cycle time. This isn't too big a deal, since the loss will be
8178 * uniform across all VCPUs (not to mention the scenario is extremely
8179 * unlikely). It is possible that a second hibernate recovery happens
8180 * much faster than a first, causing the observed TSC here to be
8181 * smaller; this would require additional padding adjustment, which is
8182 * why we set last_host_tsc to the local tsc observed here.
8184 * N.B. - this code below runs only on platforms with reliable TSC,
8185 * as that is the only way backwards_tsc is set above. Also note
8186 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8187 * have the same delta_cyc adjustment applied if backwards_tsc
8188 * is detected. Note further, this adjustment is only done once,
8189 * as we reset last_host_tsc on all VCPUs to stop this from being
8190 * called multiple times (one for each physical CPU bringup).
8192 * Platforms with unreliable TSCs don't have to deal with this, they
8193 * will be compensated by the logic in vcpu_load, which sets the TSC to
8194 * catchup mode. This will catchup all VCPUs to real time, but cannot
8195 * guarantee that they stay in perfect synchronization.
8197 if (backwards_tsc) {
8198 u64 delta_cyc = max_tsc - local_tsc;
8199 list_for_each_entry(kvm, &vm_list, vm_list) {
8200 kvm->arch.backwards_tsc_observed = true;
8201 kvm_for_each_vcpu(i, vcpu, kvm) {
8202 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8203 vcpu->arch.last_host_tsc = local_tsc;
8204 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8208 * We have to disable TSC offset matching.. if you were
8209 * booting a VM while issuing an S4 host suspend....
8210 * you may have some problem. Solving this issue is
8211 * left as an exercise to the reader.
8213 kvm->arch.last_tsc_nsec = 0;
8214 kvm->arch.last_tsc_write = 0;
8221 void kvm_arch_hardware_disable(void)
8223 kvm_x86_ops->hardware_disable();
8224 drop_user_return_notifiers();
8227 int kvm_arch_hardware_setup(void)
8231 r = kvm_x86_ops->hardware_setup();
8235 if (kvm_has_tsc_control) {
8237 * Make sure the user can only configure tsc_khz values that
8238 * fit into a signed integer.
8239 * A min value is not calculated needed because it will always
8240 * be 1 on all machines.
8242 u64 max = min(0x7fffffffULL,
8243 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8244 kvm_max_guest_tsc_khz = max;
8246 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8249 kvm_init_msr_list();
8253 void kvm_arch_hardware_unsetup(void)
8255 kvm_x86_ops->hardware_unsetup();
8258 void kvm_arch_check_processor_compat(void *rtn)
8260 kvm_x86_ops->check_processor_compatibility(rtn);
8263 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8265 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8267 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8269 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8271 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8274 struct static_key kvm_no_apic_vcpu __read_mostly;
8275 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8277 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8283 BUG_ON(vcpu->kvm == NULL);
8286 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8287 vcpu->arch.pv.pv_unhalted = false;
8288 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8289 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8290 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8292 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8294 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8299 vcpu->arch.pio_data = page_address(page);
8301 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8303 r = kvm_mmu_create(vcpu);
8305 goto fail_free_pio_data;
8307 if (irqchip_in_kernel(kvm)) {
8308 r = kvm_create_lapic(vcpu);
8310 goto fail_mmu_destroy;
8312 static_key_slow_inc(&kvm_no_apic_vcpu);
8314 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8316 if (!vcpu->arch.mce_banks) {
8318 goto fail_free_lapic;
8320 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8322 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8324 goto fail_free_mce_banks;
8329 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
8330 vcpu->arch.pv_time_enabled = false;
8332 vcpu->arch.guest_supported_xcr0 = 0;
8333 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8335 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8337 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8339 kvm_async_pf_hash_reset(vcpu);
8342 vcpu->arch.pending_external_vector = -1;
8343 vcpu->arch.preempted_in_kernel = false;
8345 kvm_hv_vcpu_init(vcpu);
8349 fail_free_mce_banks:
8350 kfree(vcpu->arch.mce_banks);
8352 kvm_free_lapic(vcpu);
8354 kvm_mmu_destroy(vcpu);
8356 free_page((unsigned long)vcpu->arch.pio_data);
8361 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8365 kvm_hv_vcpu_uninit(vcpu);
8366 kvm_pmu_destroy(vcpu);
8367 kfree(vcpu->arch.mce_banks);
8368 kvm_free_lapic(vcpu);
8369 idx = srcu_read_lock(&vcpu->kvm->srcu);
8370 kvm_mmu_destroy(vcpu);
8371 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8372 free_page((unsigned long)vcpu->arch.pio_data);
8373 if (!lapic_in_kernel(vcpu))
8374 static_key_slow_dec(&kvm_no_apic_vcpu);
8377 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8379 vcpu->arch.l1tf_flush_l1d = true;
8380 kvm_x86_ops->sched_in(vcpu, cpu);
8383 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8388 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8389 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8390 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8391 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
8392 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8393 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8395 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8396 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8397 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8398 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8399 &kvm->arch.irq_sources_bitmap);
8401 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8402 mutex_init(&kvm->arch.apic_map_lock);
8403 mutex_init(&kvm->arch.hyperv.hv_lock);
8404 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8406 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8407 pvclock_update_vm_gtod_copy(kvm);
8409 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8410 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8412 kvm_page_track_init(kvm);
8413 kvm_mmu_init_vm(kvm);
8415 if (kvm_x86_ops->vm_init)
8416 return kvm_x86_ops->vm_init(kvm);
8421 int kvm_arch_post_init_vm(struct kvm *kvm)
8423 return kvm_mmu_post_init_vm(kvm);
8426 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8429 r = vcpu_load(vcpu);
8431 kvm_mmu_unload(vcpu);
8435 static void kvm_free_vcpus(struct kvm *kvm)
8438 struct kvm_vcpu *vcpu;
8441 * Unpin any mmu pages first.
8443 kvm_for_each_vcpu(i, vcpu, kvm) {
8444 kvm_clear_async_pf_completion_queue(vcpu);
8445 kvm_unload_vcpu_mmu(vcpu);
8447 kvm_for_each_vcpu(i, vcpu, kvm)
8448 kvm_arch_vcpu_free(vcpu);
8450 mutex_lock(&kvm->lock);
8451 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8452 kvm->vcpus[i] = NULL;
8454 atomic_set(&kvm->online_vcpus, 0);
8455 mutex_unlock(&kvm->lock);
8458 void kvm_arch_sync_events(struct kvm *kvm)
8460 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8461 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8465 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8469 struct kvm_memslots *slots = kvm_memslots(kvm);
8470 struct kvm_memory_slot *slot, old;
8472 /* Called with kvm->slots_lock held. */
8473 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8476 slot = id_to_memslot(slots, id);
8482 * MAP_SHARED to prevent internal slot pages from being moved
8485 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8486 MAP_SHARED | MAP_ANONYMOUS, 0);
8487 if (IS_ERR((void *)hva))
8488 return PTR_ERR((void *)hva);
8497 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8498 struct kvm_userspace_memory_region m;
8500 m.slot = id | (i << 16);
8502 m.guest_phys_addr = gpa;
8503 m.userspace_addr = hva;
8504 m.memory_size = size;
8505 r = __kvm_set_memory_region(kvm, &m);
8511 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8515 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8517 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8521 mutex_lock(&kvm->slots_lock);
8522 r = __x86_set_memory_region(kvm, id, gpa, size);
8523 mutex_unlock(&kvm->slots_lock);
8527 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8529 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
8531 kvm_mmu_pre_destroy_vm(kvm);
8534 void kvm_arch_destroy_vm(struct kvm *kvm)
8536 if (current->mm == kvm->mm) {
8538 * Free memory regions allocated on behalf of userspace,
8539 * unless the the memory map has changed due to process exit
8542 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8543 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8544 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8546 if (kvm_x86_ops->vm_destroy)
8547 kvm_x86_ops->vm_destroy(kvm);
8548 kvm_pic_destroy(kvm);
8549 kvm_ioapic_destroy(kvm);
8550 kvm_free_vcpus(kvm);
8551 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8552 kvm_mmu_uninit_vm(kvm);
8553 kvm_page_track_cleanup(kvm);
8556 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8557 struct kvm_memory_slot *dont)
8561 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8562 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8563 kvfree(free->arch.rmap[i]);
8564 free->arch.rmap[i] = NULL;
8569 if (!dont || free->arch.lpage_info[i - 1] !=
8570 dont->arch.lpage_info[i - 1]) {
8571 kvfree(free->arch.lpage_info[i - 1]);
8572 free->arch.lpage_info[i - 1] = NULL;
8576 kvm_page_track_free_memslot(free, dont);
8579 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8580 unsigned long npages)
8585 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
8586 * old arrays will be freed by __kvm_set_memory_region() if installing
8587 * the new memslot is successful.
8589 memset(&slot->arch, 0, sizeof(slot->arch));
8591 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8592 struct kvm_lpage_info *linfo;
8597 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8598 slot->base_gfn, level) + 1;
8600 slot->arch.rmap[i] =
8601 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8602 if (!slot->arch.rmap[i])
8607 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8611 slot->arch.lpage_info[i - 1] = linfo;
8613 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8614 linfo[0].disallow_lpage = 1;
8615 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8616 linfo[lpages - 1].disallow_lpage = 1;
8617 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8619 * If the gfn and userspace address are not aligned wrt each
8620 * other, or if explicitly asked to, disable large page
8621 * support for this slot
8623 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8624 !kvm_largepages_enabled()) {
8627 for (j = 0; j < lpages; ++j)
8628 linfo[j].disallow_lpage = 1;
8632 if (kvm_page_track_create_memslot(slot, npages))
8638 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8639 kvfree(slot->arch.rmap[i]);
8640 slot->arch.rmap[i] = NULL;
8644 kvfree(slot->arch.lpage_info[i - 1]);
8645 slot->arch.lpage_info[i - 1] = NULL;
8650 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
8653 * memslots->generation has been incremented.
8654 * mmio generation may have reached its maximum value.
8656 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
8659 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8660 struct kvm_memory_slot *memslot,
8661 const struct kvm_userspace_memory_region *mem,
8662 enum kvm_mr_change change)
8664 if (change == KVM_MR_MOVE)
8665 return kvm_arch_create_memslot(kvm, memslot,
8666 mem->memory_size >> PAGE_SHIFT);
8671 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8672 struct kvm_memory_slot *new)
8674 /* Still write protect RO slot */
8675 if (new->flags & KVM_MEM_READONLY) {
8676 kvm_mmu_slot_remove_write_access(kvm, new);
8681 * Call kvm_x86_ops dirty logging hooks when they are valid.
8683 * kvm_x86_ops->slot_disable_log_dirty is called when:
8685 * - KVM_MR_CREATE with dirty logging is disabled
8686 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8688 * The reason is, in case of PML, we need to set D-bit for any slots
8689 * with dirty logging disabled in order to eliminate unnecessary GPA
8690 * logging in PML buffer (and potential PML buffer full VMEXT). This
8691 * guarantees leaving PML enabled during guest's lifetime won't have
8692 * any additonal overhead from PML when guest is running with dirty
8693 * logging disabled for memory slots.
8695 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8696 * to dirty logging mode.
8698 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8700 * In case of write protect:
8702 * Write protect all pages for dirty logging.
8704 * All the sptes including the large sptes which point to this
8705 * slot are set to readonly. We can not create any new large
8706 * spte on this slot until the end of the logging.
8708 * See the comments in fast_page_fault().
8710 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8711 if (kvm_x86_ops->slot_enable_log_dirty)
8712 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8714 kvm_mmu_slot_remove_write_access(kvm, new);
8716 if (kvm_x86_ops->slot_disable_log_dirty)
8717 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8721 void kvm_arch_commit_memory_region(struct kvm *kvm,
8722 const struct kvm_userspace_memory_region *mem,
8723 const struct kvm_memory_slot *old,
8724 const struct kvm_memory_slot *new,
8725 enum kvm_mr_change change)
8727 int nr_mmu_pages = 0;
8729 if (!kvm->arch.n_requested_mmu_pages)
8730 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8733 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8736 * Dirty logging tracks sptes in 4k granularity, meaning that large
8737 * sptes have to be split. If live migration is successful, the guest
8738 * in the source machine will be destroyed and large sptes will be
8739 * created in the destination. However, if the guest continues to run
8740 * in the source machine (for example if live migration fails), small
8741 * sptes will remain around and cause bad performance.
8743 * Scan sptes if dirty logging has been stopped, dropping those
8744 * which can be collapsed into a single large-page spte. Later
8745 * page faults will create the large-page sptes.
8747 if ((change != KVM_MR_DELETE) &&
8748 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8749 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8750 kvm_mmu_zap_collapsible_sptes(kvm, new);
8753 * Set up write protection and/or dirty logging for the new slot.
8755 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8756 * been zapped so no dirty logging staff is needed for old slot. For
8757 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8758 * new and it's also covered when dealing with the new slot.
8760 * FIXME: const-ify all uses of struct kvm_memory_slot.
8762 if (change != KVM_MR_DELETE)
8763 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8766 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8768 kvm_mmu_invalidate_zap_all_pages(kvm);
8771 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8772 struct kvm_memory_slot *slot)
8774 kvm_page_track_flush_slot(kvm, slot);
8777 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8779 if (!list_empty_careful(&vcpu->async_pf.done))
8782 if (kvm_apic_has_events(vcpu))
8785 if (vcpu->arch.pv.pv_unhalted)
8788 if (vcpu->arch.exception.pending)
8791 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8792 (vcpu->arch.nmi_pending &&
8793 kvm_x86_ops->nmi_allowed(vcpu)))
8796 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8797 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8800 if (kvm_arch_interrupt_allowed(vcpu) &&
8801 kvm_cpu_has_interrupt(vcpu))
8804 if (kvm_hv_has_stimer_pending(vcpu))
8810 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8812 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8815 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
8817 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
8820 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8821 kvm_test_request(KVM_REQ_SMI, vcpu) ||
8822 kvm_test_request(KVM_REQ_EVENT, vcpu))
8825 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
8831 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8833 return vcpu->arch.preempted_in_kernel;
8836 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8838 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8841 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8843 return kvm_x86_ops->interrupt_allowed(vcpu);
8846 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8848 if (is_64_bit_mode(vcpu))
8849 return kvm_rip_read(vcpu);
8850 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8851 kvm_rip_read(vcpu));
8853 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8855 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8857 return kvm_get_linear_rip(vcpu) == linear_rip;
8859 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8861 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8863 unsigned long rflags;
8865 rflags = kvm_x86_ops->get_rflags(vcpu);
8866 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8867 rflags &= ~X86_EFLAGS_TF;
8870 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8872 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8874 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8875 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8876 rflags |= X86_EFLAGS_TF;
8877 kvm_x86_ops->set_rflags(vcpu, rflags);
8880 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8882 __kvm_set_rflags(vcpu, rflags);
8883 kvm_make_request(KVM_REQ_EVENT, vcpu);
8885 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8887 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8891 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8895 r = kvm_mmu_reload(vcpu);
8899 if (!vcpu->arch.mmu.direct_map &&
8900 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8903 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8906 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8908 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8911 static inline u32 kvm_async_pf_next_probe(u32 key)
8913 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8916 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8918 u32 key = kvm_async_pf_hash_fn(gfn);
8920 while (vcpu->arch.apf.gfns[key] != ~0)
8921 key = kvm_async_pf_next_probe(key);
8923 vcpu->arch.apf.gfns[key] = gfn;
8926 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8929 u32 key = kvm_async_pf_hash_fn(gfn);
8931 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8932 (vcpu->arch.apf.gfns[key] != gfn &&
8933 vcpu->arch.apf.gfns[key] != ~0); i++)
8934 key = kvm_async_pf_next_probe(key);
8939 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8941 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8944 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8948 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8950 vcpu->arch.apf.gfns[i] = ~0;
8952 j = kvm_async_pf_next_probe(j);
8953 if (vcpu->arch.apf.gfns[j] == ~0)
8955 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8957 * k lies cyclically in ]i,j]
8959 * |....j i.k.| or |.k..j i...|
8961 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8962 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8967 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8970 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8974 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8977 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8981 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8982 struct kvm_async_pf *work)
8984 struct x86_exception fault;
8986 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8987 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8989 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8990 (vcpu->arch.apf.send_user_only &&
8991 kvm_x86_ops->get_cpl(vcpu) == 0))
8992 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8993 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8994 fault.vector = PF_VECTOR;
8995 fault.error_code_valid = true;
8996 fault.error_code = 0;
8997 fault.nested_page_fault = false;
8998 fault.address = work->arch.token;
8999 fault.async_page_fault = true;
9000 kvm_inject_page_fault(vcpu, &fault);
9004 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9005 struct kvm_async_pf *work)
9007 struct x86_exception fault;
9010 if (work->wakeup_all)
9011 work->arch.token = ~0; /* broadcast wakeup */
9013 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9014 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9016 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9017 !apf_get_user(vcpu, &val)) {
9018 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9019 vcpu->arch.exception.pending &&
9020 vcpu->arch.exception.nr == PF_VECTOR &&
9021 !apf_put_user(vcpu, 0)) {
9022 vcpu->arch.exception.injected = false;
9023 vcpu->arch.exception.pending = false;
9024 vcpu->arch.exception.nr = 0;
9025 vcpu->arch.exception.has_error_code = false;
9026 vcpu->arch.exception.error_code = 0;
9027 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9028 fault.vector = PF_VECTOR;
9029 fault.error_code_valid = true;
9030 fault.error_code = 0;
9031 fault.nested_page_fault = false;
9032 fault.address = work->arch.token;
9033 fault.async_page_fault = true;
9034 kvm_inject_page_fault(vcpu, &fault);
9037 vcpu->arch.apf.halted = false;
9038 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9041 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9043 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9046 return kvm_can_do_async_pf(vcpu);
9049 void kvm_arch_start_assignment(struct kvm *kvm)
9051 atomic_inc(&kvm->arch.assigned_device_count);
9053 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9055 void kvm_arch_end_assignment(struct kvm *kvm)
9057 atomic_dec(&kvm->arch.assigned_device_count);
9059 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9061 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9063 return atomic_read(&kvm->arch.assigned_device_count);
9065 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9067 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9069 atomic_inc(&kvm->arch.noncoherent_dma_count);
9071 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9073 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9075 atomic_dec(&kvm->arch.noncoherent_dma_count);
9077 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9079 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9081 return atomic_read(&kvm->arch.noncoherent_dma_count);
9083 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9085 bool kvm_arch_has_irq_bypass(void)
9087 return kvm_x86_ops->update_pi_irte != NULL;
9090 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9091 struct irq_bypass_producer *prod)
9093 struct kvm_kernel_irqfd *irqfd =
9094 container_of(cons, struct kvm_kernel_irqfd, consumer);
9096 irqfd->producer = prod;
9098 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9099 prod->irq, irqfd->gsi, 1);
9102 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9103 struct irq_bypass_producer *prod)
9106 struct kvm_kernel_irqfd *irqfd =
9107 container_of(cons, struct kvm_kernel_irqfd, consumer);
9109 WARN_ON(irqfd->producer != prod);
9110 irqfd->producer = NULL;
9113 * When producer of consumer is unregistered, we change back to
9114 * remapped mode, so we can re-use the current implementation
9115 * when the irq is masked/disabled or the consumer side (KVM
9116 * int this case doesn't want to receive the interrupts.
9118 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9120 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9121 " fails: %d\n", irqfd->consumer.token, ret);
9124 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9125 uint32_t guest_irq, bool set)
9127 if (!kvm_x86_ops->update_pi_irte)
9130 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9133 bool kvm_vector_hashing_enabled(void)
9135 return vector_hashing;
9137 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9139 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9140 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9141 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9142 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9143 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9144 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9145 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9146 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9147 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9148 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9149 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9150 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9151 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9152 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9153 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9154 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9155 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9156 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9157 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);