1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/kvm_host.h>
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
28 #include "mmu/page_track.h"
37 #include <linux/clocksource.h>
38 #include <linux/interrupt.h>
39 #include <linux/kvm.h>
41 #include <linux/vmalloc.h>
42 #include <linux/export.h>
43 #include <linux/moduleparam.h>
44 #include <linux/mman.h>
45 #include <linux/highmem.h>
46 #include <linux/iommu.h>
47 #include <linux/cpufreq.h>
48 #include <linux/user-return-notifier.h>
49 #include <linux/srcu.h>
50 #include <linux/slab.h>
51 #include <linux/perf_event.h>
52 #include <linux/uaccess.h>
53 #include <linux/hash.h>
54 #include <linux/pci.h>
55 #include <linux/timekeeper_internal.h>
56 #include <linux/pvclock_gtod.h>
57 #include <linux/kvm_irqfd.h>
58 #include <linux/irqbypass.h>
59 #include <linux/sched/stat.h>
60 #include <linux/sched/isolation.h>
61 #include <linux/mem_encrypt.h>
62 #include <linux/entry-kvm.h>
63 #include <linux/suspend.h>
64 #include <linux/smp.h>
66 #include <trace/events/ipi.h>
67 #include <trace/events/kvm.h>
69 #include <asm/debugreg.h>
74 #include <linux/kernel_stat.h>
75 #include <asm/fpu/api.h>
76 #include <asm/fpu/xcr.h>
77 #include <asm/fpu/xstate.h>
78 #include <asm/pvclock.h>
79 #include <asm/div64.h>
80 #include <asm/irq_remapping.h>
81 #include <asm/mshyperv.h>
82 #include <asm/hypervisor.h>
83 #include <asm/tlbflush.h>
84 #include <asm/intel_pt.h>
85 #include <asm/emulate_prefix.h>
87 #include <clocksource/hyperv_timer.h>
89 #define CREATE_TRACE_POINTS
92 #define MAX_IO_MSRS 256
93 #define KVM_MAX_MCE_BANKS 32
95 struct kvm_caps kvm_caps __read_mostly = {
96 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
98 EXPORT_SYMBOL_GPL(kvm_caps);
100 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
102 #define emul_to_vcpu(ctxt) \
103 ((struct kvm_vcpu *)(ctxt)->vcpu)
106 * - enable syscall per default because its emulated by KVM
107 * - enable LME and LMA per default on 64 bit KVM
111 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
113 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
116 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
118 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
120 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
122 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
123 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
125 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
126 static void process_nmi(struct kvm_vcpu *vcpu);
127 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
128 static void store_regs(struct kvm_vcpu *vcpu);
129 static int sync_regs(struct kvm_vcpu *vcpu);
130 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
132 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
133 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
135 static DEFINE_MUTEX(vendor_module_lock);
136 struct kvm_x86_ops kvm_x86_ops __read_mostly;
138 #define KVM_X86_OP(func) \
139 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
140 *(((struct kvm_x86_ops *)0)->func));
141 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
142 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
143 #include <asm/kvm-x86-ops.h>
144 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
145 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
147 static bool __read_mostly ignore_msrs = 0;
148 module_param(ignore_msrs, bool, 0644);
150 bool __read_mostly report_ignored_msrs = true;
151 module_param(report_ignored_msrs, bool, 0644);
152 EXPORT_SYMBOL_GPL(report_ignored_msrs);
154 unsigned int min_timer_period_us = 200;
155 module_param(min_timer_period_us, uint, 0644);
157 static bool __read_mostly kvmclock_periodic_sync = true;
158 module_param(kvmclock_periodic_sync, bool, 0444);
160 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
161 static u32 __read_mostly tsc_tolerance_ppm = 250;
162 module_param(tsc_tolerance_ppm, uint, 0644);
165 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
166 * adaptive tuning starting from default advancement of 1000ns. '0' disables
167 * advancement entirely. Any other value is used as-is and disables adaptive
168 * tuning, i.e. allows privileged userspace to set an exact advancement time.
170 static int __read_mostly lapic_timer_advance_ns = -1;
171 module_param(lapic_timer_advance_ns, int, 0644);
173 static bool __read_mostly vector_hashing = true;
174 module_param(vector_hashing, bool, 0444);
176 bool __read_mostly enable_vmware_backdoor = false;
177 module_param(enable_vmware_backdoor, bool, 0444);
178 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
181 * Flags to manipulate forced emulation behavior (any non-zero value will
182 * enable forced emulation).
184 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
185 static int __read_mostly force_emulation_prefix;
186 module_param(force_emulation_prefix, int, 0644);
188 int __read_mostly pi_inject_timer = -1;
189 module_param(pi_inject_timer, bint, 0644);
191 /* Enable/disable PMU virtualization */
192 bool __read_mostly enable_pmu = true;
193 EXPORT_SYMBOL_GPL(enable_pmu);
194 module_param(enable_pmu, bool, 0444);
196 bool __read_mostly eager_page_split = true;
197 module_param(eager_page_split, bool, 0644);
199 /* Enable/disable SMT_RSB bug mitigation */
200 static bool __read_mostly mitigate_smt_rsb;
201 module_param(mitigate_smt_rsb, bool, 0444);
204 * Restoring the host value for MSRs that are only consumed when running in
205 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
206 * returns to userspace, i.e. the kernel can run with the guest's value.
208 #define KVM_MAX_NR_USER_RETURN_MSRS 16
210 struct kvm_user_return_msrs {
211 struct user_return_notifier urn;
213 struct kvm_user_return_msr_values {
216 } values[KVM_MAX_NR_USER_RETURN_MSRS];
219 u32 __read_mostly kvm_nr_uret_msrs;
220 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
221 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
222 static struct kvm_user_return_msrs __percpu *user_return_msrs;
224 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
225 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
226 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
227 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
229 u64 __read_mostly host_efer;
230 EXPORT_SYMBOL_GPL(host_efer);
232 bool __read_mostly allow_smaller_maxphyaddr = 0;
233 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
235 bool __read_mostly enable_apicv = true;
236 EXPORT_SYMBOL_GPL(enable_apicv);
238 u64 __read_mostly host_xss;
239 EXPORT_SYMBOL_GPL(host_xss);
241 u64 __read_mostly host_arch_capabilities;
242 EXPORT_SYMBOL_GPL(host_arch_capabilities);
244 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
245 KVM_GENERIC_VM_STATS(),
246 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
247 STATS_DESC_COUNTER(VM, mmu_pte_write),
248 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
249 STATS_DESC_COUNTER(VM, mmu_flooded),
250 STATS_DESC_COUNTER(VM, mmu_recycled),
251 STATS_DESC_COUNTER(VM, mmu_cache_miss),
252 STATS_DESC_ICOUNTER(VM, mmu_unsync),
253 STATS_DESC_ICOUNTER(VM, pages_4k),
254 STATS_DESC_ICOUNTER(VM, pages_2m),
255 STATS_DESC_ICOUNTER(VM, pages_1g),
256 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
257 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
258 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
261 const struct kvm_stats_header kvm_vm_stats_header = {
262 .name_size = KVM_STATS_NAME_SIZE,
263 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
264 .id_offset = sizeof(struct kvm_stats_header),
265 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
266 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
267 sizeof(kvm_vm_stats_desc),
270 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
271 KVM_GENERIC_VCPU_STATS(),
272 STATS_DESC_COUNTER(VCPU, pf_taken),
273 STATS_DESC_COUNTER(VCPU, pf_fixed),
274 STATS_DESC_COUNTER(VCPU, pf_emulate),
275 STATS_DESC_COUNTER(VCPU, pf_spurious),
276 STATS_DESC_COUNTER(VCPU, pf_fast),
277 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
278 STATS_DESC_COUNTER(VCPU, pf_guest),
279 STATS_DESC_COUNTER(VCPU, tlb_flush),
280 STATS_DESC_COUNTER(VCPU, invlpg),
281 STATS_DESC_COUNTER(VCPU, exits),
282 STATS_DESC_COUNTER(VCPU, io_exits),
283 STATS_DESC_COUNTER(VCPU, mmio_exits),
284 STATS_DESC_COUNTER(VCPU, signal_exits),
285 STATS_DESC_COUNTER(VCPU, irq_window_exits),
286 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
287 STATS_DESC_COUNTER(VCPU, l1d_flush),
288 STATS_DESC_COUNTER(VCPU, halt_exits),
289 STATS_DESC_COUNTER(VCPU, request_irq_exits),
290 STATS_DESC_COUNTER(VCPU, irq_exits),
291 STATS_DESC_COUNTER(VCPU, host_state_reload),
292 STATS_DESC_COUNTER(VCPU, fpu_reload),
293 STATS_DESC_COUNTER(VCPU, insn_emulation),
294 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
295 STATS_DESC_COUNTER(VCPU, hypercalls),
296 STATS_DESC_COUNTER(VCPU, irq_injections),
297 STATS_DESC_COUNTER(VCPU, nmi_injections),
298 STATS_DESC_COUNTER(VCPU, req_event),
299 STATS_DESC_COUNTER(VCPU, nested_run),
300 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
301 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
302 STATS_DESC_COUNTER(VCPU, preemption_reported),
303 STATS_DESC_COUNTER(VCPU, preemption_other),
304 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
305 STATS_DESC_COUNTER(VCPU, notify_window_exits),
308 const struct kvm_stats_header kvm_vcpu_stats_header = {
309 .name_size = KVM_STATS_NAME_SIZE,
310 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
311 .id_offset = sizeof(struct kvm_stats_header),
312 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
313 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
314 sizeof(kvm_vcpu_stats_desc),
317 u64 __read_mostly host_xcr0;
319 static struct kmem_cache *x86_emulator_cache;
322 * When called, it means the previous get/set msr reached an invalid msr.
323 * Return true if we want to ignore/silent this failed msr access.
325 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
327 const char *op = write ? "wrmsr" : "rdmsr";
330 if (report_ignored_msrs)
331 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
336 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
342 static struct kmem_cache *kvm_alloc_emulator_cache(void)
344 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
345 unsigned int size = sizeof(struct x86_emulate_ctxt);
347 return kmem_cache_create_usercopy("x86_emulator", size,
348 __alignof__(struct x86_emulate_ctxt),
349 SLAB_ACCOUNT, useroffset,
350 size - useroffset, NULL);
353 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
355 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
358 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
359 vcpu->arch.apf.gfns[i] = ~0;
362 static void kvm_on_user_return(struct user_return_notifier *urn)
365 struct kvm_user_return_msrs *msrs
366 = container_of(urn, struct kvm_user_return_msrs, urn);
367 struct kvm_user_return_msr_values *values;
371 * Disabling irqs at this point since the following code could be
372 * interrupted and executed through kvm_arch_hardware_disable()
374 local_irq_save(flags);
375 if (msrs->registered) {
376 msrs->registered = false;
377 user_return_notifier_unregister(urn);
379 local_irq_restore(flags);
380 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
381 values = &msrs->values[slot];
382 if (values->host != values->curr) {
383 wrmsrl(kvm_uret_msrs_list[slot], values->host);
384 values->curr = values->host;
389 static int kvm_probe_user_return_msr(u32 msr)
395 ret = rdmsrl_safe(msr, &val);
398 ret = wrmsrl_safe(msr, val);
404 int kvm_add_user_return_msr(u32 msr)
406 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
408 if (kvm_probe_user_return_msr(msr))
411 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
412 return kvm_nr_uret_msrs++;
414 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
416 int kvm_find_user_return_msr(u32 msr)
420 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
421 if (kvm_uret_msrs_list[i] == msr)
426 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
428 static void kvm_user_return_msr_cpu_online(void)
430 unsigned int cpu = smp_processor_id();
431 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
435 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
436 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
437 msrs->values[i].host = value;
438 msrs->values[i].curr = value;
442 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
444 unsigned int cpu = smp_processor_id();
445 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
448 value = (value & mask) | (msrs->values[slot].host & ~mask);
449 if (value == msrs->values[slot].curr)
451 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
455 msrs->values[slot].curr = value;
456 if (!msrs->registered) {
457 msrs->urn.on_user_return = kvm_on_user_return;
458 user_return_notifier_register(&msrs->urn);
459 msrs->registered = true;
463 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
465 static void drop_user_return_notifiers(void)
467 unsigned int cpu = smp_processor_id();
468 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
470 if (msrs->registered)
471 kvm_on_user_return(&msrs->urn);
474 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
476 return vcpu->arch.apic_base;
479 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
481 return kvm_apic_mode(kvm_get_apic_base(vcpu));
483 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
485 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
487 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
488 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
489 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
490 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
492 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
494 if (!msr_info->host_initiated) {
495 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
497 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
501 kvm_lapic_set_base(vcpu, msr_info->data);
502 kvm_recalculate_apic_map(vcpu->kvm);
507 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
509 * Hardware virtualization extension instructions may fault if a reboot turns
510 * off virtualization while processes are running. Usually after catching the
511 * fault we just panic; during reboot instead the instruction is ignored.
513 noinstr void kvm_spurious_fault(void)
515 /* Fault while not rebooting. We want the trace. */
516 BUG_ON(!kvm_rebooting);
518 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
520 #define EXCPT_BENIGN 0
521 #define EXCPT_CONTRIBUTORY 1
524 static int exception_class(int vector)
534 return EXCPT_CONTRIBUTORY;
541 #define EXCPT_FAULT 0
543 #define EXCPT_ABORT 2
544 #define EXCPT_INTERRUPT 3
547 static int exception_type(int vector)
551 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
552 return EXCPT_INTERRUPT;
557 * #DBs can be trap-like or fault-like, the caller must check other CPU
558 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
560 if (mask & (1 << DB_VECTOR))
563 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
566 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
569 /* Reserved exceptions will result in fault */
573 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
574 struct kvm_queued_exception *ex)
576 if (!ex->has_payload)
579 switch (ex->vector) {
582 * "Certain debug exceptions may clear bit 0-3. The
583 * remaining contents of the DR6 register are never
584 * cleared by the processor".
586 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
588 * In order to reflect the #DB exception payload in guest
589 * dr6, three components need to be considered: active low
590 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
592 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
593 * In the target guest dr6:
594 * FIXED_1 bits should always be set.
595 * Active low bits should be cleared if 1-setting in payload.
596 * Active high bits should be set if 1-setting in payload.
598 * Note, the payload is compatible with the pending debug
599 * exceptions/exit qualification under VMX, that active_low bits
600 * are active high in payload.
601 * So they need to be flipped for DR6.
603 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
604 vcpu->arch.dr6 |= ex->payload;
605 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
608 * The #DB payload is defined as compatible with the 'pending
609 * debug exceptions' field under VMX, not DR6. While bit 12 is
610 * defined in the 'pending debug exceptions' field (enabled
611 * breakpoint), it is reserved and must be zero in DR6.
613 vcpu->arch.dr6 &= ~BIT(12);
616 vcpu->arch.cr2 = ex->payload;
620 ex->has_payload = false;
623 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
625 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
626 bool has_error_code, u32 error_code,
627 bool has_payload, unsigned long payload)
629 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
632 ex->injected = false;
634 ex->has_error_code = has_error_code;
635 ex->error_code = error_code;
636 ex->has_payload = has_payload;
637 ex->payload = payload;
640 /* Forcibly leave the nested mode in cases like a vCPU reset */
641 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
643 kvm_x86_ops.nested_ops->leave_nested(vcpu);
646 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
647 unsigned nr, bool has_error, u32 error_code,
648 bool has_payload, unsigned long payload, bool reinject)
653 kvm_make_request(KVM_REQ_EVENT, vcpu);
656 * If the exception is destined for L2 and isn't being reinjected,
657 * morph it to a VM-Exit if L1 wants to intercept the exception. A
658 * previously injected exception is not checked because it was checked
659 * when it was original queued, and re-checking is incorrect if _L1_
660 * injected the exception, in which case it's exempt from interception.
662 if (!reinject && is_guest_mode(vcpu) &&
663 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
664 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
665 has_payload, payload);
669 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
673 * On VM-Entry, an exception can be pending if and only
674 * if event injection was blocked by nested_run_pending.
675 * In that case, however, vcpu_enter_guest() requests an
676 * immediate exit, and the guest shouldn't proceed far
677 * enough to need reinjection.
679 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
680 vcpu->arch.exception.injected = true;
681 if (WARN_ON_ONCE(has_payload)) {
683 * A reinjected event has already
684 * delivered its payload.
690 vcpu->arch.exception.pending = true;
691 vcpu->arch.exception.injected = false;
693 vcpu->arch.exception.has_error_code = has_error;
694 vcpu->arch.exception.vector = nr;
695 vcpu->arch.exception.error_code = error_code;
696 vcpu->arch.exception.has_payload = has_payload;
697 vcpu->arch.exception.payload = payload;
698 if (!is_guest_mode(vcpu))
699 kvm_deliver_exception_payload(vcpu,
700 &vcpu->arch.exception);
704 /* to check exception */
705 prev_nr = vcpu->arch.exception.vector;
706 if (prev_nr == DF_VECTOR) {
707 /* triple fault -> shutdown */
708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
711 class1 = exception_class(prev_nr);
712 class2 = exception_class(nr);
713 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
714 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
716 * Synthesize #DF. Clear the previously injected or pending
717 * exception so as not to incorrectly trigger shutdown.
719 vcpu->arch.exception.injected = false;
720 vcpu->arch.exception.pending = false;
722 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
724 /* replace previous exception with a new one in a hope
725 that instruction re-execution will regenerate lost
731 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
733 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
735 EXPORT_SYMBOL_GPL(kvm_queue_exception);
737 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
739 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
741 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
743 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
744 unsigned long payload)
746 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
748 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
750 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
751 u32 error_code, unsigned long payload)
753 kvm_multiple_exception(vcpu, nr, true, error_code,
754 true, payload, false);
757 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
760 kvm_inject_gp(vcpu, 0);
762 return kvm_skip_emulated_instruction(vcpu);
766 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
768 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
771 kvm_inject_gp(vcpu, 0);
775 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
776 EMULTYPE_COMPLETE_USER_EXIT);
779 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
781 ++vcpu->stat.pf_guest;
784 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
785 * whether or not L1 wants to intercept "regular" #PF.
787 if (is_guest_mode(vcpu) && fault->async_page_fault)
788 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
789 true, fault->error_code,
790 true, fault->address);
792 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
796 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
797 struct x86_exception *fault)
799 struct kvm_mmu *fault_mmu;
800 WARN_ON_ONCE(fault->vector != PF_VECTOR);
802 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
806 * Invalidate the TLB entry for the faulting address, if it exists,
807 * else the access will fault indefinitely (and to emulate hardware).
809 if ((fault->error_code & PFERR_PRESENT_MASK) &&
810 !(fault->error_code & PFERR_RSVD_MASK))
811 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
812 KVM_MMU_ROOT_CURRENT);
814 fault_mmu->inject_page_fault(vcpu, fault);
816 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
818 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
820 atomic_inc(&vcpu->arch.nmi_queued);
821 kvm_make_request(KVM_REQ_NMI, vcpu);
824 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
826 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
828 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
830 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
832 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
834 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
837 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
838 * a #GP and return false.
840 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
842 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
844 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
848 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
850 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
853 kvm_queue_exception(vcpu, UD_VECTOR);
856 EXPORT_SYMBOL_GPL(kvm_require_dr);
858 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
860 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
864 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
866 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
868 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
869 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
873 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
876 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
879 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
880 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
881 if (real_gpa == INVALID_GPA)
884 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
885 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
886 cr3 & GENMASK(11, 5), sizeof(pdpte));
890 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
891 if ((pdpte[i] & PT_PRESENT_MASK) &&
892 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
898 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
899 * Shadow page roots need to be reconstructed instead.
901 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
902 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
904 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
905 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
906 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
907 vcpu->arch.pdptrs_from_userspace = false;
911 EXPORT_SYMBOL_GPL(load_pdptrs);
913 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
916 if (cr0 & 0xffffffff00000000UL)
920 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
923 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
926 return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0);
929 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
932 * CR0.WP is incorporated into the MMU role, but only for non-nested,
933 * indirect shadow MMUs. If paging is disabled, no updates are needed
934 * as there are no permission bits to emulate. If TDP is enabled, the
935 * MMU's metadata needs to be updated, e.g. so that emulating guest
936 * translations does the right thing, but there's no need to unload the
937 * root as CR0.WP doesn't affect SPTEs.
939 if ((cr0 ^ old_cr0) == X86_CR0_WP) {
940 if (!(cr0 & X86_CR0_PG))
949 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
950 kvm_clear_async_pf_completion_queue(vcpu);
951 kvm_async_pf_hash_reset(vcpu);
954 * Clearing CR0.PG is defined to flush the TLB from the guest's
957 if (!(cr0 & X86_CR0_PG))
958 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
961 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
962 kvm_mmu_reset_context(vcpu);
964 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
965 kvm_mmu_honors_guest_mtrrs(vcpu->kvm) &&
966 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
967 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
969 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
971 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
973 unsigned long old_cr0 = kvm_read_cr0(vcpu);
975 if (!kvm_is_valid_cr0(vcpu, cr0))
980 /* Write to CR0 reserved bits are ignored, even on Intel. */
981 cr0 &= ~CR0_RESERVED_BITS;
984 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
985 (cr0 & X86_CR0_PG)) {
990 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
995 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
996 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
997 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1000 if (!(cr0 & X86_CR0_PG) &&
1001 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
1004 static_call(kvm_x86_set_cr0)(vcpu, cr0);
1006 kvm_post_set_cr0(vcpu, old_cr0, cr0);
1010 EXPORT_SYMBOL_GPL(kvm_set_cr0);
1012 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
1014 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1016 EXPORT_SYMBOL_GPL(kvm_lmsw);
1018 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1020 if (vcpu->arch.guest_state_protected)
1023 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1025 if (vcpu->arch.xcr0 != host_xcr0)
1026 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1028 if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1029 vcpu->arch.ia32_xss != host_xss)
1030 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1033 if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1034 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1035 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1036 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1037 write_pkru(vcpu->arch.pkru);
1039 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1041 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1043 if (vcpu->arch.guest_state_protected)
1046 if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1047 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1048 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1049 vcpu->arch.pkru = rdpkru();
1050 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1051 write_pkru(vcpu->arch.host_pkru);
1054 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1056 if (vcpu->arch.xcr0 != host_xcr0)
1057 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1059 if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1060 vcpu->arch.ia32_xss != host_xss)
1061 wrmsrl(MSR_IA32_XSS, host_xss);
1065 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1067 #ifdef CONFIG_X86_64
1068 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1070 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1074 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1077 u64 old_xcr0 = vcpu->arch.xcr0;
1080 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1081 if (index != XCR_XFEATURE_ENABLED_MASK)
1083 if (!(xcr0 & XFEATURE_MASK_FP))
1085 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1089 * Do not allow the guest to set bits that we do not support
1090 * saving. However, xcr0 bit 0 is always set, even if the
1091 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1093 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1094 if (xcr0 & ~valid_bits)
1097 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1098 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1101 if (xcr0 & XFEATURE_MASK_AVX512) {
1102 if (!(xcr0 & XFEATURE_MASK_YMM))
1104 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1108 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1109 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1112 vcpu->arch.xcr0 = xcr0;
1114 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1115 kvm_update_cpuid_runtime(vcpu);
1119 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1121 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1122 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1123 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1124 kvm_inject_gp(vcpu, 0);
1128 return kvm_skip_emulated_instruction(vcpu);
1130 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1132 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1134 if (cr4 & cr4_reserved_bits)
1137 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1142 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1144 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1146 return __kvm_is_valid_cr4(vcpu, cr4) &&
1147 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1150 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1152 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1153 kvm_mmu_reset_context(vcpu);
1156 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1157 * according to the SDM; however, stale prev_roots could be reused
1158 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1159 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1160 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1164 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1165 kvm_mmu_unload(vcpu);
1168 * The TLB has to be flushed for all PCIDs if any of the following
1169 * (architecturally required) changes happen:
1170 * - CR4.PCIDE is changed from 1 to 0
1171 * - CR4.PGE is toggled
1173 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1175 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1176 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1177 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1180 * The TLB has to be flushed for the current PCID if any of the
1181 * following (architecturally required) changes happen:
1182 * - CR4.SMEP is changed from 0 to 1
1183 * - CR4.PAE is toggled
1185 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1186 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1187 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1190 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1192 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1194 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1196 if (!kvm_is_valid_cr4(vcpu, cr4))
1199 if (is_long_mode(vcpu)) {
1200 if (!(cr4 & X86_CR4_PAE))
1202 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1204 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1205 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1206 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1209 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1210 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1211 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1215 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1217 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1221 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1223 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1225 struct kvm_mmu *mmu = vcpu->arch.mmu;
1226 unsigned long roots_to_free = 0;
1230 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1231 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1232 * also via the emulator. KVM's TDP page tables are not in the scope of
1233 * the invalidation, but the guest's TLB entries need to be flushed as
1234 * the CPU may have cached entries in its TLB for the target PCID.
1236 if (unlikely(tdp_enabled)) {
1237 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1242 * If neither the current CR3 nor any of the prev_roots use the given
1243 * PCID, then nothing needs to be done here because a resync will
1244 * happen anyway before switching to any other CR3.
1246 if (kvm_get_active_pcid(vcpu) == pcid) {
1247 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1248 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1252 * If PCID is disabled, there is no need to free prev_roots even if the
1253 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1256 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1259 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1260 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1261 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1263 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1266 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1268 bool skip_tlb_flush = false;
1269 unsigned long pcid = 0;
1270 #ifdef CONFIG_X86_64
1271 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1272 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1273 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1274 pcid = cr3 & X86_CR3_PCID_MASK;
1278 /* PDPTRs are always reloaded for PAE paging. */
1279 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1280 goto handle_tlb_flush;
1283 * Do not condition the GPA check on long mode, this helper is used to
1284 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1285 * the current vCPU mode is accurate.
1287 if (!kvm_vcpu_is_legal_cr3(vcpu, cr3))
1290 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1293 if (cr3 != kvm_read_cr3(vcpu))
1294 kvm_mmu_new_pgd(vcpu, cr3);
1296 vcpu->arch.cr3 = cr3;
1297 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1298 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1302 * A load of CR3 that flushes the TLB flushes only the current PCID,
1303 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1304 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1305 * and it's impossible to use a non-zero PCID when PCID is disabled,
1306 * i.e. only PCID=0 can be relevant.
1308 if (!skip_tlb_flush)
1309 kvm_invalidate_pcid(vcpu, pcid);
1313 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1315 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1317 if (cr8 & CR8_RESERVED_BITS)
1319 if (lapic_in_kernel(vcpu))
1320 kvm_lapic_set_tpr(vcpu, cr8);
1322 vcpu->arch.cr8 = cr8;
1325 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1327 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1329 if (lapic_in_kernel(vcpu))
1330 return kvm_lapic_get_cr8(vcpu);
1332 return vcpu->arch.cr8;
1334 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1336 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1340 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1341 for (i = 0; i < KVM_NR_DB_REGS; i++)
1342 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1346 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1350 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1351 dr7 = vcpu->arch.guest_debug_dr7;
1353 dr7 = vcpu->arch.dr7;
1354 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1355 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1356 if (dr7 & DR7_BP_EN_MASK)
1357 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1359 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1361 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1363 u64 fixed = DR6_FIXED_1;
1365 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1368 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1369 fixed |= DR6_BUS_LOCK;
1373 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1375 size_t size = ARRAY_SIZE(vcpu->arch.db);
1379 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1380 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1381 vcpu->arch.eff_db[dr] = val;
1385 if (!kvm_dr6_valid(val))
1387 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1391 if (!kvm_dr7_valid(val))
1393 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1394 kvm_update_dr7(vcpu);
1400 EXPORT_SYMBOL_GPL(kvm_set_dr);
1402 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1404 size_t size = ARRAY_SIZE(vcpu->arch.db);
1408 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1412 *val = vcpu->arch.dr6;
1416 *val = vcpu->arch.dr7;
1420 EXPORT_SYMBOL_GPL(kvm_get_dr);
1422 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1424 u32 ecx = kvm_rcx_read(vcpu);
1427 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1428 kvm_inject_gp(vcpu, 0);
1432 kvm_rax_write(vcpu, (u32)data);
1433 kvm_rdx_write(vcpu, data >> 32);
1434 return kvm_skip_emulated_instruction(vcpu);
1436 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1439 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track
1440 * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
1441 * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that
1442 * require host support, i.e. should be probed via RDMSR. emulated_msrs holds
1443 * MSRs that KVM emulates without strictly requiring host support.
1444 * msr_based_features holds MSRs that enumerate features, i.e. are effectively
1445 * CPUID leafs. Note, msr_based_features isn't mutually exclusive with
1446 * msrs_to_save and emulated_msrs.
1449 static const u32 msrs_to_save_base[] = {
1450 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1452 #ifdef CONFIG_X86_64
1453 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1455 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1456 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1457 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
1458 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1459 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1460 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1461 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1462 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1463 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1464 MSR_IA32_UMWAIT_CONTROL,
1466 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1469 static const u32 msrs_to_save_pmu[] = {
1470 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1471 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1472 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1473 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1474 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1476 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1477 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1478 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1479 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1480 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1481 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1482 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1483 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1484 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1486 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1487 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1489 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1490 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1491 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1492 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1493 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1495 MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
1496 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
1497 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
1500 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1501 ARRAY_SIZE(msrs_to_save_pmu)];
1502 static unsigned num_msrs_to_save;
1504 static const u32 emulated_msrs_all[] = {
1505 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1506 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1508 #ifdef CONFIG_KVM_HYPERV
1509 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1510 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1511 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1512 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1513 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1515 HV_X64_MSR_VP_INDEX,
1516 HV_X64_MSR_VP_RUNTIME,
1517 HV_X64_MSR_SCONTROL,
1518 HV_X64_MSR_STIMER0_CONFIG,
1519 HV_X64_MSR_VP_ASSIST_PAGE,
1520 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1521 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1522 HV_X64_MSR_SYNDBG_OPTIONS,
1523 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1524 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1525 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1528 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1529 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1531 MSR_IA32_TSC_ADJUST,
1532 MSR_IA32_TSC_DEADLINE,
1533 MSR_IA32_ARCH_CAPABILITIES,
1534 MSR_IA32_PERF_CAPABILITIES,
1535 MSR_IA32_MISC_ENABLE,
1536 MSR_IA32_MCG_STATUS,
1538 MSR_IA32_MCG_EXT_CTL,
1542 MSR_MISC_FEATURES_ENABLES,
1543 MSR_AMD64_VIRT_SPEC_CTRL,
1544 MSR_AMD64_TSC_RATIO,
1549 * KVM always supports the "true" VMX control MSRs, even if the host
1550 * does not. The VMX MSRs as a whole are considered "emulated" as KVM
1551 * doesn't strictly require them to exist in the host (ignoring that
1552 * KVM would refuse to load in the first place if the core set of MSRs
1553 * aren't supported).
1556 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1557 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1558 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1559 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1561 MSR_IA32_VMX_CR0_FIXED0,
1562 MSR_IA32_VMX_CR4_FIXED0,
1563 MSR_IA32_VMX_VMCS_ENUM,
1564 MSR_IA32_VMX_PROCBASED_CTLS2,
1565 MSR_IA32_VMX_EPT_VPID_CAP,
1566 MSR_IA32_VMX_VMFUNC,
1569 MSR_KVM_POLL_CONTROL,
1572 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1573 static unsigned num_emulated_msrs;
1576 * List of MSRs that control the existence of MSR-based features, i.e. MSRs
1577 * that are effectively CPUID leafs. VMX MSRs are also included in the set of
1578 * feature MSRs, but are handled separately to allow expedited lookups.
1580 static const u32 msr_based_features_all_except_vmx[] = {
1583 MSR_IA32_ARCH_CAPABILITIES,
1584 MSR_IA32_PERF_CAPABILITIES,
1587 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) +
1588 (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)];
1589 static unsigned int num_msr_based_features;
1592 * All feature MSRs except uCode revID, which tracks the currently loaded uCode
1593 * patch, are immutable once the vCPU model is defined.
1595 static bool kvm_is_immutable_feature_msr(u32 msr)
1599 if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR)
1602 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) {
1603 if (msr == msr_based_features_all_except_vmx[i])
1604 return msr != MSR_IA32_UCODE_REV;
1611 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1612 * does not yet virtualize. These include:
1613 * 10 - MISC_PACKAGE_CTRLS
1614 * 11 - ENERGY_FILTERING_CTL
1616 * 18 - FB_CLEAR_CTRL
1617 * 21 - XAPIC_DISABLE_STATUS
1618 * 23 - OVERCLOCKING_STATUS
1621 #define KVM_SUPPORTED_ARCH_CAP \
1622 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1623 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1624 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1625 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1626 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO | \
1627 ARCH_CAP_RFDS_NO | ARCH_CAP_RFDS_CLEAR | ARCH_CAP_BHI_NO)
1629 static u64 kvm_get_arch_capabilities(void)
1631 u64 data = host_arch_capabilities & KVM_SUPPORTED_ARCH_CAP;
1634 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1635 * the nested hypervisor runs with NX huge pages. If it is not,
1636 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1637 * L1 guests, so it need not worry about its own (L2) guests.
1639 data |= ARCH_CAP_PSCHANGE_MC_NO;
1642 * If we're doing cache flushes (either "always" or "cond")
1643 * we will do one whenever the guest does a vmlaunch/vmresume.
1644 * If an outer hypervisor is doing the cache flush for us
1645 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that
1646 * capability to the guest too, and if EPT is disabled we're not
1647 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1648 * require a nested hypervisor to do a flush of its own.
1650 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1651 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1653 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1654 data |= ARCH_CAP_RDCL_NO;
1655 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1656 data |= ARCH_CAP_SSB_NO;
1657 if (!boot_cpu_has_bug(X86_BUG_MDS))
1658 data |= ARCH_CAP_MDS_NO;
1659 if (!boot_cpu_has_bug(X86_BUG_RFDS))
1660 data |= ARCH_CAP_RFDS_NO;
1662 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1664 * If RTM=0 because the kernel has disabled TSX, the host might
1665 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1666 * and therefore knows that there cannot be TAA) but keep
1667 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1668 * and we want to allow migrating those guests to tsx=off hosts.
1670 data &= ~ARCH_CAP_TAA_NO;
1671 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1672 data |= ARCH_CAP_TAA_NO;
1675 * Nothing to do here; we emulate TSX_CTRL if present on the
1676 * host so the guest can choose between disabling TSX or
1677 * using VERW to clear CPU buffers.
1681 if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated())
1682 data |= ARCH_CAP_GDS_NO;
1687 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1689 switch (msr->index) {
1690 case MSR_IA32_ARCH_CAPABILITIES:
1691 msr->data = kvm_get_arch_capabilities();
1693 case MSR_IA32_PERF_CAPABILITIES:
1694 msr->data = kvm_caps.supported_perf_cap;
1696 case MSR_IA32_UCODE_REV:
1697 rdmsrl_safe(msr->index, &msr->data);
1700 return static_call(kvm_x86_get_msr_feature)(msr);
1705 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1707 struct kvm_msr_entry msr;
1710 /* Unconditionally clear the output for simplicity */
1713 r = kvm_get_msr_feature(&msr);
1715 if (r == KVM_MSR_RET_INVALID && kvm_msr_ignored_check(index, 0, false))
1723 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1725 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1728 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1731 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1734 if (efer & (EFER_LME | EFER_LMA) &&
1735 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1738 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1744 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1746 if (efer & efer_reserved_bits)
1749 return __kvm_valid_efer(vcpu, efer);
1751 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1753 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1755 u64 old_efer = vcpu->arch.efer;
1756 u64 efer = msr_info->data;
1759 if (efer & efer_reserved_bits)
1762 if (!msr_info->host_initiated) {
1763 if (!__kvm_valid_efer(vcpu, efer))
1766 if (is_paging(vcpu) &&
1767 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1772 efer |= vcpu->arch.efer & EFER_LMA;
1774 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1780 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1781 kvm_mmu_reset_context(vcpu);
1783 if (!static_cpu_has(X86_FEATURE_XSAVES) &&
1785 kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
1790 void kvm_enable_efer_bits(u64 mask)
1792 efer_reserved_bits &= ~mask;
1794 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1796 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1798 struct kvm_x86_msr_filter *msr_filter;
1799 struct msr_bitmap_range *ranges;
1800 struct kvm *kvm = vcpu->kvm;
1805 /* x2APIC MSRs do not support filtering. */
1806 if (index >= 0x800 && index <= 0x8ff)
1809 idx = srcu_read_lock(&kvm->srcu);
1811 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1817 allowed = msr_filter->default_allow;
1818 ranges = msr_filter->ranges;
1820 for (i = 0; i < msr_filter->count; i++) {
1821 u32 start = ranges[i].base;
1822 u32 end = start + ranges[i].nmsrs;
1823 u32 flags = ranges[i].flags;
1824 unsigned long *bitmap = ranges[i].bitmap;
1826 if ((index >= start) && (index < end) && (flags & type)) {
1827 allowed = test_bit(index - start, bitmap);
1833 srcu_read_unlock(&kvm->srcu, idx);
1837 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1840 * Write @data into the MSR specified by @index. Select MSR specific fault
1841 * checks are bypassed if @host_initiated is %true.
1842 * Returns 0 on success, non-0 otherwise.
1843 * Assumes vcpu_load() was already called.
1845 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1846 bool host_initiated)
1848 struct msr_data msr;
1853 case MSR_KERNEL_GS_BASE:
1856 if (is_noncanonical_address(data, vcpu))
1859 case MSR_IA32_SYSENTER_EIP:
1860 case MSR_IA32_SYSENTER_ESP:
1862 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1863 * non-canonical address is written on Intel but not on
1864 * AMD (which ignores the top 32-bits, because it does
1865 * not implement 64-bit SYSENTER).
1867 * 64-bit code should hence be able to write a non-canonical
1868 * value on AMD. Making the address canonical ensures that
1869 * vmentry does not fail on Intel after writing a non-canonical
1870 * value, and that something deterministic happens if the guest
1871 * invokes 64-bit SYSENTER.
1873 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1876 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1879 if (!host_initiated &&
1880 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1881 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1885 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1886 * incomplete and conflicting architectural behavior. Current
1887 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1888 * reserved and always read as zeros. Enforce Intel's reserved
1889 * bits check if and only if the guest CPU is Intel, and clear
1890 * the bits in all other cases. This ensures cross-vendor
1891 * migration will provide consistent behavior for the guest.
1893 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1902 msr.host_initiated = host_initiated;
1904 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1907 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1908 u32 index, u64 data, bool host_initiated)
1910 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1912 if (ret == KVM_MSR_RET_INVALID)
1913 if (kvm_msr_ignored_check(index, data, true))
1920 * Read the MSR specified by @index into @data. Select MSR specific fault
1921 * checks are bypassed if @host_initiated is %true.
1922 * Returns 0 on success, non-0 otherwise.
1923 * Assumes vcpu_load() was already called.
1925 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1926 bool host_initiated)
1928 struct msr_data msr;
1933 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1936 if (!host_initiated &&
1937 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1938 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1944 msr.host_initiated = host_initiated;
1946 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1952 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1953 u32 index, u64 *data, bool host_initiated)
1955 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1957 if (ret == KVM_MSR_RET_INVALID) {
1958 /* Unconditionally clear *data for simplicity */
1960 if (kvm_msr_ignored_check(index, 0, false))
1967 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1969 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1970 return KVM_MSR_RET_FILTERED;
1971 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1974 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1976 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1977 return KVM_MSR_RET_FILTERED;
1978 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1981 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1983 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1985 EXPORT_SYMBOL_GPL(kvm_get_msr);
1987 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1989 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1991 EXPORT_SYMBOL_GPL(kvm_set_msr);
1993 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1995 if (!vcpu->run->msr.error) {
1996 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1997 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
2001 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
2003 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
2006 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
2008 complete_userspace_rdmsr(vcpu);
2009 return complete_emulated_msr_access(vcpu);
2012 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
2014 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
2017 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2019 complete_userspace_rdmsr(vcpu);
2020 return complete_fast_msr_access(vcpu);
2023 static u64 kvm_msr_reason(int r)
2026 case KVM_MSR_RET_INVALID:
2027 return KVM_MSR_EXIT_REASON_UNKNOWN;
2028 case KVM_MSR_RET_FILTERED:
2029 return KVM_MSR_EXIT_REASON_FILTER;
2031 return KVM_MSR_EXIT_REASON_INVAL;
2035 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2036 u32 exit_reason, u64 data,
2037 int (*completion)(struct kvm_vcpu *vcpu),
2040 u64 msr_reason = kvm_msr_reason(r);
2042 /* Check if the user wanted to know about this MSR fault */
2043 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2046 vcpu->run->exit_reason = exit_reason;
2047 vcpu->run->msr.error = 0;
2048 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2049 vcpu->run->msr.reason = msr_reason;
2050 vcpu->run->msr.index = index;
2051 vcpu->run->msr.data = data;
2052 vcpu->arch.complete_userspace_io = completion;
2057 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2059 u32 ecx = kvm_rcx_read(vcpu);
2063 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2066 trace_kvm_msr_read(ecx, data);
2068 kvm_rax_write(vcpu, data & -1u);
2069 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2071 /* MSR read failed? See if we should ask user space */
2072 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2073 complete_fast_rdmsr, r))
2075 trace_kvm_msr_read_ex(ecx);
2078 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2080 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2082 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2084 u32 ecx = kvm_rcx_read(vcpu);
2085 u64 data = kvm_read_edx_eax(vcpu);
2088 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2091 trace_kvm_msr_write(ecx, data);
2093 /* MSR write failed? See if we should ask user space */
2094 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2095 complete_fast_msr_access, r))
2097 /* Signal all other negative errors to userspace */
2100 trace_kvm_msr_write_ex(ecx, data);
2103 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2105 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2107 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2109 return kvm_skip_emulated_instruction(vcpu);
2112 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2114 /* Treat an INVD instruction as a NOP and just skip it. */
2115 return kvm_emulate_as_nop(vcpu);
2117 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2119 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2121 kvm_queue_exception(vcpu, UD_VECTOR);
2124 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2127 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2129 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2130 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2131 return kvm_handle_invalid_op(vcpu);
2133 pr_warn_once("%s instruction emulated as NOP!\n", insn);
2134 return kvm_emulate_as_nop(vcpu);
2136 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2138 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2140 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2142 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2144 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2146 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2148 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2150 xfer_to_guest_mode_prepare();
2151 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2152 xfer_to_guest_mode_work_pending();
2156 * The fast path for frequent and performance sensitive wrmsr emulation,
2157 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2158 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2159 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2160 * other cases which must be called after interrupts are enabled on the host.
2162 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2164 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2167 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2168 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2169 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2170 ((u32)(data >> 32) != X2APIC_BROADCAST))
2171 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2176 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2178 if (!kvm_can_use_hv_timer(vcpu))
2181 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2185 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2187 u32 msr = kvm_rcx_read(vcpu);
2189 fastpath_t ret = EXIT_FASTPATH_NONE;
2191 kvm_vcpu_srcu_read_lock(vcpu);
2194 case APIC_BASE_MSR + (APIC_ICR >> 4):
2195 data = kvm_read_edx_eax(vcpu);
2196 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2197 kvm_skip_emulated_instruction(vcpu);
2198 ret = EXIT_FASTPATH_EXIT_HANDLED;
2201 case MSR_IA32_TSC_DEADLINE:
2202 data = kvm_read_edx_eax(vcpu);
2203 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2204 kvm_skip_emulated_instruction(vcpu);
2205 ret = EXIT_FASTPATH_REENTER_GUEST;
2212 if (ret != EXIT_FASTPATH_NONE)
2213 trace_kvm_msr_write(msr, data);
2215 kvm_vcpu_srcu_read_unlock(vcpu);
2219 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2222 * Adapt set_msr() to msr_io()'s calling convention
2224 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2226 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2229 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2234 * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does
2235 * not support modifying the guest vCPU model on the fly, e.g. changing
2236 * the nVMX capabilities while L2 is running is nonsensical. Ignore
2237 * writes of the same value, e.g. to allow userspace to blindly stuff
2238 * all MSRs when emulating RESET.
2240 if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) {
2241 if (do_get_msr(vcpu, index, &val) || *data != val)
2247 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2250 #ifdef CONFIG_X86_64
2251 struct pvclock_clock {
2261 struct pvclock_gtod_data {
2264 struct pvclock_clock clock; /* extract of a clocksource struct */
2265 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2271 static struct pvclock_gtod_data pvclock_gtod_data;
2273 static void update_pvclock_gtod(struct timekeeper *tk)
2275 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2277 write_seqcount_begin(&vdata->seq);
2279 /* copy pvclock gtod data */
2280 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2281 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2282 vdata->clock.mask = tk->tkr_mono.mask;
2283 vdata->clock.mult = tk->tkr_mono.mult;
2284 vdata->clock.shift = tk->tkr_mono.shift;
2285 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2286 vdata->clock.offset = tk->tkr_mono.base;
2288 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2289 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2290 vdata->raw_clock.mask = tk->tkr_raw.mask;
2291 vdata->raw_clock.mult = tk->tkr_raw.mult;
2292 vdata->raw_clock.shift = tk->tkr_raw.shift;
2293 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2294 vdata->raw_clock.offset = tk->tkr_raw.base;
2296 vdata->wall_time_sec = tk->xtime_sec;
2298 vdata->offs_boot = tk->offs_boot;
2300 write_seqcount_end(&vdata->seq);
2303 static s64 get_kvmclock_base_ns(void)
2305 /* Count up from boot time, but with the frequency of the raw clock. */
2306 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2309 static s64 get_kvmclock_base_ns(void)
2311 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2312 return ktime_get_boottime_ns();
2316 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2320 struct pvclock_wall_clock wc;
2327 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2332 ++version; /* first time write, random junk */
2336 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2339 wall_nsec = kvm_get_wall_clock_epoch(kvm);
2341 wc.nsec = do_div(wall_nsec, NSEC_PER_SEC);
2342 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2343 wc.version = version;
2345 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2348 wc_sec_hi = wall_nsec >> 32;
2349 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2350 &wc_sec_hi, sizeof(wc_sec_hi));
2354 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2357 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2358 bool old_msr, bool host_initiated)
2360 struct kvm_arch *ka = &vcpu->kvm->arch;
2362 if (vcpu->vcpu_id == 0 && !host_initiated) {
2363 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2364 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2366 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2369 vcpu->arch.time = system_time;
2370 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2372 /* we verify if the enable bit is set... */
2373 if (system_time & 1)
2374 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2375 sizeof(struct pvclock_vcpu_time_info));
2377 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2382 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2384 do_shl32_div32(dividend, divisor);
2388 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2389 s8 *pshift, u32 *pmultiplier)
2397 scaled64 = scaled_hz;
2398 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2403 tps32 = (uint32_t)tps64;
2404 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2405 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2413 *pmultiplier = div_frac(scaled64, tps32);
2416 #ifdef CONFIG_X86_64
2417 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2420 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2421 static unsigned long max_tsc_khz;
2423 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2425 u64 v = (u64)khz * (1000000 + ppm);
2430 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2432 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2436 /* Guest TSC same frequency as host TSC? */
2438 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2442 /* TSC scaling supported? */
2443 if (!kvm_caps.has_tsc_control) {
2444 if (user_tsc_khz > tsc_khz) {
2445 vcpu->arch.tsc_catchup = 1;
2446 vcpu->arch.tsc_always_catchup = 1;
2449 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2454 /* TSC scaling required - calculate ratio */
2455 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2456 user_tsc_khz, tsc_khz);
2458 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2459 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2464 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2468 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2470 u32 thresh_lo, thresh_hi;
2471 int use_scaling = 0;
2473 /* tsc_khz can be zero if TSC calibration fails */
2474 if (user_tsc_khz == 0) {
2475 /* set tsc_scaling_ratio to a safe value */
2476 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2480 /* Compute a scale to convert nanoseconds in TSC cycles */
2481 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2482 &vcpu->arch.virtual_tsc_shift,
2483 &vcpu->arch.virtual_tsc_mult);
2484 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2487 * Compute the variation in TSC rate which is acceptable
2488 * within the range of tolerance and decide if the
2489 * rate being applied is within that bounds of the hardware
2490 * rate. If so, no scaling or compensation need be done.
2492 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2493 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2494 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2495 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2496 user_tsc_khz, thresh_lo, thresh_hi);
2499 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2502 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2504 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2505 vcpu->arch.virtual_tsc_mult,
2506 vcpu->arch.virtual_tsc_shift);
2507 tsc += vcpu->arch.this_tsc_write;
2511 #ifdef CONFIG_X86_64
2512 static inline bool gtod_is_based_on_tsc(int mode)
2514 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2518 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu, bool new_generation)
2520 #ifdef CONFIG_X86_64
2521 struct kvm_arch *ka = &vcpu->kvm->arch;
2522 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2525 * To use the masterclock, the host clocksource must be based on TSC
2526 * and all vCPUs must have matching TSCs. Note, the count for matching
2527 * vCPUs doesn't include the reference vCPU, hence "+1".
2529 bool use_master_clock = (ka->nr_vcpus_matched_tsc + 1 ==
2530 atomic_read(&vcpu->kvm->online_vcpus)) &&
2531 gtod_is_based_on_tsc(gtod->clock.vclock_mode);
2534 * Request a masterclock update if the masterclock needs to be toggled
2535 * on/off, or when starting a new generation and the masterclock is
2536 * enabled (compute_guest_tsc() requires the masterclock snapshot to be
2537 * taken _after_ the new generation is created).
2539 if ((ka->use_master_clock && new_generation) ||
2540 (ka->use_master_clock != use_master_clock))
2541 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2543 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2544 atomic_read(&vcpu->kvm->online_vcpus),
2545 ka->use_master_clock, gtod->clock.vclock_mode);
2550 * Multiply tsc by a fixed point number represented by ratio.
2552 * The most significant 64-N bits (mult) of ratio represent the
2553 * integral part of the fixed point number; the remaining N bits
2554 * (frac) represent the fractional part, ie. ratio represents a fixed
2555 * point number (mult + frac * 2^(-N)).
2557 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2559 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2561 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2564 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2568 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2569 _tsc = __scale_tsc(ratio, tsc);
2574 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2578 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2580 return target_tsc - tsc;
2583 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2585 return vcpu->arch.l1_tsc_offset +
2586 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2588 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2590 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2594 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2595 nested_offset = l1_offset;
2597 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2598 kvm_caps.tsc_scaling_ratio_frac_bits);
2600 nested_offset += l2_offset;
2601 return nested_offset;
2603 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2605 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2607 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2608 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2609 kvm_caps.tsc_scaling_ratio_frac_bits);
2611 return l1_multiplier;
2613 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2615 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2617 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2618 vcpu->arch.l1_tsc_offset,
2621 vcpu->arch.l1_tsc_offset = l1_offset;
2624 * If we are here because L1 chose not to trap WRMSR to TSC then
2625 * according to the spec this should set L1's TSC (as opposed to
2626 * setting L1's offset for L2).
2628 if (is_guest_mode(vcpu))
2629 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2631 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2632 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2634 vcpu->arch.tsc_offset = l1_offset;
2636 static_call(kvm_x86_write_tsc_offset)(vcpu);
2639 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2641 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2643 /* Userspace is changing the multiplier while L2 is active */
2644 if (is_guest_mode(vcpu))
2645 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2647 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2649 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2651 if (kvm_caps.has_tsc_control)
2652 static_call(kvm_x86_write_tsc_multiplier)(vcpu);
2655 static inline bool kvm_check_tsc_unstable(void)
2657 #ifdef CONFIG_X86_64
2659 * TSC is marked unstable when we're running on Hyper-V,
2660 * 'TSC page' clocksource is good.
2662 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2665 return check_tsc_unstable();
2669 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2670 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2673 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2674 u64 ns, bool matched)
2676 struct kvm *kvm = vcpu->kvm;
2678 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2681 * We also track th most recent recorded KHZ, write and time to
2682 * allow the matching interval to be extended at each write.
2684 kvm->arch.last_tsc_nsec = ns;
2685 kvm->arch.last_tsc_write = tsc;
2686 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2687 kvm->arch.last_tsc_offset = offset;
2689 vcpu->arch.last_guest_tsc = tsc;
2691 kvm_vcpu_write_tsc_offset(vcpu, offset);
2695 * We split periods of matched TSC writes into generations.
2696 * For each generation, we track the original measured
2697 * nanosecond time, offset, and write, so if TSCs are in
2698 * sync, we can match exact offset, and if not, we can match
2699 * exact software computation in compute_guest_tsc()
2701 * These values are tracked in kvm->arch.cur_xxx variables.
2703 kvm->arch.cur_tsc_generation++;
2704 kvm->arch.cur_tsc_nsec = ns;
2705 kvm->arch.cur_tsc_write = tsc;
2706 kvm->arch.cur_tsc_offset = offset;
2707 kvm->arch.nr_vcpus_matched_tsc = 0;
2708 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2709 kvm->arch.nr_vcpus_matched_tsc++;
2712 /* Keep track of which generation this VCPU has synchronized to */
2713 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2714 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2715 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2717 kvm_track_tsc_matching(vcpu, !matched);
2720 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 *user_value)
2722 u64 data = user_value ? *user_value : 0;
2723 struct kvm *kvm = vcpu->kvm;
2724 u64 offset, ns, elapsed;
2725 unsigned long flags;
2726 bool matched = false;
2727 bool synchronizing = false;
2729 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2730 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2731 ns = get_kvmclock_base_ns();
2732 elapsed = ns - kvm->arch.last_tsc_nsec;
2734 if (vcpu->arch.virtual_tsc_khz) {
2737 * Force synchronization when creating a vCPU, or when
2738 * userspace explicitly writes a zero value.
2740 synchronizing = true;
2741 } else if (kvm->arch.user_set_tsc) {
2742 u64 tsc_exp = kvm->arch.last_tsc_write +
2743 nsec_to_cycles(vcpu, elapsed);
2744 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2746 * Here lies UAPI baggage: when a user-initiated TSC write has
2747 * a small delta (1 second) of virtual cycle time against the
2748 * previously set vCPU, we assume that they were intended to be
2749 * in sync and the delta was only due to the racy nature of the
2752 * This trick falls down when restoring a guest which genuinely
2753 * has been running for less time than the 1 second of imprecision
2754 * which we allow for in the legacy API. In this case, the first
2755 * value written by userspace (on any vCPU) should not be subject
2756 * to this 'correction' to make it sync up with values that only
2757 * come from the kernel's default vCPU creation. Make the 1-second
2758 * slop hack only trigger if the user_set_tsc flag is already set.
2760 synchronizing = data < tsc_exp + tsc_hz &&
2761 data + tsc_hz > tsc_exp;
2766 kvm->arch.user_set_tsc = true;
2769 * For a reliable TSC, we can match TSC offsets, and for an unstable
2770 * TSC, we add elapsed time in this computation. We could let the
2771 * compensation code attempt to catch up if we fall behind, but
2772 * it's better to try to match offsets from the beginning.
2774 if (synchronizing &&
2775 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2776 if (!kvm_check_tsc_unstable()) {
2777 offset = kvm->arch.cur_tsc_offset;
2779 u64 delta = nsec_to_cycles(vcpu, elapsed);
2781 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2786 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2787 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2790 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2793 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2794 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2797 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2799 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2800 WARN_ON(adjustment < 0);
2801 adjustment = kvm_scale_tsc((u64) adjustment,
2802 vcpu->arch.l1_tsc_scaling_ratio);
2803 adjust_tsc_offset_guest(vcpu, adjustment);
2806 #ifdef CONFIG_X86_64
2808 static u64 read_tsc(void)
2810 u64 ret = (u64)rdtsc_ordered();
2811 u64 last = pvclock_gtod_data.clock.cycle_last;
2813 if (likely(ret >= last))
2817 * GCC likes to generate cmov here, but this branch is extremely
2818 * predictable (it's just a function of time and the likely is
2819 * very likely) and there's a data dependence, so force GCC
2820 * to generate a branch instead. I don't barrier() because
2821 * we don't actually need a barrier, and if this function
2822 * ever gets inlined it will generate worse code.
2828 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2834 switch (clock->vclock_mode) {
2835 case VDSO_CLOCKMODE_HVCLOCK:
2836 if (hv_read_tsc_page_tsc(hv_get_tsc_page(),
2837 tsc_timestamp, &tsc_pg_val)) {
2838 /* TSC page valid */
2839 *mode = VDSO_CLOCKMODE_HVCLOCK;
2840 v = (tsc_pg_val - clock->cycle_last) &
2843 /* TSC page invalid */
2844 *mode = VDSO_CLOCKMODE_NONE;
2847 case VDSO_CLOCKMODE_TSC:
2848 *mode = VDSO_CLOCKMODE_TSC;
2849 *tsc_timestamp = read_tsc();
2850 v = (*tsc_timestamp - clock->cycle_last) &
2854 *mode = VDSO_CLOCKMODE_NONE;
2857 if (*mode == VDSO_CLOCKMODE_NONE)
2858 *tsc_timestamp = v = 0;
2860 return v * clock->mult;
2863 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2865 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2871 seq = read_seqcount_begin(>od->seq);
2872 ns = gtod->raw_clock.base_cycles;
2873 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2874 ns >>= gtod->raw_clock.shift;
2875 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2876 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2882 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2884 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2890 seq = read_seqcount_begin(>od->seq);
2891 ts->tv_sec = gtod->wall_time_sec;
2892 ns = gtod->clock.base_cycles;
2893 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2894 ns >>= gtod->clock.shift;
2895 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2897 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2903 /* returns true if host is using TSC based clocksource */
2904 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2906 /* checked again under seqlock below */
2907 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2910 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2914 /* returns true if host is using TSC based clocksource */
2915 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2918 /* checked again under seqlock below */
2919 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2922 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2928 * Assuming a stable TSC across physical CPUS, and a stable TSC
2929 * across virtual CPUs, the following condition is possible.
2930 * Each numbered line represents an event visible to both
2931 * CPUs at the next numbered event.
2933 * "timespecX" represents host monotonic time. "tscX" represents
2936 * VCPU0 on CPU0 | VCPU1 on CPU1
2938 * 1. read timespec0,tsc0
2939 * 2. | timespec1 = timespec0 + N
2941 * 3. transition to guest | transition to guest
2942 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2943 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2944 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2946 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2949 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2951 * - 0 < N - M => M < N
2953 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2954 * always the case (the difference between two distinct xtime instances
2955 * might be smaller then the difference between corresponding TSC reads,
2956 * when updating guest vcpus pvclock areas).
2958 * To avoid that problem, do not allow visibility of distinct
2959 * system_timestamp/tsc_timestamp values simultaneously: use a master
2960 * copy of host monotonic time values. Update that master copy
2963 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2967 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2969 #ifdef CONFIG_X86_64
2970 struct kvm_arch *ka = &kvm->arch;
2972 bool host_tsc_clocksource, vcpus_matched;
2974 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2975 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2976 atomic_read(&kvm->online_vcpus));
2979 * If the host uses TSC clock, then passthrough TSC as stable
2982 host_tsc_clocksource = kvm_get_time_and_clockread(
2983 &ka->master_kernel_ns,
2984 &ka->master_cycle_now);
2986 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2987 && !ka->backwards_tsc_observed
2988 && !ka->boot_vcpu_runs_old_kvmclock;
2990 if (ka->use_master_clock)
2991 atomic_set(&kvm_guest_has_master_clock, 1);
2993 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2994 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2999 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
3001 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
3004 static void __kvm_start_pvclock_update(struct kvm *kvm)
3006 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
3007 write_seqcount_begin(&kvm->arch.pvclock_sc);
3010 static void kvm_start_pvclock_update(struct kvm *kvm)
3012 kvm_make_mclock_inprogress_request(kvm);
3014 /* no guest entries from this point */
3015 __kvm_start_pvclock_update(kvm);
3018 static void kvm_end_pvclock_update(struct kvm *kvm)
3020 struct kvm_arch *ka = &kvm->arch;
3021 struct kvm_vcpu *vcpu;
3024 write_seqcount_end(&ka->pvclock_sc);
3025 raw_spin_unlock_irq(&ka->tsc_write_lock);
3026 kvm_for_each_vcpu(i, vcpu, kvm)
3027 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3029 /* guest entries allowed */
3030 kvm_for_each_vcpu(i, vcpu, kvm)
3031 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
3034 static void kvm_update_masterclock(struct kvm *kvm)
3036 kvm_hv_request_tsc_page_update(kvm);
3037 kvm_start_pvclock_update(kvm);
3038 pvclock_update_vm_gtod_copy(kvm);
3039 kvm_end_pvclock_update(kvm);
3043 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
3044 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
3045 * can change during boot even if the TSC is constant, as it's possible for KVM
3046 * to be loaded before TSC calibration completes. Ideally, KVM would get a
3047 * notification when calibration completes, but practically speaking calibration
3048 * will complete before userspace is alive enough to create VMs.
3050 static unsigned long get_cpu_tsc_khz(void)
3052 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3055 return __this_cpu_read(cpu_tsc_khz);
3058 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
3059 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3061 struct kvm_arch *ka = &kvm->arch;
3062 struct pvclock_vcpu_time_info hv_clock;
3064 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
3068 if (ka->use_master_clock &&
3069 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3070 #ifdef CONFIG_X86_64
3071 struct timespec64 ts;
3073 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3074 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3075 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3078 data->host_tsc = rdtsc();
3080 data->flags |= KVM_CLOCK_TSC_STABLE;
3081 hv_clock.tsc_timestamp = ka->master_cycle_now;
3082 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3083 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3084 &hv_clock.tsc_shift,
3085 &hv_clock.tsc_to_system_mul);
3086 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3088 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3094 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3096 struct kvm_arch *ka = &kvm->arch;
3100 seq = read_seqcount_begin(&ka->pvclock_sc);
3101 __get_kvmclock(kvm, data);
3102 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3105 u64 get_kvmclock_ns(struct kvm *kvm)
3107 struct kvm_clock_data data;
3109 get_kvmclock(kvm, &data);
3113 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3114 struct gfn_to_pfn_cache *gpc,
3115 unsigned int offset,
3116 bool force_tsc_unstable)
3118 struct kvm_vcpu_arch *vcpu = &v->arch;
3119 struct pvclock_vcpu_time_info *guest_hv_clock;
3120 unsigned long flags;
3122 read_lock_irqsave(&gpc->lock, flags);
3123 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3124 read_unlock_irqrestore(&gpc->lock, flags);
3126 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3129 read_lock_irqsave(&gpc->lock, flags);
3132 guest_hv_clock = (void *)(gpc->khva + offset);
3135 * This VCPU is paused, but it's legal for a guest to read another
3136 * VCPU's kvmclock, so we really have to follow the specification where
3137 * it says that version is odd if data is being modified, and even after
3141 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3144 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3145 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3147 if (vcpu->pvclock_set_guest_stopped_request) {
3148 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3149 vcpu->pvclock_set_guest_stopped_request = false;
3152 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3154 if (force_tsc_unstable)
3155 guest_hv_clock->flags &= ~PVCLOCK_TSC_STABLE_BIT;
3159 guest_hv_clock->version = ++vcpu->hv_clock.version;
3161 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3162 read_unlock_irqrestore(&gpc->lock, flags);
3164 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3167 static int kvm_guest_time_update(struct kvm_vcpu *v)
3169 unsigned long flags, tgt_tsc_khz;
3171 struct kvm_vcpu_arch *vcpu = &v->arch;
3172 struct kvm_arch *ka = &v->kvm->arch;
3174 u64 tsc_timestamp, host_tsc;
3176 bool use_master_clock;
3177 #ifdef CONFIG_KVM_XEN
3179 * For Xen guests we may need to override PVCLOCK_TSC_STABLE_BIT as unless
3180 * explicitly told to use TSC as its clocksource Xen will not set this bit.
3181 * This default behaviour led to bugs in some guest kernels which cause
3182 * problems if they observe PVCLOCK_TSC_STABLE_BIT in the pvclock flags.
3184 bool xen_pvclock_tsc_unstable =
3185 ka->xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE;
3192 * If the host uses TSC clock, then passthrough TSC as stable
3196 seq = read_seqcount_begin(&ka->pvclock_sc);
3197 use_master_clock = ka->use_master_clock;
3198 if (use_master_clock) {
3199 host_tsc = ka->master_cycle_now;
3200 kernel_ns = ka->master_kernel_ns;
3202 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3204 /* Keep irq disabled to prevent changes to the clock */
3205 local_irq_save(flags);
3206 tgt_tsc_khz = get_cpu_tsc_khz();
3207 if (unlikely(tgt_tsc_khz == 0)) {
3208 local_irq_restore(flags);
3209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3212 if (!use_master_clock) {
3214 kernel_ns = get_kvmclock_base_ns();
3217 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3220 * We may have to catch up the TSC to match elapsed wall clock
3221 * time for two reasons, even if kvmclock is used.
3222 * 1) CPU could have been running below the maximum TSC rate
3223 * 2) Broken TSC compensation resets the base at each VCPU
3224 * entry to avoid unknown leaps of TSC even when running
3225 * again on the same CPU. This may cause apparent elapsed
3226 * time to disappear, and the guest to stand still or run
3229 if (vcpu->tsc_catchup) {
3230 u64 tsc = compute_guest_tsc(v, kernel_ns);
3231 if (tsc > tsc_timestamp) {
3232 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3233 tsc_timestamp = tsc;
3237 local_irq_restore(flags);
3239 /* With all the info we got, fill in the values */
3241 if (kvm_caps.has_tsc_control)
3242 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3243 v->arch.l1_tsc_scaling_ratio);
3245 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3246 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3247 &vcpu->hv_clock.tsc_shift,
3248 &vcpu->hv_clock.tsc_to_system_mul);
3249 vcpu->hw_tsc_khz = tgt_tsc_khz;
3250 kvm_xen_update_tsc_info(v);
3253 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3254 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3255 vcpu->last_guest_tsc = tsc_timestamp;
3257 /* If the host uses TSC clocksource, then it is stable */
3259 if (use_master_clock)
3260 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3262 vcpu->hv_clock.flags = pvclock_flags;
3264 if (vcpu->pv_time.active)
3265 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0, false);
3266 #ifdef CONFIG_KVM_XEN
3267 if (vcpu->xen.vcpu_info_cache.active)
3268 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3269 offsetof(struct compat_vcpu_info, time),
3270 xen_pvclock_tsc_unstable);
3271 if (vcpu->xen.vcpu_time_info_cache.active)
3272 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0,
3273 xen_pvclock_tsc_unstable);
3275 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3280 * The pvclock_wall_clock ABI tells the guest the wall clock time at
3281 * which it started (i.e. its epoch, when its kvmclock was zero).
3283 * In fact those clocks are subtly different; wall clock frequency is
3284 * adjusted by NTP and has leap seconds, while the kvmclock is a
3285 * simple function of the TSC without any such adjustment.
3287 * Perhaps the ABI should have exposed CLOCK_TAI and a ratio between
3288 * that and kvmclock, but even that would be subject to change over
3291 * Attempt to calculate the epoch at a given moment using the *same*
3292 * TSC reading via kvm_get_walltime_and_clockread() to obtain both
3293 * wallclock and kvmclock times, and subtracting one from the other.
3295 * Fall back to using their values at slightly different moments by
3296 * calling ktime_get_real_ns() and get_kvmclock_ns() separately.
3298 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm)
3300 #ifdef CONFIG_X86_64
3301 struct pvclock_vcpu_time_info hv_clock;
3302 struct kvm_arch *ka = &kvm->arch;
3303 unsigned long seq, local_tsc_khz;
3304 struct timespec64 ts;
3308 seq = read_seqcount_begin(&ka->pvclock_sc);
3311 if (!ka->use_master_clock)
3315 * The TSC read and the call to get_cpu_tsc_khz() must happen
3320 local_tsc_khz = get_cpu_tsc_khz();
3322 if (local_tsc_khz &&
3323 !kvm_get_walltime_and_clockread(&ts, &host_tsc))
3324 local_tsc_khz = 0; /* Fall back to old method */
3329 * These values must be snapshotted within the seqcount loop.
3330 * After that, it's just mathematics which can happen on any
3333 hv_clock.tsc_timestamp = ka->master_cycle_now;
3334 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3336 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3339 * If the conditions were right, and obtaining the wallclock+TSC was
3340 * successful, calculate the KVM clock at the corresponding time and
3341 * subtract one from the other to get the guest's epoch in nanoseconds
3344 if (local_tsc_khz) {
3345 kvm_get_time_scale(NSEC_PER_SEC, local_tsc_khz * NSEC_PER_USEC,
3346 &hv_clock.tsc_shift,
3347 &hv_clock.tsc_to_system_mul);
3348 return ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec -
3349 __pvclock_read_cycles(&hv_clock, host_tsc);
3352 return ktime_get_real_ns() - get_kvmclock_ns(kvm);
3356 * kvmclock updates which are isolated to a given vcpu, such as
3357 * vcpu->cpu migration, should not allow system_timestamp from
3358 * the rest of the vcpus to remain static. Otherwise ntp frequency
3359 * correction applies to one vcpu's system_timestamp but not
3362 * So in those cases, request a kvmclock update for all vcpus.
3363 * We need to rate-limit these requests though, as they can
3364 * considerably slow guests that have a large number of vcpus.
3365 * The time for a remote vcpu to update its kvmclock is bound
3366 * by the delay we use to rate-limit the updates.
3369 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3371 static void kvmclock_update_fn(struct work_struct *work)
3374 struct delayed_work *dwork = to_delayed_work(work);
3375 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3376 kvmclock_update_work);
3377 struct kvm *kvm = container_of(ka, struct kvm, arch);
3378 struct kvm_vcpu *vcpu;
3380 kvm_for_each_vcpu(i, vcpu, kvm) {
3381 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3382 kvm_vcpu_kick(vcpu);
3386 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3388 struct kvm *kvm = v->kvm;
3390 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3391 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3392 KVMCLOCK_UPDATE_DELAY);
3395 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3397 static void kvmclock_sync_fn(struct work_struct *work)
3399 struct delayed_work *dwork = to_delayed_work(work);
3400 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3401 kvmclock_sync_work);
3402 struct kvm *kvm = container_of(ka, struct kvm, arch);
3404 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3405 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3406 KVMCLOCK_SYNC_PERIOD);
3409 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3410 static bool is_mci_control_msr(u32 msr)
3412 return (msr & 3) == 0;
3414 static bool is_mci_status_msr(u32 msr)
3416 return (msr & 3) == 1;
3420 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3422 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3424 /* McStatusWrEn enabled? */
3425 if (guest_cpuid_is_amd_or_hygon(vcpu))
3426 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3431 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3433 u64 mcg_cap = vcpu->arch.mcg_cap;
3434 unsigned bank_num = mcg_cap & 0xff;
3435 u32 msr = msr_info->index;
3436 u64 data = msr_info->data;
3437 u32 offset, last_msr;
3440 case MSR_IA32_MCG_STATUS:
3441 vcpu->arch.mcg_status = data;
3443 case MSR_IA32_MCG_CTL:
3444 if (!(mcg_cap & MCG_CTL_P) &&
3445 (data || !msr_info->host_initiated))
3447 if (data != 0 && data != ~(u64)0)
3449 vcpu->arch.mcg_ctl = data;
3451 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3452 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3456 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3458 /* An attempt to write a 1 to a reserved bit raises #GP */
3459 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3461 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3462 last_msr + 1 - MSR_IA32_MC0_CTL2);
3463 vcpu->arch.mci_ctl2_banks[offset] = data;
3465 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3466 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3471 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3472 * values are architecturally undefined. But, some Linux
3473 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3474 * issue on AMD K8s, allow bit 10 to be clear when setting all
3475 * other bits in order to avoid an uncaught #GP in the guest.
3477 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3478 * single-bit ECC data errors.
3480 if (is_mci_control_msr(msr) &&
3481 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3485 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3486 * AMD-based CPUs allow non-zero values, but if and only if
3487 * HWCR[McStatusWrEn] is set.
3489 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3490 data != 0 && !can_set_mci_status(vcpu))
3493 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3494 last_msr + 1 - MSR_IA32_MC0_CTL);
3495 vcpu->arch.mce_banks[offset] = data;
3503 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3505 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3507 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3510 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3512 gpa_t gpa = data & ~0x3f;
3514 /* Bits 4:5 are reserved, Should be zero */
3518 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3519 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3522 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3523 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3526 if (!lapic_in_kernel(vcpu))
3527 return data ? 1 : 0;
3529 vcpu->arch.apf.msr_en_val = data;
3531 if (!kvm_pv_async_pf_enabled(vcpu)) {
3532 kvm_clear_async_pf_completion_queue(vcpu);
3533 kvm_async_pf_hash_reset(vcpu);
3537 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3541 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3542 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3544 kvm_async_pf_wakeup_all(vcpu);
3549 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3551 /* Bits 8-63 are reserved */
3555 if (!lapic_in_kernel(vcpu))
3558 vcpu->arch.apf.msr_int_val = data;
3560 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3565 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3567 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3568 vcpu->arch.time = 0;
3571 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3573 ++vcpu->stat.tlb_flush;
3574 static_call(kvm_x86_flush_tlb_all)(vcpu);
3576 /* Flushing all ASIDs flushes the current ASID... */
3577 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3580 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3582 ++vcpu->stat.tlb_flush;
3586 * A TLB flush on behalf of the guest is equivalent to
3587 * INVPCID(all), toggling CR4.PGE, etc., which requires
3588 * a forced sync of the shadow page tables. Ensure all the
3589 * roots are synced and the guest TLB in hardware is clean.
3591 kvm_mmu_sync_roots(vcpu);
3592 kvm_mmu_sync_prev_roots(vcpu);
3595 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3598 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3601 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3605 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3607 ++vcpu->stat.tlb_flush;
3608 static_call(kvm_x86_flush_tlb_current)(vcpu);
3612 * Service "local" TLB flush requests, which are specific to the current MMU
3613 * context. In addition to the generic event handling in vcpu_enter_guest(),
3614 * TLB flushes that are targeted at an MMU context also need to be serviced
3615 * prior before nested VM-Enter/VM-Exit.
3617 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3619 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3620 kvm_vcpu_flush_tlb_current(vcpu);
3622 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3623 kvm_vcpu_flush_tlb_guest(vcpu);
3625 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3627 static void record_steal_time(struct kvm_vcpu *vcpu)
3629 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3630 struct kvm_steal_time __user *st;
3631 struct kvm_memslots *slots;
3632 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3636 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3637 kvm_xen_runstate_set_running(vcpu);
3641 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3644 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3647 slots = kvm_memslots(vcpu->kvm);
3649 if (unlikely(slots->generation != ghc->generation ||
3651 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3652 /* We rely on the fact that it fits in a single page. */
3653 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3655 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3656 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3660 st = (struct kvm_steal_time __user *)ghc->hva;
3662 * Doing a TLB flush here, on the guest's behalf, can avoid
3665 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3666 u8 st_preempted = 0;
3669 if (!user_access_begin(st, sizeof(*st)))
3672 asm volatile("1: xchgb %0, %2\n"
3675 _ASM_EXTABLE_UA(1b, 2b)
3676 : "+q" (st_preempted),
3678 "+m" (st->preempted));
3684 vcpu->arch.st.preempted = 0;
3686 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3687 st_preempted & KVM_VCPU_FLUSH_TLB);
3688 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3689 kvm_vcpu_flush_tlb_guest(vcpu);
3691 if (!user_access_begin(st, sizeof(*st)))
3694 if (!user_access_begin(st, sizeof(*st)))
3697 unsafe_put_user(0, &st->preempted, out);
3698 vcpu->arch.st.preempted = 0;
3701 unsafe_get_user(version, &st->version, out);
3703 version += 1; /* first time write, random junk */
3706 unsafe_put_user(version, &st->version, out);
3710 unsafe_get_user(steal, &st->steal, out);
3711 steal += current->sched_info.run_delay -
3712 vcpu->arch.st.last_steal;
3713 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3714 unsafe_put_user(steal, &st->steal, out);
3717 unsafe_put_user(version, &st->version, out);
3722 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3725 static bool kvm_is_msr_to_save(u32 msr_index)
3729 for (i = 0; i < num_msrs_to_save; i++) {
3730 if (msrs_to_save[i] == msr_index)
3737 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3739 u32 msr = msr_info->index;
3740 u64 data = msr_info->data;
3742 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3743 return kvm_xen_write_hypercall_page(vcpu, data);
3746 case MSR_AMD64_NB_CFG:
3747 case MSR_IA32_UCODE_WRITE:
3748 case MSR_VM_HSAVE_PA:
3749 case MSR_AMD64_PATCH_LOADER:
3750 case MSR_AMD64_BU_CFG2:
3751 case MSR_AMD64_DC_CFG:
3752 case MSR_AMD64_TW_CFG:
3753 case MSR_F15H_EX_CFG:
3756 case MSR_IA32_UCODE_REV:
3757 if (msr_info->host_initiated)
3758 vcpu->arch.microcode_version = data;
3760 case MSR_IA32_ARCH_CAPABILITIES:
3761 if (!msr_info->host_initiated)
3763 vcpu->arch.arch_capabilities = data;
3765 case MSR_IA32_PERF_CAPABILITIES:
3766 if (!msr_info->host_initiated)
3768 if (data & ~kvm_caps.supported_perf_cap)
3772 * Note, this is not just a performance optimization! KVM
3773 * disallows changing feature MSRs after the vCPU has run; PMU
3774 * refresh will bug the VM if called after the vCPU has run.
3776 if (vcpu->arch.perf_capabilities == data)
3779 vcpu->arch.perf_capabilities = data;
3780 kvm_pmu_refresh(vcpu);
3782 case MSR_IA32_PRED_CMD: {
3783 u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB);
3785 if (!msr_info->host_initiated) {
3786 if ((!guest_has_pred_cmd_msr(vcpu)))
3789 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
3790 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
3791 reserved_bits |= PRED_CMD_IBPB;
3793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SBPB))
3794 reserved_bits |= PRED_CMD_SBPB;
3797 if (!boot_cpu_has(X86_FEATURE_IBPB))
3798 reserved_bits |= PRED_CMD_IBPB;
3800 if (!boot_cpu_has(X86_FEATURE_SBPB))
3801 reserved_bits |= PRED_CMD_SBPB;
3803 if (data & reserved_bits)
3809 wrmsrl(MSR_IA32_PRED_CMD, data);
3812 case MSR_IA32_FLUSH_CMD:
3813 if (!msr_info->host_initiated &&
3814 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3817 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3822 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3825 return set_efer(vcpu, msr_info);
3827 data &= ~(u64)0x40; /* ignore flush filter disable */
3828 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3829 data &= ~(u64)0x8; /* ignore TLB cache disable */
3832 * Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2
3833 * through at least v6.6 whine if TscFreqSel is clear,
3834 * depending on F/M/S.
3836 if (data & ~(BIT_ULL(18) | BIT_ULL(24))) {
3837 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3840 vcpu->arch.msr_hwcr = data;
3842 case MSR_FAM10H_MMIO_CONF_BASE:
3844 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3848 case MSR_IA32_CR_PAT:
3849 if (!kvm_pat_valid(data))
3852 vcpu->arch.pat = data;
3854 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
3855 case MSR_MTRRdefType:
3856 return kvm_mtrr_set_msr(vcpu, msr, data);
3857 case MSR_IA32_APICBASE:
3858 return kvm_set_apic_base(vcpu, msr_info);
3859 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3860 return kvm_x2apic_msr_write(vcpu, msr, data);
3861 case MSR_IA32_TSC_DEADLINE:
3862 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3864 case MSR_IA32_TSC_ADJUST:
3865 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3866 if (!msr_info->host_initiated) {
3867 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3868 adjust_tsc_offset_guest(vcpu, adj);
3869 /* Before back to guest, tsc_timestamp must be adjusted
3870 * as well, otherwise guest's percpu pvclock time could jump.
3872 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3874 vcpu->arch.ia32_tsc_adjust_msr = data;
3877 case MSR_IA32_MISC_ENABLE: {
3878 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3880 if (!msr_info->host_initiated) {
3882 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3885 /* R bits, i.e. writes are ignored, but don't fault. */
3886 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3887 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3890 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3891 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3892 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3894 vcpu->arch.ia32_misc_enable_msr = data;
3895 kvm_update_cpuid_runtime(vcpu);
3897 vcpu->arch.ia32_misc_enable_msr = data;
3901 case MSR_IA32_SMBASE:
3902 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3904 vcpu->arch.smbase = data;
3906 case MSR_IA32_POWER_CTL:
3907 vcpu->arch.msr_ia32_power_ctl = data;
3910 if (msr_info->host_initiated) {
3911 kvm_synchronize_tsc(vcpu, &data);
3913 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3914 adjust_tsc_offset_guest(vcpu, adj);
3915 vcpu->arch.ia32_tsc_adjust_msr += adj;
3919 if (!msr_info->host_initiated &&
3920 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3923 * KVM supports exposing PT to the guest, but does not support
3924 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3925 * XSAVES/XRSTORS to save/restore PT MSRs.
3927 if (data & ~kvm_caps.supported_xss)
3929 vcpu->arch.ia32_xss = data;
3930 kvm_update_cpuid_runtime(vcpu);
3933 if (!msr_info->host_initiated)
3935 vcpu->arch.smi_count = data;
3937 case MSR_KVM_WALL_CLOCK_NEW:
3938 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3941 vcpu->kvm->arch.wall_clock = data;
3942 kvm_write_wall_clock(vcpu->kvm, data, 0);
3944 case MSR_KVM_WALL_CLOCK:
3945 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3948 vcpu->kvm->arch.wall_clock = data;
3949 kvm_write_wall_clock(vcpu->kvm, data, 0);
3951 case MSR_KVM_SYSTEM_TIME_NEW:
3952 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3955 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3957 case MSR_KVM_SYSTEM_TIME:
3958 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3961 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3963 case MSR_KVM_ASYNC_PF_EN:
3964 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3967 if (kvm_pv_enable_async_pf(vcpu, data))
3970 case MSR_KVM_ASYNC_PF_INT:
3971 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3974 if (kvm_pv_enable_async_pf_int(vcpu, data))
3977 case MSR_KVM_ASYNC_PF_ACK:
3978 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3981 vcpu->arch.apf.pageready_pending = false;
3982 kvm_check_async_pf_completion(vcpu);
3985 case MSR_KVM_STEAL_TIME:
3986 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3989 if (unlikely(!sched_info_on()))
3992 if (data & KVM_STEAL_RESERVED_MASK)
3995 vcpu->arch.st.msr_val = data;
3997 if (!(data & KVM_MSR_ENABLED))
4000 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4003 case MSR_KVM_PV_EOI_EN:
4004 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4007 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
4011 case MSR_KVM_POLL_CONTROL:
4012 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4015 /* only enable bit supported */
4016 if (data & (-1ULL << 1))
4019 vcpu->arch.msr_kvm_poll_control = data;
4022 case MSR_IA32_MCG_CTL:
4023 case MSR_IA32_MCG_STATUS:
4024 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4025 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4026 return set_msr_mce(vcpu, msr_info);
4028 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4029 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4030 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4031 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4032 if (kvm_pmu_is_valid_msr(vcpu, msr))
4033 return kvm_pmu_set_msr(vcpu, msr_info);
4036 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
4038 case MSR_K7_CLK_CTL:
4040 * Ignore all writes to this no longer documented MSR.
4041 * Writes are only relevant for old K7 processors,
4042 * all pre-dating SVM, but a recommended workaround from
4043 * AMD for these chips. It is possible to specify the
4044 * affected processor models on the command line, hence
4045 * the need to ignore the workaround.
4048 #ifdef CONFIG_KVM_HYPERV
4049 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4050 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4051 case HV_X64_MSR_SYNDBG_OPTIONS:
4052 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4053 case HV_X64_MSR_CRASH_CTL:
4054 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4055 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4056 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4057 case HV_X64_MSR_TSC_EMULATION_STATUS:
4058 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4059 return kvm_hv_set_msr_common(vcpu, msr, data,
4060 msr_info->host_initiated);
4062 case MSR_IA32_BBL_CR_CTL3:
4063 /* Drop writes to this legacy MSR -- see rdmsr
4064 * counterpart for further detail.
4066 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
4068 case MSR_AMD64_OSVW_ID_LENGTH:
4069 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4071 vcpu->arch.osvw.length = data;
4073 case MSR_AMD64_OSVW_STATUS:
4074 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4076 vcpu->arch.osvw.status = data;
4078 case MSR_PLATFORM_INFO:
4079 if (!msr_info->host_initiated ||
4080 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
4081 cpuid_fault_enabled(vcpu)))
4083 vcpu->arch.msr_platform_info = data;
4085 case MSR_MISC_FEATURES_ENABLES:
4086 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
4087 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
4088 !supports_cpuid_fault(vcpu)))
4090 vcpu->arch.msr_misc_features_enables = data;
4092 #ifdef CONFIG_X86_64
4094 if (!msr_info->host_initiated &&
4095 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4098 if (data & ~kvm_guest_supported_xfd(vcpu))
4101 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
4103 case MSR_IA32_XFD_ERR:
4104 if (!msr_info->host_initiated &&
4105 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4108 if (data & ~kvm_guest_supported_xfd(vcpu))
4111 vcpu->arch.guest_fpu.xfd_err = data;
4115 if (kvm_pmu_is_valid_msr(vcpu, msr))
4116 return kvm_pmu_set_msr(vcpu, msr_info);
4119 * Userspace is allowed to write '0' to MSRs that KVM reports
4120 * as to-be-saved, even if an MSRs isn't fully supported.
4122 if (msr_info->host_initiated && !data &&
4123 kvm_is_msr_to_save(msr))
4126 return KVM_MSR_RET_INVALID;
4130 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
4132 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
4135 u64 mcg_cap = vcpu->arch.mcg_cap;
4136 unsigned bank_num = mcg_cap & 0xff;
4137 u32 offset, last_msr;
4140 case MSR_IA32_P5_MC_ADDR:
4141 case MSR_IA32_P5_MC_TYPE:
4144 case MSR_IA32_MCG_CAP:
4145 data = vcpu->arch.mcg_cap;
4147 case MSR_IA32_MCG_CTL:
4148 if (!(mcg_cap & MCG_CTL_P) && !host)
4150 data = vcpu->arch.mcg_ctl;
4152 case MSR_IA32_MCG_STATUS:
4153 data = vcpu->arch.mcg_status;
4155 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4156 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
4160 if (!(mcg_cap & MCG_CMCI_P) && !host)
4162 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
4163 last_msr + 1 - MSR_IA32_MC0_CTL2);
4164 data = vcpu->arch.mci_ctl2_banks[offset];
4166 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4167 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
4171 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
4172 last_msr + 1 - MSR_IA32_MC0_CTL);
4173 data = vcpu->arch.mce_banks[offset];
4182 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4184 switch (msr_info->index) {
4185 case MSR_IA32_PLATFORM_ID:
4186 case MSR_IA32_EBL_CR_POWERON:
4187 case MSR_IA32_LASTBRANCHFROMIP:
4188 case MSR_IA32_LASTBRANCHTOIP:
4189 case MSR_IA32_LASTINTFROMIP:
4190 case MSR_IA32_LASTINTTOIP:
4191 case MSR_AMD64_SYSCFG:
4192 case MSR_K8_TSEG_ADDR:
4193 case MSR_K8_TSEG_MASK:
4194 case MSR_VM_HSAVE_PA:
4195 case MSR_K8_INT_PENDING_MSG:
4196 case MSR_AMD64_NB_CFG:
4197 case MSR_FAM10H_MMIO_CONF_BASE:
4198 case MSR_AMD64_BU_CFG2:
4199 case MSR_IA32_PERF_CTL:
4200 case MSR_AMD64_DC_CFG:
4201 case MSR_AMD64_TW_CFG:
4202 case MSR_F15H_EX_CFG:
4204 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4205 * limit) MSRs. Just return 0, as we do not want to expose the host
4206 * data here. Do not conditionalize this on CPUID, as KVM does not do
4207 * so for existing CPU-specific MSRs.
4209 case MSR_RAPL_POWER_UNIT:
4210 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
4211 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
4212 case MSR_PKG_ENERGY_STATUS: /* Total package */
4213 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
4216 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4217 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4218 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4219 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4220 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4221 return kvm_pmu_get_msr(vcpu, msr_info);
4224 case MSR_IA32_UCODE_REV:
4225 msr_info->data = vcpu->arch.microcode_version;
4227 case MSR_IA32_ARCH_CAPABILITIES:
4228 if (!msr_info->host_initiated &&
4229 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4231 msr_info->data = vcpu->arch.arch_capabilities;
4233 case MSR_IA32_PERF_CAPABILITIES:
4234 if (!msr_info->host_initiated &&
4235 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4237 msr_info->data = vcpu->arch.perf_capabilities;
4239 case MSR_IA32_POWER_CTL:
4240 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4242 case MSR_IA32_TSC: {
4244 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4245 * even when not intercepted. AMD manual doesn't explicitly
4246 * state this but appears to behave the same.
4248 * On userspace reads and writes, however, we unconditionally
4249 * return L1's TSC value to ensure backwards-compatible
4250 * behavior for migration.
4254 if (msr_info->host_initiated) {
4255 offset = vcpu->arch.l1_tsc_offset;
4256 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4258 offset = vcpu->arch.tsc_offset;
4259 ratio = vcpu->arch.tsc_scaling_ratio;
4262 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4265 case MSR_IA32_CR_PAT:
4266 msr_info->data = vcpu->arch.pat;
4269 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
4270 case MSR_MTRRdefType:
4271 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4272 case 0xcd: /* fsb frequency */
4276 * MSR_EBC_FREQUENCY_ID
4277 * Conservative value valid for even the basic CPU models.
4278 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4279 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4280 * and 266MHz for model 3, or 4. Set Core Clock
4281 * Frequency to System Bus Frequency Ratio to 1 (bits
4282 * 31:24) even though these are only valid for CPU
4283 * models > 2, however guests may end up dividing or
4284 * multiplying by zero otherwise.
4286 case MSR_EBC_FREQUENCY_ID:
4287 msr_info->data = 1 << 24;
4289 case MSR_IA32_APICBASE:
4290 msr_info->data = kvm_get_apic_base(vcpu);
4292 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4293 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4294 case MSR_IA32_TSC_DEADLINE:
4295 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4297 case MSR_IA32_TSC_ADJUST:
4298 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4300 case MSR_IA32_MISC_ENABLE:
4301 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4303 case MSR_IA32_SMBASE:
4304 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4306 msr_info->data = vcpu->arch.smbase;
4309 msr_info->data = vcpu->arch.smi_count;
4311 case MSR_IA32_PERF_STATUS:
4312 /* TSC increment by tick */
4313 msr_info->data = 1000ULL;
4314 /* CPU multiplier */
4315 msr_info->data |= (((uint64_t)4ULL) << 40);
4318 msr_info->data = vcpu->arch.efer;
4320 case MSR_KVM_WALL_CLOCK:
4321 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4324 msr_info->data = vcpu->kvm->arch.wall_clock;
4326 case MSR_KVM_WALL_CLOCK_NEW:
4327 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4330 msr_info->data = vcpu->kvm->arch.wall_clock;
4332 case MSR_KVM_SYSTEM_TIME:
4333 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4336 msr_info->data = vcpu->arch.time;
4338 case MSR_KVM_SYSTEM_TIME_NEW:
4339 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4342 msr_info->data = vcpu->arch.time;
4344 case MSR_KVM_ASYNC_PF_EN:
4345 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4348 msr_info->data = vcpu->arch.apf.msr_en_val;
4350 case MSR_KVM_ASYNC_PF_INT:
4351 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4354 msr_info->data = vcpu->arch.apf.msr_int_val;
4356 case MSR_KVM_ASYNC_PF_ACK:
4357 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4362 case MSR_KVM_STEAL_TIME:
4363 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4366 msr_info->data = vcpu->arch.st.msr_val;
4368 case MSR_KVM_PV_EOI_EN:
4369 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4372 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4374 case MSR_KVM_POLL_CONTROL:
4375 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4378 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4380 case MSR_IA32_P5_MC_ADDR:
4381 case MSR_IA32_P5_MC_TYPE:
4382 case MSR_IA32_MCG_CAP:
4383 case MSR_IA32_MCG_CTL:
4384 case MSR_IA32_MCG_STATUS:
4385 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4386 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4387 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4388 msr_info->host_initiated);
4390 if (!msr_info->host_initiated &&
4391 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4393 msr_info->data = vcpu->arch.ia32_xss;
4395 case MSR_K7_CLK_CTL:
4397 * Provide expected ramp-up count for K7. All other
4398 * are set to zero, indicating minimum divisors for
4401 * This prevents guest kernels on AMD host with CPU
4402 * type 6, model 8 and higher from exploding due to
4403 * the rdmsr failing.
4405 msr_info->data = 0x20000000;
4407 #ifdef CONFIG_KVM_HYPERV
4408 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4409 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4410 case HV_X64_MSR_SYNDBG_OPTIONS:
4411 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4412 case HV_X64_MSR_CRASH_CTL:
4413 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4414 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4415 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4416 case HV_X64_MSR_TSC_EMULATION_STATUS:
4417 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4418 return kvm_hv_get_msr_common(vcpu,
4419 msr_info->index, &msr_info->data,
4420 msr_info->host_initiated);
4422 case MSR_IA32_BBL_CR_CTL3:
4423 /* This legacy MSR exists but isn't fully documented in current
4424 * silicon. It is however accessed by winxp in very narrow
4425 * scenarios where it sets bit #19, itself documented as
4426 * a "reserved" bit. Best effort attempt to source coherent
4427 * read data here should the balance of the register be
4428 * interpreted by the guest:
4430 * L2 cache control register 3: 64GB range, 256KB size,
4431 * enabled, latency 0x1, configured
4433 msr_info->data = 0xbe702111;
4435 case MSR_AMD64_OSVW_ID_LENGTH:
4436 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4438 msr_info->data = vcpu->arch.osvw.length;
4440 case MSR_AMD64_OSVW_STATUS:
4441 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4443 msr_info->data = vcpu->arch.osvw.status;
4445 case MSR_PLATFORM_INFO:
4446 if (!msr_info->host_initiated &&
4447 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4449 msr_info->data = vcpu->arch.msr_platform_info;
4451 case MSR_MISC_FEATURES_ENABLES:
4452 msr_info->data = vcpu->arch.msr_misc_features_enables;
4455 msr_info->data = vcpu->arch.msr_hwcr;
4457 #ifdef CONFIG_X86_64
4459 if (!msr_info->host_initiated &&
4460 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4463 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4465 case MSR_IA32_XFD_ERR:
4466 if (!msr_info->host_initiated &&
4467 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4470 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4474 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4475 return kvm_pmu_get_msr(vcpu, msr_info);
4478 * Userspace is allowed to read MSRs that KVM reports as
4479 * to-be-saved, even if an MSR isn't fully supported.
4481 if (msr_info->host_initiated &&
4482 kvm_is_msr_to_save(msr_info->index)) {
4487 return KVM_MSR_RET_INVALID;
4491 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4494 * Read or write a bunch of msrs. All parameters are kernel addresses.
4496 * @return number of msrs set successfully.
4498 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4499 struct kvm_msr_entry *entries,
4500 int (*do_msr)(struct kvm_vcpu *vcpu,
4501 unsigned index, u64 *data))
4505 for (i = 0; i < msrs->nmsrs; ++i)
4506 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4513 * Read or write a bunch of msrs. Parameters are user addresses.
4515 * @return number of msrs set successfully.
4517 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4518 int (*do_msr)(struct kvm_vcpu *vcpu,
4519 unsigned index, u64 *data),
4522 struct kvm_msrs msrs;
4523 struct kvm_msr_entry *entries;
4528 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4532 if (msrs.nmsrs >= MAX_IO_MSRS)
4535 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4536 entries = memdup_user(user_msrs->entries, size);
4537 if (IS_ERR(entries)) {
4538 r = PTR_ERR(entries);
4542 r = __msr_io(vcpu, &msrs, entries, do_msr);
4544 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4552 static inline bool kvm_can_mwait_in_guest(void)
4554 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4555 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4556 boot_cpu_has(X86_FEATURE_ARAT);
4559 #ifdef CONFIG_KVM_HYPERV
4560 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4561 struct kvm_cpuid2 __user *cpuid_arg)
4563 struct kvm_cpuid2 cpuid;
4567 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4570 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4575 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4582 static bool kvm_is_vm_type_supported(unsigned long type)
4584 return type == KVM_X86_DEFAULT_VM ||
4585 (type == KVM_X86_SW_PROTECTED_VM &&
4586 IS_ENABLED(CONFIG_KVM_SW_PROTECTED_VM) && tdp_mmu_enabled);
4589 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4594 case KVM_CAP_IRQCHIP:
4596 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4597 case KVM_CAP_SET_TSS_ADDR:
4598 case KVM_CAP_EXT_CPUID:
4599 case KVM_CAP_EXT_EMUL_CPUID:
4600 case KVM_CAP_CLOCKSOURCE:
4602 case KVM_CAP_NOP_IO_DELAY:
4603 case KVM_CAP_MP_STATE:
4604 case KVM_CAP_SYNC_MMU:
4605 case KVM_CAP_USER_NMI:
4606 case KVM_CAP_REINJECT_CONTROL:
4607 case KVM_CAP_IRQ_INJECT_STATUS:
4608 case KVM_CAP_IOEVENTFD:
4609 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4611 case KVM_CAP_PIT_STATE2:
4612 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4613 case KVM_CAP_VCPU_EVENTS:
4614 #ifdef CONFIG_KVM_HYPERV
4615 case KVM_CAP_HYPERV:
4616 case KVM_CAP_HYPERV_VAPIC:
4617 case KVM_CAP_HYPERV_SPIN:
4618 case KVM_CAP_HYPERV_TIME:
4619 case KVM_CAP_HYPERV_SYNIC:
4620 case KVM_CAP_HYPERV_SYNIC2:
4621 case KVM_CAP_HYPERV_VP_INDEX:
4622 case KVM_CAP_HYPERV_EVENTFD:
4623 case KVM_CAP_HYPERV_TLBFLUSH:
4624 case KVM_CAP_HYPERV_SEND_IPI:
4625 case KVM_CAP_HYPERV_CPUID:
4626 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4627 case KVM_CAP_SYS_HYPERV_CPUID:
4629 case KVM_CAP_PCI_SEGMENT:
4630 case KVM_CAP_DEBUGREGS:
4631 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4633 case KVM_CAP_ASYNC_PF:
4634 case KVM_CAP_ASYNC_PF_INT:
4635 case KVM_CAP_GET_TSC_KHZ:
4636 case KVM_CAP_KVMCLOCK_CTRL:
4637 case KVM_CAP_READONLY_MEM:
4638 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4639 case KVM_CAP_TSC_DEADLINE_TIMER:
4640 case KVM_CAP_DISABLE_QUIRKS:
4641 case KVM_CAP_SET_BOOT_CPU_ID:
4642 case KVM_CAP_SPLIT_IRQCHIP:
4643 case KVM_CAP_IMMEDIATE_EXIT:
4644 case KVM_CAP_PMU_EVENT_FILTER:
4645 case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4646 case KVM_CAP_GET_MSR_FEATURES:
4647 case KVM_CAP_MSR_PLATFORM_INFO:
4648 case KVM_CAP_EXCEPTION_PAYLOAD:
4649 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4650 case KVM_CAP_SET_GUEST_DEBUG:
4651 case KVM_CAP_LAST_CPU:
4652 case KVM_CAP_X86_USER_SPACE_MSR:
4653 case KVM_CAP_X86_MSR_FILTER:
4654 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4655 #ifdef CONFIG_X86_SGX_KVM
4656 case KVM_CAP_SGX_ATTRIBUTE:
4658 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4659 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4660 case KVM_CAP_SREGS2:
4661 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4662 case KVM_CAP_VCPU_ATTRIBUTES:
4663 case KVM_CAP_SYS_ATTRIBUTES:
4665 case KVM_CAP_ENABLE_CAP:
4666 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4667 case KVM_CAP_IRQFD_RESAMPLE:
4668 case KVM_CAP_MEMORY_FAULT_INFO:
4671 case KVM_CAP_EXIT_HYPERCALL:
4672 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4674 case KVM_CAP_SET_GUEST_DEBUG2:
4675 return KVM_GUESTDBG_VALID_MASK;
4676 #ifdef CONFIG_KVM_XEN
4677 case KVM_CAP_XEN_HVM:
4678 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4679 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4680 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4681 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4682 KVM_XEN_HVM_CONFIG_EVTCHN_SEND |
4683 KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE;
4684 if (sched_info_on())
4685 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4686 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4689 case KVM_CAP_SYNC_REGS:
4690 r = KVM_SYNC_X86_VALID_FIELDS;
4692 case KVM_CAP_ADJUST_CLOCK:
4693 r = KVM_CLOCK_VALID_FLAGS;
4695 case KVM_CAP_X86_DISABLE_EXITS:
4696 r = KVM_X86_DISABLE_EXITS_PAUSE;
4698 if (!mitigate_smt_rsb) {
4699 r |= KVM_X86_DISABLE_EXITS_HLT |
4700 KVM_X86_DISABLE_EXITS_CSTATE;
4702 if (kvm_can_mwait_in_guest())
4703 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4706 case KVM_CAP_X86_SMM:
4707 if (!IS_ENABLED(CONFIG_KVM_SMM))
4710 /* SMBASE is usually relocated above 1M on modern chipsets,
4711 * and SMM handlers might indeed rely on 4G segment limits,
4712 * so do not report SMM to be available if real mode is
4713 * emulated via vm86 mode. Still, do not go to great lengths
4714 * to avoid userspace's usage of the feature, because it is a
4715 * fringe case that is not enabled except via specific settings
4716 * of the module parameters.
4718 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4720 case KVM_CAP_NR_VCPUS:
4721 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4723 case KVM_CAP_MAX_VCPUS:
4726 case KVM_CAP_MAX_VCPU_ID:
4727 r = KVM_MAX_VCPU_IDS;
4729 case KVM_CAP_PV_MMU: /* obsolete */
4733 r = KVM_MAX_MCE_BANKS;
4736 r = boot_cpu_has(X86_FEATURE_XSAVE);
4738 case KVM_CAP_TSC_CONTROL:
4739 case KVM_CAP_VM_TSC_CONTROL:
4740 r = kvm_caps.has_tsc_control;
4742 case KVM_CAP_X2APIC_API:
4743 r = KVM_X2APIC_API_VALID_FLAGS;
4745 case KVM_CAP_NESTED_STATE:
4746 r = kvm_x86_ops.nested_ops->get_state ?
4747 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4749 #ifdef CONFIG_KVM_HYPERV
4750 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4751 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4753 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4754 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4757 case KVM_CAP_SMALLER_MAXPHYADDR:
4758 r = (int) allow_smaller_maxphyaddr;
4760 case KVM_CAP_STEAL_TIME:
4761 r = sched_info_on();
4763 case KVM_CAP_X86_BUS_LOCK_EXIT:
4764 if (kvm_caps.has_bus_lock_exit)
4765 r = KVM_BUS_LOCK_DETECTION_OFF |
4766 KVM_BUS_LOCK_DETECTION_EXIT;
4770 case KVM_CAP_XSAVE2: {
4771 r = xstate_required_size(kvm_get_filtered_xcr0(), false);
4772 if (r < sizeof(struct kvm_xsave))
4773 r = sizeof(struct kvm_xsave);
4776 case KVM_CAP_PMU_CAPABILITY:
4777 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4779 case KVM_CAP_DISABLE_QUIRKS2:
4780 r = KVM_X86_VALID_QUIRKS;
4782 case KVM_CAP_X86_NOTIFY_VMEXIT:
4783 r = kvm_caps.has_notify_vmexit;
4785 case KVM_CAP_VM_TYPES:
4786 r = BIT(KVM_X86_DEFAULT_VM);
4787 if (kvm_is_vm_type_supported(KVM_X86_SW_PROTECTED_VM))
4788 r |= BIT(KVM_X86_SW_PROTECTED_VM);
4796 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4798 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4800 if ((u64)(unsigned long)uaddr != attr->addr)
4801 return ERR_PTR_USR(-EFAULT);
4805 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4807 u64 __user *uaddr = kvm_get_attr_addr(attr);
4813 return PTR_ERR(uaddr);
4815 switch (attr->attr) {
4816 case KVM_X86_XCOMP_GUEST_SUPP:
4817 if (put_user(kvm_caps.supported_xcr0, uaddr))
4825 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4830 switch (attr->attr) {
4831 case KVM_X86_XCOMP_GUEST_SUPP:
4838 long kvm_arch_dev_ioctl(struct file *filp,
4839 unsigned int ioctl, unsigned long arg)
4841 void __user *argp = (void __user *)arg;
4845 case KVM_GET_MSR_INDEX_LIST: {
4846 struct kvm_msr_list __user *user_msr_list = argp;
4847 struct kvm_msr_list msr_list;
4851 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4854 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4855 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4858 if (n < msr_list.nmsrs)
4861 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4862 num_msrs_to_save * sizeof(u32)))
4864 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4866 num_emulated_msrs * sizeof(u32)))
4871 case KVM_GET_SUPPORTED_CPUID:
4872 case KVM_GET_EMULATED_CPUID: {
4873 struct kvm_cpuid2 __user *cpuid_arg = argp;
4874 struct kvm_cpuid2 cpuid;
4877 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4880 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4886 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4891 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4893 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4894 sizeof(kvm_caps.supported_mce_cap)))
4898 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4899 struct kvm_msr_list __user *user_msr_list = argp;
4900 struct kvm_msr_list msr_list;
4904 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4907 msr_list.nmsrs = num_msr_based_features;
4908 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4911 if (n < msr_list.nmsrs)
4914 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4915 num_msr_based_features * sizeof(u32)))
4921 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4923 #ifdef CONFIG_KVM_HYPERV
4924 case KVM_GET_SUPPORTED_HV_CPUID:
4925 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4928 case KVM_GET_DEVICE_ATTR: {
4929 struct kvm_device_attr attr;
4931 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4933 r = kvm_x86_dev_get_attr(&attr);
4936 case KVM_HAS_DEVICE_ATTR: {
4937 struct kvm_device_attr attr;
4939 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4941 r = kvm_x86_dev_has_attr(&attr);
4952 static void wbinvd_ipi(void *garbage)
4957 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4959 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4962 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4964 /* Address WBINVD may be executed by guest */
4965 if (need_emulate_wbinvd(vcpu)) {
4966 if (static_call(kvm_x86_has_wbinvd_exit)())
4967 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4968 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4969 smp_call_function_single(vcpu->cpu,
4970 wbinvd_ipi, NULL, 1);
4973 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4975 /* Save host pkru register if supported */
4976 vcpu->arch.host_pkru = read_pkru();
4978 /* Apply any externally detected TSC adjustments (due to suspend) */
4979 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4980 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4981 vcpu->arch.tsc_offset_adjustment = 0;
4982 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4985 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4986 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4987 rdtsc() - vcpu->arch.last_host_tsc;
4989 mark_tsc_unstable("KVM discovered backwards TSC");
4991 if (kvm_check_tsc_unstable()) {
4992 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4993 vcpu->arch.last_guest_tsc);
4994 kvm_vcpu_write_tsc_offset(vcpu, offset);
4995 vcpu->arch.tsc_catchup = 1;
4998 if (kvm_lapic_hv_timer_in_use(vcpu))
4999 kvm_lapic_restart_hv_timer(vcpu);
5002 * On a host with synchronized TSC, there is no need to update
5003 * kvmclock on vcpu->cpu migration
5005 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
5006 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
5007 if (vcpu->cpu != cpu)
5008 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
5012 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
5015 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
5017 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
5018 struct kvm_steal_time __user *st;
5019 struct kvm_memslots *slots;
5020 static const u8 preempted = KVM_VCPU_PREEMPTED;
5021 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
5024 * The vCPU can be marked preempted if and only if the VM-Exit was on
5025 * an instruction boundary and will not trigger guest emulation of any
5026 * kind (see vcpu_run). Vendor specific code controls (conservatively)
5027 * when this is true, for example allowing the vCPU to be marked
5028 * preempted if and only if the VM-Exit was due to a host interrupt.
5030 if (!vcpu->arch.at_instruction_boundary) {
5031 vcpu->stat.preemption_other++;
5035 vcpu->stat.preemption_reported++;
5036 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
5039 if (vcpu->arch.st.preempted)
5042 /* This happens on process exit */
5043 if (unlikely(current->mm != vcpu->kvm->mm))
5046 slots = kvm_memslots(vcpu->kvm);
5048 if (unlikely(slots->generation != ghc->generation ||
5050 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
5053 st = (struct kvm_steal_time __user *)ghc->hva;
5054 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
5056 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
5057 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
5059 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
5062 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
5066 if (vcpu->preempted) {
5067 if (!vcpu->arch.guest_state_protected)
5068 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
5071 * Take the srcu lock as memslots will be accessed to check the gfn
5072 * cache generation against the memslots generation.
5074 idx = srcu_read_lock(&vcpu->kvm->srcu);
5075 if (kvm_xen_msr_enabled(vcpu->kvm))
5076 kvm_xen_runstate_set_preempted(vcpu);
5078 kvm_steal_time_set_preempted(vcpu);
5079 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5082 static_call(kvm_x86_vcpu_put)(vcpu);
5083 vcpu->arch.last_host_tsc = rdtsc();
5086 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
5087 struct kvm_lapic_state *s)
5089 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
5091 return kvm_apic_get_state(vcpu, s);
5094 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
5095 struct kvm_lapic_state *s)
5099 r = kvm_apic_set_state(vcpu, s);
5102 update_cr8_intercept(vcpu);
5107 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
5110 * We can accept userspace's request for interrupt injection
5111 * as long as we have a place to store the interrupt number.
5112 * The actual injection will happen when the CPU is able to
5113 * deliver the interrupt.
5115 if (kvm_cpu_has_extint(vcpu))
5118 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
5119 return (!lapic_in_kernel(vcpu) ||
5120 kvm_apic_accept_pic_intr(vcpu));
5123 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
5126 * Do not cause an interrupt window exit if an exception
5127 * is pending or an event needs reinjection; userspace
5128 * might want to inject the interrupt manually using KVM_SET_REGS
5129 * or KVM_SET_SREGS. For that to work, we must be at an
5130 * instruction boundary and with no events half-injected.
5132 return (kvm_arch_interrupt_allowed(vcpu) &&
5133 kvm_cpu_accept_dm_intr(vcpu) &&
5134 !kvm_event_needs_reinjection(vcpu) &&
5135 !kvm_is_exception_pending(vcpu));
5138 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
5139 struct kvm_interrupt *irq)
5141 if (irq->irq >= KVM_NR_INTERRUPTS)
5144 if (!irqchip_in_kernel(vcpu->kvm)) {
5145 kvm_queue_interrupt(vcpu, irq->irq, false);
5146 kvm_make_request(KVM_REQ_EVENT, vcpu);
5151 * With in-kernel LAPIC, we only use this to inject EXTINT, so
5152 * fail for in-kernel 8259.
5154 if (pic_in_kernel(vcpu->kvm))
5157 if (vcpu->arch.pending_external_vector != -1)
5160 vcpu->arch.pending_external_vector = irq->irq;
5161 kvm_make_request(KVM_REQ_EVENT, vcpu);
5165 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
5167 kvm_inject_nmi(vcpu);
5172 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
5173 struct kvm_tpr_access_ctl *tac)
5177 vcpu->arch.tpr_access_reporting = !!tac->enabled;
5181 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
5185 unsigned bank_num = mcg_cap & 0xff, bank;
5188 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
5190 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
5193 vcpu->arch.mcg_cap = mcg_cap;
5194 /* Init IA32_MCG_CTL to all 1s */
5195 if (mcg_cap & MCG_CTL_P)
5196 vcpu->arch.mcg_ctl = ~(u64)0;
5197 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
5198 for (bank = 0; bank < bank_num; bank++) {
5199 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5200 if (mcg_cap & MCG_CMCI_P)
5201 vcpu->arch.mci_ctl2_banks[bank] = 0;
5204 kvm_apic_after_set_mcg_cap(vcpu);
5206 static_call(kvm_x86_setup_mce)(vcpu);
5212 * Validate this is an UCNA (uncorrectable no action) error by checking the
5213 * MCG_STATUS and MCi_STATUS registers:
5214 * - none of the bits for Machine Check Exceptions are set
5215 * - both the VAL (valid) and UC (uncorrectable) bits are set
5216 * MCI_STATUS_PCC - Processor Context Corrupted
5217 * MCI_STATUS_S - Signaled as a Machine Check Exception
5218 * MCI_STATUS_AR - Software recoverable Action Required
5220 static bool is_ucna(struct kvm_x86_mce *mce)
5222 return !mce->mcg_status &&
5223 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5224 (mce->status & MCI_STATUS_VAL) &&
5225 (mce->status & MCI_STATUS_UC);
5228 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5230 u64 mcg_cap = vcpu->arch.mcg_cap;
5232 banks[1] = mce->status;
5233 banks[2] = mce->addr;
5234 banks[3] = mce->misc;
5235 vcpu->arch.mcg_status = mce->mcg_status;
5237 if (!(mcg_cap & MCG_CMCI_P) ||
5238 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5241 if (lapic_in_kernel(vcpu))
5242 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5247 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5248 struct kvm_x86_mce *mce)
5250 u64 mcg_cap = vcpu->arch.mcg_cap;
5251 unsigned bank_num = mcg_cap & 0xff;
5252 u64 *banks = vcpu->arch.mce_banks;
5254 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5257 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5260 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5263 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5264 * reporting is disabled
5266 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5267 vcpu->arch.mcg_ctl != ~(u64)0)
5270 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5271 * reporting is disabled for the bank
5273 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5275 if (mce->status & MCI_STATUS_UC) {
5276 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5277 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5278 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5281 if (banks[1] & MCI_STATUS_VAL)
5282 mce->status |= MCI_STATUS_OVER;
5283 banks[2] = mce->addr;
5284 banks[3] = mce->misc;
5285 vcpu->arch.mcg_status = mce->mcg_status;
5286 banks[1] = mce->status;
5287 kvm_queue_exception(vcpu, MC_VECTOR);
5288 } else if (!(banks[1] & MCI_STATUS_VAL)
5289 || !(banks[1] & MCI_STATUS_UC)) {
5290 if (banks[1] & MCI_STATUS_VAL)
5291 mce->status |= MCI_STATUS_OVER;
5292 banks[2] = mce->addr;
5293 banks[3] = mce->misc;
5294 banks[1] = mce->status;
5296 banks[1] |= MCI_STATUS_OVER;
5300 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5301 struct kvm_vcpu_events *events)
5303 struct kvm_queued_exception *ex;
5307 #ifdef CONFIG_KVM_SMM
5308 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5313 * KVM's ABI only allows for one exception to be migrated. Luckily,
5314 * the only time there can be two queued exceptions is if there's a
5315 * non-exiting _injected_ exception, and a pending exiting exception.
5316 * In that case, ignore the VM-Exiting exception as it's an extension
5317 * of the injected exception.
5319 if (vcpu->arch.exception_vmexit.pending &&
5320 !vcpu->arch.exception.pending &&
5321 !vcpu->arch.exception.injected)
5322 ex = &vcpu->arch.exception_vmexit;
5324 ex = &vcpu->arch.exception;
5327 * In guest mode, payload delivery should be deferred if the exception
5328 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5329 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5330 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5331 * propagate the payload and so it cannot be safely deferred. Deliver
5332 * the payload if the capability hasn't been requested.
5334 if (!vcpu->kvm->arch.exception_payload_enabled &&
5335 ex->pending && ex->has_payload)
5336 kvm_deliver_exception_payload(vcpu, ex);
5338 memset(events, 0, sizeof(*events));
5341 * The API doesn't provide the instruction length for software
5342 * exceptions, so don't report them. As long as the guest RIP
5343 * isn't advanced, we should expect to encounter the exception
5346 if (!kvm_exception_is_soft(ex->vector)) {
5347 events->exception.injected = ex->injected;
5348 events->exception.pending = ex->pending;
5350 * For ABI compatibility, deliberately conflate
5351 * pending and injected exceptions when
5352 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5354 if (!vcpu->kvm->arch.exception_payload_enabled)
5355 events->exception.injected |= ex->pending;
5357 events->exception.nr = ex->vector;
5358 events->exception.has_error_code = ex->has_error_code;
5359 events->exception.error_code = ex->error_code;
5360 events->exception_has_payload = ex->has_payload;
5361 events->exception_payload = ex->payload;
5363 events->interrupt.injected =
5364 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5365 events->interrupt.nr = vcpu->arch.interrupt.nr;
5366 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5368 events->nmi.injected = vcpu->arch.nmi_injected;
5369 events->nmi.pending = kvm_get_nr_pending_nmis(vcpu);
5370 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5372 /* events->sipi_vector is never valid when reporting to user space */
5374 #ifdef CONFIG_KVM_SMM
5375 events->smi.smm = is_smm(vcpu);
5376 events->smi.pending = vcpu->arch.smi_pending;
5377 events->smi.smm_inside_nmi =
5378 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5380 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5382 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5383 | KVM_VCPUEVENT_VALID_SHADOW
5384 | KVM_VCPUEVENT_VALID_SMM);
5385 if (vcpu->kvm->arch.exception_payload_enabled)
5386 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5387 if (vcpu->kvm->arch.triple_fault_event) {
5388 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5389 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5393 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5394 struct kvm_vcpu_events *events)
5396 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5397 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5398 | KVM_VCPUEVENT_VALID_SHADOW
5399 | KVM_VCPUEVENT_VALID_SMM
5400 | KVM_VCPUEVENT_VALID_PAYLOAD
5401 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5404 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5405 if (!vcpu->kvm->arch.exception_payload_enabled)
5407 if (events->exception.pending)
5408 events->exception.injected = 0;
5410 events->exception_has_payload = 0;
5412 events->exception.pending = 0;
5413 events->exception_has_payload = 0;
5416 if ((events->exception.injected || events->exception.pending) &&
5417 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5420 /* INITs are latched while in SMM */
5421 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5422 (events->smi.smm || events->smi.pending) &&
5423 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5429 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5430 * morph the exception to a VM-Exit if appropriate. Do this only for
5431 * pending exceptions, already-injected exceptions are not subject to
5432 * intercpetion. Note, userspace that conflates pending and injected
5433 * is hosed, and will incorrectly convert an injected exception into a
5434 * pending exception, which in turn may cause a spurious VM-Exit.
5436 vcpu->arch.exception_from_userspace = events->exception.pending;
5438 vcpu->arch.exception_vmexit.pending = false;
5440 vcpu->arch.exception.injected = events->exception.injected;
5441 vcpu->arch.exception.pending = events->exception.pending;
5442 vcpu->arch.exception.vector = events->exception.nr;
5443 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5444 vcpu->arch.exception.error_code = events->exception.error_code;
5445 vcpu->arch.exception.has_payload = events->exception_has_payload;
5446 vcpu->arch.exception.payload = events->exception_payload;
5448 vcpu->arch.interrupt.injected = events->interrupt.injected;
5449 vcpu->arch.interrupt.nr = events->interrupt.nr;
5450 vcpu->arch.interrupt.soft = events->interrupt.soft;
5451 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5452 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5453 events->interrupt.shadow);
5455 vcpu->arch.nmi_injected = events->nmi.injected;
5456 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) {
5457 vcpu->arch.nmi_pending = 0;
5458 atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending);
5459 if (events->nmi.pending)
5460 kvm_make_request(KVM_REQ_NMI, vcpu);
5462 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5464 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5465 lapic_in_kernel(vcpu))
5466 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5468 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5469 #ifdef CONFIG_KVM_SMM
5470 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5471 kvm_leave_nested(vcpu);
5472 kvm_smm_changed(vcpu, events->smi.smm);
5475 vcpu->arch.smi_pending = events->smi.pending;
5477 if (events->smi.smm) {
5478 if (events->smi.smm_inside_nmi)
5479 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5481 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5485 if (events->smi.smm || events->smi.pending ||
5486 events->smi.smm_inside_nmi)
5490 if (lapic_in_kernel(vcpu)) {
5491 if (events->smi.latched_init)
5492 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5494 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5498 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5499 if (!vcpu->kvm->arch.triple_fault_event)
5501 if (events->triple_fault.pending)
5502 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5504 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5507 kvm_make_request(KVM_REQ_EVENT, vcpu);
5512 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5513 struct kvm_debugregs *dbgregs)
5517 memset(dbgregs, 0, sizeof(*dbgregs));
5518 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5519 kvm_get_dr(vcpu, 6, &val);
5521 dbgregs->dr7 = vcpu->arch.dr7;
5524 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5525 struct kvm_debugregs *dbgregs)
5530 if (!kvm_dr6_valid(dbgregs->dr6))
5532 if (!kvm_dr7_valid(dbgregs->dr7))
5535 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5536 kvm_update_dr0123(vcpu);
5537 vcpu->arch.dr6 = dbgregs->dr6;
5538 vcpu->arch.dr7 = dbgregs->dr7;
5539 kvm_update_dr7(vcpu);
5545 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5546 u8 *state, unsigned int size)
5549 * Only copy state for features that are enabled for the guest. The
5550 * state itself isn't problematic, but setting bits in the header for
5551 * features that are supported in *this* host but not exposed to the
5552 * guest can result in KVM_SET_XSAVE failing when live migrating to a
5553 * compatible host without the features that are NOT exposed to the
5556 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
5557 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
5558 * supported by the host.
5560 u64 supported_xcr0 = vcpu->arch.guest_supported_xcr0 |
5561 XFEATURE_MASK_FPSSE;
5563 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5566 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size,
5567 supported_xcr0, vcpu->arch.pkru);
5570 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5571 struct kvm_xsave *guest_xsave)
5573 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region,
5574 sizeof(guest_xsave->region));
5577 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5578 struct kvm_xsave *guest_xsave)
5580 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5583 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5584 guest_xsave->region,
5585 kvm_caps.supported_xcr0,
5589 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5590 struct kvm_xcrs *guest_xcrs)
5592 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5593 guest_xcrs->nr_xcrs = 0;
5597 guest_xcrs->nr_xcrs = 1;
5598 guest_xcrs->flags = 0;
5599 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5600 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5603 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5604 struct kvm_xcrs *guest_xcrs)
5608 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5611 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5614 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5615 /* Only support XCR0 currently */
5616 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5617 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5618 guest_xcrs->xcrs[i].value);
5627 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5628 * stopped by the hypervisor. This function will be called from the host only.
5629 * EINVAL is returned when the host attempts to set the flag for a guest that
5630 * does not support pv clocks.
5632 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5634 if (!vcpu->arch.pv_time.active)
5636 vcpu->arch.pvclock_set_guest_stopped_request = true;
5637 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5641 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5642 struct kvm_device_attr *attr)
5646 switch (attr->attr) {
5647 case KVM_VCPU_TSC_OFFSET:
5657 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5658 struct kvm_device_attr *attr)
5660 u64 __user *uaddr = kvm_get_attr_addr(attr);
5664 return PTR_ERR(uaddr);
5666 switch (attr->attr) {
5667 case KVM_VCPU_TSC_OFFSET:
5669 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5680 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5681 struct kvm_device_attr *attr)
5683 u64 __user *uaddr = kvm_get_attr_addr(attr);
5684 struct kvm *kvm = vcpu->kvm;
5688 return PTR_ERR(uaddr);
5690 switch (attr->attr) {
5691 case KVM_VCPU_TSC_OFFSET: {
5692 u64 offset, tsc, ns;
5693 unsigned long flags;
5697 if (get_user(offset, uaddr))
5700 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5702 matched = (vcpu->arch.virtual_tsc_khz &&
5703 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5704 kvm->arch.last_tsc_offset == offset);
5706 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5707 ns = get_kvmclock_base_ns();
5709 kvm->arch.user_set_tsc = true;
5710 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5711 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5723 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5727 struct kvm_device_attr attr;
5730 if (copy_from_user(&attr, argp, sizeof(attr)))
5733 if (attr.group != KVM_VCPU_TSC_CTRL)
5737 case KVM_HAS_DEVICE_ATTR:
5738 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5740 case KVM_GET_DEVICE_ATTR:
5741 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5743 case KVM_SET_DEVICE_ATTR:
5744 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5751 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5752 struct kvm_enable_cap *cap)
5758 #ifdef CONFIG_KVM_HYPERV
5759 case KVM_CAP_HYPERV_SYNIC2:
5764 case KVM_CAP_HYPERV_SYNIC:
5765 if (!irqchip_in_kernel(vcpu->kvm))
5767 return kvm_hv_activate_synic(vcpu, cap->cap ==
5768 KVM_CAP_HYPERV_SYNIC2);
5769 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5772 uint16_t vmcs_version;
5773 void __user *user_ptr;
5775 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5777 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5779 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5780 if (copy_to_user(user_ptr, &vmcs_version,
5781 sizeof(vmcs_version)))
5786 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5787 if (!kvm_x86_ops.enable_l2_tlb_flush)
5790 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5792 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5793 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5796 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5797 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5798 if (vcpu->arch.pv_cpuid.enforce)
5799 kvm_update_pv_runtime(vcpu);
5807 long kvm_arch_vcpu_ioctl(struct file *filp,
5808 unsigned int ioctl, unsigned long arg)
5810 struct kvm_vcpu *vcpu = filp->private_data;
5811 void __user *argp = (void __user *)arg;
5814 struct kvm_sregs2 *sregs2;
5815 struct kvm_lapic_state *lapic;
5816 struct kvm_xsave *xsave;
5817 struct kvm_xcrs *xcrs;
5825 case KVM_GET_LAPIC: {
5827 if (!lapic_in_kernel(vcpu))
5829 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5830 GFP_KERNEL_ACCOUNT);
5835 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5839 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5844 case KVM_SET_LAPIC: {
5846 if (!lapic_in_kernel(vcpu))
5848 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5849 if (IS_ERR(u.lapic)) {
5850 r = PTR_ERR(u.lapic);
5854 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5857 case KVM_INTERRUPT: {
5858 struct kvm_interrupt irq;
5861 if (copy_from_user(&irq, argp, sizeof(irq)))
5863 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5867 r = kvm_vcpu_ioctl_nmi(vcpu);
5871 r = kvm_inject_smi(vcpu);
5874 case KVM_SET_CPUID: {
5875 struct kvm_cpuid __user *cpuid_arg = argp;
5876 struct kvm_cpuid cpuid;
5879 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5881 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5884 case KVM_SET_CPUID2: {
5885 struct kvm_cpuid2 __user *cpuid_arg = argp;
5886 struct kvm_cpuid2 cpuid;
5889 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5891 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5892 cpuid_arg->entries);
5895 case KVM_GET_CPUID2: {
5896 struct kvm_cpuid2 __user *cpuid_arg = argp;
5897 struct kvm_cpuid2 cpuid;
5900 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5902 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5903 cpuid_arg->entries);
5907 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5912 case KVM_GET_MSRS: {
5913 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5914 r = msr_io(vcpu, argp, do_get_msr, 1);
5915 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5918 case KVM_SET_MSRS: {
5919 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5920 r = msr_io(vcpu, argp, do_set_msr, 0);
5921 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5924 case KVM_TPR_ACCESS_REPORTING: {
5925 struct kvm_tpr_access_ctl tac;
5928 if (copy_from_user(&tac, argp, sizeof(tac)))
5930 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5934 if (copy_to_user(argp, &tac, sizeof(tac)))
5939 case KVM_SET_VAPIC_ADDR: {
5940 struct kvm_vapic_addr va;
5944 if (!lapic_in_kernel(vcpu))
5947 if (copy_from_user(&va, argp, sizeof(va)))
5949 idx = srcu_read_lock(&vcpu->kvm->srcu);
5950 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5951 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5954 case KVM_X86_SETUP_MCE: {
5958 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5960 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5963 case KVM_X86_SET_MCE: {
5964 struct kvm_x86_mce mce;
5967 if (copy_from_user(&mce, argp, sizeof(mce)))
5969 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5972 case KVM_GET_VCPU_EVENTS: {
5973 struct kvm_vcpu_events events;
5975 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5978 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5983 case KVM_SET_VCPU_EVENTS: {
5984 struct kvm_vcpu_events events;
5987 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5990 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5993 case KVM_GET_DEBUGREGS: {
5994 struct kvm_debugregs dbgregs;
5996 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5999 if (copy_to_user(argp, &dbgregs,
6000 sizeof(struct kvm_debugregs)))
6005 case KVM_SET_DEBUGREGS: {
6006 struct kvm_debugregs dbgregs;
6009 if (copy_from_user(&dbgregs, argp,
6010 sizeof(struct kvm_debugregs)))
6013 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
6016 case KVM_GET_XSAVE: {
6018 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
6021 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
6026 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
6029 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
6034 case KVM_SET_XSAVE: {
6035 int size = vcpu->arch.guest_fpu.uabi_size;
6037 u.xsave = memdup_user(argp, size);
6038 if (IS_ERR(u.xsave)) {
6039 r = PTR_ERR(u.xsave);
6043 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
6047 case KVM_GET_XSAVE2: {
6048 int size = vcpu->arch.guest_fpu.uabi_size;
6050 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
6055 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
6058 if (copy_to_user(argp, u.xsave, size))
6065 case KVM_GET_XCRS: {
6066 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
6071 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
6074 if (copy_to_user(argp, u.xcrs,
6075 sizeof(struct kvm_xcrs)))
6080 case KVM_SET_XCRS: {
6081 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
6082 if (IS_ERR(u.xcrs)) {
6083 r = PTR_ERR(u.xcrs);
6087 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
6090 case KVM_SET_TSC_KHZ: {
6094 user_tsc_khz = (u32)arg;
6096 if (kvm_caps.has_tsc_control &&
6097 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6100 if (user_tsc_khz == 0)
6101 user_tsc_khz = tsc_khz;
6103 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
6108 case KVM_GET_TSC_KHZ: {
6109 r = vcpu->arch.virtual_tsc_khz;
6112 case KVM_KVMCLOCK_CTRL: {
6113 r = kvm_set_guest_paused(vcpu);
6116 case KVM_ENABLE_CAP: {
6117 struct kvm_enable_cap cap;
6120 if (copy_from_user(&cap, argp, sizeof(cap)))
6122 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
6125 case KVM_GET_NESTED_STATE: {
6126 struct kvm_nested_state __user *user_kvm_nested_state = argp;
6130 if (!kvm_x86_ops.nested_ops->get_state)
6133 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
6135 if (get_user(user_data_size, &user_kvm_nested_state->size))
6138 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
6143 if (r > user_data_size) {
6144 if (put_user(r, &user_kvm_nested_state->size))
6154 case KVM_SET_NESTED_STATE: {
6155 struct kvm_nested_state __user *user_kvm_nested_state = argp;
6156 struct kvm_nested_state kvm_state;
6160 if (!kvm_x86_ops.nested_ops->set_state)
6164 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
6168 if (kvm_state.size < sizeof(kvm_state))
6171 if (kvm_state.flags &
6172 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
6173 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
6174 | KVM_STATE_NESTED_GIF_SET))
6177 /* nested_run_pending implies guest_mode. */
6178 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
6179 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
6182 idx = srcu_read_lock(&vcpu->kvm->srcu);
6183 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
6184 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6187 #ifdef CONFIG_KVM_HYPERV
6188 case KVM_GET_SUPPORTED_HV_CPUID:
6189 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
6192 #ifdef CONFIG_KVM_XEN
6193 case KVM_XEN_VCPU_GET_ATTR: {
6194 struct kvm_xen_vcpu_attr xva;
6197 if (copy_from_user(&xva, argp, sizeof(xva)))
6199 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
6200 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
6204 case KVM_XEN_VCPU_SET_ATTR: {
6205 struct kvm_xen_vcpu_attr xva;
6208 if (copy_from_user(&xva, argp, sizeof(xva)))
6210 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
6214 case KVM_GET_SREGS2: {
6215 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
6219 __get_sregs2(vcpu, u.sregs2);
6221 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
6226 case KVM_SET_SREGS2: {
6227 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6228 if (IS_ERR(u.sregs2)) {
6229 r = PTR_ERR(u.sregs2);
6233 r = __set_sregs2(vcpu, u.sregs2);
6236 case KVM_HAS_DEVICE_ATTR:
6237 case KVM_GET_DEVICE_ATTR:
6238 case KVM_SET_DEVICE_ATTR:
6239 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6251 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6253 return VM_FAULT_SIGBUS;
6256 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6260 if (addr > (unsigned int)(-3 * PAGE_SIZE))
6262 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6266 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6269 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6272 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6273 unsigned long kvm_nr_mmu_pages)
6275 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6278 mutex_lock(&kvm->slots_lock);
6280 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6281 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6283 mutex_unlock(&kvm->slots_lock);
6287 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6289 struct kvm_pic *pic = kvm->arch.vpic;
6293 switch (chip->chip_id) {
6294 case KVM_IRQCHIP_PIC_MASTER:
6295 memcpy(&chip->chip.pic, &pic->pics[0],
6296 sizeof(struct kvm_pic_state));
6298 case KVM_IRQCHIP_PIC_SLAVE:
6299 memcpy(&chip->chip.pic, &pic->pics[1],
6300 sizeof(struct kvm_pic_state));
6302 case KVM_IRQCHIP_IOAPIC:
6303 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6312 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6314 struct kvm_pic *pic = kvm->arch.vpic;
6318 switch (chip->chip_id) {
6319 case KVM_IRQCHIP_PIC_MASTER:
6320 spin_lock(&pic->lock);
6321 memcpy(&pic->pics[0], &chip->chip.pic,
6322 sizeof(struct kvm_pic_state));
6323 spin_unlock(&pic->lock);
6325 case KVM_IRQCHIP_PIC_SLAVE:
6326 spin_lock(&pic->lock);
6327 memcpy(&pic->pics[1], &chip->chip.pic,
6328 sizeof(struct kvm_pic_state));
6329 spin_unlock(&pic->lock);
6331 case KVM_IRQCHIP_IOAPIC:
6332 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6338 kvm_pic_update_irq(pic);
6342 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6344 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6346 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6348 mutex_lock(&kps->lock);
6349 memcpy(ps, &kps->channels, sizeof(*ps));
6350 mutex_unlock(&kps->lock);
6354 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6357 struct kvm_pit *pit = kvm->arch.vpit;
6359 mutex_lock(&pit->pit_state.lock);
6360 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6361 for (i = 0; i < 3; i++)
6362 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6363 mutex_unlock(&pit->pit_state.lock);
6367 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6369 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6370 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6371 sizeof(ps->channels));
6372 ps->flags = kvm->arch.vpit->pit_state.flags;
6373 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6374 memset(&ps->reserved, 0, sizeof(ps->reserved));
6378 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6382 u32 prev_legacy, cur_legacy;
6383 struct kvm_pit *pit = kvm->arch.vpit;
6385 mutex_lock(&pit->pit_state.lock);
6386 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6387 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6388 if (!prev_legacy && cur_legacy)
6390 memcpy(&pit->pit_state.channels, &ps->channels,
6391 sizeof(pit->pit_state.channels));
6392 pit->pit_state.flags = ps->flags;
6393 for (i = 0; i < 3; i++)
6394 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6396 mutex_unlock(&pit->pit_state.lock);
6400 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6401 struct kvm_reinject_control *control)
6403 struct kvm_pit *pit = kvm->arch.vpit;
6405 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6406 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6407 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6409 mutex_lock(&pit->pit_state.lock);
6410 kvm_pit_set_reinject(pit, control->pit_reinject);
6411 mutex_unlock(&pit->pit_state.lock);
6416 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6420 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6421 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6422 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6425 struct kvm_vcpu *vcpu;
6428 if (!kvm_x86_ops.cpu_dirty_log_size)
6431 kvm_for_each_vcpu(i, vcpu, kvm)
6432 kvm_vcpu_kick(vcpu);
6435 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6438 if (!irqchip_in_kernel(kvm))
6441 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6442 irq_event->irq, irq_event->level,
6447 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6448 struct kvm_enable_cap *cap)
6456 case KVM_CAP_DISABLE_QUIRKS2:
6458 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6461 case KVM_CAP_DISABLE_QUIRKS:
6462 kvm->arch.disabled_quirks = cap->args[0];
6465 case KVM_CAP_SPLIT_IRQCHIP: {
6466 mutex_lock(&kvm->lock);
6468 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6469 goto split_irqchip_unlock;
6471 if (irqchip_in_kernel(kvm))
6472 goto split_irqchip_unlock;
6473 if (kvm->created_vcpus)
6474 goto split_irqchip_unlock;
6475 r = kvm_setup_empty_irq_routing(kvm);
6477 goto split_irqchip_unlock;
6478 /* Pairs with irqchip_in_kernel. */
6480 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6481 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6482 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6484 split_irqchip_unlock:
6485 mutex_unlock(&kvm->lock);
6488 case KVM_CAP_X2APIC_API:
6490 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6493 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6494 kvm->arch.x2apic_format = true;
6495 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6496 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6500 case KVM_CAP_X86_DISABLE_EXITS:
6502 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6505 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6506 kvm->arch.pause_in_guest = true;
6508 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6509 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6511 if (!mitigate_smt_rsb) {
6512 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6513 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6514 pr_warn_once(SMT_RSB_MSG);
6516 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6517 kvm_can_mwait_in_guest())
6518 kvm->arch.mwait_in_guest = true;
6519 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6520 kvm->arch.hlt_in_guest = true;
6521 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6522 kvm->arch.cstate_in_guest = true;
6527 case KVM_CAP_MSR_PLATFORM_INFO:
6528 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6531 case KVM_CAP_EXCEPTION_PAYLOAD:
6532 kvm->arch.exception_payload_enabled = cap->args[0];
6535 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6536 kvm->arch.triple_fault_event = cap->args[0];
6539 case KVM_CAP_X86_USER_SPACE_MSR:
6541 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6543 kvm->arch.user_space_msr_mask = cap->args[0];
6546 case KVM_CAP_X86_BUS_LOCK_EXIT:
6548 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6551 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6552 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6555 if (kvm_caps.has_bus_lock_exit &&
6556 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6557 kvm->arch.bus_lock_detection_enabled = true;
6560 #ifdef CONFIG_X86_SGX_KVM
6561 case KVM_CAP_SGX_ATTRIBUTE: {
6562 unsigned long allowed_attributes = 0;
6564 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6568 /* KVM only supports the PROVISIONKEY privileged attribute. */
6569 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6570 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6571 kvm->arch.sgx_provisioning_allowed = true;
6577 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6579 if (!kvm_x86_ops.vm_copy_enc_context_from)
6582 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6584 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6586 if (!kvm_x86_ops.vm_move_enc_context_from)
6589 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6591 case KVM_CAP_EXIT_HYPERCALL:
6592 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6596 kvm->arch.hypercall_exit_enabled = cap->args[0];
6599 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6601 if (cap->args[0] & ~1)
6603 kvm->arch.exit_on_emulation_error = cap->args[0];
6606 case KVM_CAP_PMU_CAPABILITY:
6608 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6611 mutex_lock(&kvm->lock);
6612 if (!kvm->created_vcpus) {
6613 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6616 mutex_unlock(&kvm->lock);
6618 case KVM_CAP_MAX_VCPU_ID:
6620 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6623 mutex_lock(&kvm->lock);
6624 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6626 } else if (!kvm->arch.max_vcpu_ids) {
6627 kvm->arch.max_vcpu_ids = cap->args[0];
6630 mutex_unlock(&kvm->lock);
6632 case KVM_CAP_X86_NOTIFY_VMEXIT:
6634 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6636 if (!kvm_caps.has_notify_vmexit)
6638 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6640 mutex_lock(&kvm->lock);
6641 if (!kvm->created_vcpus) {
6642 kvm->arch.notify_window = cap->args[0] >> 32;
6643 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6646 mutex_unlock(&kvm->lock);
6648 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6652 * Since the risk of disabling NX hugepages is a guest crashing
6653 * the system, ensure the userspace process has permission to
6654 * reboot the system.
6656 * Note that unlike the reboot() syscall, the process must have
6657 * this capability in the root namespace because exposing
6658 * /dev/kvm into a container does not limit the scope of the
6659 * iTLB multihit bug to that container. In other words,
6660 * this must use capable(), not ns_capable().
6662 if (!capable(CAP_SYS_BOOT)) {
6670 mutex_lock(&kvm->lock);
6671 if (!kvm->created_vcpus) {
6672 kvm->arch.disable_nx_huge_pages = true;
6675 mutex_unlock(&kvm->lock);
6684 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6686 struct kvm_x86_msr_filter *msr_filter;
6688 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6692 msr_filter->default_allow = default_allow;
6696 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6703 for (i = 0; i < msr_filter->count; i++)
6704 kfree(msr_filter->ranges[i].bitmap);
6709 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6710 struct kvm_msr_filter_range *user_range)
6712 unsigned long *bitmap;
6715 if (!user_range->nmsrs)
6718 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6721 if (!user_range->flags)
6724 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6725 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6728 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6730 return PTR_ERR(bitmap);
6732 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6733 .flags = user_range->flags,
6734 .base = user_range->base,
6735 .nmsrs = user_range->nmsrs,
6739 msr_filter->count++;
6743 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6744 struct kvm_msr_filter *filter)
6746 struct kvm_x86_msr_filter *new_filter, *old_filter;
6752 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6755 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6756 empty &= !filter->ranges[i].nmsrs;
6758 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6759 if (empty && !default_allow)
6762 new_filter = kvm_alloc_msr_filter(default_allow);
6766 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6767 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6769 kvm_free_msr_filter(new_filter);
6774 mutex_lock(&kvm->lock);
6775 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6776 mutex_is_locked(&kvm->lock));
6777 mutex_unlock(&kvm->lock);
6778 synchronize_srcu(&kvm->srcu);
6780 kvm_free_msr_filter(old_filter);
6782 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6787 #ifdef CONFIG_KVM_COMPAT
6788 /* for KVM_X86_SET_MSR_FILTER */
6789 struct kvm_msr_filter_range_compat {
6796 struct kvm_msr_filter_compat {
6798 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6801 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6803 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6806 void __user *argp = (void __user *)arg;
6807 struct kvm *kvm = filp->private_data;
6811 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6812 struct kvm_msr_filter __user *user_msr_filter = argp;
6813 struct kvm_msr_filter_compat filter_compat;
6814 struct kvm_msr_filter filter;
6817 if (copy_from_user(&filter_compat, user_msr_filter,
6818 sizeof(filter_compat)))
6821 filter.flags = filter_compat.flags;
6822 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6823 struct kvm_msr_filter_range_compat *cr;
6825 cr = &filter_compat.ranges[i];
6826 filter.ranges[i] = (struct kvm_msr_filter_range) {
6830 .bitmap = (__u8 *)(ulong)cr->bitmap,
6834 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6843 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6844 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6846 struct kvm_vcpu *vcpu;
6850 mutex_lock(&kvm->lock);
6851 kvm_for_each_vcpu(i, vcpu, kvm) {
6852 if (!vcpu->arch.pv_time.active)
6855 ret = kvm_set_guest_paused(vcpu);
6857 kvm_err("Failed to pause guest VCPU%d: %d\n",
6858 vcpu->vcpu_id, ret);
6862 mutex_unlock(&kvm->lock);
6864 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6867 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6870 case PM_HIBERNATION_PREPARE:
6871 case PM_SUSPEND_PREPARE:
6872 return kvm_arch_suspend_notifier(kvm);
6877 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6879 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6881 struct kvm_clock_data data = { 0 };
6883 get_kvmclock(kvm, &data);
6884 if (copy_to_user(argp, &data, sizeof(data)))
6890 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6892 struct kvm_arch *ka = &kvm->arch;
6893 struct kvm_clock_data data;
6896 if (copy_from_user(&data, argp, sizeof(data)))
6900 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6901 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6903 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6906 kvm_hv_request_tsc_page_update(kvm);
6907 kvm_start_pvclock_update(kvm);
6908 pvclock_update_vm_gtod_copy(kvm);
6911 * This pairs with kvm_guest_time_update(): when masterclock is
6912 * in use, we use master_kernel_ns + kvmclock_offset to set
6913 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6914 * is slightly ahead) here we risk going negative on unsigned
6915 * 'system_time' when 'data.clock' is very small.
6917 if (data.flags & KVM_CLOCK_REALTIME) {
6918 u64 now_real_ns = ktime_get_real_ns();
6921 * Avoid stepping the kvmclock backwards.
6923 if (now_real_ns > data.realtime)
6924 data.clock += now_real_ns - data.realtime;
6927 if (ka->use_master_clock)
6928 now_raw_ns = ka->master_kernel_ns;
6930 now_raw_ns = get_kvmclock_base_ns();
6931 ka->kvmclock_offset = data.clock - now_raw_ns;
6932 kvm_end_pvclock_update(kvm);
6936 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6938 struct kvm *kvm = filp->private_data;
6939 void __user *argp = (void __user *)arg;
6942 * This union makes it completely explicit to gcc-3.x
6943 * that these two variables' stack usage should be
6944 * combined, not added together.
6947 struct kvm_pit_state ps;
6948 struct kvm_pit_state2 ps2;
6949 struct kvm_pit_config pit_config;
6953 case KVM_SET_TSS_ADDR:
6954 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6956 case KVM_SET_IDENTITY_MAP_ADDR: {
6959 mutex_lock(&kvm->lock);
6961 if (kvm->created_vcpus)
6962 goto set_identity_unlock;
6964 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6965 goto set_identity_unlock;
6966 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6967 set_identity_unlock:
6968 mutex_unlock(&kvm->lock);
6971 case KVM_SET_NR_MMU_PAGES:
6972 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6974 case KVM_CREATE_IRQCHIP: {
6975 mutex_lock(&kvm->lock);
6978 if (irqchip_in_kernel(kvm))
6979 goto create_irqchip_unlock;
6982 if (kvm->created_vcpus)
6983 goto create_irqchip_unlock;
6985 r = kvm_pic_init(kvm);
6987 goto create_irqchip_unlock;
6989 r = kvm_ioapic_init(kvm);
6991 kvm_pic_destroy(kvm);
6992 goto create_irqchip_unlock;
6995 r = kvm_setup_default_irq_routing(kvm);
6997 kvm_ioapic_destroy(kvm);
6998 kvm_pic_destroy(kvm);
6999 goto create_irqchip_unlock;
7001 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
7003 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
7004 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
7005 create_irqchip_unlock:
7006 mutex_unlock(&kvm->lock);
7009 case KVM_CREATE_PIT:
7010 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
7012 case KVM_CREATE_PIT2:
7014 if (copy_from_user(&u.pit_config, argp,
7015 sizeof(struct kvm_pit_config)))
7018 mutex_lock(&kvm->lock);
7021 goto create_pit_unlock;
7023 if (!pic_in_kernel(kvm))
7024 goto create_pit_unlock;
7026 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7030 mutex_unlock(&kvm->lock);
7032 case KVM_GET_IRQCHIP: {
7033 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
7034 struct kvm_irqchip *chip;
7036 chip = memdup_user(argp, sizeof(*chip));
7043 if (!irqchip_kernel(kvm))
7044 goto get_irqchip_out;
7045 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
7047 goto get_irqchip_out;
7049 if (copy_to_user(argp, chip, sizeof(*chip)))
7050 goto get_irqchip_out;
7056 case KVM_SET_IRQCHIP: {
7057 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
7058 struct kvm_irqchip *chip;
7060 chip = memdup_user(argp, sizeof(*chip));
7067 if (!irqchip_kernel(kvm))
7068 goto set_irqchip_out;
7069 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
7076 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
7079 if (!kvm->arch.vpit)
7081 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
7085 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
7092 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
7094 mutex_lock(&kvm->lock);
7096 if (!kvm->arch.vpit)
7098 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
7100 mutex_unlock(&kvm->lock);
7103 case KVM_GET_PIT2: {
7105 if (!kvm->arch.vpit)
7107 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
7111 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
7116 case KVM_SET_PIT2: {
7118 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
7120 mutex_lock(&kvm->lock);
7122 if (!kvm->arch.vpit)
7124 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
7126 mutex_unlock(&kvm->lock);
7129 case KVM_REINJECT_CONTROL: {
7130 struct kvm_reinject_control control;
7132 if (copy_from_user(&control, argp, sizeof(control)))
7135 if (!kvm->arch.vpit)
7137 r = kvm_vm_ioctl_reinject(kvm, &control);
7140 case KVM_SET_BOOT_CPU_ID:
7142 mutex_lock(&kvm->lock);
7143 if (kvm->created_vcpus)
7146 kvm->arch.bsp_vcpu_id = arg;
7147 mutex_unlock(&kvm->lock);
7149 #ifdef CONFIG_KVM_XEN
7150 case KVM_XEN_HVM_CONFIG: {
7151 struct kvm_xen_hvm_config xhc;
7153 if (copy_from_user(&xhc, argp, sizeof(xhc)))
7155 r = kvm_xen_hvm_config(kvm, &xhc);
7158 case KVM_XEN_HVM_GET_ATTR: {
7159 struct kvm_xen_hvm_attr xha;
7162 if (copy_from_user(&xha, argp, sizeof(xha)))
7164 r = kvm_xen_hvm_get_attr(kvm, &xha);
7165 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
7169 case KVM_XEN_HVM_SET_ATTR: {
7170 struct kvm_xen_hvm_attr xha;
7173 if (copy_from_user(&xha, argp, sizeof(xha)))
7175 r = kvm_xen_hvm_set_attr(kvm, &xha);
7178 case KVM_XEN_HVM_EVTCHN_SEND: {
7179 struct kvm_irq_routing_xen_evtchn uxe;
7182 if (copy_from_user(&uxe, argp, sizeof(uxe)))
7184 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
7189 r = kvm_vm_ioctl_set_clock(kvm, argp);
7192 r = kvm_vm_ioctl_get_clock(kvm, argp);
7194 case KVM_SET_TSC_KHZ: {
7198 user_tsc_khz = (u32)arg;
7200 if (kvm_caps.has_tsc_control &&
7201 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
7204 if (user_tsc_khz == 0)
7205 user_tsc_khz = tsc_khz;
7207 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
7212 case KVM_GET_TSC_KHZ: {
7213 r = READ_ONCE(kvm->arch.default_tsc_khz);
7216 case KVM_MEMORY_ENCRYPT_OP: {
7218 if (!kvm_x86_ops.mem_enc_ioctl)
7221 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
7224 case KVM_MEMORY_ENCRYPT_REG_REGION: {
7225 struct kvm_enc_region region;
7228 if (copy_from_user(®ion, argp, sizeof(region)))
7232 if (!kvm_x86_ops.mem_enc_register_region)
7235 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
7238 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7239 struct kvm_enc_region region;
7242 if (copy_from_user(®ion, argp, sizeof(region)))
7246 if (!kvm_x86_ops.mem_enc_unregister_region)
7249 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
7252 #ifdef CONFIG_KVM_HYPERV
7253 case KVM_HYPERV_EVENTFD: {
7254 struct kvm_hyperv_eventfd hvevfd;
7257 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7259 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7263 case KVM_SET_PMU_EVENT_FILTER:
7264 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7266 case KVM_X86_SET_MSR_FILTER: {
7267 struct kvm_msr_filter __user *user_msr_filter = argp;
7268 struct kvm_msr_filter filter;
7270 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7273 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7283 static void kvm_probe_feature_msr(u32 msr_index)
7285 struct kvm_msr_entry msr = {
7289 if (kvm_get_msr_feature(&msr))
7292 msr_based_features[num_msr_based_features++] = msr_index;
7295 static void kvm_probe_msr_to_save(u32 msr_index)
7299 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7303 * Even MSRs that are valid in the host may not be exposed to guests in
7306 switch (msr_index) {
7307 case MSR_IA32_BNDCFGS:
7308 if (!kvm_mpx_supported())
7312 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7313 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7316 case MSR_IA32_UMWAIT_CONTROL:
7317 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7320 case MSR_IA32_RTIT_CTL:
7321 case MSR_IA32_RTIT_STATUS:
7322 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7325 case MSR_IA32_RTIT_CR3_MATCH:
7326 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7327 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7330 case MSR_IA32_RTIT_OUTPUT_BASE:
7331 case MSR_IA32_RTIT_OUTPUT_MASK:
7332 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7333 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7334 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7337 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7338 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7339 (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7340 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7343 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7344 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7345 kvm_pmu_cap.num_counters_gp)
7348 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7349 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7350 kvm_pmu_cap.num_counters_gp)
7353 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7354 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7355 kvm_pmu_cap.num_counters_fixed)
7358 case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
7359 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
7360 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
7361 if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
7365 case MSR_IA32_XFD_ERR:
7366 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7369 case MSR_IA32_TSX_CTRL:
7370 if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR))
7377 msrs_to_save[num_msrs_to_save++] = msr_index;
7380 static void kvm_init_msr_lists(void)
7384 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7385 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7387 num_msrs_to_save = 0;
7388 num_emulated_msrs = 0;
7389 num_msr_based_features = 0;
7391 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7392 kvm_probe_msr_to_save(msrs_to_save_base[i]);
7395 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7396 kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7399 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7400 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7403 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7406 for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++)
7407 kvm_probe_feature_msr(i);
7409 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++)
7410 kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]);
7413 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7421 if (!(lapic_in_kernel(vcpu) &&
7422 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7423 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7434 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7441 if (!(lapic_in_kernel(vcpu) &&
7442 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7444 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7446 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7456 void kvm_set_segment(struct kvm_vcpu *vcpu,
7457 struct kvm_segment *var, int seg)
7459 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7462 void kvm_get_segment(struct kvm_vcpu *vcpu,
7463 struct kvm_segment *var, int seg)
7465 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7468 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7469 struct x86_exception *exception)
7471 struct kvm_mmu *mmu = vcpu->arch.mmu;
7474 BUG_ON(!mmu_is_nested(vcpu));
7476 /* NPT walks are always user-walks */
7477 access |= PFERR_USER_MASK;
7478 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7483 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7484 struct x86_exception *exception)
7486 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7488 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7489 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7491 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7493 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7494 struct x86_exception *exception)
7496 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7498 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7499 access |= PFERR_WRITE_MASK;
7500 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7502 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7504 /* uses this to access any guest's mapped memory without checking CPL */
7505 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7506 struct x86_exception *exception)
7508 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7510 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7513 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7514 struct kvm_vcpu *vcpu, u64 access,
7515 struct x86_exception *exception)
7517 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7519 int r = X86EMUL_CONTINUE;
7522 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7523 unsigned offset = addr & (PAGE_SIZE-1);
7524 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7527 if (gpa == INVALID_GPA)
7528 return X86EMUL_PROPAGATE_FAULT;
7529 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7532 r = X86EMUL_IO_NEEDED;
7544 /* used for instruction fetching */
7545 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7546 gva_t addr, void *val, unsigned int bytes,
7547 struct x86_exception *exception)
7549 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7550 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7551 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7555 /* Inline kvm_read_guest_virt_helper for speed. */
7556 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7558 if (unlikely(gpa == INVALID_GPA))
7559 return X86EMUL_PROPAGATE_FAULT;
7561 offset = addr & (PAGE_SIZE-1);
7562 if (WARN_ON(offset + bytes > PAGE_SIZE))
7563 bytes = (unsigned)PAGE_SIZE - offset;
7564 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7566 if (unlikely(ret < 0))
7567 return X86EMUL_IO_NEEDED;
7569 return X86EMUL_CONTINUE;
7572 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7573 gva_t addr, void *val, unsigned int bytes,
7574 struct x86_exception *exception)
7576 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7579 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7580 * is returned, but our callers are not ready for that and they blindly
7581 * call kvm_inject_page_fault. Ensure that they at least do not leak
7582 * uninitialized kernel stack memory into cr2 and error code.
7584 memset(exception, 0, sizeof(*exception));
7585 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7588 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7590 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7591 gva_t addr, void *val, unsigned int bytes,
7592 struct x86_exception *exception, bool system)
7594 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7598 access |= PFERR_IMPLICIT_ACCESS;
7599 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7600 access |= PFERR_USER_MASK;
7602 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7605 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7606 struct kvm_vcpu *vcpu, u64 access,
7607 struct x86_exception *exception)
7609 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7611 int r = X86EMUL_CONTINUE;
7614 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7615 unsigned offset = addr & (PAGE_SIZE-1);
7616 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7619 if (gpa == INVALID_GPA)
7620 return X86EMUL_PROPAGATE_FAULT;
7621 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7623 r = X86EMUL_IO_NEEDED;
7635 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7636 unsigned int bytes, struct x86_exception *exception,
7639 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7640 u64 access = PFERR_WRITE_MASK;
7643 access |= PFERR_IMPLICIT_ACCESS;
7644 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7645 access |= PFERR_USER_MASK;
7647 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7651 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7652 unsigned int bytes, struct x86_exception *exception)
7654 /* kvm_write_guest_virt_system can pull in tons of pages. */
7655 vcpu->arch.l1tf_flush_l1d = true;
7657 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7658 PFERR_WRITE_MASK, exception);
7660 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7662 static int kvm_check_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7663 void *insn, int insn_len)
7665 return static_call(kvm_x86_check_emulate_instruction)(vcpu, emul_type,
7669 int handle_ud(struct kvm_vcpu *vcpu)
7671 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7672 int fep_flags = READ_ONCE(force_emulation_prefix);
7673 int emul_type = EMULTYPE_TRAP_UD;
7674 char sig[5]; /* ud2; .ascii "kvm" */
7675 struct x86_exception e;
7678 r = kvm_check_emulate_insn(vcpu, emul_type, NULL, 0);
7679 if (r != X86EMUL_CONTINUE)
7683 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7684 sig, sizeof(sig), &e) == 0 &&
7685 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7686 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7687 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7688 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7689 emul_type = EMULTYPE_TRAP_UD_FORCED;
7692 return kvm_emulate_instruction(vcpu, emul_type);
7694 EXPORT_SYMBOL_GPL(handle_ud);
7696 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7697 gpa_t gpa, bool write)
7699 /* For APIC access vmexit */
7700 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7703 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7704 trace_vcpu_match_mmio(gva, gpa, write, true);
7711 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7712 gpa_t *gpa, struct x86_exception *exception,
7715 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7716 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7717 | (write ? PFERR_WRITE_MASK : 0);
7720 * currently PKRU is only applied to ept enabled guest so
7721 * there is no pkey in EPT page table for L1 guest or EPT
7722 * shadow page table for L2 guest.
7724 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7725 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7726 vcpu->arch.mmio_access, 0, access))) {
7727 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7728 (gva & (PAGE_SIZE - 1));
7729 trace_vcpu_match_mmio(gva, *gpa, write, false);
7733 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7735 if (*gpa == INVALID_GPA)
7738 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7741 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7742 const void *val, int bytes)
7746 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7749 kvm_page_track_write(vcpu, gpa, val, bytes);
7753 struct read_write_emulator_ops {
7754 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7756 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7757 void *val, int bytes);
7758 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7759 int bytes, void *val);
7760 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7761 void *val, int bytes);
7765 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7767 if (vcpu->mmio_read_completed) {
7768 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7769 vcpu->mmio_fragments[0].gpa, val);
7770 vcpu->mmio_read_completed = 0;
7777 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7778 void *val, int bytes)
7780 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7783 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7784 void *val, int bytes)
7786 return emulator_write_phys(vcpu, gpa, val, bytes);
7789 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7791 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7792 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7795 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7796 void *val, int bytes)
7798 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7799 return X86EMUL_IO_NEEDED;
7802 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7803 void *val, int bytes)
7805 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7807 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7808 return X86EMUL_CONTINUE;
7811 static const struct read_write_emulator_ops read_emultor = {
7812 .read_write_prepare = read_prepare,
7813 .read_write_emulate = read_emulate,
7814 .read_write_mmio = vcpu_mmio_read,
7815 .read_write_exit_mmio = read_exit_mmio,
7818 static const struct read_write_emulator_ops write_emultor = {
7819 .read_write_emulate = write_emulate,
7820 .read_write_mmio = write_mmio,
7821 .read_write_exit_mmio = write_exit_mmio,
7825 static int emulator_read_write_onepage(unsigned long addr, void *val,
7827 struct x86_exception *exception,
7828 struct kvm_vcpu *vcpu,
7829 const struct read_write_emulator_ops *ops)
7833 bool write = ops->write;
7834 struct kvm_mmio_fragment *frag;
7835 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7838 * If the exit was due to a NPF we may already have a GPA.
7839 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7840 * Note, this cannot be used on string operations since string
7841 * operation using rep will only have the initial GPA from the NPF
7844 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7845 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7846 gpa = ctxt->gpa_val;
7847 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7849 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7851 return X86EMUL_PROPAGATE_FAULT;
7854 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7855 return X86EMUL_CONTINUE;
7858 * Is this MMIO handled locally?
7860 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7861 if (handled == bytes)
7862 return X86EMUL_CONTINUE;
7868 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7869 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7873 return X86EMUL_CONTINUE;
7876 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7878 void *val, unsigned int bytes,
7879 struct x86_exception *exception,
7880 const struct read_write_emulator_ops *ops)
7882 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7886 if (ops->read_write_prepare &&
7887 ops->read_write_prepare(vcpu, val, bytes))
7888 return X86EMUL_CONTINUE;
7890 vcpu->mmio_nr_fragments = 0;
7892 /* Crossing a page boundary? */
7893 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7896 now = -addr & ~PAGE_MASK;
7897 rc = emulator_read_write_onepage(addr, val, now, exception,
7900 if (rc != X86EMUL_CONTINUE)
7903 if (ctxt->mode != X86EMUL_MODE_PROT64)
7909 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7911 if (rc != X86EMUL_CONTINUE)
7914 if (!vcpu->mmio_nr_fragments)
7917 gpa = vcpu->mmio_fragments[0].gpa;
7919 vcpu->mmio_needed = 1;
7920 vcpu->mmio_cur_fragment = 0;
7922 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7923 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7924 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7925 vcpu->run->mmio.phys_addr = gpa;
7927 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7930 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7934 struct x86_exception *exception)
7936 return emulator_read_write(ctxt, addr, val, bytes,
7937 exception, &read_emultor);
7940 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7944 struct x86_exception *exception)
7946 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7947 exception, &write_emultor);
7950 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7951 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7953 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7958 struct x86_exception *exception)
7960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7966 /* guests cmpxchg8b have to be emulated atomically */
7967 if (bytes > 8 || (bytes & (bytes - 1)))
7970 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7972 if (gpa == INVALID_GPA ||
7973 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7977 * Emulate the atomic as a straight write to avoid #AC if SLD is
7978 * enabled in the host and the access splits a cache line.
7980 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7981 page_line_mask = ~(cache_line_size() - 1);
7983 page_line_mask = PAGE_MASK;
7985 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7988 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7989 if (kvm_is_error_hva(hva))
7992 hva += offset_in_page(gpa);
7996 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7999 r = emulator_try_cmpxchg_user(u16, hva, old, new);
8002 r = emulator_try_cmpxchg_user(u32, hva, old, new);
8005 r = emulator_try_cmpxchg_user(u64, hva, old, new);
8012 return X86EMUL_UNHANDLEABLE;
8015 * Mark the page dirty _before_ checking whether or not the CMPXCHG was
8016 * successful, as the old value is written back on failure. Note, for
8017 * live migration, this is unnecessarily conservative as CMPXCHG writes
8018 * back the original value and the access is atomic, but KVM's ABI is
8019 * that all writes are dirty logged, regardless of the value written.
8021 kvm_vcpu_mark_page_dirty(vcpu, gpa_to_gfn(gpa));
8024 return X86EMUL_CMPXCHG_FAILED;
8026 kvm_page_track_write(vcpu, gpa, new, bytes);
8028 return X86EMUL_CONTINUE;
8031 pr_warn_once("emulating exchange as write\n");
8033 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
8036 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
8037 unsigned short port, void *data,
8038 unsigned int count, bool in)
8043 WARN_ON_ONCE(vcpu->arch.pio.count);
8044 for (i = 0; i < count; i++) {
8046 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
8048 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
8055 * Userspace must have unregistered the device while PIO
8056 * was running. Drop writes / read as 0.
8059 memset(data, 0, size * (count - i));
8068 vcpu->arch.pio.port = port;
8069 vcpu->arch.pio.in = in;
8070 vcpu->arch.pio.count = count;
8071 vcpu->arch.pio.size = size;
8074 memset(vcpu->arch.pio_data, 0, size * count);
8076 memcpy(vcpu->arch.pio_data, data, size * count);
8078 vcpu->run->exit_reason = KVM_EXIT_IO;
8079 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
8080 vcpu->run->io.size = size;
8081 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
8082 vcpu->run->io.count = count;
8083 vcpu->run->io.port = port;
8087 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
8088 unsigned short port, void *val, unsigned int count)
8090 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
8092 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
8097 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
8099 int size = vcpu->arch.pio.size;
8100 unsigned int count = vcpu->arch.pio.count;
8101 memcpy(val, vcpu->arch.pio_data, size * count);
8102 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
8103 vcpu->arch.pio.count = 0;
8106 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
8107 int size, unsigned short port, void *val,
8110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8111 if (vcpu->arch.pio.count) {
8113 * Complete a previous iteration that required userspace I/O.
8114 * Note, @count isn't guaranteed to match pio.count as userspace
8115 * can modify ECX before rerunning the vCPU. Ignore any such
8116 * shenanigans as KVM doesn't support modifying the rep count,
8117 * and the emulator ensures @count doesn't overflow the buffer.
8119 complete_emulator_pio_in(vcpu, val);
8123 return emulator_pio_in(vcpu, size, port, val, count);
8126 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
8127 unsigned short port, const void *val,
8130 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
8131 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
8134 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
8135 int size, unsigned short port,
8136 const void *val, unsigned int count)
8138 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
8141 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
8143 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
8146 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
8148 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
8151 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
8153 if (!need_emulate_wbinvd(vcpu))
8154 return X86EMUL_CONTINUE;
8156 if (static_call(kvm_x86_has_wbinvd_exit)()) {
8157 int cpu = get_cpu();
8159 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
8160 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
8161 wbinvd_ipi, NULL, 1);
8163 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
8166 return X86EMUL_CONTINUE;
8169 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
8171 kvm_emulate_wbinvd_noskip(vcpu);
8172 return kvm_skip_emulated_instruction(vcpu);
8174 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
8178 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
8180 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
8183 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
8184 unsigned long *dest)
8186 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
8189 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
8190 unsigned long value)
8193 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
8196 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
8198 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
8201 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
8203 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8204 unsigned long value;
8208 value = kvm_read_cr0(vcpu);
8211 value = vcpu->arch.cr2;
8214 value = kvm_read_cr3(vcpu);
8217 value = kvm_read_cr4(vcpu);
8220 value = kvm_get_cr8(vcpu);
8223 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8230 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
8232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8237 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
8240 vcpu->arch.cr2 = val;
8243 res = kvm_set_cr3(vcpu, val);
8246 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8249 res = kvm_set_cr8(vcpu, val);
8252 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8259 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
8261 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
8264 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8266 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8269 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8271 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8274 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8276 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8279 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8281 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8284 static unsigned long emulator_get_cached_segment_base(
8285 struct x86_emulate_ctxt *ctxt, int seg)
8287 return get_segment_base(emul_to_vcpu(ctxt), seg);
8290 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8291 struct desc_struct *desc, u32 *base3,
8294 struct kvm_segment var;
8296 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8297 *selector = var.selector;
8300 memset(desc, 0, sizeof(*desc));
8308 set_desc_limit(desc, var.limit);
8309 set_desc_base(desc, (unsigned long)var.base);
8310 #ifdef CONFIG_X86_64
8312 *base3 = var.base >> 32;
8314 desc->type = var.type;
8316 desc->dpl = var.dpl;
8317 desc->p = var.present;
8318 desc->avl = var.avl;
8326 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8327 struct desc_struct *desc, u32 base3,
8330 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8331 struct kvm_segment var;
8333 var.selector = selector;
8334 var.base = get_desc_base(desc);
8335 #ifdef CONFIG_X86_64
8336 var.base |= ((u64)base3) << 32;
8338 var.limit = get_desc_limit(desc);
8340 var.limit = (var.limit << 12) | 0xfff;
8341 var.type = desc->type;
8342 var.dpl = desc->dpl;
8347 var.avl = desc->avl;
8348 var.present = desc->p;
8349 var.unusable = !var.present;
8352 kvm_set_segment(vcpu, &var, seg);
8356 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8357 u32 msr_index, u64 *pdata)
8359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8362 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8364 return X86EMUL_UNHANDLEABLE;
8367 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8368 complete_emulated_rdmsr, r))
8369 return X86EMUL_IO_NEEDED;
8371 trace_kvm_msr_read_ex(msr_index);
8372 return X86EMUL_PROPAGATE_FAULT;
8375 trace_kvm_msr_read(msr_index, *pdata);
8376 return X86EMUL_CONTINUE;
8379 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8380 u32 msr_index, u64 data)
8382 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8385 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8387 return X86EMUL_UNHANDLEABLE;
8390 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8391 complete_emulated_msr_access, r))
8392 return X86EMUL_IO_NEEDED;
8394 trace_kvm_msr_write_ex(msr_index, data);
8395 return X86EMUL_PROPAGATE_FAULT;
8398 trace_kvm_msr_write(msr_index, data);
8399 return X86EMUL_CONTINUE;
8402 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8403 u32 msr_index, u64 *pdata)
8405 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8408 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8411 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8416 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8417 u32 pmc, u64 *pdata)
8419 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8422 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8424 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8427 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8428 struct x86_instruction_info *info,
8429 enum x86_intercept_stage stage)
8431 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8435 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8436 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8439 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8442 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8444 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8447 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8449 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8452 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8454 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8457 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8459 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8462 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8464 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8467 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8469 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8472 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8474 return is_smm(emul_to_vcpu(ctxt));
8477 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8479 return is_guest_mode(emul_to_vcpu(ctxt));
8482 #ifndef CONFIG_KVM_SMM
8483 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8486 return X86EMUL_UNHANDLEABLE;
8490 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8492 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8495 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8497 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8500 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8502 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8504 if (!kvm->vm_bugged)
8508 static gva_t emulator_get_untagged_addr(struct x86_emulate_ctxt *ctxt,
8509 gva_t addr, unsigned int flags)
8511 if (!kvm_x86_ops.get_untagged_addr)
8514 return static_call(kvm_x86_get_untagged_addr)(emul_to_vcpu(ctxt), addr, flags);
8517 static const struct x86_emulate_ops emulate_ops = {
8518 .vm_bugged = emulator_vm_bugged,
8519 .read_gpr = emulator_read_gpr,
8520 .write_gpr = emulator_write_gpr,
8521 .read_std = emulator_read_std,
8522 .write_std = emulator_write_std,
8523 .fetch = kvm_fetch_guest_virt,
8524 .read_emulated = emulator_read_emulated,
8525 .write_emulated = emulator_write_emulated,
8526 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8527 .invlpg = emulator_invlpg,
8528 .pio_in_emulated = emulator_pio_in_emulated,
8529 .pio_out_emulated = emulator_pio_out_emulated,
8530 .get_segment = emulator_get_segment,
8531 .set_segment = emulator_set_segment,
8532 .get_cached_segment_base = emulator_get_cached_segment_base,
8533 .get_gdt = emulator_get_gdt,
8534 .get_idt = emulator_get_idt,
8535 .set_gdt = emulator_set_gdt,
8536 .set_idt = emulator_set_idt,
8537 .get_cr = emulator_get_cr,
8538 .set_cr = emulator_set_cr,
8539 .cpl = emulator_get_cpl,
8540 .get_dr = emulator_get_dr,
8541 .set_dr = emulator_set_dr,
8542 .set_msr_with_filter = emulator_set_msr_with_filter,
8543 .get_msr_with_filter = emulator_get_msr_with_filter,
8544 .get_msr = emulator_get_msr,
8545 .check_pmc = emulator_check_pmc,
8546 .read_pmc = emulator_read_pmc,
8547 .halt = emulator_halt,
8548 .wbinvd = emulator_wbinvd,
8549 .fix_hypercall = emulator_fix_hypercall,
8550 .intercept = emulator_intercept,
8551 .get_cpuid = emulator_get_cpuid,
8552 .guest_has_movbe = emulator_guest_has_movbe,
8553 .guest_has_fxsr = emulator_guest_has_fxsr,
8554 .guest_has_rdpid = emulator_guest_has_rdpid,
8555 .set_nmi_mask = emulator_set_nmi_mask,
8556 .is_smm = emulator_is_smm,
8557 .is_guest_mode = emulator_is_guest_mode,
8558 .leave_smm = emulator_leave_smm,
8559 .triple_fault = emulator_triple_fault,
8560 .set_xcr = emulator_set_xcr,
8561 .get_untagged_addr = emulator_get_untagged_addr,
8564 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8566 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8568 * an sti; sti; sequence only disable interrupts for the first
8569 * instruction. So, if the last instruction, be it emulated or
8570 * not, left the system with the INT_STI flag enabled, it
8571 * means that the last instruction is an sti. We should not
8572 * leave the flag on in this case. The same goes for mov ss
8574 if (int_shadow & mask)
8576 if (unlikely(int_shadow || mask)) {
8577 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8579 kvm_make_request(KVM_REQ_EVENT, vcpu);
8583 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8585 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8587 if (ctxt->exception.vector == PF_VECTOR)
8588 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8589 else if (ctxt->exception.error_code_valid)
8590 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8591 ctxt->exception.error_code);
8593 kvm_queue_exception(vcpu, ctxt->exception.vector);
8596 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8598 struct x86_emulate_ctxt *ctxt;
8600 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8602 pr_err("failed to allocate vcpu's emulator\n");
8607 ctxt->ops = &emulate_ops;
8608 vcpu->arch.emulate_ctxt = ctxt;
8613 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8615 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8618 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8620 ctxt->gpa_available = false;
8621 ctxt->eflags = kvm_get_rflags(vcpu);
8622 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8624 ctxt->eip = kvm_rip_read(vcpu);
8625 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8626 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8627 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8628 cs_db ? X86EMUL_MODE_PROT32 :
8629 X86EMUL_MODE_PROT16;
8630 ctxt->interruptibility = 0;
8631 ctxt->have_exception = false;
8632 ctxt->exception.vector = -1;
8633 ctxt->perm_ok = false;
8635 init_decode_cache(ctxt);
8636 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8639 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8641 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8644 init_emulate_ctxt(vcpu);
8648 ctxt->_eip = ctxt->eip + inc_eip;
8649 ret = emulate_int_real(ctxt, irq);
8651 if (ret != X86EMUL_CONTINUE) {
8652 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8654 ctxt->eip = ctxt->_eip;
8655 kvm_rip_write(vcpu, ctxt->eip);
8656 kvm_set_rflags(vcpu, ctxt->eflags);
8659 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8661 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8662 u8 ndata, u8 *insn_bytes, u8 insn_size)
8664 struct kvm_run *run = vcpu->run;
8669 * Zero the whole array used to retrieve the exit info, as casting to
8670 * u32 for select entries will leave some chunks uninitialized.
8672 memset(&info, 0, sizeof(info));
8674 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8675 &info[2], (u32 *)&info[3],
8678 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8679 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8682 * There's currently space for 13 entries, but 5 are used for the exit
8683 * reason and info. Restrict to 4 to reduce the maintenance burden
8684 * when expanding kvm_run.emulation_failure in the future.
8686 if (WARN_ON_ONCE(ndata > 4))
8689 /* Always include the flags as a 'data' entry. */
8691 run->emulation_failure.flags = 0;
8694 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8695 sizeof(run->emulation_failure.insn_bytes) != 16));
8697 run->emulation_failure.flags |=
8698 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8699 run->emulation_failure.insn_size = insn_size;
8700 memset(run->emulation_failure.insn_bytes, 0x90,
8701 sizeof(run->emulation_failure.insn_bytes));
8702 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8705 memcpy(&run->internal.data[info_start], info, sizeof(info));
8706 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8707 ndata * sizeof(data[0]));
8709 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8712 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8714 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8716 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8717 ctxt->fetch.end - ctxt->fetch.data);
8720 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8723 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8725 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8727 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8729 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8731 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8733 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8735 struct kvm *kvm = vcpu->kvm;
8737 ++vcpu->stat.insn_emulation_fail;
8738 trace_kvm_emulate_insn_failed(vcpu);
8740 if (emulation_type & EMULTYPE_VMWARE_GP) {
8741 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8745 if (kvm->arch.exit_on_emulation_error ||
8746 (emulation_type & EMULTYPE_SKIP)) {
8747 prepare_emulation_ctxt_failure_exit(vcpu);
8751 kvm_queue_exception(vcpu, UD_VECTOR);
8753 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8754 prepare_emulation_ctxt_failure_exit(vcpu);
8761 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8764 gpa_t gpa = cr2_or_gpa;
8767 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8770 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8771 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8774 if (!vcpu->arch.mmu->root_role.direct) {
8776 * Write permission should be allowed since only
8777 * write access need to be emulated.
8779 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8782 * If the mapping is invalid in guest, let cpu retry
8783 * it to generate fault.
8785 if (gpa == INVALID_GPA)
8790 * Do not retry the unhandleable instruction if it faults on the
8791 * readonly host memory, otherwise it will goto a infinite loop:
8792 * retry instruction -> write #PF -> emulation fail -> retry
8793 * instruction -> ...
8795 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8798 * If the instruction failed on the error pfn, it can not be fixed,
8799 * report the error to userspace.
8801 if (is_error_noslot_pfn(pfn))
8804 kvm_release_pfn_clean(pfn);
8806 /* The instructions are well-emulated on direct mmu. */
8807 if (vcpu->arch.mmu->root_role.direct) {
8808 unsigned int indirect_shadow_pages;
8810 write_lock(&vcpu->kvm->mmu_lock);
8811 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8812 write_unlock(&vcpu->kvm->mmu_lock);
8814 if (indirect_shadow_pages)
8815 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8821 * if emulation was due to access to shadowed page table
8822 * and it failed try to unshadow page and re-enter the
8823 * guest to let CPU execute the instruction.
8825 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8828 * If the access faults on its page table, it can not
8829 * be fixed by unprotecting shadow page and it should
8830 * be reported to userspace.
8832 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8835 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8836 gpa_t cr2_or_gpa, int emulation_type)
8838 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8839 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8841 last_retry_eip = vcpu->arch.last_retry_eip;
8842 last_retry_addr = vcpu->arch.last_retry_addr;
8845 * If the emulation is caused by #PF and it is non-page_table
8846 * writing instruction, it means the VM-EXIT is caused by shadow
8847 * page protected, we can zap the shadow page and retry this
8848 * instruction directly.
8850 * Note: if the guest uses a non-page-table modifying instruction
8851 * on the PDE that points to the instruction, then we will unmap
8852 * the instruction and go to an infinite loop. So, we cache the
8853 * last retried eip and the last fault address, if we meet the eip
8854 * and the address again, we can break out of the potential infinite
8857 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8859 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8862 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8863 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8866 if (x86_page_table_writing_insn(ctxt))
8869 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8872 vcpu->arch.last_retry_eip = ctxt->eip;
8873 vcpu->arch.last_retry_addr = cr2_or_gpa;
8875 if (!vcpu->arch.mmu->root_role.direct)
8876 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8878 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8883 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8884 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8886 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8895 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8896 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8901 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8903 struct kvm_run *kvm_run = vcpu->run;
8905 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8906 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8907 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8908 kvm_run->debug.arch.exception = DB_VECTOR;
8909 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8912 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8916 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8918 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8921 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8925 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8928 * rflags is the old, "raw" value of the flags. The new value has
8929 * not been saved yet.
8931 * This is correct even for TF set by the guest, because "the
8932 * processor will not generate this exception after the instruction
8933 * that sets the TF flag".
8935 if (unlikely(rflags & X86_EFLAGS_TF))
8936 r = kvm_vcpu_do_singlestep(vcpu);
8939 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8941 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8945 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8949 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8950 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8951 * to avoid the relatively expensive CPUID lookup.
8953 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8954 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8955 guest_cpuid_is_intel(vcpu);
8958 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8959 int emulation_type, int *r)
8961 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8964 * Do not check for code breakpoints if hardware has already done the
8965 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8966 * the instruction has passed all exception checks, and all intercepted
8967 * exceptions that trigger emulation have lower priority than code
8968 * breakpoints, i.e. the fact that the intercepted exception occurred
8969 * means any code breakpoints have already been serviced.
8971 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8972 * hardware has checked the RIP of the magic prefix, but not the RIP of
8973 * the instruction being emulated. The intent of forced emulation is
8974 * to behave as if KVM intercepted the instruction without an exception
8975 * and without a prefix.
8977 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8978 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8981 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8982 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8983 struct kvm_run *kvm_run = vcpu->run;
8984 unsigned long eip = kvm_get_linear_rip(vcpu);
8985 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8986 vcpu->arch.guest_debug_dr7,
8990 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8991 kvm_run->debug.arch.pc = eip;
8992 kvm_run->debug.arch.exception = DB_VECTOR;
8993 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8999 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
9000 !kvm_is_code_breakpoint_inhibited(vcpu)) {
9001 unsigned long eip = kvm_get_linear_rip(vcpu);
9002 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
9007 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
9016 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
9018 switch (ctxt->opcode_len) {
9025 case 0xe6: /* OUT */
9029 case 0x6c: /* INS */
9031 case 0x6e: /* OUTS */
9038 case 0x33: /* RDPMC */
9048 * Decode an instruction for emulation. The caller is responsible for handling
9049 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
9050 * (and wrong) when emulating on an intercepted fault-like exception[*], as
9051 * code breakpoints have higher priority and thus have already been done by
9054 * [*] Except #MC, which is higher priority, but KVM should never emulate in
9055 * response to a machine check.
9057 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
9058 void *insn, int insn_len)
9060 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9063 init_emulate_ctxt(vcpu);
9065 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
9067 trace_kvm_emulate_insn_start(vcpu);
9068 ++vcpu->stat.insn_emulation;
9072 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
9074 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
9075 int emulation_type, void *insn, int insn_len)
9078 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9079 bool writeback = true;
9081 r = kvm_check_emulate_insn(vcpu, emulation_type, insn, insn_len);
9082 if (r != X86EMUL_CONTINUE) {
9083 if (r == X86EMUL_RETRY_INSTR || r == X86EMUL_PROPAGATE_FAULT)
9086 WARN_ON_ONCE(r != X86EMUL_UNHANDLEABLE);
9087 return handle_emulation_failure(vcpu, emulation_type);
9090 vcpu->arch.l1tf_flush_l1d = true;
9092 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
9093 kvm_clear_exception_queue(vcpu);
9096 * Return immediately if RIP hits a code breakpoint, such #DBs
9097 * are fault-like and are higher priority than any faults on
9098 * the code fetch itself.
9100 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
9103 r = x86_decode_emulated_instruction(vcpu, emulation_type,
9105 if (r != EMULATION_OK) {
9106 if ((emulation_type & EMULTYPE_TRAP_UD) ||
9107 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
9108 kvm_queue_exception(vcpu, UD_VECTOR);
9111 if (reexecute_instruction(vcpu, cr2_or_gpa,
9115 if (ctxt->have_exception &&
9116 !(emulation_type & EMULTYPE_SKIP)) {
9118 * #UD should result in just EMULATION_FAILED, and trap-like
9119 * exception should not be encountered during decode.
9121 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
9122 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
9123 inject_emulated_exception(vcpu);
9126 return handle_emulation_failure(vcpu, emulation_type);
9130 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
9131 !is_vmware_backdoor_opcode(ctxt)) {
9132 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
9137 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
9138 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
9139 * The caller is responsible for updating interruptibility state and
9140 * injecting single-step #DBs.
9142 if (emulation_type & EMULTYPE_SKIP) {
9143 if (ctxt->mode != X86EMUL_MODE_PROT64)
9144 ctxt->eip = (u32)ctxt->_eip;
9146 ctxt->eip = ctxt->_eip;
9148 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
9153 kvm_rip_write(vcpu, ctxt->eip);
9154 if (ctxt->eflags & X86_EFLAGS_RF)
9155 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
9159 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
9162 /* this is needed for vmware backdoor interface to work since it
9163 changes registers values during IO operation */
9164 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
9165 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9166 emulator_invalidate_register_cache(ctxt);
9170 if (emulation_type & EMULTYPE_PF) {
9171 /* Save the faulting GPA (cr2) in the address field */
9172 ctxt->exception.address = cr2_or_gpa;
9174 /* With shadow page tables, cr2 contains a GVA or nGPA. */
9175 if (vcpu->arch.mmu->root_role.direct) {
9176 ctxt->gpa_available = true;
9177 ctxt->gpa_val = cr2_or_gpa;
9180 /* Sanitize the address out of an abundance of paranoia. */
9181 ctxt->exception.address = 0;
9184 r = x86_emulate_insn(ctxt);
9186 if (r == EMULATION_INTERCEPTED)
9189 if (r == EMULATION_FAILED) {
9190 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
9193 return handle_emulation_failure(vcpu, emulation_type);
9196 if (ctxt->have_exception) {
9197 WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write);
9198 vcpu->mmio_needed = false;
9200 inject_emulated_exception(vcpu);
9201 } else if (vcpu->arch.pio.count) {
9202 if (!vcpu->arch.pio.in) {
9203 /* FIXME: return into emulator if single-stepping. */
9204 vcpu->arch.pio.count = 0;
9207 vcpu->arch.complete_userspace_io = complete_emulated_pio;
9210 } else if (vcpu->mmio_needed) {
9211 ++vcpu->stat.mmio_exits;
9213 if (!vcpu->mmio_is_write)
9216 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9217 } else if (vcpu->arch.complete_userspace_io) {
9220 } else if (r == EMULATION_RESTART)
9227 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
9228 toggle_interruptibility(vcpu, ctxt->interruptibility);
9229 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9232 * Note, EXCPT_DB is assumed to be fault-like as the emulator
9233 * only supports code breakpoints and general detect #DB, both
9234 * of which are fault-like.
9236 if (!ctxt->have_exception ||
9237 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
9238 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
9239 if (ctxt->is_branch)
9240 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
9241 kvm_rip_write(vcpu, ctxt->eip);
9242 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
9243 r = kvm_vcpu_do_singlestep(vcpu);
9244 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
9245 __kvm_set_rflags(vcpu, ctxt->eflags);
9249 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
9250 * do nothing, and it will be requested again as soon as
9251 * the shadow expires. But we still need to check here,
9252 * because POPF has no interrupt shadow.
9254 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9255 kvm_make_request(KVM_REQ_EVENT, vcpu);
9257 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9262 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9264 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9266 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9268 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9269 void *insn, int insn_len)
9271 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9273 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9275 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9277 vcpu->arch.pio.count = 0;
9281 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9283 vcpu->arch.pio.count = 0;
9285 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9288 return kvm_skip_emulated_instruction(vcpu);
9291 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9292 unsigned short port)
9294 unsigned long val = kvm_rax_read(vcpu);
9295 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9301 * Workaround userspace that relies on old KVM behavior of %rip being
9302 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9305 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9306 vcpu->arch.complete_userspace_io =
9307 complete_fast_pio_out_port_0x7e;
9308 kvm_skip_emulated_instruction(vcpu);
9310 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9311 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9316 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9320 /* We should only ever be called with arch.pio.count equal to 1 */
9321 BUG_ON(vcpu->arch.pio.count != 1);
9323 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9324 vcpu->arch.pio.count = 0;
9328 /* For size less than 4 we merge, else we zero extend */
9329 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9331 complete_emulator_pio_in(vcpu, &val);
9332 kvm_rax_write(vcpu, val);
9334 return kvm_skip_emulated_instruction(vcpu);
9337 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9338 unsigned short port)
9343 /* For size less than 4 we merge, else we zero extend */
9344 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9346 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9348 kvm_rax_write(vcpu, val);
9352 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9353 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9358 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9363 ret = kvm_fast_pio_in(vcpu, size, port);
9365 ret = kvm_fast_pio_out(vcpu, size, port);
9366 return ret && kvm_skip_emulated_instruction(vcpu);
9368 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9370 static int kvmclock_cpu_down_prep(unsigned int cpu)
9372 __this_cpu_write(cpu_tsc_khz, 0);
9376 static void tsc_khz_changed(void *data)
9378 struct cpufreq_freqs *freq = data;
9381 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9386 khz = cpufreq_quick_get(raw_smp_processor_id());
9389 __this_cpu_write(cpu_tsc_khz, khz);
9392 #ifdef CONFIG_X86_64
9393 static void kvm_hyperv_tsc_notifier(void)
9398 mutex_lock(&kvm_lock);
9399 list_for_each_entry(kvm, &vm_list, vm_list)
9400 kvm_make_mclock_inprogress_request(kvm);
9402 /* no guest entries from this point */
9403 hyperv_stop_tsc_emulation();
9405 /* TSC frequency always matches when on Hyper-V */
9406 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9407 for_each_present_cpu(cpu)
9408 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9410 kvm_caps.max_guest_tsc_khz = tsc_khz;
9412 list_for_each_entry(kvm, &vm_list, vm_list) {
9413 __kvm_start_pvclock_update(kvm);
9414 pvclock_update_vm_gtod_copy(kvm);
9415 kvm_end_pvclock_update(kvm);
9418 mutex_unlock(&kvm_lock);
9422 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9425 struct kvm_vcpu *vcpu;
9430 * We allow guests to temporarily run on slowing clocks,
9431 * provided we notify them after, or to run on accelerating
9432 * clocks, provided we notify them before. Thus time never
9435 * However, we have a problem. We can't atomically update
9436 * the frequency of a given CPU from this function; it is
9437 * merely a notifier, which can be called from any CPU.
9438 * Changing the TSC frequency at arbitrary points in time
9439 * requires a recomputation of local variables related to
9440 * the TSC for each VCPU. We must flag these local variables
9441 * to be updated and be sure the update takes place with the
9442 * new frequency before any guests proceed.
9444 * Unfortunately, the combination of hotplug CPU and frequency
9445 * change creates an intractable locking scenario; the order
9446 * of when these callouts happen is undefined with respect to
9447 * CPU hotplug, and they can race with each other. As such,
9448 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9449 * undefined; you can actually have a CPU frequency change take
9450 * place in between the computation of X and the setting of the
9451 * variable. To protect against this problem, all updates of
9452 * the per_cpu tsc_khz variable are done in an interrupt
9453 * protected IPI, and all callers wishing to update the value
9454 * must wait for a synchronous IPI to complete (which is trivial
9455 * if the caller is on the CPU already). This establishes the
9456 * necessary total order on variable updates.
9458 * Note that because a guest time update may take place
9459 * anytime after the setting of the VCPU's request bit, the
9460 * correct TSC value must be set before the request. However,
9461 * to ensure the update actually makes it to any guest which
9462 * starts running in hardware virtualization between the set
9463 * and the acquisition of the spinlock, we must also ping the
9464 * CPU after setting the request bit.
9468 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9470 mutex_lock(&kvm_lock);
9471 list_for_each_entry(kvm, &vm_list, vm_list) {
9472 kvm_for_each_vcpu(i, vcpu, kvm) {
9473 if (vcpu->cpu != cpu)
9475 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9476 if (vcpu->cpu != raw_smp_processor_id())
9480 mutex_unlock(&kvm_lock);
9482 if (freq->old < freq->new && send_ipi) {
9484 * We upscale the frequency. Must make the guest
9485 * doesn't see old kvmclock values while running with
9486 * the new frequency, otherwise we risk the guest sees
9487 * time go backwards.
9489 * In case we update the frequency for another cpu
9490 * (which might be in guest context) send an interrupt
9491 * to kick the cpu out of guest context. Next time
9492 * guest context is entered kvmclock will be updated,
9493 * so the guest will not see stale values.
9495 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9499 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9502 struct cpufreq_freqs *freq = data;
9505 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9507 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9510 for_each_cpu(cpu, freq->policy->cpus)
9511 __kvmclock_cpufreq_notifier(freq, cpu);
9516 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9517 .notifier_call = kvmclock_cpufreq_notifier
9520 static int kvmclock_cpu_online(unsigned int cpu)
9522 tsc_khz_changed(NULL);
9526 static void kvm_timer_init(void)
9528 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9529 max_tsc_khz = tsc_khz;
9531 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9532 struct cpufreq_policy *policy;
9536 policy = cpufreq_cpu_get(cpu);
9538 if (policy->cpuinfo.max_freq)
9539 max_tsc_khz = policy->cpuinfo.max_freq;
9540 cpufreq_cpu_put(policy);
9544 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9545 CPUFREQ_TRANSITION_NOTIFIER);
9547 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9548 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9552 #ifdef CONFIG_X86_64
9553 static void pvclock_gtod_update_fn(struct work_struct *work)
9556 struct kvm_vcpu *vcpu;
9559 mutex_lock(&kvm_lock);
9560 list_for_each_entry(kvm, &vm_list, vm_list)
9561 kvm_for_each_vcpu(i, vcpu, kvm)
9562 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9563 atomic_set(&kvm_guest_has_master_clock, 0);
9564 mutex_unlock(&kvm_lock);
9567 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9570 * Indirection to move queue_work() out of the tk_core.seq write held
9571 * region to prevent possible deadlocks against time accessors which
9572 * are invoked with work related locks held.
9574 static void pvclock_irq_work_fn(struct irq_work *w)
9576 queue_work(system_long_wq, &pvclock_gtod_work);
9579 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9582 * Notification about pvclock gtod data update.
9584 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9588 struct timekeeper *tk = priv;
9590 update_pvclock_gtod(tk);
9593 * Disable master clock if host does not trust, or does not use,
9594 * TSC based clocksource. Delegate queue_work() to irq_work as
9595 * this is invoked with tk_core.seq write held.
9597 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9598 atomic_read(&kvm_guest_has_master_clock) != 0)
9599 irq_work_queue(&pvclock_irq_work);
9603 static struct notifier_block pvclock_gtod_notifier = {
9604 .notifier_call = pvclock_gtod_notify,
9608 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9610 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9612 #define __KVM_X86_OP(func) \
9613 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9614 #define KVM_X86_OP(func) \
9615 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9616 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9617 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9618 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9619 (void *)__static_call_return0);
9620 #include <asm/kvm-x86-ops.h>
9623 kvm_pmu_ops_update(ops->pmu_ops);
9626 static int kvm_x86_check_processor_compatibility(void)
9628 int cpu = smp_processor_id();
9629 struct cpuinfo_x86 *c = &cpu_data(cpu);
9632 * Compatibility checks are done when loading KVM and when enabling
9633 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9634 * compatible, i.e. KVM should never perform a compatibility check on
9637 WARN_ON(!cpu_online(cpu));
9639 if (__cr4_reserved_bits(cpu_has, c) !=
9640 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9643 return static_call(kvm_x86_check_processor_compatibility)();
9646 static void kvm_x86_check_cpu_compat(void *ret)
9648 *(int *)ret = kvm_x86_check_processor_compatibility();
9651 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9656 if (kvm_x86_ops.hardware_enable) {
9657 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9662 * KVM explicitly assumes that the guest has an FPU and
9663 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9664 * vCPU's FPU state as a fxregs_state struct.
9666 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9667 pr_err("inadequate fpu\n");
9671 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9672 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9677 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9678 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9679 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9680 * with an exception. PAT[0] is set to WB on RESET and also by the
9681 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9683 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9684 (host_pat & GENMASK(2, 0)) != 6) {
9685 pr_err("host PAT[0] is not WB\n");
9689 x86_emulator_cache = kvm_alloc_emulator_cache();
9690 if (!x86_emulator_cache) {
9691 pr_err("failed to allocate cache for x86 emulator\n");
9695 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9696 if (!user_return_msrs) {
9697 pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9699 goto out_free_x86_emulator_cache;
9701 kvm_nr_uret_msrs = 0;
9703 r = kvm_mmu_vendor_module_init();
9705 goto out_free_percpu;
9707 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9708 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9709 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9712 rdmsrl_safe(MSR_EFER, &host_efer);
9714 if (boot_cpu_has(X86_FEATURE_XSAVES))
9715 rdmsrl(MSR_IA32_XSS, host_xss);
9717 kvm_init_pmu_capability(ops->pmu_ops);
9719 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
9720 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, host_arch_capabilities);
9722 r = ops->hardware_setup();
9726 kvm_ops_update(ops);
9728 for_each_online_cpu(cpu) {
9729 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9731 goto out_unwind_ops;
9735 * Point of no return! DO NOT add error paths below this point unless
9736 * absolutely necessary, as most operations from this point forward
9737 * require unwinding.
9741 if (pi_inject_timer == -1)
9742 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9743 #ifdef CONFIG_X86_64
9744 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9746 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9747 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9750 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9752 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9753 kvm_caps.supported_xss = 0;
9755 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9756 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9757 #undef __kvm_cpu_cap_has
9759 if (kvm_caps.has_tsc_control) {
9761 * Make sure the user can only configure tsc_khz values that
9762 * fit into a signed integer.
9763 * A min value is not calculated because it will always
9764 * be 1 on all machines.
9766 u64 max = min(0x7fffffffULL,
9767 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9768 kvm_caps.max_guest_tsc_khz = max;
9770 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9771 kvm_init_msr_lists();
9775 kvm_x86_ops.hardware_enable = NULL;
9776 static_call(kvm_x86_hardware_unsetup)();
9778 kvm_mmu_vendor_module_exit();
9780 free_percpu(user_return_msrs);
9781 out_free_x86_emulator_cache:
9782 kmem_cache_destroy(x86_emulator_cache);
9786 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9790 mutex_lock(&vendor_module_lock);
9791 r = __kvm_x86_vendor_init(ops);
9792 mutex_unlock(&vendor_module_lock);
9796 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9798 void kvm_x86_vendor_exit(void)
9800 kvm_unregister_perf_callbacks();
9802 #ifdef CONFIG_X86_64
9803 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9804 clear_hv_tscchange_cb();
9808 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9809 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9810 CPUFREQ_TRANSITION_NOTIFIER);
9811 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9813 #ifdef CONFIG_X86_64
9814 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9815 irq_work_sync(&pvclock_irq_work);
9816 cancel_work_sync(&pvclock_gtod_work);
9818 static_call(kvm_x86_hardware_unsetup)();
9819 kvm_mmu_vendor_module_exit();
9820 free_percpu(user_return_msrs);
9821 kmem_cache_destroy(x86_emulator_cache);
9822 #ifdef CONFIG_KVM_XEN
9823 static_key_deferred_flush(&kvm_xen_enabled);
9824 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9826 mutex_lock(&vendor_module_lock);
9827 kvm_x86_ops.hardware_enable = NULL;
9828 mutex_unlock(&vendor_module_lock);
9830 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9832 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9835 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9836 * local APIC is in-kernel, the run loop will detect the non-runnable
9837 * state and halt the vCPU. Exit to userspace if the local APIC is
9838 * managed by userspace, in which case userspace is responsible for
9839 * handling wake events.
9841 ++vcpu->stat.halt_exits;
9842 if (lapic_in_kernel(vcpu)) {
9843 vcpu->arch.mp_state = state;
9846 vcpu->run->exit_reason = reason;
9851 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9853 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9855 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9857 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9859 int ret = kvm_skip_emulated_instruction(vcpu);
9861 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9862 * KVM_EXIT_DEBUG here.
9864 return kvm_emulate_halt_noskip(vcpu) && ret;
9866 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9868 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9870 int ret = kvm_skip_emulated_instruction(vcpu);
9872 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9873 KVM_EXIT_AP_RESET_HOLD) && ret;
9875 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9877 #ifdef CONFIG_X86_64
9878 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9879 unsigned long clock_type)
9881 struct kvm_clock_pairing clock_pairing;
9882 struct timespec64 ts;
9886 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9887 return -KVM_EOPNOTSUPP;
9890 * When tsc is in permanent catchup mode guests won't be able to use
9891 * pvclock_read_retry loop to get consistent view of pvclock
9893 if (vcpu->arch.tsc_always_catchup)
9894 return -KVM_EOPNOTSUPP;
9896 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9897 return -KVM_EOPNOTSUPP;
9899 clock_pairing.sec = ts.tv_sec;
9900 clock_pairing.nsec = ts.tv_nsec;
9901 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9902 clock_pairing.flags = 0;
9903 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9906 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9907 sizeof(struct kvm_clock_pairing)))
9915 * kvm_pv_kick_cpu_op: Kick a vcpu.
9917 * @apicid - apicid of vcpu to be kicked.
9919 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9922 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9923 * common code, e.g. for tracing. Defer initialization to the compiler.
9925 struct kvm_lapic_irq lapic_irq = {
9926 .delivery_mode = APIC_DM_REMRD,
9927 .dest_mode = APIC_DEST_PHYSICAL,
9928 .shorthand = APIC_DEST_NOSHORT,
9932 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9935 bool kvm_apicv_activated(struct kvm *kvm)
9937 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9939 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9941 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9943 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9944 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9946 return (vm_reasons | vcpu_reasons) == 0;
9948 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9950 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9951 enum kvm_apicv_inhibit reason, bool set)
9954 __set_bit(reason, inhibits);
9956 __clear_bit(reason, inhibits);
9958 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9961 static void kvm_apicv_init(struct kvm *kvm)
9963 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9965 init_rwsem(&kvm->arch.apicv_update_lock);
9967 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9970 set_or_clear_apicv_inhibit(inhibits,
9971 APICV_INHIBIT_REASON_DISABLE, true);
9974 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9976 struct kvm_vcpu *target = NULL;
9977 struct kvm_apic_map *map;
9979 vcpu->stat.directed_yield_attempted++;
9981 if (single_task_running())
9985 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9987 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9988 target = map->phys_map[dest_id]->vcpu;
9992 if (!target || !READ_ONCE(target->ready))
9995 /* Ignore requests to yield to self */
9999 if (kvm_vcpu_yield_to(target) <= 0)
10002 vcpu->stat.directed_yield_successful++;
10008 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
10010 u64 ret = vcpu->run->hypercall.ret;
10012 if (!is_64_bit_mode(vcpu))
10014 kvm_rax_write(vcpu, ret);
10015 ++vcpu->stat.hypercalls;
10016 return kvm_skip_emulated_instruction(vcpu);
10019 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
10021 unsigned long nr, a0, a1, a2, a3, ret;
10024 if (kvm_xen_hypercall_enabled(vcpu->kvm))
10025 return kvm_xen_hypercall(vcpu);
10027 if (kvm_hv_hypercall_enabled(vcpu))
10028 return kvm_hv_hypercall(vcpu);
10030 nr = kvm_rax_read(vcpu);
10031 a0 = kvm_rbx_read(vcpu);
10032 a1 = kvm_rcx_read(vcpu);
10033 a2 = kvm_rdx_read(vcpu);
10034 a3 = kvm_rsi_read(vcpu);
10036 trace_kvm_hypercall(nr, a0, a1, a2, a3);
10038 op_64_bit = is_64_bit_hypercall(vcpu);
10047 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
10055 case KVM_HC_VAPIC_POLL_IRQ:
10058 case KVM_HC_KICK_CPU:
10059 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
10062 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
10063 kvm_sched_yield(vcpu, a1);
10066 #ifdef CONFIG_X86_64
10067 case KVM_HC_CLOCK_PAIRING:
10068 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
10071 case KVM_HC_SEND_IPI:
10072 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
10075 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
10077 case KVM_HC_SCHED_YIELD:
10078 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
10081 kvm_sched_yield(vcpu, a0);
10084 case KVM_HC_MAP_GPA_RANGE: {
10085 u64 gpa = a0, npages = a1, attrs = a2;
10088 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
10091 if (!PAGE_ALIGNED(gpa) || !npages ||
10092 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
10097 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
10098 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
10099 vcpu->run->hypercall.args[0] = gpa;
10100 vcpu->run->hypercall.args[1] = npages;
10101 vcpu->run->hypercall.args[2] = attrs;
10102 vcpu->run->hypercall.flags = 0;
10104 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
10106 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
10107 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
10117 kvm_rax_write(vcpu, ret);
10119 ++vcpu->stat.hypercalls;
10120 return kvm_skip_emulated_instruction(vcpu);
10122 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
10124 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
10126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
10127 char instruction[3];
10128 unsigned long rip = kvm_rip_read(vcpu);
10131 * If the quirk is disabled, synthesize a #UD and let the guest pick up
10134 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
10135 ctxt->exception.error_code_valid = false;
10136 ctxt->exception.vector = UD_VECTOR;
10137 ctxt->have_exception = true;
10138 return X86EMUL_PROPAGATE_FAULT;
10141 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
10143 return emulator_write_emulated(ctxt, rip, instruction, 3,
10147 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
10149 return vcpu->run->request_interrupt_window &&
10150 likely(!pic_in_kernel(vcpu->kvm));
10153 /* Called within kvm->srcu read side. */
10154 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
10156 struct kvm_run *kvm_run = vcpu->run;
10158 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
10159 kvm_run->cr8 = kvm_get_cr8(vcpu);
10160 kvm_run->apic_base = kvm_get_apic_base(vcpu);
10162 kvm_run->ready_for_interrupt_injection =
10163 pic_in_kernel(vcpu->kvm) ||
10164 kvm_vcpu_ready_for_interrupt_injection(vcpu);
10167 kvm_run->flags |= KVM_RUN_X86_SMM;
10170 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
10174 if (!kvm_x86_ops.update_cr8_intercept)
10177 if (!lapic_in_kernel(vcpu))
10180 if (vcpu->arch.apic->apicv_active)
10183 if (!vcpu->arch.apic->vapic_addr)
10184 max_irr = kvm_lapic_find_highest_irr(vcpu);
10191 tpr = kvm_lapic_get_cr8(vcpu);
10193 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
10197 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
10199 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10200 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10204 return kvm_x86_ops.nested_ops->check_events(vcpu);
10207 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
10210 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
10211 * exceptions don't report error codes. The presence of an error code
10212 * is carried with the exception and only stripped when the exception
10213 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
10214 * report an error code despite the CPU being in Real Mode.
10216 vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
10218 trace_kvm_inj_exception(vcpu->arch.exception.vector,
10219 vcpu->arch.exception.has_error_code,
10220 vcpu->arch.exception.error_code,
10221 vcpu->arch.exception.injected);
10223 static_call(kvm_x86_inject_exception)(vcpu);
10227 * Check for any event (interrupt or exception) that is ready to be injected,
10228 * and if there is at least one event, inject the event with the highest
10229 * priority. This handles both "pending" events, i.e. events that have never
10230 * been injected into the guest, and "injected" events, i.e. events that were
10231 * injected as part of a previous VM-Enter, but weren't successfully delivered
10232 * and need to be re-injected.
10234 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
10235 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
10236 * be able to inject exceptions in the "middle" of an instruction, and so must
10237 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
10238 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
10239 * boundaries is necessary and correct.
10241 * For simplicity, KVM uses a single path to inject all events (except events
10242 * that are injected directly from L1 to L2) and doesn't explicitly track
10243 * instruction boundaries for asynchronous events. However, because VM-Exits
10244 * that can occur during instruction execution typically result in KVM skipping
10245 * the instruction or injecting an exception, e.g. instruction and exception
10246 * intercepts, and because pending exceptions have higher priority than pending
10247 * interrupts, KVM still honors instruction boundaries in most scenarios.
10249 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
10250 * the instruction or inject an exception, then KVM can incorrecty inject a new
10251 * asynchronous event if the event became pending after the CPU fetched the
10252 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
10253 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
10254 * injected on the restarted instruction instead of being deferred until the
10255 * instruction completes.
10257 * In practice, this virtualization hole is unlikely to be observed by the
10258 * guest, and even less likely to cause functional problems. To detect the
10259 * hole, the guest would have to trigger an event on a side effect of an early
10260 * phase of instruction execution, e.g. on the instruction fetch from memory.
10261 * And for it to be a functional problem, the guest would need to depend on the
10262 * ordering between that side effect, the instruction completing, _and_ the
10263 * delivery of the asynchronous event.
10265 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
10266 bool *req_immediate_exit)
10272 * Process nested events first, as nested VM-Exit supersedes event
10273 * re-injection. If there's an event queued for re-injection, it will
10274 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
10276 if (is_guest_mode(vcpu))
10277 r = kvm_check_nested_events(vcpu);
10282 * Re-inject exceptions and events *especially* if immediate entry+exit
10283 * to/from L2 is needed, as any event that has already been injected
10284 * into L2 needs to complete its lifecycle before injecting a new event.
10286 * Don't re-inject an NMI or interrupt if there is a pending exception.
10287 * This collision arises if an exception occurred while vectoring the
10288 * injected event, KVM intercepted said exception, and KVM ultimately
10289 * determined the fault belongs to the guest and queues the exception
10290 * for injection back into the guest.
10292 * "Injected" interrupts can also collide with pending exceptions if
10293 * userspace ignores the "ready for injection" flag and blindly queues
10294 * an interrupt. In that case, prioritizing the exception is correct,
10295 * as the exception "occurred" before the exit to userspace. Trap-like
10296 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10297 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10298 * priority, they're only generated (pended) during instruction
10299 * execution, and interrupts are recognized at instruction boundaries.
10300 * Thus a pending fault-like exception means the fault occurred on the
10301 * *previous* instruction and must be serviced prior to recognizing any
10302 * new events in order to fully complete the previous instruction.
10304 if (vcpu->arch.exception.injected)
10305 kvm_inject_exception(vcpu);
10306 else if (kvm_is_exception_pending(vcpu))
10308 else if (vcpu->arch.nmi_injected)
10309 static_call(kvm_x86_inject_nmi)(vcpu);
10310 else if (vcpu->arch.interrupt.injected)
10311 static_call(kvm_x86_inject_irq)(vcpu, true);
10314 * Exceptions that morph to VM-Exits are handled above, and pending
10315 * exceptions on top of injected exceptions that do not VM-Exit should
10316 * either morph to #DF or, sadly, override the injected exception.
10318 WARN_ON_ONCE(vcpu->arch.exception.injected &&
10319 vcpu->arch.exception.pending);
10322 * Bail if immediate entry+exit to/from the guest is needed to complete
10323 * nested VM-Enter or event re-injection so that a different pending
10324 * event can be serviced (or if KVM needs to exit to userspace).
10326 * Otherwise, continue processing events even if VM-Exit occurred. The
10327 * VM-Exit will have cleared exceptions that were meant for L2, but
10328 * there may now be events that can be injected into L1.
10334 * A pending exception VM-Exit should either result in nested VM-Exit
10335 * or force an immediate re-entry and exit to/from L2, and exception
10336 * VM-Exits cannot be injected (flag should _never_ be set).
10338 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10339 vcpu->arch.exception_vmexit.pending);
10342 * New events, other than exceptions, cannot be injected if KVM needs
10343 * to re-inject a previous event. See above comments on re-injecting
10344 * for why pending exceptions get priority.
10346 can_inject = !kvm_event_needs_reinjection(vcpu);
10348 if (vcpu->arch.exception.pending) {
10350 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10351 * value pushed on the stack. Trap-like exception and all #DBs
10352 * leave RF as-is (KVM follows Intel's behavior in this regard;
10353 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10355 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10356 * describe the behavior of General Detect #DBs, which are
10357 * fault-like. They do _not_ set RF, a la code breakpoints.
10359 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10360 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10363 if (vcpu->arch.exception.vector == DB_VECTOR) {
10364 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10365 if (vcpu->arch.dr7 & DR7_GD) {
10366 vcpu->arch.dr7 &= ~DR7_GD;
10367 kvm_update_dr7(vcpu);
10371 kvm_inject_exception(vcpu);
10373 vcpu->arch.exception.pending = false;
10374 vcpu->arch.exception.injected = true;
10376 can_inject = false;
10379 /* Don't inject interrupts if the user asked to avoid doing so */
10380 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10384 * Finally, inject interrupt events. If an event cannot be injected
10385 * due to architectural conditions (e.g. IF=0) a window-open exit
10386 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10387 * and can architecturally be injected, but we cannot do it right now:
10388 * an interrupt could have arrived just now and we have to inject it
10389 * as a vmexit, or there could already an event in the queue, which is
10390 * indicated by can_inject. In that case we request an immediate exit
10391 * in order to make progress and get back here for another iteration.
10392 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10394 #ifdef CONFIG_KVM_SMM
10395 if (vcpu->arch.smi_pending) {
10396 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10400 vcpu->arch.smi_pending = false;
10401 ++vcpu->arch.smi_count;
10403 can_inject = false;
10405 static_call(kvm_x86_enable_smi_window)(vcpu);
10409 if (vcpu->arch.nmi_pending) {
10410 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10414 --vcpu->arch.nmi_pending;
10415 vcpu->arch.nmi_injected = true;
10416 static_call(kvm_x86_inject_nmi)(vcpu);
10417 can_inject = false;
10418 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10420 if (vcpu->arch.nmi_pending)
10421 static_call(kvm_x86_enable_nmi_window)(vcpu);
10424 if (kvm_cpu_has_injectable_intr(vcpu)) {
10425 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10429 int irq = kvm_cpu_get_interrupt(vcpu);
10431 if (!WARN_ON_ONCE(irq == -1)) {
10432 kvm_queue_interrupt(vcpu, irq, false);
10433 static_call(kvm_x86_inject_irq)(vcpu, false);
10434 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10437 if (kvm_cpu_has_injectable_intr(vcpu))
10438 static_call(kvm_x86_enable_irq_window)(vcpu);
10441 if (is_guest_mode(vcpu) &&
10442 kvm_x86_ops.nested_ops->has_events &&
10443 kvm_x86_ops.nested_ops->has_events(vcpu))
10444 *req_immediate_exit = true;
10447 * KVM must never queue a new exception while injecting an event; KVM
10448 * is done emulating and should only propagate the to-be-injected event
10449 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10450 * infinite loop as KVM will bail from VM-Enter to inject the pending
10451 * exception and start the cycle all over.
10453 * Exempt triple faults as they have special handling and won't put the
10454 * vCPU into an infinite loop. Triple fault can be queued when running
10455 * VMX without unrestricted guest, as that requires KVM to emulate Real
10456 * Mode events (see kvm_inject_realmode_interrupt()).
10458 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10459 vcpu->arch.exception_vmexit.pending);
10464 *req_immediate_exit = true;
10470 static void process_nmi(struct kvm_vcpu *vcpu)
10472 unsigned int limit;
10475 * x86 is limited to one NMI pending, but because KVM can't react to
10476 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is
10477 * scheduled out, KVM needs to play nice with two queued NMIs showing
10478 * up at the same time. To handle this scenario, allow two NMIs to be
10479 * (temporarily) pending so long as NMIs are not blocked and KVM is not
10480 * waiting for a previous NMI injection to complete (which effectively
10481 * blocks NMIs). KVM will immediately inject one of the two NMIs, and
10482 * will request an NMI window to handle the second NMI.
10484 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10490 * Adjust the limit to account for pending virtual NMIs, which aren't
10491 * tracked in vcpu->arch.nmi_pending.
10493 if (static_call(kvm_x86_is_vnmi_pending)(vcpu))
10496 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10497 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10499 if (vcpu->arch.nmi_pending &&
10500 (static_call(kvm_x86_set_vnmi_pending)(vcpu)))
10501 vcpu->arch.nmi_pending--;
10503 if (vcpu->arch.nmi_pending)
10504 kvm_make_request(KVM_REQ_EVENT, vcpu);
10507 /* Return total number of NMIs pending injection to the VM */
10508 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu)
10510 return vcpu->arch.nmi_pending +
10511 static_call(kvm_x86_is_vnmi_pending)(vcpu);
10514 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10515 unsigned long *vcpu_bitmap)
10517 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10520 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10522 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10525 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10527 struct kvm_lapic *apic = vcpu->arch.apic;
10530 if (!lapic_in_kernel(vcpu))
10533 down_read(&vcpu->kvm->arch.apicv_update_lock);
10536 /* Do not activate APICV when APIC is disabled */
10537 activate = kvm_vcpu_apicv_activated(vcpu) &&
10538 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10540 if (apic->apicv_active == activate)
10543 apic->apicv_active = activate;
10544 kvm_apic_update_apicv(vcpu);
10545 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10548 * When APICv gets disabled, we may still have injected interrupts
10549 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10550 * still active when the interrupt got accepted. Make sure
10551 * kvm_check_and_inject_events() is called to check for that.
10553 if (!apic->apicv_active)
10554 kvm_make_request(KVM_REQ_EVENT, vcpu);
10558 up_read(&vcpu->kvm->arch.apicv_update_lock);
10560 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10562 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10564 if (!lapic_in_kernel(vcpu))
10568 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10569 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10570 * and hardware doesn't support x2APIC virtualization. E.g. some AMD
10571 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in
10572 * this case so that KVM can the AVIC doorbell to inject interrupts to
10573 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10574 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10575 * despite being in x2APIC mode. For simplicity, inhibiting the APIC
10576 * access page is sticky.
10578 if (apic_x2apic_mode(vcpu->arch.apic) &&
10579 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10580 kvm_inhibit_apic_access_page(vcpu);
10582 __kvm_vcpu_update_apicv(vcpu);
10585 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10586 enum kvm_apicv_inhibit reason, bool set)
10588 unsigned long old, new;
10590 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10592 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10595 old = new = kvm->arch.apicv_inhibit_reasons;
10597 set_or_clear_apicv_inhibit(&new, reason, set);
10599 if (!!old != !!new) {
10601 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10602 * false positives in the sanity check WARN in svm_vcpu_run().
10603 * This task will wait for all vCPUs to ack the kick IRQ before
10604 * updating apicv_inhibit_reasons, and all other vCPUs will
10605 * block on acquiring apicv_update_lock so that vCPUs can't
10606 * redo svm_vcpu_run() without seeing the new inhibit state.
10608 * Note, holding apicv_update_lock and taking it in the read
10609 * side (handling the request) also prevents other vCPUs from
10610 * servicing the request with a stale apicv_inhibit_reasons.
10612 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10613 kvm->arch.apicv_inhibit_reasons = new;
10615 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10616 int idx = srcu_read_lock(&kvm->srcu);
10618 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10619 srcu_read_unlock(&kvm->srcu, idx);
10622 kvm->arch.apicv_inhibit_reasons = new;
10626 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10627 enum kvm_apicv_inhibit reason, bool set)
10632 down_write(&kvm->arch.apicv_update_lock);
10633 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10634 up_write(&kvm->arch.apicv_update_lock);
10636 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10638 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10640 if (!kvm_apic_present(vcpu))
10643 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10645 if (irqchip_split(vcpu->kvm))
10646 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10648 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10649 if (ioapic_in_kernel(vcpu->kvm))
10650 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10653 if (is_guest_mode(vcpu))
10654 vcpu->arch.load_eoi_exitmap_pending = true;
10656 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10659 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10661 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10664 #ifdef CONFIG_KVM_HYPERV
10665 if (to_hv_vcpu(vcpu)) {
10666 u64 eoi_exit_bitmap[4];
10668 bitmap_or((ulong *)eoi_exit_bitmap,
10669 vcpu->arch.ioapic_handled_vectors,
10670 to_hv_synic(vcpu)->vec_bitmap, 256);
10671 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10675 static_call_cond(kvm_x86_load_eoi_exitmap)(
10676 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10679 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10681 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10684 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10686 if (!lapic_in_kernel(vcpu))
10689 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10692 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10694 smp_send_reschedule(vcpu->cpu);
10696 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10699 * Called within kvm->srcu read side.
10700 * Returns 1 to let vcpu_run() continue the guest execution loop without
10701 * exiting to the userspace. Otherwise, the value will be returned to the
10704 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10708 dm_request_for_irq_injection(vcpu) &&
10709 kvm_cpu_accept_dm_intr(vcpu);
10710 fastpath_t exit_fastpath;
10712 bool req_immediate_exit = false;
10714 if (kvm_request_pending(vcpu)) {
10715 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10720 if (kvm_dirty_ring_check_request(vcpu)) {
10725 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10726 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10731 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10732 kvm_mmu_free_obsolete_roots(vcpu);
10733 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10734 __kvm_migrate_timers(vcpu);
10735 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10736 kvm_update_masterclock(vcpu->kvm);
10737 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10738 kvm_gen_kvmclock_update(vcpu);
10739 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10740 r = kvm_guest_time_update(vcpu);
10744 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10745 kvm_mmu_sync_roots(vcpu);
10746 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10747 kvm_mmu_load_pgd(vcpu);
10750 * Note, the order matters here, as flushing "all" TLB entries
10751 * also flushes the "current" TLB entries, i.e. servicing the
10752 * flush "all" will clear any request to flush "current".
10754 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10755 kvm_vcpu_flush_tlb_all(vcpu);
10757 kvm_service_local_tlb_flush_requests(vcpu);
10760 * Fall back to a "full" guest flush if Hyper-V's precise
10761 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10762 * the flushes are considered "remote" and not "local" because
10763 * the requests can be initiated from other vCPUs.
10765 #ifdef CONFIG_KVM_HYPERV
10766 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10767 kvm_hv_vcpu_flush_tlb(vcpu))
10768 kvm_vcpu_flush_tlb_guest(vcpu);
10771 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10772 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10776 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10777 if (is_guest_mode(vcpu))
10778 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10780 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10781 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10782 vcpu->mmio_needed = 0;
10787 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10788 /* Page is swapped out. Do synthetic halt */
10789 vcpu->arch.apf.halted = true;
10793 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10794 record_steal_time(vcpu);
10795 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10796 kvm_pmu_handle_event(vcpu);
10797 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10798 kvm_pmu_deliver_pmi(vcpu);
10799 #ifdef CONFIG_KVM_SMM
10800 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10803 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10805 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10806 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10807 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10808 vcpu->arch.ioapic_handled_vectors)) {
10809 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10810 vcpu->run->eoi.vector =
10811 vcpu->arch.pending_ioapic_eoi;
10816 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10817 vcpu_scan_ioapic(vcpu);
10818 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10819 vcpu_load_eoi_exitmap(vcpu);
10820 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10821 kvm_vcpu_reload_apic_access_page(vcpu);
10822 #ifdef CONFIG_KVM_HYPERV
10823 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10824 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10825 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10826 vcpu->run->system_event.ndata = 0;
10830 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10831 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10832 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10833 vcpu->run->system_event.ndata = 0;
10837 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10838 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10840 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10841 vcpu->run->hyperv = hv_vcpu->exit;
10847 * KVM_REQ_HV_STIMER has to be processed after
10848 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10849 * depend on the guest clock being up-to-date
10851 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10852 kvm_hv_process_stimers(vcpu);
10854 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10855 kvm_vcpu_update_apicv(vcpu);
10856 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10857 kvm_check_async_pf_completion(vcpu);
10858 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10859 static_call(kvm_x86_msr_filter_changed)(vcpu);
10861 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10862 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10865 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10866 kvm_xen_has_interrupt(vcpu)) {
10867 ++vcpu->stat.req_event;
10868 r = kvm_apic_accept_events(vcpu);
10873 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10878 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10884 static_call(kvm_x86_enable_irq_window)(vcpu);
10886 if (kvm_lapic_enabled(vcpu)) {
10887 update_cr8_intercept(vcpu);
10888 kvm_lapic_sync_to_vapic(vcpu);
10892 r = kvm_mmu_reload(vcpu);
10894 goto cancel_injection;
10899 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10902 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10903 * IPI are then delayed after guest entry, which ensures that they
10904 * result in virtual interrupt delivery.
10906 local_irq_disable();
10908 /* Store vcpu->apicv_active before vcpu->mode. */
10909 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10911 kvm_vcpu_srcu_read_unlock(vcpu);
10914 * 1) We should set ->mode before checking ->requests. Please see
10915 * the comment in kvm_vcpu_exiting_guest_mode().
10917 * 2) For APICv, we should set ->mode before checking PID.ON. This
10918 * pairs with the memory barrier implicit in pi_test_and_set_on
10919 * (see vmx_deliver_posted_interrupt).
10921 * 3) This also orders the write to mode from any reads to the page
10922 * tables done while the VCPU is running. Please see the comment
10923 * in kvm_flush_remote_tlbs.
10925 smp_mb__after_srcu_read_unlock();
10928 * Process pending posted interrupts to handle the case where the
10929 * notification IRQ arrived in the host, or was never sent (because the
10930 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10931 * status, KVM doesn't update assigned devices when APICv is inhibited,
10932 * i.e. they can post interrupts even if APICv is temporarily disabled.
10934 if (kvm_lapic_enabled(vcpu))
10935 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10937 if (kvm_vcpu_exit_request(vcpu)) {
10938 vcpu->mode = OUTSIDE_GUEST_MODE;
10940 local_irq_enable();
10942 kvm_vcpu_srcu_read_lock(vcpu);
10944 goto cancel_injection;
10947 if (req_immediate_exit) {
10948 kvm_make_request(KVM_REQ_EVENT, vcpu);
10949 static_call(kvm_x86_request_immediate_exit)(vcpu);
10952 fpregs_assert_state_consistent();
10953 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10954 switch_fpu_return();
10956 if (vcpu->arch.guest_fpu.xfd_err)
10957 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10959 if (unlikely(vcpu->arch.switch_db_regs)) {
10960 set_debugreg(0, 7);
10961 set_debugreg(vcpu->arch.eff_db[0], 0);
10962 set_debugreg(vcpu->arch.eff_db[1], 1);
10963 set_debugreg(vcpu->arch.eff_db[2], 2);
10964 set_debugreg(vcpu->arch.eff_db[3], 3);
10965 } else if (unlikely(hw_breakpoint_active())) {
10966 set_debugreg(0, 7);
10969 guest_timing_enter_irqoff();
10973 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10974 * update must kick and wait for all vCPUs before toggling the
10975 * per-VM state, and responding vCPUs must wait for the update
10976 * to complete before servicing KVM_REQ_APICV_UPDATE.
10978 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10979 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10981 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10982 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10985 if (kvm_lapic_enabled(vcpu))
10986 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10988 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10989 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10993 /* Note, VM-Exits that go down the "slow" path are accounted below. */
10994 ++vcpu->stat.exits;
10998 * Do this here before restoring debug registers on the host. And
10999 * since we do this before handling the vmexit, a DR access vmexit
11000 * can (a) read the correct value of the debug registers, (b) set
11001 * KVM_DEBUGREG_WONT_EXIT again.
11003 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
11004 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
11005 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
11006 kvm_update_dr0123(vcpu);
11007 kvm_update_dr7(vcpu);
11011 * If the guest has used debug registers, at least dr7
11012 * will be disabled while returning to the host.
11013 * If we don't have active breakpoints in the host, we don't
11014 * care about the messed up debug address registers. But if
11015 * we have some of them active, restore the old state.
11017 if (hw_breakpoint_active())
11018 hw_breakpoint_restore();
11020 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
11021 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
11023 vcpu->mode = OUTSIDE_GUEST_MODE;
11027 * Sync xfd before calling handle_exit_irqoff() which may
11028 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
11029 * in #NM irqoff handler).
11031 if (vcpu->arch.xfd_no_write_intercept)
11032 fpu_sync_guest_vmexit_xfd_state();
11034 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
11036 if (vcpu->arch.guest_fpu.xfd_err)
11037 wrmsrl(MSR_IA32_XFD_ERR, 0);
11040 * Consume any pending interrupts, including the possible source of
11041 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
11042 * An instruction is required after local_irq_enable() to fully unblock
11043 * interrupts on processors that implement an interrupt shadow, the
11044 * stat.exits increment will do nicely.
11046 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
11047 local_irq_enable();
11048 ++vcpu->stat.exits;
11049 local_irq_disable();
11050 kvm_after_interrupt(vcpu);
11053 * Wait until after servicing IRQs to account guest time so that any
11054 * ticks that occurred while running the guest are properly accounted
11055 * to the guest. Waiting until IRQs are enabled degrades the accuracy
11056 * of accounting via context tracking, but the loss of accuracy is
11057 * acceptable for all known use cases.
11059 guest_timing_exit_irqoff();
11061 local_irq_enable();
11064 kvm_vcpu_srcu_read_lock(vcpu);
11067 * Profile KVM exit RIPs:
11069 if (unlikely(prof_on == KVM_PROFILING)) {
11070 unsigned long rip = kvm_rip_read(vcpu);
11071 profile_hit(KVM_PROFILING, (void *)rip);
11074 if (unlikely(vcpu->arch.tsc_always_catchup))
11075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11077 if (vcpu->arch.apic_attention)
11078 kvm_lapic_sync_from_vapic(vcpu);
11080 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
11084 if (req_immediate_exit)
11085 kvm_make_request(KVM_REQ_EVENT, vcpu);
11086 static_call(kvm_x86_cancel_injection)(vcpu);
11087 if (unlikely(vcpu->arch.apic_attention))
11088 kvm_lapic_sync_from_vapic(vcpu);
11093 /* Called within kvm->srcu read side. */
11094 static inline int vcpu_block(struct kvm_vcpu *vcpu)
11098 if (!kvm_arch_vcpu_runnable(vcpu)) {
11100 * Switch to the software timer before halt-polling/blocking as
11101 * the guest's timer may be a break event for the vCPU, and the
11102 * hypervisor timer runs only when the CPU is in guest mode.
11103 * Switch before halt-polling so that KVM recognizes an expired
11104 * timer before blocking.
11106 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
11108 kvm_lapic_switch_to_sw_timer(vcpu);
11110 kvm_vcpu_srcu_read_unlock(vcpu);
11111 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11112 kvm_vcpu_halt(vcpu);
11114 kvm_vcpu_block(vcpu);
11115 kvm_vcpu_srcu_read_lock(vcpu);
11118 kvm_lapic_switch_to_hv_timer(vcpu);
11121 * If the vCPU is not runnable, a signal or another host event
11122 * of some kind is pending; service it without changing the
11123 * vCPU's activity state.
11125 if (!kvm_arch_vcpu_runnable(vcpu))
11130 * Evaluate nested events before exiting the halted state. This allows
11131 * the halt state to be recorded properly in the VMCS12's activity
11132 * state field (AMD does not have a similar field and a VM-Exit always
11133 * causes a spurious wakeup from HLT).
11135 if (is_guest_mode(vcpu)) {
11136 if (kvm_check_nested_events(vcpu) < 0)
11140 if (kvm_apic_accept_events(vcpu) < 0)
11142 switch(vcpu->arch.mp_state) {
11143 case KVM_MP_STATE_HALTED:
11144 case KVM_MP_STATE_AP_RESET_HOLD:
11145 vcpu->arch.pv.pv_unhalted = false;
11146 vcpu->arch.mp_state =
11147 KVM_MP_STATE_RUNNABLE;
11149 case KVM_MP_STATE_RUNNABLE:
11150 vcpu->arch.apf.halted = false;
11152 case KVM_MP_STATE_INIT_RECEIVED:
11161 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
11163 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
11164 !vcpu->arch.apf.halted);
11167 /* Called within kvm->srcu read side. */
11168 static int vcpu_run(struct kvm_vcpu *vcpu)
11172 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
11173 vcpu->arch.l1tf_flush_l1d = true;
11177 * If another guest vCPU requests a PV TLB flush in the middle
11178 * of instruction emulation, the rest of the emulation could
11179 * use a stale page translation. Assume that any code after
11180 * this point can start executing an instruction.
11182 vcpu->arch.at_instruction_boundary = false;
11183 if (kvm_vcpu_running(vcpu)) {
11184 r = vcpu_enter_guest(vcpu);
11186 r = vcpu_block(vcpu);
11192 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
11193 if (kvm_xen_has_pending_events(vcpu))
11194 kvm_xen_inject_pending_events(vcpu);
11196 if (kvm_cpu_has_pending_timer(vcpu))
11197 kvm_inject_pending_timer_irqs(vcpu);
11199 if (dm_request_for_irq_injection(vcpu) &&
11200 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
11202 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
11203 ++vcpu->stat.request_irq_exits;
11207 if (__xfer_to_guest_mode_work_pending()) {
11208 kvm_vcpu_srcu_read_unlock(vcpu);
11209 r = xfer_to_guest_mode_handle_work(vcpu);
11210 kvm_vcpu_srcu_read_lock(vcpu);
11219 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
11221 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
11224 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
11226 BUG_ON(!vcpu->arch.pio.count);
11228 return complete_emulated_io(vcpu);
11232 * Implements the following, as a state machine:
11235 * for each fragment
11236 * for each mmio piece in the fragment
11243 * for each fragment
11244 * for each mmio piece in the fragment
11249 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11251 struct kvm_run *run = vcpu->run;
11252 struct kvm_mmio_fragment *frag;
11255 BUG_ON(!vcpu->mmio_needed);
11257 /* Complete previous fragment */
11258 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11259 len = min(8u, frag->len);
11260 if (!vcpu->mmio_is_write)
11261 memcpy(frag->data, run->mmio.data, len);
11263 if (frag->len <= 8) {
11264 /* Switch to the next fragment. */
11266 vcpu->mmio_cur_fragment++;
11268 /* Go forward to the next mmio piece. */
11274 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11275 vcpu->mmio_needed = 0;
11277 /* FIXME: return into emulator if single-stepping. */
11278 if (vcpu->mmio_is_write)
11280 vcpu->mmio_read_completed = 1;
11281 return complete_emulated_io(vcpu);
11284 run->exit_reason = KVM_EXIT_MMIO;
11285 run->mmio.phys_addr = frag->gpa;
11286 if (vcpu->mmio_is_write)
11287 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11288 run->mmio.len = min(8u, frag->len);
11289 run->mmio.is_write = vcpu->mmio_is_write;
11290 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11294 /* Swap (qemu) user FPU context for the guest FPU context. */
11295 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11297 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11298 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11302 /* When vcpu_run ends, restore user space FPU context. */
11303 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11305 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11306 ++vcpu->stat.fpu_reload;
11310 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11312 struct kvm_queued_exception *ex = &vcpu->arch.exception;
11313 struct kvm_run *kvm_run = vcpu->run;
11317 kvm_sigset_activate(vcpu);
11318 kvm_run->flags = 0;
11319 kvm_load_guest_fpu(vcpu);
11321 kvm_vcpu_srcu_read_lock(vcpu);
11322 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11323 if (kvm_run->immediate_exit) {
11329 * Don't bother switching APIC timer emulation from the
11330 * hypervisor timer to the software timer, the only way for the
11331 * APIC timer to be active is if userspace stuffed vCPU state,
11332 * i.e. put the vCPU into a nonsensical state. Only an INIT
11333 * will transition the vCPU out of UNINITIALIZED (without more
11334 * state stuffing from userspace), which will reset the local
11335 * APIC and thus cancel the timer or drop the IRQ (if the timer
11336 * already expired).
11338 kvm_vcpu_srcu_read_unlock(vcpu);
11339 kvm_vcpu_block(vcpu);
11340 kvm_vcpu_srcu_read_lock(vcpu);
11342 if (kvm_apic_accept_events(vcpu) < 0) {
11347 if (signal_pending(current)) {
11349 kvm_run->exit_reason = KVM_EXIT_INTR;
11350 ++vcpu->stat.signal_exits;
11355 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11356 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11361 if (kvm_run->kvm_dirty_regs) {
11362 r = sync_regs(vcpu);
11367 /* re-sync apic's tpr */
11368 if (!lapic_in_kernel(vcpu)) {
11369 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11376 * If userspace set a pending exception and L2 is active, convert it to
11377 * a pending VM-Exit if L1 wants to intercept the exception.
11379 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11380 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11382 kvm_queue_exception_vmexit(vcpu, ex->vector,
11383 ex->has_error_code, ex->error_code,
11384 ex->has_payload, ex->payload);
11385 ex->injected = false;
11386 ex->pending = false;
11388 vcpu->arch.exception_from_userspace = false;
11390 if (unlikely(vcpu->arch.complete_userspace_io)) {
11391 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11392 vcpu->arch.complete_userspace_io = NULL;
11397 WARN_ON_ONCE(vcpu->arch.pio.count);
11398 WARN_ON_ONCE(vcpu->mmio_needed);
11401 if (kvm_run->immediate_exit) {
11406 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11410 r = vcpu_run(vcpu);
11413 kvm_put_guest_fpu(vcpu);
11414 if (kvm_run->kvm_valid_regs)
11416 post_kvm_run_save(vcpu);
11417 kvm_vcpu_srcu_read_unlock(vcpu);
11419 kvm_sigset_deactivate(vcpu);
11424 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11426 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11428 * We are here if userspace calls get_regs() in the middle of
11429 * instruction emulation. Registers state needs to be copied
11430 * back from emulation context to vcpu. Userspace shouldn't do
11431 * that usually, but some bad designed PV devices (vmware
11432 * backdoor interface) need this to work
11434 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11435 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11437 regs->rax = kvm_rax_read(vcpu);
11438 regs->rbx = kvm_rbx_read(vcpu);
11439 regs->rcx = kvm_rcx_read(vcpu);
11440 regs->rdx = kvm_rdx_read(vcpu);
11441 regs->rsi = kvm_rsi_read(vcpu);
11442 regs->rdi = kvm_rdi_read(vcpu);
11443 regs->rsp = kvm_rsp_read(vcpu);
11444 regs->rbp = kvm_rbp_read(vcpu);
11445 #ifdef CONFIG_X86_64
11446 regs->r8 = kvm_r8_read(vcpu);
11447 regs->r9 = kvm_r9_read(vcpu);
11448 regs->r10 = kvm_r10_read(vcpu);
11449 regs->r11 = kvm_r11_read(vcpu);
11450 regs->r12 = kvm_r12_read(vcpu);
11451 regs->r13 = kvm_r13_read(vcpu);
11452 regs->r14 = kvm_r14_read(vcpu);
11453 regs->r15 = kvm_r15_read(vcpu);
11456 regs->rip = kvm_rip_read(vcpu);
11457 regs->rflags = kvm_get_rflags(vcpu);
11460 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11463 __get_regs(vcpu, regs);
11468 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11470 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11471 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11473 kvm_rax_write(vcpu, regs->rax);
11474 kvm_rbx_write(vcpu, regs->rbx);
11475 kvm_rcx_write(vcpu, regs->rcx);
11476 kvm_rdx_write(vcpu, regs->rdx);
11477 kvm_rsi_write(vcpu, regs->rsi);
11478 kvm_rdi_write(vcpu, regs->rdi);
11479 kvm_rsp_write(vcpu, regs->rsp);
11480 kvm_rbp_write(vcpu, regs->rbp);
11481 #ifdef CONFIG_X86_64
11482 kvm_r8_write(vcpu, regs->r8);
11483 kvm_r9_write(vcpu, regs->r9);
11484 kvm_r10_write(vcpu, regs->r10);
11485 kvm_r11_write(vcpu, regs->r11);
11486 kvm_r12_write(vcpu, regs->r12);
11487 kvm_r13_write(vcpu, regs->r13);
11488 kvm_r14_write(vcpu, regs->r14);
11489 kvm_r15_write(vcpu, regs->r15);
11492 kvm_rip_write(vcpu, regs->rip);
11493 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11495 vcpu->arch.exception.pending = false;
11496 vcpu->arch.exception_vmexit.pending = false;
11498 kvm_make_request(KVM_REQ_EVENT, vcpu);
11501 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11504 __set_regs(vcpu, regs);
11509 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11511 struct desc_ptr dt;
11513 if (vcpu->arch.guest_state_protected)
11514 goto skip_protected_regs;
11516 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11517 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11518 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11519 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11520 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11521 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11523 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11524 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11526 static_call(kvm_x86_get_idt)(vcpu, &dt);
11527 sregs->idt.limit = dt.size;
11528 sregs->idt.base = dt.address;
11529 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11530 sregs->gdt.limit = dt.size;
11531 sregs->gdt.base = dt.address;
11533 sregs->cr2 = vcpu->arch.cr2;
11534 sregs->cr3 = kvm_read_cr3(vcpu);
11536 skip_protected_regs:
11537 sregs->cr0 = kvm_read_cr0(vcpu);
11538 sregs->cr4 = kvm_read_cr4(vcpu);
11539 sregs->cr8 = kvm_get_cr8(vcpu);
11540 sregs->efer = vcpu->arch.efer;
11541 sregs->apic_base = kvm_get_apic_base(vcpu);
11544 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11546 __get_sregs_common(vcpu, sregs);
11548 if (vcpu->arch.guest_state_protected)
11551 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11552 set_bit(vcpu->arch.interrupt.nr,
11553 (unsigned long *)sregs->interrupt_bitmap);
11556 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11560 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11562 if (vcpu->arch.guest_state_protected)
11565 if (is_pae_paging(vcpu)) {
11566 for (i = 0 ; i < 4 ; i++)
11567 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11568 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11572 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11573 struct kvm_sregs *sregs)
11576 __get_sregs(vcpu, sregs);
11581 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11582 struct kvm_mp_state *mp_state)
11587 if (kvm_mpx_supported())
11588 kvm_load_guest_fpu(vcpu);
11590 r = kvm_apic_accept_events(vcpu);
11595 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11596 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11597 vcpu->arch.pv.pv_unhalted)
11598 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11600 mp_state->mp_state = vcpu->arch.mp_state;
11603 if (kvm_mpx_supported())
11604 kvm_put_guest_fpu(vcpu);
11609 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11610 struct kvm_mp_state *mp_state)
11616 switch (mp_state->mp_state) {
11617 case KVM_MP_STATE_UNINITIALIZED:
11618 case KVM_MP_STATE_HALTED:
11619 case KVM_MP_STATE_AP_RESET_HOLD:
11620 case KVM_MP_STATE_INIT_RECEIVED:
11621 case KVM_MP_STATE_SIPI_RECEIVED:
11622 if (!lapic_in_kernel(vcpu))
11626 case KVM_MP_STATE_RUNNABLE:
11634 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11635 * forcing the guest into INIT/SIPI if those events are supposed to be
11636 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11637 * if an SMI is pending as well.
11639 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11640 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11641 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11644 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11645 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11646 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11648 vcpu->arch.mp_state = mp_state->mp_state;
11649 kvm_make_request(KVM_REQ_EVENT, vcpu);
11657 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11658 int reason, bool has_error_code, u32 error_code)
11660 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11663 init_emulate_ctxt(vcpu);
11665 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11666 has_error_code, error_code);
11668 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11669 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11670 vcpu->run->internal.ndata = 0;
11674 kvm_rip_write(vcpu, ctxt->eip);
11675 kvm_set_rflags(vcpu, ctxt->eflags);
11678 EXPORT_SYMBOL_GPL(kvm_task_switch);
11680 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11682 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11684 * When EFER.LME and CR0.PG are set, the processor is in
11685 * 64-bit mode (though maybe in a 32-bit code segment).
11686 * CR4.PAE and EFER.LMA must be set.
11688 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11690 if (!kvm_vcpu_is_legal_cr3(vcpu, sregs->cr3))
11694 * Not in 64-bit mode: EFER.LMA is clear and the code
11695 * segment cannot be 64-bit.
11697 if (sregs->efer & EFER_LMA || sregs->cs.l)
11701 return kvm_is_valid_cr4(vcpu, sregs->cr4) &&
11702 kvm_is_valid_cr0(vcpu, sregs->cr0);
11705 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11706 int *mmu_reset_needed, bool update_pdptrs)
11708 struct msr_data apic_base_msr;
11710 struct desc_ptr dt;
11712 if (!kvm_is_valid_sregs(vcpu, sregs))
11715 apic_base_msr.data = sregs->apic_base;
11716 apic_base_msr.host_initiated = true;
11717 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11720 if (vcpu->arch.guest_state_protected)
11723 dt.size = sregs->idt.limit;
11724 dt.address = sregs->idt.base;
11725 static_call(kvm_x86_set_idt)(vcpu, &dt);
11726 dt.size = sregs->gdt.limit;
11727 dt.address = sregs->gdt.base;
11728 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11730 vcpu->arch.cr2 = sregs->cr2;
11731 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11732 vcpu->arch.cr3 = sregs->cr3;
11733 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11734 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11736 kvm_set_cr8(vcpu, sregs->cr8);
11738 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11739 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11741 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11742 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11744 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11745 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11747 if (update_pdptrs) {
11748 idx = srcu_read_lock(&vcpu->kvm->srcu);
11749 if (is_pae_paging(vcpu)) {
11750 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11751 *mmu_reset_needed = 1;
11753 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11756 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11757 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11758 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11759 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11760 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11761 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11763 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11764 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11766 update_cr8_intercept(vcpu);
11768 /* Older userspace won't unhalt the vcpu on reset. */
11769 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11770 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11771 !is_protmode(vcpu))
11772 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11777 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11779 int pending_vec, max_bits;
11780 int mmu_reset_needed = 0;
11781 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11786 if (mmu_reset_needed) {
11787 kvm_mmu_reset_context(vcpu);
11788 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11791 max_bits = KVM_NR_INTERRUPTS;
11792 pending_vec = find_first_bit(
11793 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11795 if (pending_vec < max_bits) {
11796 kvm_queue_interrupt(vcpu, pending_vec, false);
11797 pr_debug("Set back pending irq %d\n", pending_vec);
11798 kvm_make_request(KVM_REQ_EVENT, vcpu);
11803 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11805 int mmu_reset_needed = 0;
11806 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11807 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11808 !(sregs2->efer & EFER_LMA);
11811 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11814 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11817 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11818 &mmu_reset_needed, !valid_pdptrs);
11822 if (valid_pdptrs) {
11823 for (i = 0; i < 4 ; i++)
11824 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11826 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11827 mmu_reset_needed = 1;
11828 vcpu->arch.pdptrs_from_userspace = true;
11830 if (mmu_reset_needed) {
11831 kvm_mmu_reset_context(vcpu);
11832 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11837 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11838 struct kvm_sregs *sregs)
11843 ret = __set_sregs(vcpu, sregs);
11848 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11851 struct kvm_vcpu *vcpu;
11857 down_write(&kvm->arch.apicv_update_lock);
11859 kvm_for_each_vcpu(i, vcpu, kvm) {
11860 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11865 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11866 up_write(&kvm->arch.apicv_update_lock);
11869 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11870 struct kvm_guest_debug *dbg)
11872 unsigned long rflags;
11875 if (vcpu->arch.guest_state_protected)
11880 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11882 if (kvm_is_exception_pending(vcpu))
11884 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11885 kvm_queue_exception(vcpu, DB_VECTOR);
11887 kvm_queue_exception(vcpu, BP_VECTOR);
11891 * Read rflags as long as potentially injected trace flags are still
11894 rflags = kvm_get_rflags(vcpu);
11896 vcpu->guest_debug = dbg->control;
11897 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11898 vcpu->guest_debug = 0;
11900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11901 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11902 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11903 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11905 for (i = 0; i < KVM_NR_DB_REGS; i++)
11906 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11908 kvm_update_dr7(vcpu);
11910 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11911 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11914 * Trigger an rflags update that will inject or remove the trace
11917 kvm_set_rflags(vcpu, rflags);
11919 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11921 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11931 * Translate a guest virtual address to a guest physical address.
11933 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11934 struct kvm_translation *tr)
11936 unsigned long vaddr = tr->linear_address;
11942 idx = srcu_read_lock(&vcpu->kvm->srcu);
11943 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11944 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11945 tr->physical_address = gpa;
11946 tr->valid = gpa != INVALID_GPA;
11954 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11956 struct fxregs_state *fxsave;
11958 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11963 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11964 memcpy(fpu->fpr, fxsave->st_space, 128);
11965 fpu->fcw = fxsave->cwd;
11966 fpu->fsw = fxsave->swd;
11967 fpu->ftwx = fxsave->twd;
11968 fpu->last_opcode = fxsave->fop;
11969 fpu->last_ip = fxsave->rip;
11970 fpu->last_dp = fxsave->rdp;
11971 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11977 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11979 struct fxregs_state *fxsave;
11981 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11986 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11988 memcpy(fxsave->st_space, fpu->fpr, 128);
11989 fxsave->cwd = fpu->fcw;
11990 fxsave->swd = fpu->fsw;
11991 fxsave->twd = fpu->ftwx;
11992 fxsave->fop = fpu->last_opcode;
11993 fxsave->rip = fpu->last_ip;
11994 fxsave->rdp = fpu->last_dp;
11995 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
12001 static void store_regs(struct kvm_vcpu *vcpu)
12003 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
12005 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
12006 __get_regs(vcpu, &vcpu->run->s.regs.regs);
12008 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
12009 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
12011 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
12012 kvm_vcpu_ioctl_x86_get_vcpu_events(
12013 vcpu, &vcpu->run->s.regs.events);
12016 static int sync_regs(struct kvm_vcpu *vcpu)
12018 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
12019 __set_regs(vcpu, &vcpu->run->s.regs.regs);
12020 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
12023 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
12024 struct kvm_sregs sregs = vcpu->run->s.regs.sregs;
12026 if (__set_sregs(vcpu, &sregs))
12029 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
12032 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
12033 struct kvm_vcpu_events events = vcpu->run->s.regs.events;
12035 if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events))
12038 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
12044 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
12046 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
12047 pr_warn_once("SMP vm created on host with unstable TSC; "
12048 "guest TSC will not be reliable\n");
12050 if (!kvm->arch.max_vcpu_ids)
12051 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
12053 if (id >= kvm->arch.max_vcpu_ids)
12056 return static_call(kvm_x86_vcpu_precreate)(kvm);
12059 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
12064 vcpu->arch.last_vmentry_cpu = -1;
12065 vcpu->arch.regs_avail = ~0;
12066 vcpu->arch.regs_dirty = ~0;
12068 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
12070 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
12071 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12073 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
12075 r = kvm_mmu_create(vcpu);
12079 if (irqchip_in_kernel(vcpu->kvm)) {
12080 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
12082 goto fail_mmu_destroy;
12085 * Defer evaluating inhibits until the vCPU is first run, as
12086 * this vCPU will not get notified of any changes until this
12087 * vCPU is visible to other vCPUs (marked online and added to
12088 * the set of vCPUs). Opportunistically mark APICv active as
12089 * VMX in particularly is highly unlikely to have inhibits.
12090 * Ignore the current per-VM APICv state so that vCPU creation
12091 * is guaranteed to run with a deterministic value, the request
12092 * will ensure the vCPU gets the correct state before VM-Entry.
12094 if (enable_apicv) {
12095 vcpu->arch.apic->apicv_active = true;
12096 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
12099 static_branch_inc(&kvm_has_noapic_vcpu);
12103 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
12105 goto fail_free_lapic;
12106 vcpu->arch.pio_data = page_address(page);
12108 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
12109 GFP_KERNEL_ACCOUNT);
12110 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
12111 GFP_KERNEL_ACCOUNT);
12112 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
12113 goto fail_free_mce_banks;
12114 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
12116 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
12117 GFP_KERNEL_ACCOUNT))
12118 goto fail_free_mce_banks;
12120 if (!alloc_emulate_ctxt(vcpu))
12121 goto free_wbinvd_dirty_mask;
12123 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
12124 pr_err("failed to allocate vcpu's fpu\n");
12125 goto free_emulate_ctxt;
12128 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
12129 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
12131 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
12133 kvm_async_pf_hash_reset(vcpu);
12135 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
12136 kvm_pmu_init(vcpu);
12138 vcpu->arch.pending_external_vector = -1;
12139 vcpu->arch.preempted_in_kernel = false;
12141 #if IS_ENABLED(CONFIG_HYPERV)
12142 vcpu->arch.hv_root_tdp = INVALID_PAGE;
12145 r = static_call(kvm_x86_vcpu_create)(vcpu);
12147 goto free_guest_fpu;
12149 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
12150 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
12151 kvm_xen_init_vcpu(vcpu);
12152 kvm_vcpu_mtrr_init(vcpu);
12154 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
12155 kvm_vcpu_reset(vcpu, false);
12156 kvm_init_mmu(vcpu);
12161 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12163 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12164 free_wbinvd_dirty_mask:
12165 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12166 fail_free_mce_banks:
12167 kfree(vcpu->arch.mce_banks);
12168 kfree(vcpu->arch.mci_ctl2_banks);
12169 free_page((unsigned long)vcpu->arch.pio_data);
12171 kvm_free_lapic(vcpu);
12173 kvm_mmu_destroy(vcpu);
12177 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
12179 struct kvm *kvm = vcpu->kvm;
12181 if (mutex_lock_killable(&vcpu->mutex))
12184 kvm_synchronize_tsc(vcpu, NULL);
12187 /* poll control enabled by default */
12188 vcpu->arch.msr_kvm_poll_control = 1;
12190 mutex_unlock(&vcpu->mutex);
12192 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
12193 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
12194 KVMCLOCK_SYNC_PERIOD);
12197 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
12201 kvmclock_reset(vcpu);
12203 static_call(kvm_x86_vcpu_free)(vcpu);
12205 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12206 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12207 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12209 kvm_xen_destroy_vcpu(vcpu);
12210 kvm_hv_vcpu_uninit(vcpu);
12211 kvm_pmu_destroy(vcpu);
12212 kfree(vcpu->arch.mce_banks);
12213 kfree(vcpu->arch.mci_ctl2_banks);
12214 kvm_free_lapic(vcpu);
12215 idx = srcu_read_lock(&vcpu->kvm->srcu);
12216 kvm_mmu_destroy(vcpu);
12217 srcu_read_unlock(&vcpu->kvm->srcu, idx);
12218 free_page((unsigned long)vcpu->arch.pio_data);
12219 kvfree(vcpu->arch.cpuid_entries);
12220 if (!lapic_in_kernel(vcpu))
12221 static_branch_dec(&kvm_has_noapic_vcpu);
12224 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
12226 struct kvm_cpuid_entry2 *cpuid_0x1;
12227 unsigned long old_cr0 = kvm_read_cr0(vcpu);
12228 unsigned long new_cr0;
12231 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12232 * to handle side effects. RESET emulation hits those flows and relies
12233 * on emulated/virtualized registers, including those that are loaded
12234 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
12235 * to detect improper or missing initialization.
12237 WARN_ON_ONCE(!init_event &&
12238 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
12241 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
12242 * possible to INIT the vCPU while L2 is active. Force the vCPU back
12243 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
12244 * bits), i.e. virtualization is disabled.
12246 if (is_guest_mode(vcpu))
12247 kvm_leave_nested(vcpu);
12249 kvm_lapic_reset(vcpu, init_event);
12251 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12252 vcpu->arch.hflags = 0;
12254 vcpu->arch.smi_pending = 0;
12255 vcpu->arch.smi_count = 0;
12256 atomic_set(&vcpu->arch.nmi_queued, 0);
12257 vcpu->arch.nmi_pending = 0;
12258 vcpu->arch.nmi_injected = false;
12259 kvm_clear_interrupt_queue(vcpu);
12260 kvm_clear_exception_queue(vcpu);
12262 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12263 kvm_update_dr0123(vcpu);
12264 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12265 vcpu->arch.dr7 = DR7_FIXED_1;
12266 kvm_update_dr7(vcpu);
12268 vcpu->arch.cr2 = 0;
12270 kvm_make_request(KVM_REQ_EVENT, vcpu);
12271 vcpu->arch.apf.msr_en_val = 0;
12272 vcpu->arch.apf.msr_int_val = 0;
12273 vcpu->arch.st.msr_val = 0;
12275 kvmclock_reset(vcpu);
12277 kvm_clear_async_pf_completion_queue(vcpu);
12278 kvm_async_pf_hash_reset(vcpu);
12279 vcpu->arch.apf.halted = false;
12281 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12282 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12285 * All paths that lead to INIT are required to load the guest's
12286 * FPU state (because most paths are buried in KVM_RUN).
12289 kvm_put_guest_fpu(vcpu);
12291 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12292 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12295 kvm_load_guest_fpu(vcpu);
12299 vcpu->arch.smbase = 0x30000;
12301 vcpu->arch.msr_misc_features_enables = 0;
12302 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12303 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12305 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12306 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12309 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12310 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12311 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12314 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12315 * if no CPUID match is found. Note, it's impossible to get a match at
12316 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12317 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12318 * on RESET. But, go through the motions in case that's ever remedied.
12320 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12321 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12323 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12325 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12326 kvm_rip_write(vcpu, 0xfff0);
12328 vcpu->arch.cr3 = 0;
12329 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12332 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12333 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12334 * (or qualify) that with a footnote stating that CD/NW are preserved.
12336 new_cr0 = X86_CR0_ET;
12338 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12340 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12342 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12343 static_call(kvm_x86_set_cr4)(vcpu, 0);
12344 static_call(kvm_x86_set_efer)(vcpu, 0);
12345 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12348 * On the standard CR0/CR4/EFER modification paths, there are several
12349 * complex conditions determining whether the MMU has to be reset and/or
12350 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12351 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12352 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12353 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12355 if (old_cr0 & X86_CR0_PG) {
12356 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12357 kvm_mmu_reset_context(vcpu);
12361 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12362 * APM states the TLBs are untouched by INIT, but it also states that
12363 * the TLBs are flushed on "External initialization of the processor."
12364 * Flush the guest TLB regardless of vendor, there is no meaningful
12365 * benefit in relying on the guest to flush the TLB immediately after
12366 * INIT. A spurious TLB flush is benign and likely negligible from a
12367 * performance perspective.
12370 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12372 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12374 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12376 struct kvm_segment cs;
12378 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12379 cs.selector = vector << 8;
12380 cs.base = vector << 12;
12381 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12382 kvm_rip_write(vcpu, 0);
12384 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12386 int kvm_arch_hardware_enable(void)
12389 struct kvm_vcpu *vcpu;
12394 bool stable, backwards_tsc = false;
12396 kvm_user_return_msr_cpu_online();
12398 ret = kvm_x86_check_processor_compatibility();
12402 ret = static_call(kvm_x86_hardware_enable)();
12406 local_tsc = rdtsc();
12407 stable = !kvm_check_tsc_unstable();
12408 list_for_each_entry(kvm, &vm_list, vm_list) {
12409 kvm_for_each_vcpu(i, vcpu, kvm) {
12410 if (!stable && vcpu->cpu == smp_processor_id())
12411 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12412 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12413 backwards_tsc = true;
12414 if (vcpu->arch.last_host_tsc > max_tsc)
12415 max_tsc = vcpu->arch.last_host_tsc;
12421 * Sometimes, even reliable TSCs go backwards. This happens on
12422 * platforms that reset TSC during suspend or hibernate actions, but
12423 * maintain synchronization. We must compensate. Fortunately, we can
12424 * detect that condition here, which happens early in CPU bringup,
12425 * before any KVM threads can be running. Unfortunately, we can't
12426 * bring the TSCs fully up to date with real time, as we aren't yet far
12427 * enough into CPU bringup that we know how much real time has actually
12428 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12429 * variables that haven't been updated yet.
12431 * So we simply find the maximum observed TSC above, then record the
12432 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12433 * the adjustment will be applied. Note that we accumulate
12434 * adjustments, in case multiple suspend cycles happen before some VCPU
12435 * gets a chance to run again. In the event that no KVM threads get a
12436 * chance to run, we will miss the entire elapsed period, as we'll have
12437 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12438 * loose cycle time. This isn't too big a deal, since the loss will be
12439 * uniform across all VCPUs (not to mention the scenario is extremely
12440 * unlikely). It is possible that a second hibernate recovery happens
12441 * much faster than a first, causing the observed TSC here to be
12442 * smaller; this would require additional padding adjustment, which is
12443 * why we set last_host_tsc to the local tsc observed here.
12445 * N.B. - this code below runs only on platforms with reliable TSC,
12446 * as that is the only way backwards_tsc is set above. Also note
12447 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12448 * have the same delta_cyc adjustment applied if backwards_tsc
12449 * is detected. Note further, this adjustment is only done once,
12450 * as we reset last_host_tsc on all VCPUs to stop this from being
12451 * called multiple times (one for each physical CPU bringup).
12453 * Platforms with unreliable TSCs don't have to deal with this, they
12454 * will be compensated by the logic in vcpu_load, which sets the TSC to
12455 * catchup mode. This will catchup all VCPUs to real time, but cannot
12456 * guarantee that they stay in perfect synchronization.
12458 if (backwards_tsc) {
12459 u64 delta_cyc = max_tsc - local_tsc;
12460 list_for_each_entry(kvm, &vm_list, vm_list) {
12461 kvm->arch.backwards_tsc_observed = true;
12462 kvm_for_each_vcpu(i, vcpu, kvm) {
12463 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12464 vcpu->arch.last_host_tsc = local_tsc;
12465 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12469 * We have to disable TSC offset matching.. if you were
12470 * booting a VM while issuing an S4 host suspend....
12471 * you may have some problem. Solving this issue is
12472 * left as an exercise to the reader.
12474 kvm->arch.last_tsc_nsec = 0;
12475 kvm->arch.last_tsc_write = 0;
12482 void kvm_arch_hardware_disable(void)
12484 static_call(kvm_x86_hardware_disable)();
12485 drop_user_return_notifiers();
12488 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12490 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12493 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12495 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12498 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12499 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12501 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12503 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12505 vcpu->arch.l1tf_flush_l1d = true;
12506 if (pmu->version && unlikely(pmu->event_count)) {
12507 pmu->need_cleanup = true;
12508 kvm_make_request(KVM_REQ_PMU, vcpu);
12510 static_call(kvm_x86_sched_in)(vcpu, cpu);
12513 void kvm_arch_free_vm(struct kvm *kvm)
12515 #if IS_ENABLED(CONFIG_HYPERV)
12516 kfree(kvm->arch.hv_pa_pg);
12518 __kvm_arch_free_vm(kvm);
12522 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12525 unsigned long flags;
12527 if (!kvm_is_vm_type_supported(type))
12530 kvm->arch.vm_type = type;
12532 ret = kvm_page_track_init(kvm);
12536 kvm_mmu_init_vm(kvm);
12538 ret = static_call(kvm_x86_vm_init)(kvm);
12540 goto out_uninit_mmu;
12542 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12543 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12545 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12546 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12547 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12548 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12549 &kvm->arch.irq_sources_bitmap);
12551 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12552 mutex_init(&kvm->arch.apic_map_lock);
12553 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12554 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12556 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12557 pvclock_update_vm_gtod_copy(kvm);
12558 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12560 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12561 kvm->arch.guest_can_read_msr_platform_info = true;
12562 kvm->arch.enable_pmu = enable_pmu;
12564 #if IS_ENABLED(CONFIG_HYPERV)
12565 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12566 kvm->arch.hv_root_tdp = INVALID_PAGE;
12569 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12570 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12572 kvm_apicv_init(kvm);
12573 kvm_hv_init_vm(kvm);
12574 kvm_xen_init_vm(kvm);
12579 kvm_mmu_uninit_vm(kvm);
12580 kvm_page_track_cleanup(kvm);
12585 int kvm_arch_post_init_vm(struct kvm *kvm)
12587 return kvm_mmu_post_init_vm(kvm);
12590 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12593 kvm_mmu_unload(vcpu);
12597 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12600 struct kvm_vcpu *vcpu;
12602 kvm_for_each_vcpu(i, vcpu, kvm) {
12603 kvm_clear_async_pf_completion_queue(vcpu);
12604 kvm_unload_vcpu_mmu(vcpu);
12608 void kvm_arch_sync_events(struct kvm *kvm)
12610 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12611 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12616 * __x86_set_memory_region: Setup KVM internal memory slot
12618 * @kvm: the kvm pointer to the VM.
12619 * @id: the slot ID to setup.
12620 * @gpa: the GPA to install the slot (unused when @size == 0).
12621 * @size: the size of the slot. Set to zero to uninstall a slot.
12623 * This function helps to setup a KVM internal memory slot. Specify
12624 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12625 * slot. The return code can be one of the following:
12627 * HVA: on success (uninstall will return a bogus HVA)
12630 * The caller should always use IS_ERR() to check the return value
12631 * before use. Note, the KVM internal memory slots are guaranteed to
12632 * remain valid and unchanged until the VM is destroyed, i.e., the
12633 * GPA->HVA translation will not change. However, the HVA is a user
12634 * address, i.e. its accessibility is not guaranteed, and must be
12635 * accessed via __copy_{to,from}_user().
12637 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12641 unsigned long hva, old_npages;
12642 struct kvm_memslots *slots = kvm_memslots(kvm);
12643 struct kvm_memory_slot *slot;
12645 /* Called with kvm->slots_lock held. */
12646 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12647 return ERR_PTR_USR(-EINVAL);
12649 slot = id_to_memslot(slots, id);
12651 if (slot && slot->npages)
12652 return ERR_PTR_USR(-EEXIST);
12655 * MAP_SHARED to prevent internal slot pages from being moved
12658 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12659 MAP_SHARED | MAP_ANONYMOUS, 0);
12660 if (IS_ERR_VALUE(hva))
12661 return (void __user *)hva;
12663 if (!slot || !slot->npages)
12666 old_npages = slot->npages;
12667 hva = slot->userspace_addr;
12670 for (i = 0; i < kvm_arch_nr_memslot_as_ids(kvm); i++) {
12671 struct kvm_userspace_memory_region2 m;
12673 m.slot = id | (i << 16);
12675 m.guest_phys_addr = gpa;
12676 m.userspace_addr = hva;
12677 m.memory_size = size;
12678 r = __kvm_set_memory_region(kvm, &m);
12680 return ERR_PTR_USR(r);
12684 vm_munmap(hva, old_npages * PAGE_SIZE);
12686 return (void __user *)hva;
12688 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12690 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12692 kvm_mmu_pre_destroy_vm(kvm);
12695 void kvm_arch_destroy_vm(struct kvm *kvm)
12697 if (current->mm == kvm->mm) {
12699 * Free memory regions allocated on behalf of userspace,
12700 * unless the memory map has changed due to process exit
12703 mutex_lock(&kvm->slots_lock);
12704 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12706 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12708 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12709 mutex_unlock(&kvm->slots_lock);
12711 kvm_unload_vcpu_mmus(kvm);
12712 static_call_cond(kvm_x86_vm_destroy)(kvm);
12713 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12714 kvm_pic_destroy(kvm);
12715 kvm_ioapic_destroy(kvm);
12716 kvm_destroy_vcpus(kvm);
12717 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12718 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12719 kvm_mmu_uninit_vm(kvm);
12720 kvm_page_track_cleanup(kvm);
12721 kvm_xen_destroy_vm(kvm);
12722 kvm_hv_destroy_vm(kvm);
12725 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12729 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12730 kvfree(slot->arch.rmap[i]);
12731 slot->arch.rmap[i] = NULL;
12735 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12739 memslot_rmap_free(slot);
12741 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12742 kvfree(slot->arch.lpage_info[i - 1]);
12743 slot->arch.lpage_info[i - 1] = NULL;
12746 kvm_page_track_free_memslot(slot);
12749 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12751 const int sz = sizeof(*slot->arch.rmap[0]);
12754 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12756 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12758 if (slot->arch.rmap[i])
12761 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12762 if (!slot->arch.rmap[i]) {
12763 memslot_rmap_free(slot);
12771 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12772 struct kvm_memory_slot *slot)
12774 unsigned long npages = slot->npages;
12778 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12779 * old arrays will be freed by __kvm_set_memory_region() if installing
12780 * the new memslot is successful.
12782 memset(&slot->arch, 0, sizeof(slot->arch));
12784 if (kvm_memslots_have_rmaps(kvm)) {
12785 r = memslot_rmap_alloc(slot, npages);
12790 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12791 struct kvm_lpage_info *linfo;
12792 unsigned long ugfn;
12796 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12798 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12802 slot->arch.lpage_info[i - 1] = linfo;
12804 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12805 linfo[0].disallow_lpage = 1;
12806 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12807 linfo[lpages - 1].disallow_lpage = 1;
12808 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12810 * If the gfn and userspace address are not aligned wrt each
12811 * other, disable large page support for this slot.
12813 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12816 for (j = 0; j < lpages; ++j)
12817 linfo[j].disallow_lpage = 1;
12821 #ifdef CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES
12822 kvm_mmu_init_memslot_memory_attributes(kvm, slot);
12825 if (kvm_page_track_create_memslot(kvm, slot, npages))
12831 memslot_rmap_free(slot);
12833 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12834 kvfree(slot->arch.lpage_info[i - 1]);
12835 slot->arch.lpage_info[i - 1] = NULL;
12840 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12842 struct kvm_vcpu *vcpu;
12846 * memslots->generation has been incremented.
12847 * mmio generation may have reached its maximum value.
12849 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12851 /* Force re-initialization of steal_time cache */
12852 kvm_for_each_vcpu(i, vcpu, kvm)
12853 kvm_vcpu_kick(vcpu);
12856 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12857 const struct kvm_memory_slot *old,
12858 struct kvm_memory_slot *new,
12859 enum kvm_mr_change change)
12862 * KVM doesn't support moving memslots when there are external page
12863 * trackers attached to the VM, i.e. if KVMGT is in use.
12865 if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm))
12868 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12869 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12872 return kvm_alloc_memslot_metadata(kvm, new);
12875 if (change == KVM_MR_FLAGS_ONLY)
12876 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12877 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12884 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12888 if (!kvm_x86_ops.cpu_dirty_log_size)
12891 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12892 if ((enable && nr_slots == 1) || !nr_slots)
12893 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12896 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12897 struct kvm_memory_slot *old,
12898 const struct kvm_memory_slot *new,
12899 enum kvm_mr_change change)
12901 u32 old_flags = old ? old->flags : 0;
12902 u32 new_flags = new ? new->flags : 0;
12903 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12906 * Update CPU dirty logging if dirty logging is being toggled. This
12907 * applies to all operations.
12909 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12910 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12913 * Nothing more to do for RO slots (which can't be dirtied and can't be
12914 * made writable) or CREATE/MOVE/DELETE of a slot.
12916 * For a memslot with dirty logging disabled:
12917 * CREATE: No dirty mappings will already exist.
12918 * MOVE/DELETE: The old mappings will already have been cleaned up by
12919 * kvm_arch_flush_shadow_memslot()
12921 * For a memslot with dirty logging enabled:
12922 * CREATE: No shadow pages exist, thus nothing to write-protect
12923 * and no dirty bits to clear.
12924 * MOVE/DELETE: The old mappings will already have been cleaned up by
12925 * kvm_arch_flush_shadow_memslot().
12927 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12931 * READONLY and non-flags changes were filtered out above, and the only
12932 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12933 * logging isn't being toggled on or off.
12935 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12938 if (!log_dirty_pages) {
12940 * Dirty logging tracks sptes in 4k granularity, meaning that
12941 * large sptes have to be split. If live migration succeeds,
12942 * the guest in the source machine will be destroyed and large
12943 * sptes will be created in the destination. However, if the
12944 * guest continues to run in the source machine (for example if
12945 * live migration fails), small sptes will remain around and
12946 * cause bad performance.
12948 * Scan sptes if dirty logging has been stopped, dropping those
12949 * which can be collapsed into a single large-page spte. Later
12950 * page faults will create the large-page sptes.
12952 kvm_mmu_zap_collapsible_sptes(kvm, new);
12955 * Initially-all-set does not require write protecting any page,
12956 * because they're all assumed to be dirty.
12958 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12961 if (READ_ONCE(eager_page_split))
12962 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12964 if (kvm_x86_ops.cpu_dirty_log_size) {
12965 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12966 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12968 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12972 * Unconditionally flush the TLBs after enabling dirty logging.
12973 * A flush is almost always going to be necessary (see below),
12974 * and unconditionally flushing allows the helpers to omit
12975 * the subtly complex checks when removing write access.
12977 * Do the flush outside of mmu_lock to reduce the amount of
12978 * time mmu_lock is held. Flushing after dropping mmu_lock is
12979 * safe as KVM only needs to guarantee the slot is fully
12980 * write-protected before returning to userspace, i.e. before
12981 * userspace can consume the dirty status.
12983 * Flushing outside of mmu_lock requires KVM to be careful when
12984 * making decisions based on writable status of an SPTE, e.g. a
12985 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12987 * Specifically, KVM also write-protects guest page tables to
12988 * monitor changes when using shadow paging, and must guarantee
12989 * no CPUs can write to those page before mmu_lock is dropped.
12990 * Because CPUs may have stale TLB entries at this point, a
12991 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12993 * KVM also allows making SPTES writable outside of mmu_lock,
12994 * e.g. to allow dirty logging without taking mmu_lock.
12996 * To handle these scenarios, KVM uses a separate software-only
12997 * bit (MMU-writable) to track if a SPTE is !writable due to
12998 * a guest page table being write-protected (KVM clears the
12999 * MMU-writable flag when write-protecting for shadow paging).
13001 * The use of MMU-writable is also the primary motivation for
13002 * the unconditional flush. Because KVM must guarantee that a
13003 * CPU doesn't contain stale, writable TLB entries for a
13004 * !MMU-writable SPTE, KVM must flush if it encounters any
13005 * MMU-writable SPTE regardless of whether the actual hardware
13006 * writable bit was set. I.e. KVM is almost guaranteed to need
13007 * to flush, while unconditionally flushing allows the "remove
13008 * write access" helpers to ignore MMU-writable entirely.
13010 * See is_writable_pte() for more details (the case involving
13011 * access-tracked SPTEs is particularly relevant).
13013 kvm_flush_remote_tlbs_memslot(kvm, new);
13017 void kvm_arch_commit_memory_region(struct kvm *kvm,
13018 struct kvm_memory_slot *old,
13019 const struct kvm_memory_slot *new,
13020 enum kvm_mr_change change)
13022 if (change == KVM_MR_DELETE)
13023 kvm_page_track_delete_slot(kvm, old);
13025 if (!kvm->arch.n_requested_mmu_pages &&
13026 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
13027 unsigned long nr_mmu_pages;
13029 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
13030 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
13031 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
13034 kvm_mmu_slot_apply_flags(kvm, old, new, change);
13036 /* Free the arrays associated with the old memslot. */
13037 if (change == KVM_MR_MOVE)
13038 kvm_arch_free_memslot(kvm, old);
13041 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
13043 return (is_guest_mode(vcpu) &&
13044 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
13047 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
13049 if (!list_empty_careful(&vcpu->async_pf.done))
13052 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
13053 kvm_apic_init_sipi_allowed(vcpu))
13056 if (vcpu->arch.pv.pv_unhalted)
13059 if (kvm_is_exception_pending(vcpu))
13062 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
13063 (vcpu->arch.nmi_pending &&
13064 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
13067 #ifdef CONFIG_KVM_SMM
13068 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
13069 (vcpu->arch.smi_pending &&
13070 static_call(kvm_x86_smi_allowed)(vcpu, false)))
13074 if (kvm_test_request(KVM_REQ_PMI, vcpu))
13077 if (kvm_arch_interrupt_allowed(vcpu) &&
13078 (kvm_cpu_has_interrupt(vcpu) ||
13079 kvm_guest_apic_has_interrupt(vcpu)))
13082 if (kvm_hv_has_stimer_pending(vcpu))
13085 if (is_guest_mode(vcpu) &&
13086 kvm_x86_ops.nested_ops->has_events &&
13087 kvm_x86_ops.nested_ops->has_events(vcpu))
13090 if (kvm_xen_has_pending_events(vcpu))
13096 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
13098 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
13101 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
13103 if (kvm_vcpu_apicv_active(vcpu) &&
13104 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
13110 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
13112 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
13115 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
13116 #ifdef CONFIG_KVM_SMM
13117 kvm_test_request(KVM_REQ_SMI, vcpu) ||
13119 kvm_test_request(KVM_REQ_EVENT, vcpu))
13122 return kvm_arch_dy_has_pending_interrupt(vcpu);
13125 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
13127 if (vcpu->arch.guest_state_protected)
13130 if (vcpu != kvm_get_running_vcpu())
13131 return vcpu->arch.preempted_in_kernel;
13133 return static_call(kvm_x86_get_cpl)(vcpu) == 0;
13136 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
13138 return kvm_rip_read(vcpu);
13141 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
13143 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
13146 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
13148 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
13151 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
13153 /* Can't read the RIP when guest state is protected, just return 0 */
13154 if (vcpu->arch.guest_state_protected)
13157 if (is_64_bit_mode(vcpu))
13158 return kvm_rip_read(vcpu);
13159 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
13160 kvm_rip_read(vcpu));
13162 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
13164 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
13166 return kvm_get_linear_rip(vcpu) == linear_rip;
13168 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
13170 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
13172 unsigned long rflags;
13174 rflags = static_call(kvm_x86_get_rflags)(vcpu);
13175 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
13176 rflags &= ~X86_EFLAGS_TF;
13179 EXPORT_SYMBOL_GPL(kvm_get_rflags);
13181 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13183 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
13184 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
13185 rflags |= X86_EFLAGS_TF;
13186 static_call(kvm_x86_set_rflags)(vcpu, rflags);
13189 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13191 __kvm_set_rflags(vcpu, rflags);
13192 kvm_make_request(KVM_REQ_EVENT, vcpu);
13194 EXPORT_SYMBOL_GPL(kvm_set_rflags);
13196 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
13198 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
13200 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
13203 static inline u32 kvm_async_pf_next_probe(u32 key)
13205 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
13208 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13210 u32 key = kvm_async_pf_hash_fn(gfn);
13212 while (vcpu->arch.apf.gfns[key] != ~0)
13213 key = kvm_async_pf_next_probe(key);
13215 vcpu->arch.apf.gfns[key] = gfn;
13218 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
13221 u32 key = kvm_async_pf_hash_fn(gfn);
13223 for (i = 0; i < ASYNC_PF_PER_VCPU &&
13224 (vcpu->arch.apf.gfns[key] != gfn &&
13225 vcpu->arch.apf.gfns[key] != ~0); i++)
13226 key = kvm_async_pf_next_probe(key);
13231 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13233 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
13236 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13240 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
13242 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
13246 vcpu->arch.apf.gfns[i] = ~0;
13248 j = kvm_async_pf_next_probe(j);
13249 if (vcpu->arch.apf.gfns[j] == ~0)
13251 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
13253 * k lies cyclically in ]i,j]
13255 * |....j i.k.| or |.k..j i...|
13257 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13258 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13263 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13265 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13267 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13271 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13273 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13275 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13276 &token, offset, sizeof(token));
13279 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13281 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13284 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13285 &val, offset, sizeof(val)))
13291 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13294 if (!kvm_pv_async_pf_enabled(vcpu))
13297 if (vcpu->arch.apf.send_user_only &&
13298 static_call(kvm_x86_get_cpl)(vcpu) == 0)
13301 if (is_guest_mode(vcpu)) {
13303 * L1 needs to opt into the special #PF vmexits that are
13304 * used to deliver async page faults.
13306 return vcpu->arch.apf.delivery_as_pf_vmexit;
13309 * Play it safe in case the guest temporarily disables paging.
13310 * The real mode IDT in particular is unlikely to have a #PF
13313 return is_paging(vcpu);
13317 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13319 if (unlikely(!lapic_in_kernel(vcpu) ||
13320 kvm_event_needs_reinjection(vcpu) ||
13321 kvm_is_exception_pending(vcpu)))
13324 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13328 * If interrupts are off we cannot even use an artificial
13331 return kvm_arch_interrupt_allowed(vcpu);
13334 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13335 struct kvm_async_pf *work)
13337 struct x86_exception fault;
13339 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13340 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13342 if (kvm_can_deliver_async_pf(vcpu) &&
13343 !apf_put_user_notpresent(vcpu)) {
13344 fault.vector = PF_VECTOR;
13345 fault.error_code_valid = true;
13346 fault.error_code = 0;
13347 fault.nested_page_fault = false;
13348 fault.address = work->arch.token;
13349 fault.async_page_fault = true;
13350 kvm_inject_page_fault(vcpu, &fault);
13354 * It is not possible to deliver a paravirtualized asynchronous
13355 * page fault, but putting the guest in an artificial halt state
13356 * can be beneficial nevertheless: if an interrupt arrives, we
13357 * can deliver it timely and perhaps the guest will schedule
13358 * another process. When the instruction that triggered a page
13359 * fault is retried, hopefully the page will be ready in the host.
13361 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13366 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13367 struct kvm_async_pf *work)
13369 struct kvm_lapic_irq irq = {
13370 .delivery_mode = APIC_DM_FIXED,
13371 .vector = vcpu->arch.apf.vec
13374 if (work->wakeup_all)
13375 work->arch.token = ~0; /* broadcast wakeup */
13377 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13378 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13380 if ((work->wakeup_all || work->notpresent_injected) &&
13381 kvm_pv_async_pf_enabled(vcpu) &&
13382 !apf_put_user_ready(vcpu, work->arch.token)) {
13383 vcpu->arch.apf.pageready_pending = true;
13384 kvm_apic_set_irq(vcpu, &irq, NULL);
13387 vcpu->arch.apf.halted = false;
13388 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13391 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13393 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13394 if (!vcpu->arch.apf.pageready_pending)
13395 kvm_vcpu_kick(vcpu);
13398 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13400 if (!kvm_pv_async_pf_enabled(vcpu))
13403 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13406 void kvm_arch_start_assignment(struct kvm *kvm)
13408 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13409 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13411 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13413 void kvm_arch_end_assignment(struct kvm *kvm)
13415 atomic_dec(&kvm->arch.assigned_device_count);
13417 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13419 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13421 return raw_atomic_read(&kvm->arch.assigned_device_count);
13423 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13425 static void kvm_noncoherent_dma_assignment_start_or_stop(struct kvm *kvm)
13428 * Non-coherent DMA assignment and de-assignment will affect
13429 * whether KVM honors guest MTRRs and cause changes in memtypes
13431 * So, pass %true unconditionally to indicate non-coherent DMA was,
13432 * or will be involved, and that zapping SPTEs might be necessary.
13434 if (__kvm_mmu_honors_guest_mtrrs(true))
13435 kvm_zap_gfn_range(kvm, gpa_to_gfn(0), gpa_to_gfn(~0ULL));
13438 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13440 if (atomic_inc_return(&kvm->arch.noncoherent_dma_count) == 1)
13441 kvm_noncoherent_dma_assignment_start_or_stop(kvm);
13443 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13445 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13447 if (!atomic_dec_return(&kvm->arch.noncoherent_dma_count))
13448 kvm_noncoherent_dma_assignment_start_or_stop(kvm);
13450 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13452 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13454 return atomic_read(&kvm->arch.noncoherent_dma_count);
13456 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13458 bool kvm_arch_has_irq_bypass(void)
13460 return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP);
13463 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13464 struct irq_bypass_producer *prod)
13466 struct kvm_kernel_irqfd *irqfd =
13467 container_of(cons, struct kvm_kernel_irqfd, consumer);
13470 irqfd->producer = prod;
13471 kvm_arch_start_assignment(irqfd->kvm);
13472 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13473 prod->irq, irqfd->gsi, 1);
13476 kvm_arch_end_assignment(irqfd->kvm);
13481 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13482 struct irq_bypass_producer *prod)
13485 struct kvm_kernel_irqfd *irqfd =
13486 container_of(cons, struct kvm_kernel_irqfd, consumer);
13488 WARN_ON(irqfd->producer != prod);
13489 irqfd->producer = NULL;
13492 * When producer of consumer is unregistered, we change back to
13493 * remapped mode, so we can re-use the current implementation
13494 * when the irq is masked/disabled or the consumer side (KVM
13495 * int this case doesn't want to receive the interrupts.
13497 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13499 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13500 " fails: %d\n", irqfd->consumer.token, ret);
13502 kvm_arch_end_assignment(irqfd->kvm);
13505 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13506 uint32_t guest_irq, bool set)
13508 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13511 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13512 struct kvm_kernel_irq_routing_entry *new)
13514 if (new->type != KVM_IRQ_ROUTING_MSI)
13517 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13520 bool kvm_vector_hashing_enabled(void)
13522 return vector_hashing;
13525 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13527 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13529 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13532 int kvm_spec_ctrl_test_value(u64 value)
13535 * test that setting IA32_SPEC_CTRL to given value
13536 * is allowed by the host processor
13540 unsigned long flags;
13543 local_irq_save(flags);
13545 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13547 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13550 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13552 local_irq_restore(flags);
13556 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13558 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13560 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13561 struct x86_exception fault;
13562 u64 access = error_code &
13563 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13565 if (!(error_code & PFERR_PRESENT_MASK) ||
13566 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13568 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13569 * tables probably do not match the TLB. Just proceed
13570 * with the error code that the processor gave.
13572 fault.vector = PF_VECTOR;
13573 fault.error_code_valid = true;
13574 fault.error_code = error_code;
13575 fault.nested_page_fault = false;
13576 fault.address = gva;
13577 fault.async_page_fault = false;
13579 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13581 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13584 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13585 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13586 * indicates whether exit to userspace is needed.
13588 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13589 struct x86_exception *e)
13591 if (r == X86EMUL_PROPAGATE_FAULT) {
13592 if (KVM_BUG_ON(!e, vcpu->kvm))
13595 kvm_inject_emulated_page_fault(vcpu, e);
13600 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13601 * while handling a VMX instruction KVM could've handled the request
13602 * correctly by exiting to userspace and performing I/O but there
13603 * doesn't seem to be a real use-case behind such requests, just return
13604 * KVM_EXIT_INTERNAL_ERROR for now.
13606 kvm_prepare_emulation_failure_exit(vcpu);
13610 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13612 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13615 struct x86_exception e;
13622 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13623 if (r != X86EMUL_CONTINUE)
13624 return kvm_handle_memory_failure(vcpu, r, &e);
13626 if (operand.pcid >> 12 != 0) {
13627 kvm_inject_gp(vcpu, 0);
13631 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13634 case INVPCID_TYPE_INDIV_ADDR:
13636 * LAM doesn't apply to addresses that are inputs to TLB
13639 if ((!pcid_enabled && (operand.pcid != 0)) ||
13640 is_noncanonical_address(operand.gla, vcpu)) {
13641 kvm_inject_gp(vcpu, 0);
13644 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13645 return kvm_skip_emulated_instruction(vcpu);
13647 case INVPCID_TYPE_SINGLE_CTXT:
13648 if (!pcid_enabled && (operand.pcid != 0)) {
13649 kvm_inject_gp(vcpu, 0);
13653 kvm_invalidate_pcid(vcpu, operand.pcid);
13654 return kvm_skip_emulated_instruction(vcpu);
13656 case INVPCID_TYPE_ALL_NON_GLOBAL:
13658 * Currently, KVM doesn't mark global entries in the shadow
13659 * page tables, so a non-global flush just degenerates to a
13660 * global flush. If needed, we could optimize this later by
13661 * keeping track of global entries in shadow page tables.
13665 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13666 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13667 return kvm_skip_emulated_instruction(vcpu);
13670 kvm_inject_gp(vcpu, 0);
13674 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13676 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13678 struct kvm_run *run = vcpu->run;
13679 struct kvm_mmio_fragment *frag;
13682 BUG_ON(!vcpu->mmio_needed);
13684 /* Complete previous fragment */
13685 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13686 len = min(8u, frag->len);
13687 if (!vcpu->mmio_is_write)
13688 memcpy(frag->data, run->mmio.data, len);
13690 if (frag->len <= 8) {
13691 /* Switch to the next fragment. */
13693 vcpu->mmio_cur_fragment++;
13695 /* Go forward to the next mmio piece. */
13701 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13702 vcpu->mmio_needed = 0;
13704 // VMG change, at this point, we're always done
13705 // RIP has already been advanced
13709 // More MMIO is needed
13710 run->mmio.phys_addr = frag->gpa;
13711 run->mmio.len = min(8u, frag->len);
13712 run->mmio.is_write = vcpu->mmio_is_write;
13713 if (run->mmio.is_write)
13714 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13715 run->exit_reason = KVM_EXIT_MMIO;
13717 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13722 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13726 struct kvm_mmio_fragment *frag;
13731 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13732 if (handled == bytes)
13739 /*TODO: Check if need to increment number of frags */
13740 frag = vcpu->mmio_fragments;
13741 vcpu->mmio_nr_fragments = 1;
13746 vcpu->mmio_needed = 1;
13747 vcpu->mmio_cur_fragment = 0;
13749 vcpu->run->mmio.phys_addr = gpa;
13750 vcpu->run->mmio.len = min(8u, frag->len);
13751 vcpu->run->mmio.is_write = 1;
13752 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13753 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13755 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13759 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13761 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13765 struct kvm_mmio_fragment *frag;
13770 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13771 if (handled == bytes)
13778 /*TODO: Check if need to increment number of frags */
13779 frag = vcpu->mmio_fragments;
13780 vcpu->mmio_nr_fragments = 1;
13785 vcpu->mmio_needed = 1;
13786 vcpu->mmio_cur_fragment = 0;
13788 vcpu->run->mmio.phys_addr = gpa;
13789 vcpu->run->mmio.len = min(8u, frag->len);
13790 vcpu->run->mmio.is_write = 0;
13791 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13793 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13797 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13799 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13801 vcpu->arch.sev_pio_count -= count;
13802 vcpu->arch.sev_pio_data += count * size;
13805 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13806 unsigned int port);
13808 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13810 int size = vcpu->arch.pio.size;
13811 int port = vcpu->arch.pio.port;
13813 vcpu->arch.pio.count = 0;
13814 if (vcpu->arch.sev_pio_count)
13815 return kvm_sev_es_outs(vcpu, size, port);
13819 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13823 unsigned int count =
13824 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13825 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13827 /* memcpy done already by emulator_pio_out. */
13828 advance_sev_es_emulated_pio(vcpu, count, size);
13832 /* Emulation done by the kernel. */
13833 if (!vcpu->arch.sev_pio_count)
13837 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13841 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13842 unsigned int port);
13844 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13846 unsigned count = vcpu->arch.pio.count;
13847 int size = vcpu->arch.pio.size;
13848 int port = vcpu->arch.pio.port;
13850 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13851 advance_sev_es_emulated_pio(vcpu, count, size);
13852 if (vcpu->arch.sev_pio_count)
13853 return kvm_sev_es_ins(vcpu, size, port);
13857 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13861 unsigned int count =
13862 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13863 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13866 /* Emulation done by the kernel. */
13867 advance_sev_es_emulated_pio(vcpu, count, size);
13868 if (!vcpu->arch.sev_pio_count)
13872 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13876 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13877 unsigned int port, void *data, unsigned int count,
13880 vcpu->arch.sev_pio_data = data;
13881 vcpu->arch.sev_pio_count = count;
13882 return in ? kvm_sev_es_ins(vcpu, size, port)
13883 : kvm_sev_es_outs(vcpu, size, port);
13885 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13895 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13896 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13897 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13898 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13899 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13900 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13901 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13902 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13903 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13904 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13905 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13906 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13907 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13908 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13909 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13910 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13911 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13912 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13913 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13914 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13915 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13917 static int __init kvm_x86_init(void)
13919 kvm_mmu_x86_module_init();
13920 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13923 module_init(kvm_x86_init);
13925 static void __exit kvm_x86_exit(void)
13928 * If module_init() is implemented, module_exit() must also be
13929 * implemented to allow module unload.
13932 module_exit(kvm_x86_exit);