1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60 #include <linux/suspend.h>
62 #include <trace/events/kvm.h>
64 #include <asm/debugreg.h>
69 #include <linux/kernel_stat.h>
70 #include <asm/fpu/api.h>
71 #include <asm/fpu/xcr.h>
72 #include <asm/fpu/xstate.h>
73 #include <asm/pvclock.h>
74 #include <asm/div64.h>
75 #include <asm/irq_remapping.h>
76 #include <asm/mshyperv.h>
77 #include <asm/hypervisor.h>
78 #include <asm/tlbflush.h>
79 #include <asm/intel_pt.h>
80 #include <asm/emulate_prefix.h>
82 #include <clocksource/hyperv_timer.h>
84 #define CREATE_TRACE_POINTS
87 #define MAX_IO_MSRS 256
88 #define KVM_MAX_MCE_BANKS 32
90 struct kvm_caps kvm_caps __read_mostly = {
91 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
93 EXPORT_SYMBOL_GPL(kvm_caps);
95 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
97 #define emul_to_vcpu(ctxt) \
98 ((struct kvm_vcpu *)(ctxt)->vcpu)
101 * - enable syscall per default because its emulated by KVM
102 * - enable LME and LMA per default on 64 bit KVM
106 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
108 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
111 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
113 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
115 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
117 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
118 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
120 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
121 static void process_nmi(struct kvm_vcpu *vcpu);
122 static void process_smi(struct kvm_vcpu *vcpu);
123 static void enter_smm(struct kvm_vcpu *vcpu);
124 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
125 static void store_regs(struct kvm_vcpu *vcpu);
126 static int sync_regs(struct kvm_vcpu *vcpu);
127 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
129 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
132 struct kvm_x86_ops kvm_x86_ops __read_mostly;
134 #define KVM_X86_OP(func) \
135 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
136 *(((struct kvm_x86_ops *)0)->func));
137 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
138 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
139 #include <asm/kvm-x86-ops.h>
140 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
141 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
143 static bool __read_mostly ignore_msrs = 0;
144 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
146 bool __read_mostly report_ignored_msrs = true;
147 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
148 EXPORT_SYMBOL_GPL(report_ignored_msrs);
150 unsigned int min_timer_period_us = 200;
151 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
153 static bool __read_mostly kvmclock_periodic_sync = true;
154 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
156 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
157 static u32 __read_mostly tsc_tolerance_ppm = 250;
158 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
161 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
162 * adaptive tuning starting from default advancement of 1000ns. '0' disables
163 * advancement entirely. Any other value is used as-is and disables adaptive
164 * tuning, i.e. allows privileged userspace to set an exact advancement time.
166 static int __read_mostly lapic_timer_advance_ns = -1;
167 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
169 static bool __read_mostly vector_hashing = true;
170 module_param(vector_hashing, bool, S_IRUGO);
172 bool __read_mostly enable_vmware_backdoor = false;
173 module_param(enable_vmware_backdoor, bool, S_IRUGO);
174 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
177 * Flags to manipulate forced emulation behavior (any non-zero value will
178 * enable forced emulation).
180 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
181 static int __read_mostly force_emulation_prefix;
182 module_param(force_emulation_prefix, int, 0644);
184 int __read_mostly pi_inject_timer = -1;
185 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
187 /* Enable/disable PMU virtualization */
188 bool __read_mostly enable_pmu = true;
189 EXPORT_SYMBOL_GPL(enable_pmu);
190 module_param(enable_pmu, bool, 0444);
192 bool __read_mostly eager_page_split = true;
193 module_param(eager_page_split, bool, 0644);
195 /* Enable/disable SMT_RSB bug mitigation */
196 bool __read_mostly mitigate_smt_rsb;
197 module_param(mitigate_smt_rsb, bool, 0444);
200 * Restoring the host value for MSRs that are only consumed when running in
201 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
202 * returns to userspace, i.e. the kernel can run with the guest's value.
204 #define KVM_MAX_NR_USER_RETURN_MSRS 16
206 struct kvm_user_return_msrs {
207 struct user_return_notifier urn;
209 struct kvm_user_return_msr_values {
212 } values[KVM_MAX_NR_USER_RETURN_MSRS];
215 u32 __read_mostly kvm_nr_uret_msrs;
216 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
217 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
218 static struct kvm_user_return_msrs __percpu *user_return_msrs;
220 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
221 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
222 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
223 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
225 u64 __read_mostly host_efer;
226 EXPORT_SYMBOL_GPL(host_efer);
228 bool __read_mostly allow_smaller_maxphyaddr = 0;
229 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
231 bool __read_mostly enable_apicv = true;
232 EXPORT_SYMBOL_GPL(enable_apicv);
234 u64 __read_mostly host_xss;
235 EXPORT_SYMBOL_GPL(host_xss);
237 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
238 KVM_GENERIC_VM_STATS(),
239 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
240 STATS_DESC_COUNTER(VM, mmu_pte_write),
241 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
242 STATS_DESC_COUNTER(VM, mmu_flooded),
243 STATS_DESC_COUNTER(VM, mmu_recycled),
244 STATS_DESC_COUNTER(VM, mmu_cache_miss),
245 STATS_DESC_ICOUNTER(VM, mmu_unsync),
246 STATS_DESC_ICOUNTER(VM, pages_4k),
247 STATS_DESC_ICOUNTER(VM, pages_2m),
248 STATS_DESC_ICOUNTER(VM, pages_1g),
249 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
250 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
251 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
254 const struct kvm_stats_header kvm_vm_stats_header = {
255 .name_size = KVM_STATS_NAME_SIZE,
256 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
257 .id_offset = sizeof(struct kvm_stats_header),
258 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
259 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
260 sizeof(kvm_vm_stats_desc),
263 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
264 KVM_GENERIC_VCPU_STATS(),
265 STATS_DESC_COUNTER(VCPU, pf_taken),
266 STATS_DESC_COUNTER(VCPU, pf_fixed),
267 STATS_DESC_COUNTER(VCPU, pf_emulate),
268 STATS_DESC_COUNTER(VCPU, pf_spurious),
269 STATS_DESC_COUNTER(VCPU, pf_fast),
270 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
271 STATS_DESC_COUNTER(VCPU, pf_guest),
272 STATS_DESC_COUNTER(VCPU, tlb_flush),
273 STATS_DESC_COUNTER(VCPU, invlpg),
274 STATS_DESC_COUNTER(VCPU, exits),
275 STATS_DESC_COUNTER(VCPU, io_exits),
276 STATS_DESC_COUNTER(VCPU, mmio_exits),
277 STATS_DESC_COUNTER(VCPU, signal_exits),
278 STATS_DESC_COUNTER(VCPU, irq_window_exits),
279 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
280 STATS_DESC_COUNTER(VCPU, l1d_flush),
281 STATS_DESC_COUNTER(VCPU, halt_exits),
282 STATS_DESC_COUNTER(VCPU, request_irq_exits),
283 STATS_DESC_COUNTER(VCPU, irq_exits),
284 STATS_DESC_COUNTER(VCPU, host_state_reload),
285 STATS_DESC_COUNTER(VCPU, fpu_reload),
286 STATS_DESC_COUNTER(VCPU, insn_emulation),
287 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
288 STATS_DESC_COUNTER(VCPU, hypercalls),
289 STATS_DESC_COUNTER(VCPU, irq_injections),
290 STATS_DESC_COUNTER(VCPU, nmi_injections),
291 STATS_DESC_COUNTER(VCPU, req_event),
292 STATS_DESC_COUNTER(VCPU, nested_run),
293 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
294 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
295 STATS_DESC_COUNTER(VCPU, preemption_reported),
296 STATS_DESC_COUNTER(VCPU, preemption_other),
297 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
298 STATS_DESC_COUNTER(VCPU, notify_window_exits),
301 const struct kvm_stats_header kvm_vcpu_stats_header = {
302 .name_size = KVM_STATS_NAME_SIZE,
303 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
304 .id_offset = sizeof(struct kvm_stats_header),
305 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
306 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
307 sizeof(kvm_vcpu_stats_desc),
310 u64 __read_mostly host_xcr0;
312 static struct kmem_cache *x86_emulator_cache;
315 * When called, it means the previous get/set msr reached an invalid msr.
316 * Return true if we want to ignore/silent this failed msr access.
318 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
320 const char *op = write ? "wrmsr" : "rdmsr";
323 if (report_ignored_msrs)
324 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
329 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
335 static struct kmem_cache *kvm_alloc_emulator_cache(void)
337 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
338 unsigned int size = sizeof(struct x86_emulate_ctxt);
340 return kmem_cache_create_usercopy("x86_emulator", size,
341 __alignof__(struct x86_emulate_ctxt),
342 SLAB_ACCOUNT, useroffset,
343 size - useroffset, NULL);
346 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
348 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
351 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
352 vcpu->arch.apf.gfns[i] = ~0;
355 static void kvm_on_user_return(struct user_return_notifier *urn)
358 struct kvm_user_return_msrs *msrs
359 = container_of(urn, struct kvm_user_return_msrs, urn);
360 struct kvm_user_return_msr_values *values;
364 * Disabling irqs at this point since the following code could be
365 * interrupted and executed through kvm_arch_hardware_disable()
367 local_irq_save(flags);
368 if (msrs->registered) {
369 msrs->registered = false;
370 user_return_notifier_unregister(urn);
372 local_irq_restore(flags);
373 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
374 values = &msrs->values[slot];
375 if (values->host != values->curr) {
376 wrmsrl(kvm_uret_msrs_list[slot], values->host);
377 values->curr = values->host;
382 static int kvm_probe_user_return_msr(u32 msr)
388 ret = rdmsrl_safe(msr, &val);
391 ret = wrmsrl_safe(msr, val);
397 int kvm_add_user_return_msr(u32 msr)
399 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
401 if (kvm_probe_user_return_msr(msr))
404 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
405 return kvm_nr_uret_msrs++;
407 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
409 int kvm_find_user_return_msr(u32 msr)
413 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
414 if (kvm_uret_msrs_list[i] == msr)
419 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
421 static void kvm_user_return_msr_cpu_online(void)
423 unsigned int cpu = smp_processor_id();
424 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
428 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
429 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
430 msrs->values[i].host = value;
431 msrs->values[i].curr = value;
435 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
437 unsigned int cpu = smp_processor_id();
438 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
441 value = (value & mask) | (msrs->values[slot].host & ~mask);
442 if (value == msrs->values[slot].curr)
444 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
448 msrs->values[slot].curr = value;
449 if (!msrs->registered) {
450 msrs->urn.on_user_return = kvm_on_user_return;
451 user_return_notifier_register(&msrs->urn);
452 msrs->registered = true;
456 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
458 static void drop_user_return_notifiers(void)
460 unsigned int cpu = smp_processor_id();
461 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
463 if (msrs->registered)
464 kvm_on_user_return(&msrs->urn);
467 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
469 return vcpu->arch.apic_base;
471 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
473 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
475 return kvm_apic_mode(kvm_get_apic_base(vcpu));
477 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
479 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
481 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
482 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
483 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
484 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
486 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
488 if (!msr_info->host_initiated) {
489 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
491 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
495 kvm_lapic_set_base(vcpu, msr_info->data);
496 kvm_recalculate_apic_map(vcpu->kvm);
499 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
502 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
504 * Hardware virtualization extension instructions may fault if a reboot turns
505 * off virtualization while processes are running. Usually after catching the
506 * fault we just panic; during reboot instead the instruction is ignored.
508 noinstr void kvm_spurious_fault(void)
510 /* Fault while not rebooting. We want the trace. */
511 BUG_ON(!kvm_rebooting);
513 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
515 #define EXCPT_BENIGN 0
516 #define EXCPT_CONTRIBUTORY 1
519 static int exception_class(int vector)
529 return EXCPT_CONTRIBUTORY;
536 #define EXCPT_FAULT 0
538 #define EXCPT_ABORT 2
539 #define EXCPT_INTERRUPT 3
542 static int exception_type(int vector)
546 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
547 return EXCPT_INTERRUPT;
552 * #DBs can be trap-like or fault-like, the caller must check other CPU
553 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
555 if (mask & (1 << DB_VECTOR))
558 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
561 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
564 /* Reserved exceptions will result in fault */
568 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
569 struct kvm_queued_exception *ex)
571 if (!ex->has_payload)
574 switch (ex->vector) {
577 * "Certain debug exceptions may clear bit 0-3. The
578 * remaining contents of the DR6 register are never
579 * cleared by the processor".
581 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
583 * In order to reflect the #DB exception payload in guest
584 * dr6, three components need to be considered: active low
585 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
587 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
588 * In the target guest dr6:
589 * FIXED_1 bits should always be set.
590 * Active low bits should be cleared if 1-setting in payload.
591 * Active high bits should be set if 1-setting in payload.
593 * Note, the payload is compatible with the pending debug
594 * exceptions/exit qualification under VMX, that active_low bits
595 * are active high in payload.
596 * So they need to be flipped for DR6.
598 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
599 vcpu->arch.dr6 |= ex->payload;
600 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
603 * The #DB payload is defined as compatible with the 'pending
604 * debug exceptions' field under VMX, not DR6. While bit 12 is
605 * defined in the 'pending debug exceptions' field (enabled
606 * breakpoint), it is reserved and must be zero in DR6.
608 vcpu->arch.dr6 &= ~BIT(12);
611 vcpu->arch.cr2 = ex->payload;
615 ex->has_payload = false;
618 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
620 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
621 bool has_error_code, u32 error_code,
622 bool has_payload, unsigned long payload)
624 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
627 ex->injected = false;
629 ex->has_error_code = has_error_code;
630 ex->error_code = error_code;
631 ex->has_payload = has_payload;
632 ex->payload = payload;
635 /* Forcibly leave the nested mode in cases like a vCPU reset */
636 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
638 kvm_x86_ops.nested_ops->leave_nested(vcpu);
641 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
642 unsigned nr, bool has_error, u32 error_code,
643 bool has_payload, unsigned long payload, bool reinject)
648 kvm_make_request(KVM_REQ_EVENT, vcpu);
651 * If the exception is destined for L2 and isn't being reinjected,
652 * morph it to a VM-Exit if L1 wants to intercept the exception. A
653 * previously injected exception is not checked because it was checked
654 * when it was original queued, and re-checking is incorrect if _L1_
655 * injected the exception, in which case it's exempt from interception.
657 if (!reinject && is_guest_mode(vcpu) &&
658 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
659 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
660 has_payload, payload);
664 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
668 * On VM-Entry, an exception can be pending if and only
669 * if event injection was blocked by nested_run_pending.
670 * In that case, however, vcpu_enter_guest() requests an
671 * immediate exit, and the guest shouldn't proceed far
672 * enough to need reinjection.
674 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
675 vcpu->arch.exception.injected = true;
676 if (WARN_ON_ONCE(has_payload)) {
678 * A reinjected event has already
679 * delivered its payload.
685 vcpu->arch.exception.pending = true;
686 vcpu->arch.exception.injected = false;
688 vcpu->arch.exception.has_error_code = has_error;
689 vcpu->arch.exception.vector = nr;
690 vcpu->arch.exception.error_code = error_code;
691 vcpu->arch.exception.has_payload = has_payload;
692 vcpu->arch.exception.payload = payload;
693 if (!is_guest_mode(vcpu))
694 kvm_deliver_exception_payload(vcpu,
695 &vcpu->arch.exception);
699 /* to check exception */
700 prev_nr = vcpu->arch.exception.vector;
701 if (prev_nr == DF_VECTOR) {
702 /* triple fault -> shutdown */
703 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
706 class1 = exception_class(prev_nr);
707 class2 = exception_class(nr);
708 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
709 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
711 * Synthesize #DF. Clear the previously injected or pending
712 * exception so as not to incorrectly trigger shutdown.
714 vcpu->arch.exception.injected = false;
715 vcpu->arch.exception.pending = false;
717 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
719 /* replace previous exception with a new one in a hope
720 that instruction re-execution will regenerate lost
726 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
728 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
730 EXPORT_SYMBOL_GPL(kvm_queue_exception);
732 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
734 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
736 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
738 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
739 unsigned long payload)
741 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
743 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
745 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
746 u32 error_code, unsigned long payload)
748 kvm_multiple_exception(vcpu, nr, true, error_code,
749 true, payload, false);
752 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
755 kvm_inject_gp(vcpu, 0);
757 return kvm_skip_emulated_instruction(vcpu);
761 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
763 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
766 kvm_inject_gp(vcpu, 0);
770 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
771 EMULTYPE_COMPLETE_USER_EXIT);
774 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
776 ++vcpu->stat.pf_guest;
779 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
780 * whether or not L1 wants to intercept "regular" #PF.
782 if (is_guest_mode(vcpu) && fault->async_page_fault)
783 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
784 true, fault->error_code,
785 true, fault->address);
787 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
790 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
792 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
793 struct x86_exception *fault)
795 struct kvm_mmu *fault_mmu;
796 WARN_ON_ONCE(fault->vector != PF_VECTOR);
798 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
802 * Invalidate the TLB entry for the faulting address, if it exists,
803 * else the access will fault indefinitely (and to emulate hardware).
805 if ((fault->error_code & PFERR_PRESENT_MASK) &&
806 !(fault->error_code & PFERR_RSVD_MASK))
807 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
808 fault_mmu->root.hpa);
810 fault_mmu->inject_page_fault(vcpu, fault);
812 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
814 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
816 atomic_inc(&vcpu->arch.nmi_queued);
817 kvm_make_request(KVM_REQ_NMI, vcpu);
819 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
821 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
823 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
825 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
827 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
829 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
831 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
834 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
835 * a #GP and return false.
837 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
839 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
841 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
844 EXPORT_SYMBOL_GPL(kvm_require_cpl);
846 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
848 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
851 kvm_queue_exception(vcpu, UD_VECTOR);
854 EXPORT_SYMBOL_GPL(kvm_require_dr);
856 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
858 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
862 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
864 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
866 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
867 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
871 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
874 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
877 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
878 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
879 if (real_gpa == INVALID_GPA)
882 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
883 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
884 cr3 & GENMASK(11, 5), sizeof(pdpte));
888 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
889 if ((pdpte[i] & PT_PRESENT_MASK) &&
890 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
896 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
897 * Shadow page roots need to be reconstructed instead.
899 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
900 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
902 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
903 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
904 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
905 vcpu->arch.pdptrs_from_userspace = false;
909 EXPORT_SYMBOL_GPL(load_pdptrs);
911 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
913 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
914 kvm_clear_async_pf_completion_queue(vcpu);
915 kvm_async_pf_hash_reset(vcpu);
918 * Clearing CR0.PG is defined to flush the TLB from the guest's
921 if (!(cr0 & X86_CR0_PG))
922 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
925 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
926 kvm_mmu_reset_context(vcpu);
928 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
929 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
930 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
931 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
933 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
935 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
937 unsigned long old_cr0 = kvm_read_cr0(vcpu);
942 if (cr0 & 0xffffffff00000000UL)
946 cr0 &= ~CR0_RESERVED_BITS;
948 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
951 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
955 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
956 (cr0 & X86_CR0_PG)) {
961 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
966 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
967 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
968 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
971 if (!(cr0 & X86_CR0_PG) &&
972 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
975 static_call(kvm_x86_set_cr0)(vcpu, cr0);
977 kvm_post_set_cr0(vcpu, old_cr0, cr0);
981 EXPORT_SYMBOL_GPL(kvm_set_cr0);
983 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
985 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
987 EXPORT_SYMBOL_GPL(kvm_lmsw);
989 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
991 if (vcpu->arch.guest_state_protected)
994 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
996 if (vcpu->arch.xcr0 != host_xcr0)
997 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
999 if (vcpu->arch.xsaves_enabled &&
1000 vcpu->arch.ia32_xss != host_xss)
1001 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1004 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1005 if (static_cpu_has(X86_FEATURE_PKU) &&
1006 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1007 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1008 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
1009 write_pkru(vcpu->arch.pkru);
1010 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1012 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1014 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1016 if (vcpu->arch.guest_state_protected)
1019 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1020 if (static_cpu_has(X86_FEATURE_PKU) &&
1021 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1022 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
1023 vcpu->arch.pkru = rdpkru();
1024 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1025 write_pkru(vcpu->arch.host_pkru);
1027 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1029 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
1031 if (vcpu->arch.xcr0 != host_xcr0)
1032 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1034 if (vcpu->arch.xsaves_enabled &&
1035 vcpu->arch.ia32_xss != host_xss)
1036 wrmsrl(MSR_IA32_XSS, host_xss);
1040 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1042 #ifdef CONFIG_X86_64
1043 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1045 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1049 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1052 u64 old_xcr0 = vcpu->arch.xcr0;
1055 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1056 if (index != XCR_XFEATURE_ENABLED_MASK)
1058 if (!(xcr0 & XFEATURE_MASK_FP))
1060 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1064 * Do not allow the guest to set bits that we do not support
1065 * saving. However, xcr0 bit 0 is always set, even if the
1066 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1068 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1069 if (xcr0 & ~valid_bits)
1072 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1073 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1076 if (xcr0 & XFEATURE_MASK_AVX512) {
1077 if (!(xcr0 & XFEATURE_MASK_YMM))
1079 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1083 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1084 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1087 vcpu->arch.xcr0 = xcr0;
1089 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1090 kvm_update_cpuid_runtime(vcpu);
1094 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1096 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1097 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1098 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1099 kvm_inject_gp(vcpu, 0);
1103 return kvm_skip_emulated_instruction(vcpu);
1105 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1107 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1109 if (cr4 & cr4_reserved_bits)
1112 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1117 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1119 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1121 return __kvm_is_valid_cr4(vcpu, cr4) &&
1122 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1125 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1127 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1128 kvm_mmu_reset_context(vcpu);
1131 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1132 * according to the SDM; however, stale prev_roots could be reused
1133 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1134 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1135 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1139 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1140 kvm_mmu_unload(vcpu);
1143 * The TLB has to be flushed for all PCIDs if any of the following
1144 * (architecturally required) changes happen:
1145 * - CR4.PCIDE is changed from 1 to 0
1146 * - CR4.PGE is toggled
1148 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1150 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1151 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1152 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1155 * The TLB has to be flushed for the current PCID if any of the
1156 * following (architecturally required) changes happen:
1157 * - CR4.SMEP is changed from 0 to 1
1158 * - CR4.PAE is toggled
1160 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1161 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1162 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1165 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1167 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1169 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1171 if (!kvm_is_valid_cr4(vcpu, cr4))
1174 if (is_long_mode(vcpu)) {
1175 if (!(cr4 & X86_CR4_PAE))
1177 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1179 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1180 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1181 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1184 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1185 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1188 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1189 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1193 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1195 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1199 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1201 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1203 struct kvm_mmu *mmu = vcpu->arch.mmu;
1204 unsigned long roots_to_free = 0;
1208 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1209 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1210 * also via the emulator. KVM's TDP page tables are not in the scope of
1211 * the invalidation, but the guest's TLB entries need to be flushed as
1212 * the CPU may have cached entries in its TLB for the target PCID.
1214 if (unlikely(tdp_enabled)) {
1215 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1220 * If neither the current CR3 nor any of the prev_roots use the given
1221 * PCID, then nothing needs to be done here because a resync will
1222 * happen anyway before switching to any other CR3.
1224 if (kvm_get_active_pcid(vcpu) == pcid) {
1225 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1226 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1230 * If PCID is disabled, there is no need to free prev_roots even if the
1231 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1234 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1237 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1238 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1239 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1241 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1244 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1246 bool skip_tlb_flush = false;
1247 unsigned long pcid = 0;
1248 #ifdef CONFIG_X86_64
1249 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1252 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1253 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1254 pcid = cr3 & X86_CR3_PCID_MASK;
1258 /* PDPTRs are always reloaded for PAE paging. */
1259 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1260 goto handle_tlb_flush;
1263 * Do not condition the GPA check on long mode, this helper is used to
1264 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1265 * the current vCPU mode is accurate.
1267 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1270 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1273 if (cr3 != kvm_read_cr3(vcpu))
1274 kvm_mmu_new_pgd(vcpu, cr3);
1276 vcpu->arch.cr3 = cr3;
1277 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1278 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1282 * A load of CR3 that flushes the TLB flushes only the current PCID,
1283 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1284 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1285 * and it's impossible to use a non-zero PCID when PCID is disabled,
1286 * i.e. only PCID=0 can be relevant.
1288 if (!skip_tlb_flush)
1289 kvm_invalidate_pcid(vcpu, pcid);
1293 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1295 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1297 if (cr8 & CR8_RESERVED_BITS)
1299 if (lapic_in_kernel(vcpu))
1300 kvm_lapic_set_tpr(vcpu, cr8);
1302 vcpu->arch.cr8 = cr8;
1305 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1307 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1309 if (lapic_in_kernel(vcpu))
1310 return kvm_lapic_get_cr8(vcpu);
1312 return vcpu->arch.cr8;
1314 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1316 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1320 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1321 for (i = 0; i < KVM_NR_DB_REGS; i++)
1322 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1326 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1330 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1331 dr7 = vcpu->arch.guest_debug_dr7;
1333 dr7 = vcpu->arch.dr7;
1334 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1335 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1336 if (dr7 & DR7_BP_EN_MASK)
1337 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1339 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1341 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1343 u64 fixed = DR6_FIXED_1;
1345 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1348 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1349 fixed |= DR6_BUS_LOCK;
1353 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1355 size_t size = ARRAY_SIZE(vcpu->arch.db);
1359 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1360 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1361 vcpu->arch.eff_db[dr] = val;
1365 if (!kvm_dr6_valid(val))
1367 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1371 if (!kvm_dr7_valid(val))
1373 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1374 kvm_update_dr7(vcpu);
1380 EXPORT_SYMBOL_GPL(kvm_set_dr);
1382 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1384 size_t size = ARRAY_SIZE(vcpu->arch.db);
1388 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1392 *val = vcpu->arch.dr6;
1396 *val = vcpu->arch.dr7;
1400 EXPORT_SYMBOL_GPL(kvm_get_dr);
1402 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1404 u32 ecx = kvm_rcx_read(vcpu);
1407 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1408 kvm_inject_gp(vcpu, 0);
1412 kvm_rax_write(vcpu, (u32)data);
1413 kvm_rdx_write(vcpu, data >> 32);
1414 return kvm_skip_emulated_instruction(vcpu);
1416 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1419 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1420 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1422 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1423 * extract the supported MSRs from the related const lists.
1424 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1425 * capabilities of the host cpu. This capabilities test skips MSRs that are
1426 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1427 * may depend on host virtualization features rather than host cpu features.
1430 static const u32 msrs_to_save_all[] = {
1431 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1433 #ifdef CONFIG_X86_64
1434 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1436 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1437 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1439 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1440 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1441 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1442 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1443 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1444 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1445 MSR_IA32_UMWAIT_CONTROL,
1447 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1448 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1449 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1450 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1451 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1453 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1454 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1455 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1456 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1457 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1458 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1459 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1460 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1461 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1463 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1464 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1466 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1467 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1468 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1469 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1470 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1472 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1475 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1476 static unsigned num_msrs_to_save;
1478 static const u32 emulated_msrs_all[] = {
1479 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1480 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1481 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1482 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1483 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1484 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1485 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1487 HV_X64_MSR_VP_INDEX,
1488 HV_X64_MSR_VP_RUNTIME,
1489 HV_X64_MSR_SCONTROL,
1490 HV_X64_MSR_STIMER0_CONFIG,
1491 HV_X64_MSR_VP_ASSIST_PAGE,
1492 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1493 HV_X64_MSR_TSC_EMULATION_STATUS,
1494 HV_X64_MSR_SYNDBG_OPTIONS,
1495 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1496 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1497 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1499 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1500 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1502 MSR_IA32_TSC_ADJUST,
1503 MSR_IA32_TSC_DEADLINE,
1504 MSR_IA32_ARCH_CAPABILITIES,
1505 MSR_IA32_PERF_CAPABILITIES,
1506 MSR_IA32_MISC_ENABLE,
1507 MSR_IA32_MCG_STATUS,
1509 MSR_IA32_MCG_EXT_CTL,
1513 MSR_MISC_FEATURES_ENABLES,
1514 MSR_AMD64_VIRT_SPEC_CTRL,
1515 MSR_AMD64_TSC_RATIO,
1520 * The following list leaves out MSRs whose values are determined
1521 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1522 * We always support the "true" VMX control MSRs, even if the host
1523 * processor does not, so I am putting these registers here rather
1524 * than in msrs_to_save_all.
1527 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1528 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1529 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1530 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1532 MSR_IA32_VMX_CR0_FIXED0,
1533 MSR_IA32_VMX_CR4_FIXED0,
1534 MSR_IA32_VMX_VMCS_ENUM,
1535 MSR_IA32_VMX_PROCBASED_CTLS2,
1536 MSR_IA32_VMX_EPT_VPID_CAP,
1537 MSR_IA32_VMX_VMFUNC,
1540 MSR_KVM_POLL_CONTROL,
1543 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1544 static unsigned num_emulated_msrs;
1547 * List of msr numbers which are used to expose MSR-based features that
1548 * can be used by a hypervisor to validate requested CPU features.
1550 static const u32 msr_based_features_all[] = {
1552 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1553 MSR_IA32_VMX_PINBASED_CTLS,
1554 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1555 MSR_IA32_VMX_PROCBASED_CTLS,
1556 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1557 MSR_IA32_VMX_EXIT_CTLS,
1558 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1559 MSR_IA32_VMX_ENTRY_CTLS,
1561 MSR_IA32_VMX_CR0_FIXED0,
1562 MSR_IA32_VMX_CR0_FIXED1,
1563 MSR_IA32_VMX_CR4_FIXED0,
1564 MSR_IA32_VMX_CR4_FIXED1,
1565 MSR_IA32_VMX_VMCS_ENUM,
1566 MSR_IA32_VMX_PROCBASED_CTLS2,
1567 MSR_IA32_VMX_EPT_VPID_CAP,
1568 MSR_IA32_VMX_VMFUNC,
1572 MSR_IA32_ARCH_CAPABILITIES,
1573 MSR_IA32_PERF_CAPABILITIES,
1576 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1577 static unsigned int num_msr_based_features;
1580 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1581 * does not yet virtualize. These include:
1582 * 10 - MISC_PACKAGE_CTRLS
1583 * 11 - ENERGY_FILTERING_CTL
1585 * 18 - FB_CLEAR_CTRL
1586 * 21 - XAPIC_DISABLE_STATUS
1587 * 23 - OVERCLOCKING_STATUS
1590 #define KVM_SUPPORTED_ARCH_CAP \
1591 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1592 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1593 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1594 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1595 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO)
1597 static u64 kvm_get_arch_capabilities(void)
1601 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1602 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1603 data &= KVM_SUPPORTED_ARCH_CAP;
1607 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1608 * the nested hypervisor runs with NX huge pages. If it is not,
1609 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1610 * L1 guests, so it need not worry about its own (L2) guests.
1612 data |= ARCH_CAP_PSCHANGE_MC_NO;
1615 * If we're doing cache flushes (either "always" or "cond")
1616 * we will do one whenever the guest does a vmlaunch/vmresume.
1617 * If an outer hypervisor is doing the cache flush for us
1618 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1619 * capability to the guest too, and if EPT is disabled we're not
1620 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1621 * require a nested hypervisor to do a flush of its own.
1623 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1624 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1626 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1627 data |= ARCH_CAP_RDCL_NO;
1628 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1629 data |= ARCH_CAP_SSB_NO;
1630 if (!boot_cpu_has_bug(X86_BUG_MDS))
1631 data |= ARCH_CAP_MDS_NO;
1633 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1635 * If RTM=0 because the kernel has disabled TSX, the host might
1636 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1637 * and therefore knows that there cannot be TAA) but keep
1638 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1639 * and we want to allow migrating those guests to tsx=off hosts.
1641 data &= ~ARCH_CAP_TAA_NO;
1642 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1643 data |= ARCH_CAP_TAA_NO;
1646 * Nothing to do here; we emulate TSX_CTRL if present on the
1647 * host so the guest can choose between disabling TSX or
1648 * using VERW to clear CPU buffers.
1655 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1657 switch (msr->index) {
1658 case MSR_IA32_ARCH_CAPABILITIES:
1659 msr->data = kvm_get_arch_capabilities();
1661 case MSR_IA32_UCODE_REV:
1662 rdmsrl_safe(msr->index, &msr->data);
1665 return static_call(kvm_x86_get_msr_feature)(msr);
1670 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1672 struct kvm_msr_entry msr;
1676 r = kvm_get_msr_feature(&msr);
1678 if (r == KVM_MSR_RET_INVALID) {
1679 /* Unconditionally clear the output for simplicity */
1681 if (kvm_msr_ignored_check(index, 0, false))
1693 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1695 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1698 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1701 if (efer & (EFER_LME | EFER_LMA) &&
1702 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1705 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1711 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1713 if (efer & efer_reserved_bits)
1716 return __kvm_valid_efer(vcpu, efer);
1718 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1720 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1722 u64 old_efer = vcpu->arch.efer;
1723 u64 efer = msr_info->data;
1726 if (efer & efer_reserved_bits)
1729 if (!msr_info->host_initiated) {
1730 if (!__kvm_valid_efer(vcpu, efer))
1733 if (is_paging(vcpu) &&
1734 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1739 efer |= vcpu->arch.efer & EFER_LMA;
1741 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1747 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1748 kvm_mmu_reset_context(vcpu);
1753 void kvm_enable_efer_bits(u64 mask)
1755 efer_reserved_bits &= ~mask;
1757 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1759 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1761 struct kvm_x86_msr_filter *msr_filter;
1762 struct msr_bitmap_range *ranges;
1763 struct kvm *kvm = vcpu->kvm;
1768 /* x2APIC MSRs do not support filtering. */
1769 if (index >= 0x800 && index <= 0x8ff)
1772 idx = srcu_read_lock(&kvm->srcu);
1774 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1780 allowed = msr_filter->default_allow;
1781 ranges = msr_filter->ranges;
1783 for (i = 0; i < msr_filter->count; i++) {
1784 u32 start = ranges[i].base;
1785 u32 end = start + ranges[i].nmsrs;
1786 u32 flags = ranges[i].flags;
1787 unsigned long *bitmap = ranges[i].bitmap;
1789 if ((index >= start) && (index < end) && (flags & type)) {
1790 allowed = !!test_bit(index - start, bitmap);
1796 srcu_read_unlock(&kvm->srcu, idx);
1800 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1803 * Write @data into the MSR specified by @index. Select MSR specific fault
1804 * checks are bypassed if @host_initiated is %true.
1805 * Returns 0 on success, non-0 otherwise.
1806 * Assumes vcpu_load() was already called.
1808 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1809 bool host_initiated)
1811 struct msr_data msr;
1816 case MSR_KERNEL_GS_BASE:
1819 if (is_noncanonical_address(data, vcpu))
1822 case MSR_IA32_SYSENTER_EIP:
1823 case MSR_IA32_SYSENTER_ESP:
1825 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1826 * non-canonical address is written on Intel but not on
1827 * AMD (which ignores the top 32-bits, because it does
1828 * not implement 64-bit SYSENTER).
1830 * 64-bit code should hence be able to write a non-canonical
1831 * value on AMD. Making the address canonical ensures that
1832 * vmentry does not fail on Intel after writing a non-canonical
1833 * value, and that something deterministic happens if the guest
1834 * invokes 64-bit SYSENTER.
1836 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1839 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1842 if (!host_initiated &&
1843 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1844 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1848 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1849 * incomplete and conflicting architectural behavior. Current
1850 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1851 * reserved and always read as zeros. Enforce Intel's reserved
1852 * bits check if and only if the guest CPU is Intel, and clear
1853 * the bits in all other cases. This ensures cross-vendor
1854 * migration will provide consistent behavior for the guest.
1856 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1865 msr.host_initiated = host_initiated;
1867 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1870 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1871 u32 index, u64 data, bool host_initiated)
1873 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1875 if (ret == KVM_MSR_RET_INVALID)
1876 if (kvm_msr_ignored_check(index, data, true))
1883 * Read the MSR specified by @index into @data. Select MSR specific fault
1884 * checks are bypassed if @host_initiated is %true.
1885 * Returns 0 on success, non-0 otherwise.
1886 * Assumes vcpu_load() was already called.
1888 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1889 bool host_initiated)
1891 struct msr_data msr;
1896 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1899 if (!host_initiated &&
1900 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1901 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1907 msr.host_initiated = host_initiated;
1909 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1915 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1916 u32 index, u64 *data, bool host_initiated)
1918 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1920 if (ret == KVM_MSR_RET_INVALID) {
1921 /* Unconditionally clear *data for simplicity */
1923 if (kvm_msr_ignored_check(index, 0, false))
1930 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1932 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1933 return KVM_MSR_RET_FILTERED;
1934 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1937 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1939 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1940 return KVM_MSR_RET_FILTERED;
1941 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1944 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1946 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1948 EXPORT_SYMBOL_GPL(kvm_get_msr);
1950 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1952 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1954 EXPORT_SYMBOL_GPL(kvm_set_msr);
1956 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1958 if (!vcpu->run->msr.error) {
1959 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1960 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1964 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1966 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1969 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1971 complete_userspace_rdmsr(vcpu);
1972 return complete_emulated_msr_access(vcpu);
1975 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1977 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1980 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1982 complete_userspace_rdmsr(vcpu);
1983 return complete_fast_msr_access(vcpu);
1986 static u64 kvm_msr_reason(int r)
1989 case KVM_MSR_RET_INVALID:
1990 return KVM_MSR_EXIT_REASON_UNKNOWN;
1991 case KVM_MSR_RET_FILTERED:
1992 return KVM_MSR_EXIT_REASON_FILTER;
1994 return KVM_MSR_EXIT_REASON_INVAL;
1998 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1999 u32 exit_reason, u64 data,
2000 int (*completion)(struct kvm_vcpu *vcpu),
2003 u64 msr_reason = kvm_msr_reason(r);
2005 /* Check if the user wanted to know about this MSR fault */
2006 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2009 vcpu->run->exit_reason = exit_reason;
2010 vcpu->run->msr.error = 0;
2011 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2012 vcpu->run->msr.reason = msr_reason;
2013 vcpu->run->msr.index = index;
2014 vcpu->run->msr.data = data;
2015 vcpu->arch.complete_userspace_io = completion;
2020 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2022 u32 ecx = kvm_rcx_read(vcpu);
2026 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2029 trace_kvm_msr_read(ecx, data);
2031 kvm_rax_write(vcpu, data & -1u);
2032 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2034 /* MSR read failed? See if we should ask user space */
2035 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2036 complete_fast_rdmsr, r))
2038 trace_kvm_msr_read_ex(ecx);
2041 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2043 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2045 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2047 u32 ecx = kvm_rcx_read(vcpu);
2048 u64 data = kvm_read_edx_eax(vcpu);
2051 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2054 trace_kvm_msr_write(ecx, data);
2056 /* MSR write failed? See if we should ask user space */
2057 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2058 complete_fast_msr_access, r))
2060 /* Signal all other negative errors to userspace */
2063 trace_kvm_msr_write_ex(ecx, data);
2066 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2068 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2070 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2072 return kvm_skip_emulated_instruction(vcpu);
2074 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
2076 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2078 /* Treat an INVD instruction as a NOP and just skip it. */
2079 return kvm_emulate_as_nop(vcpu);
2081 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2083 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2085 kvm_queue_exception(vcpu, UD_VECTOR);
2088 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2091 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2093 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2094 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2095 return kvm_handle_invalid_op(vcpu);
2097 pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn);
2098 return kvm_emulate_as_nop(vcpu);
2100 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2102 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2104 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2106 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2108 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2110 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2112 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2114 xfer_to_guest_mode_prepare();
2115 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2116 xfer_to_guest_mode_work_pending();
2120 * The fast path for frequent and performance sensitive wrmsr emulation,
2121 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2122 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2123 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2124 * other cases which must be called after interrupts are enabled on the host.
2126 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2128 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2131 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2132 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2133 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2134 ((u32)(data >> 32) != X2APIC_BROADCAST))
2135 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2140 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2142 if (!kvm_can_use_hv_timer(vcpu))
2145 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2149 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2151 u32 msr = kvm_rcx_read(vcpu);
2153 fastpath_t ret = EXIT_FASTPATH_NONE;
2156 case APIC_BASE_MSR + (APIC_ICR >> 4):
2157 data = kvm_read_edx_eax(vcpu);
2158 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2159 kvm_skip_emulated_instruction(vcpu);
2160 ret = EXIT_FASTPATH_EXIT_HANDLED;
2163 case MSR_IA32_TSC_DEADLINE:
2164 data = kvm_read_edx_eax(vcpu);
2165 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2166 kvm_skip_emulated_instruction(vcpu);
2167 ret = EXIT_FASTPATH_REENTER_GUEST;
2174 if (ret != EXIT_FASTPATH_NONE)
2175 trace_kvm_msr_write(msr, data);
2179 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2182 * Adapt set_msr() to msr_io()'s calling convention
2184 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2186 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2189 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2191 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2194 #ifdef CONFIG_X86_64
2195 struct pvclock_clock {
2205 struct pvclock_gtod_data {
2208 struct pvclock_clock clock; /* extract of a clocksource struct */
2209 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2215 static struct pvclock_gtod_data pvclock_gtod_data;
2217 static void update_pvclock_gtod(struct timekeeper *tk)
2219 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2221 write_seqcount_begin(&vdata->seq);
2223 /* copy pvclock gtod data */
2224 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2225 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2226 vdata->clock.mask = tk->tkr_mono.mask;
2227 vdata->clock.mult = tk->tkr_mono.mult;
2228 vdata->clock.shift = tk->tkr_mono.shift;
2229 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2230 vdata->clock.offset = tk->tkr_mono.base;
2232 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2233 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2234 vdata->raw_clock.mask = tk->tkr_raw.mask;
2235 vdata->raw_clock.mult = tk->tkr_raw.mult;
2236 vdata->raw_clock.shift = tk->tkr_raw.shift;
2237 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2238 vdata->raw_clock.offset = tk->tkr_raw.base;
2240 vdata->wall_time_sec = tk->xtime_sec;
2242 vdata->offs_boot = tk->offs_boot;
2244 write_seqcount_end(&vdata->seq);
2247 static s64 get_kvmclock_base_ns(void)
2249 /* Count up from boot time, but with the frequency of the raw clock. */
2250 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2253 static s64 get_kvmclock_base_ns(void)
2255 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2256 return ktime_get_boottime_ns();
2260 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2264 struct pvclock_wall_clock wc;
2271 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2276 ++version; /* first time write, random junk */
2280 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2284 * The guest calculates current wall clock time by adding
2285 * system time (updated by kvm_guest_time_update below) to the
2286 * wall clock specified here. We do the reverse here.
2288 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2290 wc.nsec = do_div(wall_nsec, 1000000000);
2291 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2292 wc.version = version;
2294 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2297 wc_sec_hi = wall_nsec >> 32;
2298 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2299 &wc_sec_hi, sizeof(wc_sec_hi));
2303 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2306 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2307 bool old_msr, bool host_initiated)
2309 struct kvm_arch *ka = &vcpu->kvm->arch;
2311 if (vcpu->vcpu_id == 0 && !host_initiated) {
2312 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2313 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2315 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2318 vcpu->arch.time = system_time;
2319 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2321 /* we verify if the enable bit is set... */
2322 if (system_time & 1) {
2323 kvm_gpc_activate(vcpu->kvm, &vcpu->arch.pv_time, vcpu,
2324 KVM_HOST_USES_PFN, system_time & ~1ULL,
2325 sizeof(struct pvclock_vcpu_time_info));
2327 kvm_gpc_deactivate(vcpu->kvm, &vcpu->arch.pv_time);
2333 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2335 do_shl32_div32(dividend, divisor);
2339 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2340 s8 *pshift, u32 *pmultiplier)
2348 scaled64 = scaled_hz;
2349 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2354 tps32 = (uint32_t)tps64;
2355 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2356 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2364 *pmultiplier = div_frac(scaled64, tps32);
2367 #ifdef CONFIG_X86_64
2368 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2371 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2372 static unsigned long max_tsc_khz;
2374 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2376 u64 v = (u64)khz * (1000000 + ppm);
2381 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2383 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2387 /* Guest TSC same frequency as host TSC? */
2389 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2393 /* TSC scaling supported? */
2394 if (!kvm_caps.has_tsc_control) {
2395 if (user_tsc_khz > tsc_khz) {
2396 vcpu->arch.tsc_catchup = 1;
2397 vcpu->arch.tsc_always_catchup = 1;
2400 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2405 /* TSC scaling required - calculate ratio */
2406 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2407 user_tsc_khz, tsc_khz);
2409 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2410 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2415 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2419 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2421 u32 thresh_lo, thresh_hi;
2422 int use_scaling = 0;
2424 /* tsc_khz can be zero if TSC calibration fails */
2425 if (user_tsc_khz == 0) {
2426 /* set tsc_scaling_ratio to a safe value */
2427 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2431 /* Compute a scale to convert nanoseconds in TSC cycles */
2432 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2433 &vcpu->arch.virtual_tsc_shift,
2434 &vcpu->arch.virtual_tsc_mult);
2435 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2438 * Compute the variation in TSC rate which is acceptable
2439 * within the range of tolerance and decide if the
2440 * rate being applied is within that bounds of the hardware
2441 * rate. If so, no scaling or compensation need be done.
2443 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2444 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2445 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2446 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2449 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2452 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2454 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2455 vcpu->arch.virtual_tsc_mult,
2456 vcpu->arch.virtual_tsc_shift);
2457 tsc += vcpu->arch.this_tsc_write;
2461 #ifdef CONFIG_X86_64
2462 static inline int gtod_is_based_on_tsc(int mode)
2464 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2468 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2470 #ifdef CONFIG_X86_64
2472 struct kvm_arch *ka = &vcpu->kvm->arch;
2473 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2475 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2476 atomic_read(&vcpu->kvm->online_vcpus));
2479 * Once the masterclock is enabled, always perform request in
2480 * order to update it.
2482 * In order to enable masterclock, the host clocksource must be TSC
2483 * and the vcpus need to have matched TSCs. When that happens,
2484 * perform request to enable masterclock.
2486 if (ka->use_master_clock ||
2487 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2488 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2490 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2491 atomic_read(&vcpu->kvm->online_vcpus),
2492 ka->use_master_clock, gtod->clock.vclock_mode);
2497 * Multiply tsc by a fixed point number represented by ratio.
2499 * The most significant 64-N bits (mult) of ratio represent the
2500 * integral part of the fixed point number; the remaining N bits
2501 * (frac) represent the fractional part, ie. ratio represents a fixed
2502 * point number (mult + frac * 2^(-N)).
2504 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2506 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2508 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2511 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2515 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2516 _tsc = __scale_tsc(ratio, tsc);
2520 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2522 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2526 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2528 return target_tsc - tsc;
2531 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2533 return vcpu->arch.l1_tsc_offset +
2534 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2536 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2538 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2542 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2543 nested_offset = l1_offset;
2545 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2546 kvm_caps.tsc_scaling_ratio_frac_bits);
2548 nested_offset += l2_offset;
2549 return nested_offset;
2551 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2553 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2555 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2556 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2557 kvm_caps.tsc_scaling_ratio_frac_bits);
2559 return l1_multiplier;
2561 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2563 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2565 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2566 vcpu->arch.l1_tsc_offset,
2569 vcpu->arch.l1_tsc_offset = l1_offset;
2572 * If we are here because L1 chose not to trap WRMSR to TSC then
2573 * according to the spec this should set L1's TSC (as opposed to
2574 * setting L1's offset for L2).
2576 if (is_guest_mode(vcpu))
2577 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2579 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2580 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2582 vcpu->arch.tsc_offset = l1_offset;
2584 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2587 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2589 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2591 /* Userspace is changing the multiplier while L2 is active */
2592 if (is_guest_mode(vcpu))
2593 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2595 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2597 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2599 if (kvm_caps.has_tsc_control)
2600 static_call(kvm_x86_write_tsc_multiplier)(
2601 vcpu, vcpu->arch.tsc_scaling_ratio);
2604 static inline bool kvm_check_tsc_unstable(void)
2606 #ifdef CONFIG_X86_64
2608 * TSC is marked unstable when we're running on Hyper-V,
2609 * 'TSC page' clocksource is good.
2611 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2614 return check_tsc_unstable();
2618 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2619 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2622 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2623 u64 ns, bool matched)
2625 struct kvm *kvm = vcpu->kvm;
2627 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2630 * We also track th most recent recorded KHZ, write and time to
2631 * allow the matching interval to be extended at each write.
2633 kvm->arch.last_tsc_nsec = ns;
2634 kvm->arch.last_tsc_write = tsc;
2635 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2636 kvm->arch.last_tsc_offset = offset;
2638 vcpu->arch.last_guest_tsc = tsc;
2640 kvm_vcpu_write_tsc_offset(vcpu, offset);
2644 * We split periods of matched TSC writes into generations.
2645 * For each generation, we track the original measured
2646 * nanosecond time, offset, and write, so if TSCs are in
2647 * sync, we can match exact offset, and if not, we can match
2648 * exact software computation in compute_guest_tsc()
2650 * These values are tracked in kvm->arch.cur_xxx variables.
2652 kvm->arch.cur_tsc_generation++;
2653 kvm->arch.cur_tsc_nsec = ns;
2654 kvm->arch.cur_tsc_write = tsc;
2655 kvm->arch.cur_tsc_offset = offset;
2656 kvm->arch.nr_vcpus_matched_tsc = 0;
2657 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2658 kvm->arch.nr_vcpus_matched_tsc++;
2661 /* Keep track of which generation this VCPU has synchronized to */
2662 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2663 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2664 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2666 kvm_track_tsc_matching(vcpu);
2669 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2671 struct kvm *kvm = vcpu->kvm;
2672 u64 offset, ns, elapsed;
2673 unsigned long flags;
2674 bool matched = false;
2675 bool synchronizing = false;
2677 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2678 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2679 ns = get_kvmclock_base_ns();
2680 elapsed = ns - kvm->arch.last_tsc_nsec;
2682 if (vcpu->arch.virtual_tsc_khz) {
2685 * detection of vcpu initialization -- need to sync
2686 * with other vCPUs. This particularly helps to keep
2687 * kvm_clock stable after CPU hotplug
2689 synchronizing = true;
2691 u64 tsc_exp = kvm->arch.last_tsc_write +
2692 nsec_to_cycles(vcpu, elapsed);
2693 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2695 * Special case: TSC write with a small delta (1 second)
2696 * of virtual cycle time against real time is
2697 * interpreted as an attempt to synchronize the CPU.
2699 synchronizing = data < tsc_exp + tsc_hz &&
2700 data + tsc_hz > tsc_exp;
2705 * For a reliable TSC, we can match TSC offsets, and for an unstable
2706 * TSC, we add elapsed time in this computation. We could let the
2707 * compensation code attempt to catch up if we fall behind, but
2708 * it's better to try to match offsets from the beginning.
2710 if (synchronizing &&
2711 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2712 if (!kvm_check_tsc_unstable()) {
2713 offset = kvm->arch.cur_tsc_offset;
2715 u64 delta = nsec_to_cycles(vcpu, elapsed);
2717 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2722 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2723 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2726 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2729 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2730 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2733 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2735 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2736 WARN_ON(adjustment < 0);
2737 adjustment = kvm_scale_tsc((u64) adjustment,
2738 vcpu->arch.l1_tsc_scaling_ratio);
2739 adjust_tsc_offset_guest(vcpu, adjustment);
2742 #ifdef CONFIG_X86_64
2744 static u64 read_tsc(void)
2746 u64 ret = (u64)rdtsc_ordered();
2747 u64 last = pvclock_gtod_data.clock.cycle_last;
2749 if (likely(ret >= last))
2753 * GCC likes to generate cmov here, but this branch is extremely
2754 * predictable (it's just a function of time and the likely is
2755 * very likely) and there's a data dependence, so force GCC
2756 * to generate a branch instead. I don't barrier() because
2757 * we don't actually need a barrier, and if this function
2758 * ever gets inlined it will generate worse code.
2764 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2770 switch (clock->vclock_mode) {
2771 case VDSO_CLOCKMODE_HVCLOCK:
2772 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2774 if (tsc_pg_val != U64_MAX) {
2775 /* TSC page valid */
2776 *mode = VDSO_CLOCKMODE_HVCLOCK;
2777 v = (tsc_pg_val - clock->cycle_last) &
2780 /* TSC page invalid */
2781 *mode = VDSO_CLOCKMODE_NONE;
2784 case VDSO_CLOCKMODE_TSC:
2785 *mode = VDSO_CLOCKMODE_TSC;
2786 *tsc_timestamp = read_tsc();
2787 v = (*tsc_timestamp - clock->cycle_last) &
2791 *mode = VDSO_CLOCKMODE_NONE;
2794 if (*mode == VDSO_CLOCKMODE_NONE)
2795 *tsc_timestamp = v = 0;
2797 return v * clock->mult;
2800 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2802 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2808 seq = read_seqcount_begin(>od->seq);
2809 ns = gtod->raw_clock.base_cycles;
2810 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2811 ns >>= gtod->raw_clock.shift;
2812 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2813 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2819 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2821 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2827 seq = read_seqcount_begin(>od->seq);
2828 ts->tv_sec = gtod->wall_time_sec;
2829 ns = gtod->clock.base_cycles;
2830 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2831 ns >>= gtod->clock.shift;
2832 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2834 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2840 /* returns true if host is using TSC based clocksource */
2841 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2843 /* checked again under seqlock below */
2844 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2847 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2851 /* returns true if host is using TSC based clocksource */
2852 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2855 /* checked again under seqlock below */
2856 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2859 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2865 * Assuming a stable TSC across physical CPUS, and a stable TSC
2866 * across virtual CPUs, the following condition is possible.
2867 * Each numbered line represents an event visible to both
2868 * CPUs at the next numbered event.
2870 * "timespecX" represents host monotonic time. "tscX" represents
2873 * VCPU0 on CPU0 | VCPU1 on CPU1
2875 * 1. read timespec0,tsc0
2876 * 2. | timespec1 = timespec0 + N
2878 * 3. transition to guest | transition to guest
2879 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2880 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2881 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2883 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2886 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2888 * - 0 < N - M => M < N
2890 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2891 * always the case (the difference between two distinct xtime instances
2892 * might be smaller then the difference between corresponding TSC reads,
2893 * when updating guest vcpus pvclock areas).
2895 * To avoid that problem, do not allow visibility of distinct
2896 * system_timestamp/tsc_timestamp values simultaneously: use a master
2897 * copy of host monotonic time values. Update that master copy
2900 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2904 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2906 #ifdef CONFIG_X86_64
2907 struct kvm_arch *ka = &kvm->arch;
2909 bool host_tsc_clocksource, vcpus_matched;
2911 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2912 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2913 atomic_read(&kvm->online_vcpus));
2916 * If the host uses TSC clock, then passthrough TSC as stable
2919 host_tsc_clocksource = kvm_get_time_and_clockread(
2920 &ka->master_kernel_ns,
2921 &ka->master_cycle_now);
2923 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2924 && !ka->backwards_tsc_observed
2925 && !ka->boot_vcpu_runs_old_kvmclock;
2927 if (ka->use_master_clock)
2928 atomic_set(&kvm_guest_has_master_clock, 1);
2930 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2931 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2936 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2938 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2941 static void __kvm_start_pvclock_update(struct kvm *kvm)
2943 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2944 write_seqcount_begin(&kvm->arch.pvclock_sc);
2947 static void kvm_start_pvclock_update(struct kvm *kvm)
2949 kvm_make_mclock_inprogress_request(kvm);
2951 /* no guest entries from this point */
2952 __kvm_start_pvclock_update(kvm);
2955 static void kvm_end_pvclock_update(struct kvm *kvm)
2957 struct kvm_arch *ka = &kvm->arch;
2958 struct kvm_vcpu *vcpu;
2961 write_seqcount_end(&ka->pvclock_sc);
2962 raw_spin_unlock_irq(&ka->tsc_write_lock);
2963 kvm_for_each_vcpu(i, vcpu, kvm)
2964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2966 /* guest entries allowed */
2967 kvm_for_each_vcpu(i, vcpu, kvm)
2968 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2971 static void kvm_update_masterclock(struct kvm *kvm)
2973 kvm_hv_request_tsc_page_update(kvm);
2974 kvm_start_pvclock_update(kvm);
2975 pvclock_update_vm_gtod_copy(kvm);
2976 kvm_end_pvclock_update(kvm);
2979 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2980 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2982 struct kvm_arch *ka = &kvm->arch;
2983 struct pvclock_vcpu_time_info hv_clock;
2985 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2989 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2990 #ifdef CONFIG_X86_64
2991 struct timespec64 ts;
2993 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2994 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2995 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2998 data->host_tsc = rdtsc();
3000 data->flags |= KVM_CLOCK_TSC_STABLE;
3001 hv_clock.tsc_timestamp = ka->master_cycle_now;
3002 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3003 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
3004 &hv_clock.tsc_shift,
3005 &hv_clock.tsc_to_system_mul);
3006 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3008 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3014 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3016 struct kvm_arch *ka = &kvm->arch;
3020 seq = read_seqcount_begin(&ka->pvclock_sc);
3021 __get_kvmclock(kvm, data);
3022 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3025 u64 get_kvmclock_ns(struct kvm *kvm)
3027 struct kvm_clock_data data;
3029 get_kvmclock(kvm, &data);
3033 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3034 struct gfn_to_pfn_cache *gpc,
3035 unsigned int offset)
3037 struct kvm_vcpu_arch *vcpu = &v->arch;
3038 struct pvclock_vcpu_time_info *guest_hv_clock;
3039 unsigned long flags;
3041 read_lock_irqsave(&gpc->lock, flags);
3042 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa,
3043 offset + sizeof(*guest_hv_clock))) {
3044 read_unlock_irqrestore(&gpc->lock, flags);
3046 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa,
3047 offset + sizeof(*guest_hv_clock)))
3050 read_lock_irqsave(&gpc->lock, flags);
3053 guest_hv_clock = (void *)(gpc->khva + offset);
3056 * This VCPU is paused, but it's legal for a guest to read another
3057 * VCPU's kvmclock, so we really have to follow the specification where
3058 * it says that version is odd if data is being modified, and even after
3062 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3065 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3066 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3068 if (vcpu->pvclock_set_guest_stopped_request) {
3069 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3070 vcpu->pvclock_set_guest_stopped_request = false;
3073 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3076 guest_hv_clock->version = ++vcpu->hv_clock.version;
3078 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3079 read_unlock_irqrestore(&gpc->lock, flags);
3081 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3084 static int kvm_guest_time_update(struct kvm_vcpu *v)
3086 unsigned long flags, tgt_tsc_khz;
3088 struct kvm_vcpu_arch *vcpu = &v->arch;
3089 struct kvm_arch *ka = &v->kvm->arch;
3091 u64 tsc_timestamp, host_tsc;
3093 bool use_master_clock;
3099 * If the host uses TSC clock, then passthrough TSC as stable
3103 seq = read_seqcount_begin(&ka->pvclock_sc);
3104 use_master_clock = ka->use_master_clock;
3105 if (use_master_clock) {
3106 host_tsc = ka->master_cycle_now;
3107 kernel_ns = ka->master_kernel_ns;
3109 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3111 /* Keep irq disabled to prevent changes to the clock */
3112 local_irq_save(flags);
3113 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3114 if (unlikely(tgt_tsc_khz == 0)) {
3115 local_irq_restore(flags);
3116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3119 if (!use_master_clock) {
3121 kernel_ns = get_kvmclock_base_ns();
3124 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3127 * We may have to catch up the TSC to match elapsed wall clock
3128 * time for two reasons, even if kvmclock is used.
3129 * 1) CPU could have been running below the maximum TSC rate
3130 * 2) Broken TSC compensation resets the base at each VCPU
3131 * entry to avoid unknown leaps of TSC even when running
3132 * again on the same CPU. This may cause apparent elapsed
3133 * time to disappear, and the guest to stand still or run
3136 if (vcpu->tsc_catchup) {
3137 u64 tsc = compute_guest_tsc(v, kernel_ns);
3138 if (tsc > tsc_timestamp) {
3139 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3140 tsc_timestamp = tsc;
3144 local_irq_restore(flags);
3146 /* With all the info we got, fill in the values */
3148 if (kvm_caps.has_tsc_control)
3149 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3150 v->arch.l1_tsc_scaling_ratio);
3152 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3153 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3154 &vcpu->hv_clock.tsc_shift,
3155 &vcpu->hv_clock.tsc_to_system_mul);
3156 vcpu->hw_tsc_khz = tgt_tsc_khz;
3159 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3160 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3161 vcpu->last_guest_tsc = tsc_timestamp;
3163 /* If the host uses TSC clocksource, then it is stable */
3165 if (use_master_clock)
3166 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3168 vcpu->hv_clock.flags = pvclock_flags;
3170 if (vcpu->pv_time.active)
3171 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3172 if (vcpu->xen.vcpu_info_cache.active)
3173 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3174 offsetof(struct compat_vcpu_info, time));
3175 if (vcpu->xen.vcpu_time_info_cache.active)
3176 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3177 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3182 * kvmclock updates which are isolated to a given vcpu, such as
3183 * vcpu->cpu migration, should not allow system_timestamp from
3184 * the rest of the vcpus to remain static. Otherwise ntp frequency
3185 * correction applies to one vcpu's system_timestamp but not
3188 * So in those cases, request a kvmclock update for all vcpus.
3189 * We need to rate-limit these requests though, as they can
3190 * considerably slow guests that have a large number of vcpus.
3191 * The time for a remote vcpu to update its kvmclock is bound
3192 * by the delay we use to rate-limit the updates.
3195 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3197 static void kvmclock_update_fn(struct work_struct *work)
3200 struct delayed_work *dwork = to_delayed_work(work);
3201 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3202 kvmclock_update_work);
3203 struct kvm *kvm = container_of(ka, struct kvm, arch);
3204 struct kvm_vcpu *vcpu;
3206 kvm_for_each_vcpu(i, vcpu, kvm) {
3207 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3208 kvm_vcpu_kick(vcpu);
3212 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3214 struct kvm *kvm = v->kvm;
3216 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3217 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3218 KVMCLOCK_UPDATE_DELAY);
3221 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3223 static void kvmclock_sync_fn(struct work_struct *work)
3225 struct delayed_work *dwork = to_delayed_work(work);
3226 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3227 kvmclock_sync_work);
3228 struct kvm *kvm = container_of(ka, struct kvm, arch);
3230 if (!kvmclock_periodic_sync)
3233 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3234 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3235 KVMCLOCK_SYNC_PERIOD);
3238 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3239 static bool is_mci_control_msr(u32 msr)
3241 return (msr & 3) == 0;
3243 static bool is_mci_status_msr(u32 msr)
3245 return (msr & 3) == 1;
3249 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3251 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3253 /* McStatusWrEn enabled? */
3254 if (guest_cpuid_is_amd_or_hygon(vcpu))
3255 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3260 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3262 u64 mcg_cap = vcpu->arch.mcg_cap;
3263 unsigned bank_num = mcg_cap & 0xff;
3264 u32 msr = msr_info->index;
3265 u64 data = msr_info->data;
3266 u32 offset, last_msr;
3269 case MSR_IA32_MCG_STATUS:
3270 vcpu->arch.mcg_status = data;
3272 case MSR_IA32_MCG_CTL:
3273 if (!(mcg_cap & MCG_CTL_P) &&
3274 (data || !msr_info->host_initiated))
3276 if (data != 0 && data != ~(u64)0)
3278 vcpu->arch.mcg_ctl = data;
3280 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3281 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3285 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3287 /* An attempt to write a 1 to a reserved bit raises #GP */
3288 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3290 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3291 last_msr + 1 - MSR_IA32_MC0_CTL2);
3292 vcpu->arch.mci_ctl2_banks[offset] = data;
3294 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3295 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3300 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3301 * values are architecturally undefined. But, some Linux
3302 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3303 * issue on AMD K8s, allow bit 10 to be clear when setting all
3304 * other bits in order to avoid an uncaught #GP in the guest.
3306 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3307 * single-bit ECC data errors.
3309 if (is_mci_control_msr(msr) &&
3310 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3314 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3315 * AMD-based CPUs allow non-zero values, but if and only if
3316 * HWCR[McStatusWrEn] is set.
3318 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3319 data != 0 && !can_set_mci_status(vcpu))
3322 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3323 last_msr + 1 - MSR_IA32_MC0_CTL);
3324 vcpu->arch.mce_banks[offset] = data;
3332 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3334 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3336 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3339 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3341 gpa_t gpa = data & ~0x3f;
3343 /* Bits 4:5 are reserved, Should be zero */
3347 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3348 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3351 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3352 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3355 if (!lapic_in_kernel(vcpu))
3356 return data ? 1 : 0;
3358 vcpu->arch.apf.msr_en_val = data;
3360 if (!kvm_pv_async_pf_enabled(vcpu)) {
3361 kvm_clear_async_pf_completion_queue(vcpu);
3362 kvm_async_pf_hash_reset(vcpu);
3366 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3370 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3371 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3373 kvm_async_pf_wakeup_all(vcpu);
3378 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3380 /* Bits 8-63 are reserved */
3384 if (!lapic_in_kernel(vcpu))
3387 vcpu->arch.apf.msr_int_val = data;
3389 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3394 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3396 kvm_gpc_deactivate(vcpu->kvm, &vcpu->arch.pv_time);
3397 vcpu->arch.time = 0;
3400 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3402 ++vcpu->stat.tlb_flush;
3403 static_call(kvm_x86_flush_tlb_all)(vcpu);
3406 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3408 ++vcpu->stat.tlb_flush;
3412 * A TLB flush on behalf of the guest is equivalent to
3413 * INVPCID(all), toggling CR4.PGE, etc., which requires
3414 * a forced sync of the shadow page tables. Ensure all the
3415 * roots are synced and the guest TLB in hardware is clean.
3417 kvm_mmu_sync_roots(vcpu);
3418 kvm_mmu_sync_prev_roots(vcpu);
3421 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3425 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3427 ++vcpu->stat.tlb_flush;
3428 static_call(kvm_x86_flush_tlb_current)(vcpu);
3432 * Service "local" TLB flush requests, which are specific to the current MMU
3433 * context. In addition to the generic event handling in vcpu_enter_guest(),
3434 * TLB flushes that are targeted at an MMU context also need to be serviced
3435 * prior before nested VM-Enter/VM-Exit.
3437 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3439 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3440 kvm_vcpu_flush_tlb_current(vcpu);
3442 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3443 kvm_vcpu_flush_tlb_guest(vcpu);
3445 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3447 static void record_steal_time(struct kvm_vcpu *vcpu)
3449 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3450 struct kvm_steal_time __user *st;
3451 struct kvm_memslots *slots;
3452 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3456 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3457 kvm_xen_runstate_set_running(vcpu);
3461 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3464 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3467 slots = kvm_memslots(vcpu->kvm);
3469 if (unlikely(slots->generation != ghc->generation ||
3471 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3472 /* We rely on the fact that it fits in a single page. */
3473 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3475 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3476 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3480 st = (struct kvm_steal_time __user *)ghc->hva;
3482 * Doing a TLB flush here, on the guest's behalf, can avoid
3485 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3486 u8 st_preempted = 0;
3489 if (!user_access_begin(st, sizeof(*st)))
3492 asm volatile("1: xchgb %0, %2\n"
3495 _ASM_EXTABLE_UA(1b, 2b)
3496 : "+q" (st_preempted),
3498 "+m" (st->preempted));
3504 vcpu->arch.st.preempted = 0;
3506 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3507 st_preempted & KVM_VCPU_FLUSH_TLB);
3508 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3509 kvm_vcpu_flush_tlb_guest(vcpu);
3511 if (!user_access_begin(st, sizeof(*st)))
3514 if (!user_access_begin(st, sizeof(*st)))
3517 unsafe_put_user(0, &st->preempted, out);
3518 vcpu->arch.st.preempted = 0;
3521 unsafe_get_user(version, &st->version, out);
3523 version += 1; /* first time write, random junk */
3526 unsafe_put_user(version, &st->version, out);
3530 unsafe_get_user(steal, &st->steal, out);
3531 steal += current->sched_info.run_delay -
3532 vcpu->arch.st.last_steal;
3533 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3534 unsafe_put_user(steal, &st->steal, out);
3537 unsafe_put_user(version, &st->version, out);
3542 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3545 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3548 u32 msr = msr_info->index;
3549 u64 data = msr_info->data;
3551 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3552 return kvm_xen_write_hypercall_page(vcpu, data);
3555 case MSR_AMD64_NB_CFG:
3556 case MSR_IA32_UCODE_WRITE:
3557 case MSR_VM_HSAVE_PA:
3558 case MSR_AMD64_PATCH_LOADER:
3559 case MSR_AMD64_BU_CFG2:
3560 case MSR_AMD64_DC_CFG:
3561 case MSR_F15H_EX_CFG:
3564 case MSR_IA32_UCODE_REV:
3565 if (msr_info->host_initiated)
3566 vcpu->arch.microcode_version = data;
3568 case MSR_IA32_ARCH_CAPABILITIES:
3569 if (!msr_info->host_initiated)
3571 vcpu->arch.arch_capabilities = data;
3573 case MSR_IA32_PERF_CAPABILITIES: {
3574 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3576 if (!msr_info->host_initiated)
3578 if (kvm_get_msr_feature(&msr_ent))
3580 if (data & ~msr_ent.data)
3583 vcpu->arch.perf_capabilities = data;
3584 kvm_pmu_refresh(vcpu);
3588 return set_efer(vcpu, msr_info);
3590 data &= ~(u64)0x40; /* ignore flush filter disable */
3591 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3592 data &= ~(u64)0x8; /* ignore TLB cache disable */
3594 /* Handle McStatusWrEn */
3595 if (data == BIT_ULL(18)) {
3596 vcpu->arch.msr_hwcr = data;
3597 } else if (data != 0) {
3598 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3603 case MSR_FAM10H_MMIO_CONF_BASE:
3605 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3610 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3611 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3612 return kvm_mtrr_set_msr(vcpu, msr, data);
3613 case MSR_IA32_APICBASE:
3614 return kvm_set_apic_base(vcpu, msr_info);
3615 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3616 return kvm_x2apic_msr_write(vcpu, msr, data);
3617 case MSR_IA32_TSC_DEADLINE:
3618 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3620 case MSR_IA32_TSC_ADJUST:
3621 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3622 if (!msr_info->host_initiated) {
3623 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3624 adjust_tsc_offset_guest(vcpu, adj);
3625 /* Before back to guest, tsc_timestamp must be adjusted
3626 * as well, otherwise guest's percpu pvclock time could jump.
3628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3630 vcpu->arch.ia32_tsc_adjust_msr = data;
3633 case MSR_IA32_MISC_ENABLE: {
3634 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3636 if (!msr_info->host_initiated) {
3638 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3641 /* R bits, i.e. writes are ignored, but don't fault. */
3642 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3643 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3646 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3647 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3648 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3650 vcpu->arch.ia32_misc_enable_msr = data;
3651 kvm_update_cpuid_runtime(vcpu);
3653 vcpu->arch.ia32_misc_enable_msr = data;
3657 case MSR_IA32_SMBASE:
3658 if (!msr_info->host_initiated)
3660 vcpu->arch.smbase = data;
3662 case MSR_IA32_POWER_CTL:
3663 vcpu->arch.msr_ia32_power_ctl = data;
3666 if (msr_info->host_initiated) {
3667 kvm_synchronize_tsc(vcpu, data);
3669 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3670 adjust_tsc_offset_guest(vcpu, adj);
3671 vcpu->arch.ia32_tsc_adjust_msr += adj;
3675 if (!msr_info->host_initiated &&
3676 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3679 * KVM supports exposing PT to the guest, but does not support
3680 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3681 * XSAVES/XRSTORS to save/restore PT MSRs.
3683 if (data & ~kvm_caps.supported_xss)
3685 vcpu->arch.ia32_xss = data;
3686 kvm_update_cpuid_runtime(vcpu);
3689 if (!msr_info->host_initiated)
3691 vcpu->arch.smi_count = data;
3693 case MSR_KVM_WALL_CLOCK_NEW:
3694 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3697 vcpu->kvm->arch.wall_clock = data;
3698 kvm_write_wall_clock(vcpu->kvm, data, 0);
3700 case MSR_KVM_WALL_CLOCK:
3701 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3704 vcpu->kvm->arch.wall_clock = data;
3705 kvm_write_wall_clock(vcpu->kvm, data, 0);
3707 case MSR_KVM_SYSTEM_TIME_NEW:
3708 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3711 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3713 case MSR_KVM_SYSTEM_TIME:
3714 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3717 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3719 case MSR_KVM_ASYNC_PF_EN:
3720 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3723 if (kvm_pv_enable_async_pf(vcpu, data))
3726 case MSR_KVM_ASYNC_PF_INT:
3727 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3730 if (kvm_pv_enable_async_pf_int(vcpu, data))
3733 case MSR_KVM_ASYNC_PF_ACK:
3734 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3737 vcpu->arch.apf.pageready_pending = false;
3738 kvm_check_async_pf_completion(vcpu);
3741 case MSR_KVM_STEAL_TIME:
3742 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3745 if (unlikely(!sched_info_on()))
3748 if (data & KVM_STEAL_RESERVED_MASK)
3751 vcpu->arch.st.msr_val = data;
3753 if (!(data & KVM_MSR_ENABLED))
3756 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3759 case MSR_KVM_PV_EOI_EN:
3760 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3763 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3767 case MSR_KVM_POLL_CONTROL:
3768 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3771 /* only enable bit supported */
3772 if (data & (-1ULL << 1))
3775 vcpu->arch.msr_kvm_poll_control = data;
3778 case MSR_IA32_MCG_CTL:
3779 case MSR_IA32_MCG_STATUS:
3780 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3781 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3782 return set_msr_mce(vcpu, msr_info);
3784 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3785 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3788 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3789 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3790 if (kvm_pmu_is_valid_msr(vcpu, msr))
3791 return kvm_pmu_set_msr(vcpu, msr_info);
3793 if (pr || data != 0)
3794 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3795 "0x%x data 0x%llx\n", msr, data);
3797 case MSR_K7_CLK_CTL:
3799 * Ignore all writes to this no longer documented MSR.
3800 * Writes are only relevant for old K7 processors,
3801 * all pre-dating SVM, but a recommended workaround from
3802 * AMD for these chips. It is possible to specify the
3803 * affected processor models on the command line, hence
3804 * the need to ignore the workaround.
3807 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3808 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3809 case HV_X64_MSR_SYNDBG_OPTIONS:
3810 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3811 case HV_X64_MSR_CRASH_CTL:
3812 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3813 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3814 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3815 case HV_X64_MSR_TSC_EMULATION_STATUS:
3816 return kvm_hv_set_msr_common(vcpu, msr, data,
3817 msr_info->host_initiated);
3818 case MSR_IA32_BBL_CR_CTL3:
3819 /* Drop writes to this legacy MSR -- see rdmsr
3820 * counterpart for further detail.
3822 if (report_ignored_msrs)
3823 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3826 case MSR_AMD64_OSVW_ID_LENGTH:
3827 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3829 vcpu->arch.osvw.length = data;
3831 case MSR_AMD64_OSVW_STATUS:
3832 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3834 vcpu->arch.osvw.status = data;
3836 case MSR_PLATFORM_INFO:
3837 if (!msr_info->host_initiated ||
3838 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3839 cpuid_fault_enabled(vcpu)))
3841 vcpu->arch.msr_platform_info = data;
3843 case MSR_MISC_FEATURES_ENABLES:
3844 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3845 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3846 !supports_cpuid_fault(vcpu)))
3848 vcpu->arch.msr_misc_features_enables = data;
3850 #ifdef CONFIG_X86_64
3852 if (!msr_info->host_initiated &&
3853 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3856 if (data & ~kvm_guest_supported_xfd(vcpu))
3859 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3861 case MSR_IA32_XFD_ERR:
3862 if (!msr_info->host_initiated &&
3863 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3866 if (data & ~kvm_guest_supported_xfd(vcpu))
3869 vcpu->arch.guest_fpu.xfd_err = data;
3872 case MSR_IA32_PEBS_ENABLE:
3873 case MSR_IA32_DS_AREA:
3874 case MSR_PEBS_DATA_CFG:
3875 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3876 if (kvm_pmu_is_valid_msr(vcpu, msr))
3877 return kvm_pmu_set_msr(vcpu, msr_info);
3879 * Userspace is allowed to write '0' to MSRs that KVM reports
3880 * as to-be-saved, even if an MSRs isn't fully supported.
3882 return !msr_info->host_initiated || data;
3884 if (kvm_pmu_is_valid_msr(vcpu, msr))
3885 return kvm_pmu_set_msr(vcpu, msr_info);
3886 return KVM_MSR_RET_INVALID;
3890 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3892 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3895 u64 mcg_cap = vcpu->arch.mcg_cap;
3896 unsigned bank_num = mcg_cap & 0xff;
3897 u32 offset, last_msr;
3900 case MSR_IA32_P5_MC_ADDR:
3901 case MSR_IA32_P5_MC_TYPE:
3904 case MSR_IA32_MCG_CAP:
3905 data = vcpu->arch.mcg_cap;
3907 case MSR_IA32_MCG_CTL:
3908 if (!(mcg_cap & MCG_CTL_P) && !host)
3910 data = vcpu->arch.mcg_ctl;
3912 case MSR_IA32_MCG_STATUS:
3913 data = vcpu->arch.mcg_status;
3915 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3916 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3920 if (!(mcg_cap & MCG_CMCI_P) && !host)
3922 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3923 last_msr + 1 - MSR_IA32_MC0_CTL2);
3924 data = vcpu->arch.mci_ctl2_banks[offset];
3926 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3927 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3931 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3932 last_msr + 1 - MSR_IA32_MC0_CTL);
3933 data = vcpu->arch.mce_banks[offset];
3942 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3944 switch (msr_info->index) {
3945 case MSR_IA32_PLATFORM_ID:
3946 case MSR_IA32_EBL_CR_POWERON:
3947 case MSR_IA32_LASTBRANCHFROMIP:
3948 case MSR_IA32_LASTBRANCHTOIP:
3949 case MSR_IA32_LASTINTFROMIP:
3950 case MSR_IA32_LASTINTTOIP:
3951 case MSR_AMD64_SYSCFG:
3952 case MSR_K8_TSEG_ADDR:
3953 case MSR_K8_TSEG_MASK:
3954 case MSR_VM_HSAVE_PA:
3955 case MSR_K8_INT_PENDING_MSG:
3956 case MSR_AMD64_NB_CFG:
3957 case MSR_FAM10H_MMIO_CONF_BASE:
3958 case MSR_AMD64_BU_CFG2:
3959 case MSR_IA32_PERF_CTL:
3960 case MSR_AMD64_DC_CFG:
3961 case MSR_F15H_EX_CFG:
3963 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3964 * limit) MSRs. Just return 0, as we do not want to expose the host
3965 * data here. Do not conditionalize this on CPUID, as KVM does not do
3966 * so for existing CPU-specific MSRs.
3968 case MSR_RAPL_POWER_UNIT:
3969 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3970 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3971 case MSR_PKG_ENERGY_STATUS: /* Total package */
3972 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3975 case MSR_IA32_PEBS_ENABLE:
3976 case MSR_IA32_DS_AREA:
3977 case MSR_PEBS_DATA_CFG:
3978 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3979 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3980 return kvm_pmu_get_msr(vcpu, msr_info);
3982 * Userspace is allowed to read MSRs that KVM reports as
3983 * to-be-saved, even if an MSR isn't fully supported.
3985 if (!msr_info->host_initiated)
3989 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3990 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3991 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3992 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3993 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3994 return kvm_pmu_get_msr(vcpu, msr_info);
3997 case MSR_IA32_UCODE_REV:
3998 msr_info->data = vcpu->arch.microcode_version;
4000 case MSR_IA32_ARCH_CAPABILITIES:
4001 if (!msr_info->host_initiated &&
4002 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4004 msr_info->data = vcpu->arch.arch_capabilities;
4006 case MSR_IA32_PERF_CAPABILITIES:
4007 if (!msr_info->host_initiated &&
4008 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4010 msr_info->data = vcpu->arch.perf_capabilities;
4012 case MSR_IA32_POWER_CTL:
4013 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4015 case MSR_IA32_TSC: {
4017 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4018 * even when not intercepted. AMD manual doesn't explicitly
4019 * state this but appears to behave the same.
4021 * On userspace reads and writes, however, we unconditionally
4022 * return L1's TSC value to ensure backwards-compatible
4023 * behavior for migration.
4027 if (msr_info->host_initiated) {
4028 offset = vcpu->arch.l1_tsc_offset;
4029 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4031 offset = vcpu->arch.tsc_offset;
4032 ratio = vcpu->arch.tsc_scaling_ratio;
4035 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4039 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
4040 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
4041 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4042 case 0xcd: /* fsb frequency */
4046 * MSR_EBC_FREQUENCY_ID
4047 * Conservative value valid for even the basic CPU models.
4048 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4049 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4050 * and 266MHz for model 3, or 4. Set Core Clock
4051 * Frequency to System Bus Frequency Ratio to 1 (bits
4052 * 31:24) even though these are only valid for CPU
4053 * models > 2, however guests may end up dividing or
4054 * multiplying by zero otherwise.
4056 case MSR_EBC_FREQUENCY_ID:
4057 msr_info->data = 1 << 24;
4059 case MSR_IA32_APICBASE:
4060 msr_info->data = kvm_get_apic_base(vcpu);
4062 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4063 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4064 case MSR_IA32_TSC_DEADLINE:
4065 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4067 case MSR_IA32_TSC_ADJUST:
4068 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4070 case MSR_IA32_MISC_ENABLE:
4071 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4073 case MSR_IA32_SMBASE:
4074 if (!msr_info->host_initiated)
4076 msr_info->data = vcpu->arch.smbase;
4079 msr_info->data = vcpu->arch.smi_count;
4081 case MSR_IA32_PERF_STATUS:
4082 /* TSC increment by tick */
4083 msr_info->data = 1000ULL;
4084 /* CPU multiplier */
4085 msr_info->data |= (((uint64_t)4ULL) << 40);
4088 msr_info->data = vcpu->arch.efer;
4090 case MSR_KVM_WALL_CLOCK:
4091 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4094 msr_info->data = vcpu->kvm->arch.wall_clock;
4096 case MSR_KVM_WALL_CLOCK_NEW:
4097 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4100 msr_info->data = vcpu->kvm->arch.wall_clock;
4102 case MSR_KVM_SYSTEM_TIME:
4103 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4106 msr_info->data = vcpu->arch.time;
4108 case MSR_KVM_SYSTEM_TIME_NEW:
4109 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4112 msr_info->data = vcpu->arch.time;
4114 case MSR_KVM_ASYNC_PF_EN:
4115 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4118 msr_info->data = vcpu->arch.apf.msr_en_val;
4120 case MSR_KVM_ASYNC_PF_INT:
4121 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4124 msr_info->data = vcpu->arch.apf.msr_int_val;
4126 case MSR_KVM_ASYNC_PF_ACK:
4127 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4132 case MSR_KVM_STEAL_TIME:
4133 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4136 msr_info->data = vcpu->arch.st.msr_val;
4138 case MSR_KVM_PV_EOI_EN:
4139 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4142 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4144 case MSR_KVM_POLL_CONTROL:
4145 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4148 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4150 case MSR_IA32_P5_MC_ADDR:
4151 case MSR_IA32_P5_MC_TYPE:
4152 case MSR_IA32_MCG_CAP:
4153 case MSR_IA32_MCG_CTL:
4154 case MSR_IA32_MCG_STATUS:
4155 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4156 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4157 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4158 msr_info->host_initiated);
4160 if (!msr_info->host_initiated &&
4161 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4163 msr_info->data = vcpu->arch.ia32_xss;
4165 case MSR_K7_CLK_CTL:
4167 * Provide expected ramp-up count for K7. All other
4168 * are set to zero, indicating minimum divisors for
4171 * This prevents guest kernels on AMD host with CPU
4172 * type 6, model 8 and higher from exploding due to
4173 * the rdmsr failing.
4175 msr_info->data = 0x20000000;
4177 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4178 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4179 case HV_X64_MSR_SYNDBG_OPTIONS:
4180 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4181 case HV_X64_MSR_CRASH_CTL:
4182 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4183 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4184 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4185 case HV_X64_MSR_TSC_EMULATION_STATUS:
4186 return kvm_hv_get_msr_common(vcpu,
4187 msr_info->index, &msr_info->data,
4188 msr_info->host_initiated);
4189 case MSR_IA32_BBL_CR_CTL3:
4190 /* This legacy MSR exists but isn't fully documented in current
4191 * silicon. It is however accessed by winxp in very narrow
4192 * scenarios where it sets bit #19, itself documented as
4193 * a "reserved" bit. Best effort attempt to source coherent
4194 * read data here should the balance of the register be
4195 * interpreted by the guest:
4197 * L2 cache control register 3: 64GB range, 256KB size,
4198 * enabled, latency 0x1, configured
4200 msr_info->data = 0xbe702111;
4202 case MSR_AMD64_OSVW_ID_LENGTH:
4203 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4205 msr_info->data = vcpu->arch.osvw.length;
4207 case MSR_AMD64_OSVW_STATUS:
4208 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4210 msr_info->data = vcpu->arch.osvw.status;
4212 case MSR_PLATFORM_INFO:
4213 if (!msr_info->host_initiated &&
4214 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4216 msr_info->data = vcpu->arch.msr_platform_info;
4218 case MSR_MISC_FEATURES_ENABLES:
4219 msr_info->data = vcpu->arch.msr_misc_features_enables;
4222 msr_info->data = vcpu->arch.msr_hwcr;
4224 #ifdef CONFIG_X86_64
4226 if (!msr_info->host_initiated &&
4227 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4230 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4232 case MSR_IA32_XFD_ERR:
4233 if (!msr_info->host_initiated &&
4234 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4237 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4241 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4242 return kvm_pmu_get_msr(vcpu, msr_info);
4243 return KVM_MSR_RET_INVALID;
4247 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4250 * Read or write a bunch of msrs. All parameters are kernel addresses.
4252 * @return number of msrs set successfully.
4254 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4255 struct kvm_msr_entry *entries,
4256 int (*do_msr)(struct kvm_vcpu *vcpu,
4257 unsigned index, u64 *data))
4261 for (i = 0; i < msrs->nmsrs; ++i)
4262 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4269 * Read or write a bunch of msrs. Parameters are user addresses.
4271 * @return number of msrs set successfully.
4273 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4274 int (*do_msr)(struct kvm_vcpu *vcpu,
4275 unsigned index, u64 *data),
4278 struct kvm_msrs msrs;
4279 struct kvm_msr_entry *entries;
4284 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4288 if (msrs.nmsrs >= MAX_IO_MSRS)
4291 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4292 entries = memdup_user(user_msrs->entries, size);
4293 if (IS_ERR(entries)) {
4294 r = PTR_ERR(entries);
4298 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4303 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4314 static inline bool kvm_can_mwait_in_guest(void)
4316 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4317 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4318 boot_cpu_has(X86_FEATURE_ARAT);
4321 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4322 struct kvm_cpuid2 __user *cpuid_arg)
4324 struct kvm_cpuid2 cpuid;
4328 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4331 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4336 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4342 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4347 case KVM_CAP_IRQCHIP:
4349 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4350 case KVM_CAP_SET_TSS_ADDR:
4351 case KVM_CAP_EXT_CPUID:
4352 case KVM_CAP_EXT_EMUL_CPUID:
4353 case KVM_CAP_CLOCKSOURCE:
4355 case KVM_CAP_NOP_IO_DELAY:
4356 case KVM_CAP_MP_STATE:
4357 case KVM_CAP_SYNC_MMU:
4358 case KVM_CAP_USER_NMI:
4359 case KVM_CAP_REINJECT_CONTROL:
4360 case KVM_CAP_IRQ_INJECT_STATUS:
4361 case KVM_CAP_IOEVENTFD:
4362 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4364 case KVM_CAP_PIT_STATE2:
4365 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4366 case KVM_CAP_VCPU_EVENTS:
4367 case KVM_CAP_HYPERV:
4368 case KVM_CAP_HYPERV_VAPIC:
4369 case KVM_CAP_HYPERV_SPIN:
4370 case KVM_CAP_HYPERV_SYNIC:
4371 case KVM_CAP_HYPERV_SYNIC2:
4372 case KVM_CAP_HYPERV_VP_INDEX:
4373 case KVM_CAP_HYPERV_EVENTFD:
4374 case KVM_CAP_HYPERV_TLBFLUSH:
4375 case KVM_CAP_HYPERV_SEND_IPI:
4376 case KVM_CAP_HYPERV_CPUID:
4377 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4378 case KVM_CAP_SYS_HYPERV_CPUID:
4379 case KVM_CAP_PCI_SEGMENT:
4380 case KVM_CAP_DEBUGREGS:
4381 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4383 case KVM_CAP_ASYNC_PF:
4384 case KVM_CAP_ASYNC_PF_INT:
4385 case KVM_CAP_GET_TSC_KHZ:
4386 case KVM_CAP_KVMCLOCK_CTRL:
4387 case KVM_CAP_READONLY_MEM:
4388 case KVM_CAP_HYPERV_TIME:
4389 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4390 case KVM_CAP_TSC_DEADLINE_TIMER:
4391 case KVM_CAP_DISABLE_QUIRKS:
4392 case KVM_CAP_SET_BOOT_CPU_ID:
4393 case KVM_CAP_SPLIT_IRQCHIP:
4394 case KVM_CAP_IMMEDIATE_EXIT:
4395 case KVM_CAP_PMU_EVENT_FILTER:
4396 case KVM_CAP_GET_MSR_FEATURES:
4397 case KVM_CAP_MSR_PLATFORM_INFO:
4398 case KVM_CAP_EXCEPTION_PAYLOAD:
4399 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4400 case KVM_CAP_SET_GUEST_DEBUG:
4401 case KVM_CAP_LAST_CPU:
4402 case KVM_CAP_X86_USER_SPACE_MSR:
4403 case KVM_CAP_X86_MSR_FILTER:
4404 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4405 #ifdef CONFIG_X86_SGX_KVM
4406 case KVM_CAP_SGX_ATTRIBUTE:
4408 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4409 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4410 case KVM_CAP_SREGS2:
4411 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4412 case KVM_CAP_VCPU_ATTRIBUTES:
4413 case KVM_CAP_SYS_ATTRIBUTES:
4415 case KVM_CAP_ENABLE_CAP:
4416 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4419 case KVM_CAP_EXIT_HYPERCALL:
4420 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4422 case KVM_CAP_SET_GUEST_DEBUG2:
4423 return KVM_GUESTDBG_VALID_MASK;
4424 #ifdef CONFIG_KVM_XEN
4425 case KVM_CAP_XEN_HVM:
4426 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4427 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4428 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4429 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4430 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4431 if (sched_info_on())
4432 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4435 case KVM_CAP_SYNC_REGS:
4436 r = KVM_SYNC_X86_VALID_FIELDS;
4438 case KVM_CAP_ADJUST_CLOCK:
4439 r = KVM_CLOCK_VALID_FLAGS;
4441 case KVM_CAP_X86_DISABLE_EXITS:
4442 r = KVM_X86_DISABLE_EXITS_PAUSE;
4444 if (!mitigate_smt_rsb) {
4445 r |= KVM_X86_DISABLE_EXITS_HLT |
4446 KVM_X86_DISABLE_EXITS_CSTATE;
4448 if (kvm_can_mwait_in_guest())
4449 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4452 case KVM_CAP_X86_SMM:
4453 /* SMBASE is usually relocated above 1M on modern chipsets,
4454 * and SMM handlers might indeed rely on 4G segment limits,
4455 * so do not report SMM to be available if real mode is
4456 * emulated via vm86 mode. Still, do not go to great lengths
4457 * to avoid userspace's usage of the feature, because it is a
4458 * fringe case that is not enabled except via specific settings
4459 * of the module parameters.
4461 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4463 case KVM_CAP_NR_VCPUS:
4464 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4466 case KVM_CAP_MAX_VCPUS:
4469 case KVM_CAP_MAX_VCPU_ID:
4470 r = KVM_MAX_VCPU_IDS;
4472 case KVM_CAP_PV_MMU: /* obsolete */
4476 r = KVM_MAX_MCE_BANKS;
4479 r = boot_cpu_has(X86_FEATURE_XSAVE);
4481 case KVM_CAP_TSC_CONTROL:
4482 case KVM_CAP_VM_TSC_CONTROL:
4483 r = kvm_caps.has_tsc_control;
4485 case KVM_CAP_X2APIC_API:
4486 r = KVM_X2APIC_API_VALID_FLAGS;
4488 case KVM_CAP_NESTED_STATE:
4489 r = kvm_x86_ops.nested_ops->get_state ?
4490 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4492 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4493 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4495 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4496 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4498 case KVM_CAP_SMALLER_MAXPHYADDR:
4499 r = (int) allow_smaller_maxphyaddr;
4501 case KVM_CAP_STEAL_TIME:
4502 r = sched_info_on();
4504 case KVM_CAP_X86_BUS_LOCK_EXIT:
4505 if (kvm_caps.has_bus_lock_exit)
4506 r = KVM_BUS_LOCK_DETECTION_OFF |
4507 KVM_BUS_LOCK_DETECTION_EXIT;
4511 case KVM_CAP_XSAVE2: {
4512 u64 guest_perm = xstate_get_guest_group_perm();
4514 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
4515 if (r < sizeof(struct kvm_xsave))
4516 r = sizeof(struct kvm_xsave);
4519 case KVM_CAP_PMU_CAPABILITY:
4520 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4522 case KVM_CAP_DISABLE_QUIRKS2:
4523 r = KVM_X86_VALID_QUIRKS;
4525 case KVM_CAP_X86_NOTIFY_VMEXIT:
4526 r = kvm_caps.has_notify_vmexit;
4534 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4536 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4538 if ((u64)(unsigned long)uaddr != attr->addr)
4539 return ERR_PTR_USR(-EFAULT);
4543 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4545 u64 __user *uaddr = kvm_get_attr_addr(attr);
4551 return PTR_ERR(uaddr);
4553 switch (attr->attr) {
4554 case KVM_X86_XCOMP_GUEST_SUPP:
4555 if (put_user(kvm_caps.supported_xcr0, uaddr))
4564 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4569 switch (attr->attr) {
4570 case KVM_X86_XCOMP_GUEST_SUPP:
4577 long kvm_arch_dev_ioctl(struct file *filp,
4578 unsigned int ioctl, unsigned long arg)
4580 void __user *argp = (void __user *)arg;
4584 case KVM_GET_MSR_INDEX_LIST: {
4585 struct kvm_msr_list __user *user_msr_list = argp;
4586 struct kvm_msr_list msr_list;
4590 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4593 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4594 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4597 if (n < msr_list.nmsrs)
4600 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4601 num_msrs_to_save * sizeof(u32)))
4603 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4605 num_emulated_msrs * sizeof(u32)))
4610 case KVM_GET_SUPPORTED_CPUID:
4611 case KVM_GET_EMULATED_CPUID: {
4612 struct kvm_cpuid2 __user *cpuid_arg = argp;
4613 struct kvm_cpuid2 cpuid;
4616 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4619 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4625 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4630 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4632 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4633 sizeof(kvm_caps.supported_mce_cap)))
4637 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4638 struct kvm_msr_list __user *user_msr_list = argp;
4639 struct kvm_msr_list msr_list;
4643 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4646 msr_list.nmsrs = num_msr_based_features;
4647 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4650 if (n < msr_list.nmsrs)
4653 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4654 num_msr_based_features * sizeof(u32)))
4660 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4662 case KVM_GET_SUPPORTED_HV_CPUID:
4663 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4665 case KVM_GET_DEVICE_ATTR: {
4666 struct kvm_device_attr attr;
4668 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4670 r = kvm_x86_dev_get_attr(&attr);
4673 case KVM_HAS_DEVICE_ATTR: {
4674 struct kvm_device_attr attr;
4676 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4678 r = kvm_x86_dev_has_attr(&attr);
4689 static void wbinvd_ipi(void *garbage)
4694 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4696 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4699 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4701 /* Address WBINVD may be executed by guest */
4702 if (need_emulate_wbinvd(vcpu)) {
4703 if (static_call(kvm_x86_has_wbinvd_exit)())
4704 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4705 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4706 smp_call_function_single(vcpu->cpu,
4707 wbinvd_ipi, NULL, 1);
4710 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4712 /* Save host pkru register if supported */
4713 vcpu->arch.host_pkru = read_pkru();
4715 /* Apply any externally detected TSC adjustments (due to suspend) */
4716 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4717 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4718 vcpu->arch.tsc_offset_adjustment = 0;
4719 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4722 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4723 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4724 rdtsc() - vcpu->arch.last_host_tsc;
4726 mark_tsc_unstable("KVM discovered backwards TSC");
4728 if (kvm_check_tsc_unstable()) {
4729 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4730 vcpu->arch.last_guest_tsc);
4731 kvm_vcpu_write_tsc_offset(vcpu, offset);
4732 vcpu->arch.tsc_catchup = 1;
4735 if (kvm_lapic_hv_timer_in_use(vcpu))
4736 kvm_lapic_restart_hv_timer(vcpu);
4739 * On a host with synchronized TSC, there is no need to update
4740 * kvmclock on vcpu->cpu migration
4742 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4743 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4744 if (vcpu->cpu != cpu)
4745 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4749 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4752 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4754 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4755 struct kvm_steal_time __user *st;
4756 struct kvm_memslots *slots;
4757 static const u8 preempted = KVM_VCPU_PREEMPTED;
4758 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4761 * The vCPU can be marked preempted if and only if the VM-Exit was on
4762 * an instruction boundary and will not trigger guest emulation of any
4763 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4764 * when this is true, for example allowing the vCPU to be marked
4765 * preempted if and only if the VM-Exit was due to a host interrupt.
4767 if (!vcpu->arch.at_instruction_boundary) {
4768 vcpu->stat.preemption_other++;
4772 vcpu->stat.preemption_reported++;
4773 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4776 if (vcpu->arch.st.preempted)
4779 /* This happens on process exit */
4780 if (unlikely(current->mm != vcpu->kvm->mm))
4783 slots = kvm_memslots(vcpu->kvm);
4785 if (unlikely(slots->generation != ghc->generation ||
4787 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4790 st = (struct kvm_steal_time __user *)ghc->hva;
4791 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4793 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4794 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4796 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4799 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4803 if (vcpu->preempted) {
4804 if (!vcpu->arch.guest_state_protected)
4805 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4808 * Take the srcu lock as memslots will be accessed to check the gfn
4809 * cache generation against the memslots generation.
4811 idx = srcu_read_lock(&vcpu->kvm->srcu);
4812 if (kvm_xen_msr_enabled(vcpu->kvm))
4813 kvm_xen_runstate_set_preempted(vcpu);
4815 kvm_steal_time_set_preempted(vcpu);
4816 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4819 static_call(kvm_x86_vcpu_put)(vcpu);
4820 vcpu->arch.last_host_tsc = rdtsc();
4823 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4824 struct kvm_lapic_state *s)
4826 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4828 return kvm_apic_get_state(vcpu, s);
4831 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4832 struct kvm_lapic_state *s)
4836 r = kvm_apic_set_state(vcpu, s);
4839 update_cr8_intercept(vcpu);
4844 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4847 * We can accept userspace's request for interrupt injection
4848 * as long as we have a place to store the interrupt number.
4849 * The actual injection will happen when the CPU is able to
4850 * deliver the interrupt.
4852 if (kvm_cpu_has_extint(vcpu))
4855 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4856 return (!lapic_in_kernel(vcpu) ||
4857 kvm_apic_accept_pic_intr(vcpu));
4860 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4863 * Do not cause an interrupt window exit if an exception
4864 * is pending or an event needs reinjection; userspace
4865 * might want to inject the interrupt manually using KVM_SET_REGS
4866 * or KVM_SET_SREGS. For that to work, we must be at an
4867 * instruction boundary and with no events half-injected.
4869 return (kvm_arch_interrupt_allowed(vcpu) &&
4870 kvm_cpu_accept_dm_intr(vcpu) &&
4871 !kvm_event_needs_reinjection(vcpu) &&
4872 !kvm_is_exception_pending(vcpu));
4875 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4876 struct kvm_interrupt *irq)
4878 if (irq->irq >= KVM_NR_INTERRUPTS)
4881 if (!irqchip_in_kernel(vcpu->kvm)) {
4882 kvm_queue_interrupt(vcpu, irq->irq, false);
4883 kvm_make_request(KVM_REQ_EVENT, vcpu);
4888 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4889 * fail for in-kernel 8259.
4891 if (pic_in_kernel(vcpu->kvm))
4894 if (vcpu->arch.pending_external_vector != -1)
4897 vcpu->arch.pending_external_vector = irq->irq;
4898 kvm_make_request(KVM_REQ_EVENT, vcpu);
4902 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4904 kvm_inject_nmi(vcpu);
4909 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4911 kvm_make_request(KVM_REQ_SMI, vcpu);
4916 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4917 struct kvm_tpr_access_ctl *tac)
4921 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4925 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4929 unsigned bank_num = mcg_cap & 0xff, bank;
4932 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4934 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
4937 vcpu->arch.mcg_cap = mcg_cap;
4938 /* Init IA32_MCG_CTL to all 1s */
4939 if (mcg_cap & MCG_CTL_P)
4940 vcpu->arch.mcg_ctl = ~(u64)0;
4941 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
4942 for (bank = 0; bank < bank_num; bank++) {
4943 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4944 if (mcg_cap & MCG_CMCI_P)
4945 vcpu->arch.mci_ctl2_banks[bank] = 0;
4948 kvm_apic_after_set_mcg_cap(vcpu);
4950 static_call(kvm_x86_setup_mce)(vcpu);
4956 * Validate this is an UCNA (uncorrectable no action) error by checking the
4957 * MCG_STATUS and MCi_STATUS registers:
4958 * - none of the bits for Machine Check Exceptions are set
4959 * - both the VAL (valid) and UC (uncorrectable) bits are set
4960 * MCI_STATUS_PCC - Processor Context Corrupted
4961 * MCI_STATUS_S - Signaled as a Machine Check Exception
4962 * MCI_STATUS_AR - Software recoverable Action Required
4964 static bool is_ucna(struct kvm_x86_mce *mce)
4966 return !mce->mcg_status &&
4967 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
4968 (mce->status & MCI_STATUS_VAL) &&
4969 (mce->status & MCI_STATUS_UC);
4972 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
4974 u64 mcg_cap = vcpu->arch.mcg_cap;
4976 banks[1] = mce->status;
4977 banks[2] = mce->addr;
4978 banks[3] = mce->misc;
4979 vcpu->arch.mcg_status = mce->mcg_status;
4981 if (!(mcg_cap & MCG_CMCI_P) ||
4982 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
4985 if (lapic_in_kernel(vcpu))
4986 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
4991 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4992 struct kvm_x86_mce *mce)
4994 u64 mcg_cap = vcpu->arch.mcg_cap;
4995 unsigned bank_num = mcg_cap & 0xff;
4996 u64 *banks = vcpu->arch.mce_banks;
4998 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5001 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5004 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5007 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5008 * reporting is disabled
5010 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5011 vcpu->arch.mcg_ctl != ~(u64)0)
5014 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5015 * reporting is disabled for the bank
5017 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5019 if (mce->status & MCI_STATUS_UC) {
5020 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5021 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
5022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5025 if (banks[1] & MCI_STATUS_VAL)
5026 mce->status |= MCI_STATUS_OVER;
5027 banks[2] = mce->addr;
5028 banks[3] = mce->misc;
5029 vcpu->arch.mcg_status = mce->mcg_status;
5030 banks[1] = mce->status;
5031 kvm_queue_exception(vcpu, MC_VECTOR);
5032 } else if (!(banks[1] & MCI_STATUS_VAL)
5033 || !(banks[1] & MCI_STATUS_UC)) {
5034 if (banks[1] & MCI_STATUS_VAL)
5035 mce->status |= MCI_STATUS_OVER;
5036 banks[2] = mce->addr;
5037 banks[3] = mce->misc;
5038 banks[1] = mce->status;
5040 banks[1] |= MCI_STATUS_OVER;
5044 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5045 struct kvm_vcpu_events *events)
5047 struct kvm_queued_exception *ex;
5051 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5055 * KVM's ABI only allows for one exception to be migrated. Luckily,
5056 * the only time there can be two queued exceptions is if there's a
5057 * non-exiting _injected_ exception, and a pending exiting exception.
5058 * In that case, ignore the VM-Exiting exception as it's an extension
5059 * of the injected exception.
5061 if (vcpu->arch.exception_vmexit.pending &&
5062 !vcpu->arch.exception.pending &&
5063 !vcpu->arch.exception.injected)
5064 ex = &vcpu->arch.exception_vmexit;
5066 ex = &vcpu->arch.exception;
5069 * In guest mode, payload delivery should be deferred if the exception
5070 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5071 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5072 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5073 * propagate the payload and so it cannot be safely deferred. Deliver
5074 * the payload if the capability hasn't been requested.
5076 if (!vcpu->kvm->arch.exception_payload_enabled &&
5077 ex->pending && ex->has_payload)
5078 kvm_deliver_exception_payload(vcpu, ex);
5081 * The API doesn't provide the instruction length for software
5082 * exceptions, so don't report them. As long as the guest RIP
5083 * isn't advanced, we should expect to encounter the exception
5086 if (kvm_exception_is_soft(ex->vector)) {
5087 events->exception.injected = 0;
5088 events->exception.pending = 0;
5090 events->exception.injected = ex->injected;
5091 events->exception.pending = ex->pending;
5093 * For ABI compatibility, deliberately conflate
5094 * pending and injected exceptions when
5095 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5097 if (!vcpu->kvm->arch.exception_payload_enabled)
5098 events->exception.injected |= ex->pending;
5100 events->exception.nr = ex->vector;
5101 events->exception.has_error_code = ex->has_error_code;
5102 events->exception.error_code = ex->error_code;
5103 events->exception_has_payload = ex->has_payload;
5104 events->exception_payload = ex->payload;
5106 events->interrupt.injected =
5107 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5108 events->interrupt.nr = vcpu->arch.interrupt.nr;
5109 events->interrupt.soft = 0;
5110 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5112 events->nmi.injected = vcpu->arch.nmi_injected;
5113 events->nmi.pending = vcpu->arch.nmi_pending != 0;
5114 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5115 events->nmi.pad = 0;
5117 events->sipi_vector = 0; /* never valid when reporting to user space */
5119 events->smi.smm = is_smm(vcpu);
5120 events->smi.pending = vcpu->arch.smi_pending;
5121 events->smi.smm_inside_nmi =
5122 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5123 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5125 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5126 | KVM_VCPUEVENT_VALID_SHADOW
5127 | KVM_VCPUEVENT_VALID_SMM);
5128 if (vcpu->kvm->arch.exception_payload_enabled)
5129 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5130 if (vcpu->kvm->arch.triple_fault_event) {
5131 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5132 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5135 memset(&events->reserved, 0, sizeof(events->reserved));
5138 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
5140 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5141 struct kvm_vcpu_events *events)
5143 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5144 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5145 | KVM_VCPUEVENT_VALID_SHADOW
5146 | KVM_VCPUEVENT_VALID_SMM
5147 | KVM_VCPUEVENT_VALID_PAYLOAD
5148 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5151 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5152 if (!vcpu->kvm->arch.exception_payload_enabled)
5154 if (events->exception.pending)
5155 events->exception.injected = 0;
5157 events->exception_has_payload = 0;
5159 events->exception.pending = 0;
5160 events->exception_has_payload = 0;
5163 if ((events->exception.injected || events->exception.pending) &&
5164 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5167 /* INITs are latched while in SMM */
5168 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5169 (events->smi.smm || events->smi.pending) &&
5170 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5176 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5177 * morph the exception to a VM-Exit if appropriate. Do this only for
5178 * pending exceptions, already-injected exceptions are not subject to
5179 * intercpetion. Note, userspace that conflates pending and injected
5180 * is hosed, and will incorrectly convert an injected exception into a
5181 * pending exception, which in turn may cause a spurious VM-Exit.
5183 vcpu->arch.exception_from_userspace = events->exception.pending;
5185 vcpu->arch.exception_vmexit.pending = false;
5187 vcpu->arch.exception.injected = events->exception.injected;
5188 vcpu->arch.exception.pending = events->exception.pending;
5189 vcpu->arch.exception.vector = events->exception.nr;
5190 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5191 vcpu->arch.exception.error_code = events->exception.error_code;
5192 vcpu->arch.exception.has_payload = events->exception_has_payload;
5193 vcpu->arch.exception.payload = events->exception_payload;
5195 vcpu->arch.interrupt.injected = events->interrupt.injected;
5196 vcpu->arch.interrupt.nr = events->interrupt.nr;
5197 vcpu->arch.interrupt.soft = events->interrupt.soft;
5198 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5199 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5200 events->interrupt.shadow);
5202 vcpu->arch.nmi_injected = events->nmi.injected;
5203 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
5204 vcpu->arch.nmi_pending = events->nmi.pending;
5205 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5207 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5208 lapic_in_kernel(vcpu))
5209 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5211 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5212 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5213 kvm_leave_nested(vcpu);
5214 kvm_smm_changed(vcpu, events->smi.smm);
5217 vcpu->arch.smi_pending = events->smi.pending;
5219 if (events->smi.smm) {
5220 if (events->smi.smm_inside_nmi)
5221 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5223 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5226 if (lapic_in_kernel(vcpu)) {
5227 if (events->smi.latched_init)
5228 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5230 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5234 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5235 if (!vcpu->kvm->arch.triple_fault_event)
5237 if (events->triple_fault.pending)
5238 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5240 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5243 kvm_make_request(KVM_REQ_EVENT, vcpu);
5248 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5249 struct kvm_debugregs *dbgregs)
5253 memset(dbgregs, 0, sizeof(*dbgregs));
5254 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5255 kvm_get_dr(vcpu, 6, &val);
5257 dbgregs->dr7 = vcpu->arch.dr7;
5260 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5261 struct kvm_debugregs *dbgregs)
5266 if (!kvm_dr6_valid(dbgregs->dr6))
5268 if (!kvm_dr7_valid(dbgregs->dr7))
5271 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5272 kvm_update_dr0123(vcpu);
5273 vcpu->arch.dr6 = dbgregs->dr6;
5274 vcpu->arch.dr7 = dbgregs->dr7;
5275 kvm_update_dr7(vcpu);
5280 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5281 struct kvm_xsave *guest_xsave)
5283 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5286 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5287 guest_xsave->region,
5288 sizeof(guest_xsave->region),
5292 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5293 u8 *state, unsigned int size)
5295 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5298 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5299 state, size, vcpu->arch.pkru);
5302 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5303 struct kvm_xsave *guest_xsave)
5305 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5308 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5309 guest_xsave->region,
5310 kvm_caps.supported_xcr0,
5314 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5315 struct kvm_xcrs *guest_xcrs)
5317 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5318 guest_xcrs->nr_xcrs = 0;
5322 guest_xcrs->nr_xcrs = 1;
5323 guest_xcrs->flags = 0;
5324 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5325 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5328 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5329 struct kvm_xcrs *guest_xcrs)
5333 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5336 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5339 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5340 /* Only support XCR0 currently */
5341 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5342 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5343 guest_xcrs->xcrs[i].value);
5352 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5353 * stopped by the hypervisor. This function will be called from the host only.
5354 * EINVAL is returned when the host attempts to set the flag for a guest that
5355 * does not support pv clocks.
5357 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5359 if (!vcpu->arch.pv_time.active)
5361 vcpu->arch.pvclock_set_guest_stopped_request = true;
5362 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5366 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5367 struct kvm_device_attr *attr)
5371 switch (attr->attr) {
5372 case KVM_VCPU_TSC_OFFSET:
5382 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5383 struct kvm_device_attr *attr)
5385 u64 __user *uaddr = kvm_get_attr_addr(attr);
5389 return PTR_ERR(uaddr);
5391 switch (attr->attr) {
5392 case KVM_VCPU_TSC_OFFSET:
5394 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5405 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5406 struct kvm_device_attr *attr)
5408 u64 __user *uaddr = kvm_get_attr_addr(attr);
5409 struct kvm *kvm = vcpu->kvm;
5413 return PTR_ERR(uaddr);
5415 switch (attr->attr) {
5416 case KVM_VCPU_TSC_OFFSET: {
5417 u64 offset, tsc, ns;
5418 unsigned long flags;
5422 if (get_user(offset, uaddr))
5425 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5427 matched = (vcpu->arch.virtual_tsc_khz &&
5428 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5429 kvm->arch.last_tsc_offset == offset);
5431 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5432 ns = get_kvmclock_base_ns();
5434 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5435 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5447 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5451 struct kvm_device_attr attr;
5454 if (copy_from_user(&attr, argp, sizeof(attr)))
5457 if (attr.group != KVM_VCPU_TSC_CTRL)
5461 case KVM_HAS_DEVICE_ATTR:
5462 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5464 case KVM_GET_DEVICE_ATTR:
5465 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5467 case KVM_SET_DEVICE_ATTR:
5468 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5475 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5476 struct kvm_enable_cap *cap)
5479 uint16_t vmcs_version;
5480 void __user *user_ptr;
5486 case KVM_CAP_HYPERV_SYNIC2:
5491 case KVM_CAP_HYPERV_SYNIC:
5492 if (!irqchip_in_kernel(vcpu->kvm))
5494 return kvm_hv_activate_synic(vcpu, cap->cap ==
5495 KVM_CAP_HYPERV_SYNIC2);
5496 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5497 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5499 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5501 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5502 if (copy_to_user(user_ptr, &vmcs_version,
5503 sizeof(vmcs_version)))
5507 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5508 if (!kvm_x86_ops.enable_direct_tlbflush)
5511 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5513 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5514 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5516 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5517 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5518 if (vcpu->arch.pv_cpuid.enforce)
5519 kvm_update_pv_runtime(vcpu);
5527 long kvm_arch_vcpu_ioctl(struct file *filp,
5528 unsigned int ioctl, unsigned long arg)
5530 struct kvm_vcpu *vcpu = filp->private_data;
5531 void __user *argp = (void __user *)arg;
5534 struct kvm_sregs2 *sregs2;
5535 struct kvm_lapic_state *lapic;
5536 struct kvm_xsave *xsave;
5537 struct kvm_xcrs *xcrs;
5545 case KVM_GET_LAPIC: {
5547 if (!lapic_in_kernel(vcpu))
5549 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5550 GFP_KERNEL_ACCOUNT);
5555 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5559 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5564 case KVM_SET_LAPIC: {
5566 if (!lapic_in_kernel(vcpu))
5568 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5569 if (IS_ERR(u.lapic)) {
5570 r = PTR_ERR(u.lapic);
5574 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5577 case KVM_INTERRUPT: {
5578 struct kvm_interrupt irq;
5581 if (copy_from_user(&irq, argp, sizeof(irq)))
5583 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5587 r = kvm_vcpu_ioctl_nmi(vcpu);
5591 r = kvm_vcpu_ioctl_smi(vcpu);
5594 case KVM_SET_CPUID: {
5595 struct kvm_cpuid __user *cpuid_arg = argp;
5596 struct kvm_cpuid cpuid;
5599 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5601 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5604 case KVM_SET_CPUID2: {
5605 struct kvm_cpuid2 __user *cpuid_arg = argp;
5606 struct kvm_cpuid2 cpuid;
5609 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5611 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5612 cpuid_arg->entries);
5615 case KVM_GET_CPUID2: {
5616 struct kvm_cpuid2 __user *cpuid_arg = argp;
5617 struct kvm_cpuid2 cpuid;
5620 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5622 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5623 cpuid_arg->entries);
5627 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5632 case KVM_GET_MSRS: {
5633 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5634 r = msr_io(vcpu, argp, do_get_msr, 1);
5635 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5638 case KVM_SET_MSRS: {
5639 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5640 r = msr_io(vcpu, argp, do_set_msr, 0);
5641 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5644 case KVM_TPR_ACCESS_REPORTING: {
5645 struct kvm_tpr_access_ctl tac;
5648 if (copy_from_user(&tac, argp, sizeof(tac)))
5650 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5654 if (copy_to_user(argp, &tac, sizeof(tac)))
5659 case KVM_SET_VAPIC_ADDR: {
5660 struct kvm_vapic_addr va;
5664 if (!lapic_in_kernel(vcpu))
5667 if (copy_from_user(&va, argp, sizeof(va)))
5669 idx = srcu_read_lock(&vcpu->kvm->srcu);
5670 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5671 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5674 case KVM_X86_SETUP_MCE: {
5678 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5680 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5683 case KVM_X86_SET_MCE: {
5684 struct kvm_x86_mce mce;
5687 if (copy_from_user(&mce, argp, sizeof(mce)))
5689 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5692 case KVM_GET_VCPU_EVENTS: {
5693 struct kvm_vcpu_events events;
5695 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5698 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5703 case KVM_SET_VCPU_EVENTS: {
5704 struct kvm_vcpu_events events;
5707 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5710 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5713 case KVM_GET_DEBUGREGS: {
5714 struct kvm_debugregs dbgregs;
5716 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5719 if (copy_to_user(argp, &dbgregs,
5720 sizeof(struct kvm_debugregs)))
5725 case KVM_SET_DEBUGREGS: {
5726 struct kvm_debugregs dbgregs;
5729 if (copy_from_user(&dbgregs, argp,
5730 sizeof(struct kvm_debugregs)))
5733 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5736 case KVM_GET_XSAVE: {
5738 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5741 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5746 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5749 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5754 case KVM_SET_XSAVE: {
5755 int size = vcpu->arch.guest_fpu.uabi_size;
5757 u.xsave = memdup_user(argp, size);
5758 if (IS_ERR(u.xsave)) {
5759 r = PTR_ERR(u.xsave);
5763 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5767 case KVM_GET_XSAVE2: {
5768 int size = vcpu->arch.guest_fpu.uabi_size;
5770 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5775 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5778 if (copy_to_user(argp, u.xsave, size))
5785 case KVM_GET_XCRS: {
5786 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5791 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5794 if (copy_to_user(argp, u.xcrs,
5795 sizeof(struct kvm_xcrs)))
5800 case KVM_SET_XCRS: {
5801 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5802 if (IS_ERR(u.xcrs)) {
5803 r = PTR_ERR(u.xcrs);
5807 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5810 case KVM_SET_TSC_KHZ: {
5814 user_tsc_khz = (u32)arg;
5816 if (kvm_caps.has_tsc_control &&
5817 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5820 if (user_tsc_khz == 0)
5821 user_tsc_khz = tsc_khz;
5823 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5828 case KVM_GET_TSC_KHZ: {
5829 r = vcpu->arch.virtual_tsc_khz;
5832 case KVM_KVMCLOCK_CTRL: {
5833 r = kvm_set_guest_paused(vcpu);
5836 case KVM_ENABLE_CAP: {
5837 struct kvm_enable_cap cap;
5840 if (copy_from_user(&cap, argp, sizeof(cap)))
5842 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5845 case KVM_GET_NESTED_STATE: {
5846 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5850 if (!kvm_x86_ops.nested_ops->get_state)
5853 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5855 if (get_user(user_data_size, &user_kvm_nested_state->size))
5858 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5863 if (r > user_data_size) {
5864 if (put_user(r, &user_kvm_nested_state->size))
5874 case KVM_SET_NESTED_STATE: {
5875 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5876 struct kvm_nested_state kvm_state;
5880 if (!kvm_x86_ops.nested_ops->set_state)
5884 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5888 if (kvm_state.size < sizeof(kvm_state))
5891 if (kvm_state.flags &
5892 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5893 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5894 | KVM_STATE_NESTED_GIF_SET))
5897 /* nested_run_pending implies guest_mode. */
5898 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5899 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5902 idx = srcu_read_lock(&vcpu->kvm->srcu);
5903 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5904 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5907 case KVM_GET_SUPPORTED_HV_CPUID:
5908 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5910 #ifdef CONFIG_KVM_XEN
5911 case KVM_XEN_VCPU_GET_ATTR: {
5912 struct kvm_xen_vcpu_attr xva;
5915 if (copy_from_user(&xva, argp, sizeof(xva)))
5917 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5918 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5922 case KVM_XEN_VCPU_SET_ATTR: {
5923 struct kvm_xen_vcpu_attr xva;
5926 if (copy_from_user(&xva, argp, sizeof(xva)))
5928 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5932 case KVM_GET_SREGS2: {
5933 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5937 __get_sregs2(vcpu, u.sregs2);
5939 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5944 case KVM_SET_SREGS2: {
5945 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5946 if (IS_ERR(u.sregs2)) {
5947 r = PTR_ERR(u.sregs2);
5951 r = __set_sregs2(vcpu, u.sregs2);
5954 case KVM_HAS_DEVICE_ATTR:
5955 case KVM_GET_DEVICE_ATTR:
5956 case KVM_SET_DEVICE_ATTR:
5957 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5969 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5971 return VM_FAULT_SIGBUS;
5974 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5978 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5980 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5984 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5987 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5990 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5991 unsigned long kvm_nr_mmu_pages)
5993 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5996 mutex_lock(&kvm->slots_lock);
5998 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5999 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6001 mutex_unlock(&kvm->slots_lock);
6005 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
6007 return kvm->arch.n_max_mmu_pages;
6010 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6012 struct kvm_pic *pic = kvm->arch.vpic;
6016 switch (chip->chip_id) {
6017 case KVM_IRQCHIP_PIC_MASTER:
6018 memcpy(&chip->chip.pic, &pic->pics[0],
6019 sizeof(struct kvm_pic_state));
6021 case KVM_IRQCHIP_PIC_SLAVE:
6022 memcpy(&chip->chip.pic, &pic->pics[1],
6023 sizeof(struct kvm_pic_state));
6025 case KVM_IRQCHIP_IOAPIC:
6026 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6035 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6037 struct kvm_pic *pic = kvm->arch.vpic;
6041 switch (chip->chip_id) {
6042 case KVM_IRQCHIP_PIC_MASTER:
6043 spin_lock(&pic->lock);
6044 memcpy(&pic->pics[0], &chip->chip.pic,
6045 sizeof(struct kvm_pic_state));
6046 spin_unlock(&pic->lock);
6048 case KVM_IRQCHIP_PIC_SLAVE:
6049 spin_lock(&pic->lock);
6050 memcpy(&pic->pics[1], &chip->chip.pic,
6051 sizeof(struct kvm_pic_state));
6052 spin_unlock(&pic->lock);
6054 case KVM_IRQCHIP_IOAPIC:
6055 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6061 kvm_pic_update_irq(pic);
6065 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6067 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6069 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6071 mutex_lock(&kps->lock);
6072 memcpy(ps, &kps->channels, sizeof(*ps));
6073 mutex_unlock(&kps->lock);
6077 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6080 struct kvm_pit *pit = kvm->arch.vpit;
6082 mutex_lock(&pit->pit_state.lock);
6083 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6084 for (i = 0; i < 3; i++)
6085 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6086 mutex_unlock(&pit->pit_state.lock);
6090 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6093 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6094 sizeof(ps->channels));
6095 ps->flags = kvm->arch.vpit->pit_state.flags;
6096 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6097 memset(&ps->reserved, 0, sizeof(ps->reserved));
6101 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6105 u32 prev_legacy, cur_legacy;
6106 struct kvm_pit *pit = kvm->arch.vpit;
6108 mutex_lock(&pit->pit_state.lock);
6109 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6110 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6111 if (!prev_legacy && cur_legacy)
6113 memcpy(&pit->pit_state.channels, &ps->channels,
6114 sizeof(pit->pit_state.channels));
6115 pit->pit_state.flags = ps->flags;
6116 for (i = 0; i < 3; i++)
6117 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6119 mutex_unlock(&pit->pit_state.lock);
6123 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6124 struct kvm_reinject_control *control)
6126 struct kvm_pit *pit = kvm->arch.vpit;
6128 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6129 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6130 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6132 mutex_lock(&pit->pit_state.lock);
6133 kvm_pit_set_reinject(pit, control->pit_reinject);
6134 mutex_unlock(&pit->pit_state.lock);
6139 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6143 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6144 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6145 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6148 struct kvm_vcpu *vcpu;
6151 kvm_for_each_vcpu(i, vcpu, kvm)
6152 kvm_vcpu_kick(vcpu);
6155 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6158 if (!irqchip_in_kernel(kvm))
6161 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6162 irq_event->irq, irq_event->level,
6167 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6168 struct kvm_enable_cap *cap)
6176 case KVM_CAP_DISABLE_QUIRKS2:
6178 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6181 case KVM_CAP_DISABLE_QUIRKS:
6182 kvm->arch.disabled_quirks = cap->args[0];
6185 case KVM_CAP_SPLIT_IRQCHIP: {
6186 mutex_lock(&kvm->lock);
6188 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6189 goto split_irqchip_unlock;
6191 if (irqchip_in_kernel(kvm))
6192 goto split_irqchip_unlock;
6193 if (kvm->created_vcpus)
6194 goto split_irqchip_unlock;
6195 r = kvm_setup_empty_irq_routing(kvm);
6197 goto split_irqchip_unlock;
6198 /* Pairs with irqchip_in_kernel. */
6200 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6201 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6202 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6204 split_irqchip_unlock:
6205 mutex_unlock(&kvm->lock);
6208 case KVM_CAP_X2APIC_API:
6210 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6213 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6214 kvm->arch.x2apic_format = true;
6215 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6216 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6220 case KVM_CAP_X86_DISABLE_EXITS:
6222 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6225 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6226 kvm->arch.pause_in_guest = true;
6228 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6229 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6231 if (!mitigate_smt_rsb) {
6232 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6233 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6234 pr_warn_once(SMT_RSB_MSG);
6236 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6237 kvm_can_mwait_in_guest())
6238 kvm->arch.mwait_in_guest = true;
6239 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6240 kvm->arch.hlt_in_guest = true;
6241 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6242 kvm->arch.cstate_in_guest = true;
6247 case KVM_CAP_MSR_PLATFORM_INFO:
6248 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6251 case KVM_CAP_EXCEPTION_PAYLOAD:
6252 kvm->arch.exception_payload_enabled = cap->args[0];
6255 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6256 kvm->arch.triple_fault_event = cap->args[0];
6259 case KVM_CAP_X86_USER_SPACE_MSR:
6261 if (cap->args[0] & ~(KVM_MSR_EXIT_REASON_INVAL |
6262 KVM_MSR_EXIT_REASON_UNKNOWN |
6263 KVM_MSR_EXIT_REASON_FILTER))
6265 kvm->arch.user_space_msr_mask = cap->args[0];
6268 case KVM_CAP_X86_BUS_LOCK_EXIT:
6270 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6273 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6274 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6277 if (kvm_caps.has_bus_lock_exit &&
6278 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6279 kvm->arch.bus_lock_detection_enabled = true;
6282 #ifdef CONFIG_X86_SGX_KVM
6283 case KVM_CAP_SGX_ATTRIBUTE: {
6284 unsigned long allowed_attributes = 0;
6286 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6290 /* KVM only supports the PROVISIONKEY privileged attribute. */
6291 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6292 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6293 kvm->arch.sgx_provisioning_allowed = true;
6299 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6301 if (!kvm_x86_ops.vm_copy_enc_context_from)
6304 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6306 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6308 if (!kvm_x86_ops.vm_move_enc_context_from)
6311 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6313 case KVM_CAP_EXIT_HYPERCALL:
6314 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6318 kvm->arch.hypercall_exit_enabled = cap->args[0];
6321 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6323 if (cap->args[0] & ~1)
6325 kvm->arch.exit_on_emulation_error = cap->args[0];
6328 case KVM_CAP_PMU_CAPABILITY:
6330 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6333 mutex_lock(&kvm->lock);
6334 if (!kvm->created_vcpus) {
6335 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6338 mutex_unlock(&kvm->lock);
6340 case KVM_CAP_MAX_VCPU_ID:
6342 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6345 mutex_lock(&kvm->lock);
6346 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6348 } else if (!kvm->arch.max_vcpu_ids) {
6349 kvm->arch.max_vcpu_ids = cap->args[0];
6352 mutex_unlock(&kvm->lock);
6354 case KVM_CAP_X86_NOTIFY_VMEXIT:
6356 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6358 if (!kvm_caps.has_notify_vmexit)
6360 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6362 mutex_lock(&kvm->lock);
6363 if (!kvm->created_vcpus) {
6364 kvm->arch.notify_window = cap->args[0] >> 32;
6365 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6368 mutex_unlock(&kvm->lock);
6370 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6374 * Since the risk of disabling NX hugepages is a guest crashing
6375 * the system, ensure the userspace process has permission to
6376 * reboot the system.
6378 * Note that unlike the reboot() syscall, the process must have
6379 * this capability in the root namespace because exposing
6380 * /dev/kvm into a container does not limit the scope of the
6381 * iTLB multihit bug to that container. In other words,
6382 * this must use capable(), not ns_capable().
6384 if (!capable(CAP_SYS_BOOT)) {
6392 mutex_lock(&kvm->lock);
6393 if (!kvm->created_vcpus) {
6394 kvm->arch.disable_nx_huge_pages = true;
6397 mutex_unlock(&kvm->lock);
6406 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6408 struct kvm_x86_msr_filter *msr_filter;
6410 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6414 msr_filter->default_allow = default_allow;
6418 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6425 for (i = 0; i < msr_filter->count; i++)
6426 kfree(msr_filter->ranges[i].bitmap);
6431 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6432 struct kvm_msr_filter_range *user_range)
6434 unsigned long *bitmap = NULL;
6437 if (!user_range->nmsrs)
6440 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6443 if (!user_range->flags)
6446 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6447 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6450 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6452 return PTR_ERR(bitmap);
6454 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6455 .flags = user_range->flags,
6456 .base = user_range->base,
6457 .nmsrs = user_range->nmsrs,
6461 msr_filter->count++;
6465 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6466 struct kvm_msr_filter *filter)
6468 struct kvm_x86_msr_filter *new_filter, *old_filter;
6474 if (filter->flags & ~KVM_MSR_FILTER_DEFAULT_DENY)
6477 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6478 empty &= !filter->ranges[i].nmsrs;
6480 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6481 if (empty && !default_allow)
6484 new_filter = kvm_alloc_msr_filter(default_allow);
6488 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6489 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6491 kvm_free_msr_filter(new_filter);
6496 mutex_lock(&kvm->lock);
6498 /* The per-VM filter is protected by kvm->lock... */
6499 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6501 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6502 synchronize_srcu(&kvm->srcu);
6504 kvm_free_msr_filter(old_filter);
6506 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6507 mutex_unlock(&kvm->lock);
6512 #ifdef CONFIG_KVM_COMPAT
6513 /* for KVM_X86_SET_MSR_FILTER */
6514 struct kvm_msr_filter_range_compat {
6521 struct kvm_msr_filter_compat {
6523 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6526 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6528 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6531 void __user *argp = (void __user *)arg;
6532 struct kvm *kvm = filp->private_data;
6536 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6537 struct kvm_msr_filter __user *user_msr_filter = argp;
6538 struct kvm_msr_filter_compat filter_compat;
6539 struct kvm_msr_filter filter;
6542 if (copy_from_user(&filter_compat, user_msr_filter,
6543 sizeof(filter_compat)))
6546 filter.flags = filter_compat.flags;
6547 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6548 struct kvm_msr_filter_range_compat *cr;
6550 cr = &filter_compat.ranges[i];
6551 filter.ranges[i] = (struct kvm_msr_filter_range) {
6555 .bitmap = (__u8 *)(ulong)cr->bitmap,
6559 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6568 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6569 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6571 struct kvm_vcpu *vcpu;
6575 mutex_lock(&kvm->lock);
6576 kvm_for_each_vcpu(i, vcpu, kvm) {
6577 if (!vcpu->arch.pv_time.active)
6580 ret = kvm_set_guest_paused(vcpu);
6582 kvm_err("Failed to pause guest VCPU%d: %d\n",
6583 vcpu->vcpu_id, ret);
6587 mutex_unlock(&kvm->lock);
6589 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6592 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6595 case PM_HIBERNATION_PREPARE:
6596 case PM_SUSPEND_PREPARE:
6597 return kvm_arch_suspend_notifier(kvm);
6602 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6604 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6606 struct kvm_clock_data data = { 0 };
6608 get_kvmclock(kvm, &data);
6609 if (copy_to_user(argp, &data, sizeof(data)))
6615 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6617 struct kvm_arch *ka = &kvm->arch;
6618 struct kvm_clock_data data;
6621 if (copy_from_user(&data, argp, sizeof(data)))
6625 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6626 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6628 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6631 kvm_hv_request_tsc_page_update(kvm);
6632 kvm_start_pvclock_update(kvm);
6633 pvclock_update_vm_gtod_copy(kvm);
6636 * This pairs with kvm_guest_time_update(): when masterclock is
6637 * in use, we use master_kernel_ns + kvmclock_offset to set
6638 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6639 * is slightly ahead) here we risk going negative on unsigned
6640 * 'system_time' when 'data.clock' is very small.
6642 if (data.flags & KVM_CLOCK_REALTIME) {
6643 u64 now_real_ns = ktime_get_real_ns();
6646 * Avoid stepping the kvmclock backwards.
6648 if (now_real_ns > data.realtime)
6649 data.clock += now_real_ns - data.realtime;
6652 if (ka->use_master_clock)
6653 now_raw_ns = ka->master_kernel_ns;
6655 now_raw_ns = get_kvmclock_base_ns();
6656 ka->kvmclock_offset = data.clock - now_raw_ns;
6657 kvm_end_pvclock_update(kvm);
6661 long kvm_arch_vm_ioctl(struct file *filp,
6662 unsigned int ioctl, unsigned long arg)
6664 struct kvm *kvm = filp->private_data;
6665 void __user *argp = (void __user *)arg;
6668 * This union makes it completely explicit to gcc-3.x
6669 * that these two variables' stack usage should be
6670 * combined, not added together.
6673 struct kvm_pit_state ps;
6674 struct kvm_pit_state2 ps2;
6675 struct kvm_pit_config pit_config;
6679 case KVM_SET_TSS_ADDR:
6680 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6682 case KVM_SET_IDENTITY_MAP_ADDR: {
6685 mutex_lock(&kvm->lock);
6687 if (kvm->created_vcpus)
6688 goto set_identity_unlock;
6690 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6691 goto set_identity_unlock;
6692 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6693 set_identity_unlock:
6694 mutex_unlock(&kvm->lock);
6697 case KVM_SET_NR_MMU_PAGES:
6698 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6700 case KVM_GET_NR_MMU_PAGES:
6701 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6703 case KVM_CREATE_IRQCHIP: {
6704 mutex_lock(&kvm->lock);
6707 if (irqchip_in_kernel(kvm))
6708 goto create_irqchip_unlock;
6711 if (kvm->created_vcpus)
6712 goto create_irqchip_unlock;
6714 r = kvm_pic_init(kvm);
6716 goto create_irqchip_unlock;
6718 r = kvm_ioapic_init(kvm);
6720 kvm_pic_destroy(kvm);
6721 goto create_irqchip_unlock;
6724 r = kvm_setup_default_irq_routing(kvm);
6726 kvm_ioapic_destroy(kvm);
6727 kvm_pic_destroy(kvm);
6728 goto create_irqchip_unlock;
6730 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6732 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6733 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6734 create_irqchip_unlock:
6735 mutex_unlock(&kvm->lock);
6738 case KVM_CREATE_PIT:
6739 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6741 case KVM_CREATE_PIT2:
6743 if (copy_from_user(&u.pit_config, argp,
6744 sizeof(struct kvm_pit_config)))
6747 mutex_lock(&kvm->lock);
6750 goto create_pit_unlock;
6752 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6756 mutex_unlock(&kvm->lock);
6758 case KVM_GET_IRQCHIP: {
6759 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6760 struct kvm_irqchip *chip;
6762 chip = memdup_user(argp, sizeof(*chip));
6769 if (!irqchip_kernel(kvm))
6770 goto get_irqchip_out;
6771 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6773 goto get_irqchip_out;
6775 if (copy_to_user(argp, chip, sizeof(*chip)))
6776 goto get_irqchip_out;
6782 case KVM_SET_IRQCHIP: {
6783 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6784 struct kvm_irqchip *chip;
6786 chip = memdup_user(argp, sizeof(*chip));
6793 if (!irqchip_kernel(kvm))
6794 goto set_irqchip_out;
6795 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6802 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6805 if (!kvm->arch.vpit)
6807 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6811 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6818 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6820 mutex_lock(&kvm->lock);
6822 if (!kvm->arch.vpit)
6824 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6826 mutex_unlock(&kvm->lock);
6829 case KVM_GET_PIT2: {
6831 if (!kvm->arch.vpit)
6833 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6837 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6842 case KVM_SET_PIT2: {
6844 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6846 mutex_lock(&kvm->lock);
6848 if (!kvm->arch.vpit)
6850 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6852 mutex_unlock(&kvm->lock);
6855 case KVM_REINJECT_CONTROL: {
6856 struct kvm_reinject_control control;
6858 if (copy_from_user(&control, argp, sizeof(control)))
6861 if (!kvm->arch.vpit)
6863 r = kvm_vm_ioctl_reinject(kvm, &control);
6866 case KVM_SET_BOOT_CPU_ID:
6868 mutex_lock(&kvm->lock);
6869 if (kvm->created_vcpus)
6872 kvm->arch.bsp_vcpu_id = arg;
6873 mutex_unlock(&kvm->lock);
6875 #ifdef CONFIG_KVM_XEN
6876 case KVM_XEN_HVM_CONFIG: {
6877 struct kvm_xen_hvm_config xhc;
6879 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6881 r = kvm_xen_hvm_config(kvm, &xhc);
6884 case KVM_XEN_HVM_GET_ATTR: {
6885 struct kvm_xen_hvm_attr xha;
6888 if (copy_from_user(&xha, argp, sizeof(xha)))
6890 r = kvm_xen_hvm_get_attr(kvm, &xha);
6891 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6895 case KVM_XEN_HVM_SET_ATTR: {
6896 struct kvm_xen_hvm_attr xha;
6899 if (copy_from_user(&xha, argp, sizeof(xha)))
6901 r = kvm_xen_hvm_set_attr(kvm, &xha);
6904 case KVM_XEN_HVM_EVTCHN_SEND: {
6905 struct kvm_irq_routing_xen_evtchn uxe;
6908 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6910 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6915 r = kvm_vm_ioctl_set_clock(kvm, argp);
6918 r = kvm_vm_ioctl_get_clock(kvm, argp);
6920 case KVM_SET_TSC_KHZ: {
6924 user_tsc_khz = (u32)arg;
6926 if (kvm_caps.has_tsc_control &&
6927 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6930 if (user_tsc_khz == 0)
6931 user_tsc_khz = tsc_khz;
6933 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6938 case KVM_GET_TSC_KHZ: {
6939 r = READ_ONCE(kvm->arch.default_tsc_khz);
6942 case KVM_MEMORY_ENCRYPT_OP: {
6944 if (!kvm_x86_ops.mem_enc_ioctl)
6947 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6950 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6951 struct kvm_enc_region region;
6954 if (copy_from_user(®ion, argp, sizeof(region)))
6958 if (!kvm_x86_ops.mem_enc_register_region)
6961 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6964 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6965 struct kvm_enc_region region;
6968 if (copy_from_user(®ion, argp, sizeof(region)))
6972 if (!kvm_x86_ops.mem_enc_unregister_region)
6975 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6978 case KVM_HYPERV_EVENTFD: {
6979 struct kvm_hyperv_eventfd hvevfd;
6982 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6984 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6987 case KVM_SET_PMU_EVENT_FILTER:
6988 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6990 case KVM_X86_SET_MSR_FILTER: {
6991 struct kvm_msr_filter __user *user_msr_filter = argp;
6992 struct kvm_msr_filter filter;
6994 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6997 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7007 static void kvm_init_msr_list(void)
7012 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7013 "Please update the fixed PMCs in msrs_to_saved_all[]");
7015 num_msrs_to_save = 0;
7016 num_emulated_msrs = 0;
7017 num_msr_based_features = 0;
7019 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
7020 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
7024 * Even MSRs that are valid in the host may not be exposed
7025 * to the guests in some cases.
7027 switch (msrs_to_save_all[i]) {
7028 case MSR_IA32_BNDCFGS:
7029 if (!kvm_mpx_supported())
7033 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7034 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7037 case MSR_IA32_UMWAIT_CONTROL:
7038 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7041 case MSR_IA32_RTIT_CTL:
7042 case MSR_IA32_RTIT_STATUS:
7043 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7046 case MSR_IA32_RTIT_CR3_MATCH:
7047 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7048 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7051 case MSR_IA32_RTIT_OUTPUT_BASE:
7052 case MSR_IA32_RTIT_OUTPUT_MASK:
7053 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7054 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7055 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7058 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7059 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7060 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
7061 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
7064 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7065 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
7066 min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
7069 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7070 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
7071 min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
7075 case MSR_IA32_XFD_ERR:
7076 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7083 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
7086 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7087 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7090 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7093 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
7094 struct kvm_msr_entry msr;
7096 msr.index = msr_based_features_all[i];
7097 if (kvm_get_msr_feature(&msr))
7100 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
7104 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7112 if (!(lapic_in_kernel(vcpu) &&
7113 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7114 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7125 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7132 if (!(lapic_in_kernel(vcpu) &&
7133 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7135 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7137 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7147 static void kvm_set_segment(struct kvm_vcpu *vcpu,
7148 struct kvm_segment *var, int seg)
7150 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7153 void kvm_get_segment(struct kvm_vcpu *vcpu,
7154 struct kvm_segment *var, int seg)
7156 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7159 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7160 struct x86_exception *exception)
7162 struct kvm_mmu *mmu = vcpu->arch.mmu;
7165 BUG_ON(!mmu_is_nested(vcpu));
7167 /* NPT walks are always user-walks */
7168 access |= PFERR_USER_MASK;
7169 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7174 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7175 struct x86_exception *exception)
7177 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7179 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7180 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7182 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7184 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
7185 struct x86_exception *exception)
7187 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7189 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7190 access |= PFERR_FETCH_MASK;
7191 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7194 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7195 struct x86_exception *exception)
7197 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7199 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7200 access |= PFERR_WRITE_MASK;
7201 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7203 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7205 /* uses this to access any guest's mapped memory without checking CPL */
7206 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7207 struct x86_exception *exception)
7209 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7211 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7214 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7215 struct kvm_vcpu *vcpu, u64 access,
7216 struct x86_exception *exception)
7218 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7220 int r = X86EMUL_CONTINUE;
7223 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7224 unsigned offset = addr & (PAGE_SIZE-1);
7225 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7228 if (gpa == INVALID_GPA)
7229 return X86EMUL_PROPAGATE_FAULT;
7230 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7233 r = X86EMUL_IO_NEEDED;
7245 /* used for instruction fetching */
7246 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7247 gva_t addr, void *val, unsigned int bytes,
7248 struct x86_exception *exception)
7250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7251 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7252 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7256 /* Inline kvm_read_guest_virt_helper for speed. */
7257 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7259 if (unlikely(gpa == INVALID_GPA))
7260 return X86EMUL_PROPAGATE_FAULT;
7262 offset = addr & (PAGE_SIZE-1);
7263 if (WARN_ON(offset + bytes > PAGE_SIZE))
7264 bytes = (unsigned)PAGE_SIZE - offset;
7265 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7267 if (unlikely(ret < 0))
7268 return X86EMUL_IO_NEEDED;
7270 return X86EMUL_CONTINUE;
7273 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7274 gva_t addr, void *val, unsigned int bytes,
7275 struct x86_exception *exception)
7277 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7280 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7281 * is returned, but our callers are not ready for that and they blindly
7282 * call kvm_inject_page_fault. Ensure that they at least do not leak
7283 * uninitialized kernel stack memory into cr2 and error code.
7285 memset(exception, 0, sizeof(*exception));
7286 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7289 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7291 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7292 gva_t addr, void *val, unsigned int bytes,
7293 struct x86_exception *exception, bool system)
7295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7299 access |= PFERR_IMPLICIT_ACCESS;
7300 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7301 access |= PFERR_USER_MASK;
7303 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7306 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
7307 unsigned long addr, void *val, unsigned int bytes)
7309 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7310 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
7312 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
7315 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7316 struct kvm_vcpu *vcpu, u64 access,
7317 struct x86_exception *exception)
7319 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7321 int r = X86EMUL_CONTINUE;
7324 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7325 unsigned offset = addr & (PAGE_SIZE-1);
7326 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7329 if (gpa == INVALID_GPA)
7330 return X86EMUL_PROPAGATE_FAULT;
7331 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7333 r = X86EMUL_IO_NEEDED;
7345 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7346 unsigned int bytes, struct x86_exception *exception,
7349 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7350 u64 access = PFERR_WRITE_MASK;
7353 access |= PFERR_IMPLICIT_ACCESS;
7354 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7355 access |= PFERR_USER_MASK;
7357 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7361 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7362 unsigned int bytes, struct x86_exception *exception)
7364 /* kvm_write_guest_virt_system can pull in tons of pages. */
7365 vcpu->arch.l1tf_flush_l1d = true;
7367 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7368 PFERR_WRITE_MASK, exception);
7370 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7372 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7373 void *insn, int insn_len)
7375 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7379 int handle_ud(struct kvm_vcpu *vcpu)
7381 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7382 int fep_flags = READ_ONCE(force_emulation_prefix);
7383 int emul_type = EMULTYPE_TRAP_UD;
7384 char sig[5]; /* ud2; .ascii "kvm" */
7385 struct x86_exception e;
7387 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7391 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7392 sig, sizeof(sig), &e) == 0 &&
7393 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7394 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7395 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7396 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7397 emul_type = EMULTYPE_TRAP_UD_FORCED;
7400 return kvm_emulate_instruction(vcpu, emul_type);
7402 EXPORT_SYMBOL_GPL(handle_ud);
7404 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7405 gpa_t gpa, bool write)
7407 /* For APIC access vmexit */
7408 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7411 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7412 trace_vcpu_match_mmio(gva, gpa, write, true);
7419 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7420 gpa_t *gpa, struct x86_exception *exception,
7423 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7424 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7425 | (write ? PFERR_WRITE_MASK : 0);
7428 * currently PKRU is only applied to ept enabled guest so
7429 * there is no pkey in EPT page table for L1 guest or EPT
7430 * shadow page table for L2 guest.
7432 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7433 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7434 vcpu->arch.mmio_access, 0, access))) {
7435 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7436 (gva & (PAGE_SIZE - 1));
7437 trace_vcpu_match_mmio(gva, *gpa, write, false);
7441 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7443 if (*gpa == INVALID_GPA)
7446 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7449 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7450 const void *val, int bytes)
7454 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7457 kvm_page_track_write(vcpu, gpa, val, bytes);
7461 struct read_write_emulator_ops {
7462 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7464 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7465 void *val, int bytes);
7466 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7467 int bytes, void *val);
7468 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7469 void *val, int bytes);
7473 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7475 if (vcpu->mmio_read_completed) {
7476 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7477 vcpu->mmio_fragments[0].gpa, val);
7478 vcpu->mmio_read_completed = 0;
7485 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7486 void *val, int bytes)
7488 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7491 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7492 void *val, int bytes)
7494 return emulator_write_phys(vcpu, gpa, val, bytes);
7497 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7499 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7500 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7503 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7504 void *val, int bytes)
7506 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7507 return X86EMUL_IO_NEEDED;
7510 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7511 void *val, int bytes)
7513 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7515 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7516 return X86EMUL_CONTINUE;
7519 static const struct read_write_emulator_ops read_emultor = {
7520 .read_write_prepare = read_prepare,
7521 .read_write_emulate = read_emulate,
7522 .read_write_mmio = vcpu_mmio_read,
7523 .read_write_exit_mmio = read_exit_mmio,
7526 static const struct read_write_emulator_ops write_emultor = {
7527 .read_write_emulate = write_emulate,
7528 .read_write_mmio = write_mmio,
7529 .read_write_exit_mmio = write_exit_mmio,
7533 static int emulator_read_write_onepage(unsigned long addr, void *val,
7535 struct x86_exception *exception,
7536 struct kvm_vcpu *vcpu,
7537 const struct read_write_emulator_ops *ops)
7541 bool write = ops->write;
7542 struct kvm_mmio_fragment *frag;
7543 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7546 * If the exit was due to a NPF we may already have a GPA.
7547 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7548 * Note, this cannot be used on string operations since string
7549 * operation using rep will only have the initial GPA from the NPF
7552 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7553 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7554 gpa = ctxt->gpa_val;
7555 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7557 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7559 return X86EMUL_PROPAGATE_FAULT;
7562 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7563 return X86EMUL_CONTINUE;
7566 * Is this MMIO handled locally?
7568 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7569 if (handled == bytes)
7570 return X86EMUL_CONTINUE;
7576 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7577 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7581 return X86EMUL_CONTINUE;
7584 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7586 void *val, unsigned int bytes,
7587 struct x86_exception *exception,
7588 const struct read_write_emulator_ops *ops)
7590 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7594 if (ops->read_write_prepare &&
7595 ops->read_write_prepare(vcpu, val, bytes))
7596 return X86EMUL_CONTINUE;
7598 vcpu->mmio_nr_fragments = 0;
7600 /* Crossing a page boundary? */
7601 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7604 now = -addr & ~PAGE_MASK;
7605 rc = emulator_read_write_onepage(addr, val, now, exception,
7608 if (rc != X86EMUL_CONTINUE)
7611 if (ctxt->mode != X86EMUL_MODE_PROT64)
7617 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7619 if (rc != X86EMUL_CONTINUE)
7622 if (!vcpu->mmio_nr_fragments)
7625 gpa = vcpu->mmio_fragments[0].gpa;
7627 vcpu->mmio_needed = 1;
7628 vcpu->mmio_cur_fragment = 0;
7630 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7631 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7632 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7633 vcpu->run->mmio.phys_addr = gpa;
7635 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7638 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7642 struct x86_exception *exception)
7644 return emulator_read_write(ctxt, addr, val, bytes,
7645 exception, &read_emultor);
7648 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7652 struct x86_exception *exception)
7654 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7655 exception, &write_emultor);
7658 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7659 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7661 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7666 struct x86_exception *exception)
7668 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7674 /* guests cmpxchg8b have to be emulated atomically */
7675 if (bytes > 8 || (bytes & (bytes - 1)))
7678 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7680 if (gpa == INVALID_GPA ||
7681 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7685 * Emulate the atomic as a straight write to avoid #AC if SLD is
7686 * enabled in the host and the access splits a cache line.
7688 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7689 page_line_mask = ~(cache_line_size() - 1);
7691 page_line_mask = PAGE_MASK;
7693 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7696 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7697 if (kvm_is_error_hva(hva))
7700 hva += offset_in_page(gpa);
7704 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7707 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7710 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7713 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7720 return X86EMUL_UNHANDLEABLE;
7722 return X86EMUL_CMPXCHG_FAILED;
7724 kvm_page_track_write(vcpu, gpa, new, bytes);
7726 return X86EMUL_CONTINUE;
7729 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7731 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7734 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7735 unsigned short port, void *data,
7736 unsigned int count, bool in)
7741 WARN_ON_ONCE(vcpu->arch.pio.count);
7742 for (i = 0; i < count; i++) {
7744 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7746 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7753 * Userspace must have unregistered the device while PIO
7754 * was running. Drop writes / read as 0.
7757 memset(data, 0, size * (count - i));
7766 vcpu->arch.pio.port = port;
7767 vcpu->arch.pio.in = in;
7768 vcpu->arch.pio.count = count;
7769 vcpu->arch.pio.size = size;
7772 memset(vcpu->arch.pio_data, 0, size * count);
7774 memcpy(vcpu->arch.pio_data, data, size * count);
7776 vcpu->run->exit_reason = KVM_EXIT_IO;
7777 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7778 vcpu->run->io.size = size;
7779 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7780 vcpu->run->io.count = count;
7781 vcpu->run->io.port = port;
7785 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7786 unsigned short port, void *val, unsigned int count)
7788 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7790 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7795 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7797 int size = vcpu->arch.pio.size;
7798 unsigned int count = vcpu->arch.pio.count;
7799 memcpy(val, vcpu->arch.pio_data, size * count);
7800 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7801 vcpu->arch.pio.count = 0;
7804 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7805 int size, unsigned short port, void *val,
7808 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7809 if (vcpu->arch.pio.count) {
7811 * Complete a previous iteration that required userspace I/O.
7812 * Note, @count isn't guaranteed to match pio.count as userspace
7813 * can modify ECX before rerunning the vCPU. Ignore any such
7814 * shenanigans as KVM doesn't support modifying the rep count,
7815 * and the emulator ensures @count doesn't overflow the buffer.
7817 complete_emulator_pio_in(vcpu, val);
7821 return emulator_pio_in(vcpu, size, port, val, count);
7824 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7825 unsigned short port, const void *val,
7828 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7829 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7832 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7833 int size, unsigned short port,
7834 const void *val, unsigned int count)
7836 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7839 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7841 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7844 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7846 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7849 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7851 if (!need_emulate_wbinvd(vcpu))
7852 return X86EMUL_CONTINUE;
7854 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7855 int cpu = get_cpu();
7857 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7858 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7859 wbinvd_ipi, NULL, 1);
7861 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7864 return X86EMUL_CONTINUE;
7867 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7869 kvm_emulate_wbinvd_noskip(vcpu);
7870 return kvm_skip_emulated_instruction(vcpu);
7872 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7876 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7878 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7881 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7882 unsigned long *dest)
7884 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7887 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7888 unsigned long value)
7891 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7894 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7896 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7899 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7902 unsigned long value;
7906 value = kvm_read_cr0(vcpu);
7909 value = vcpu->arch.cr2;
7912 value = kvm_read_cr3(vcpu);
7915 value = kvm_read_cr4(vcpu);
7918 value = kvm_get_cr8(vcpu);
7921 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7928 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7930 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7935 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7938 vcpu->arch.cr2 = val;
7941 res = kvm_set_cr3(vcpu, val);
7944 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7947 res = kvm_set_cr8(vcpu, val);
7950 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7957 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7959 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7962 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7964 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7967 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7969 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7972 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7974 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7977 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7979 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7982 static unsigned long emulator_get_cached_segment_base(
7983 struct x86_emulate_ctxt *ctxt, int seg)
7985 return get_segment_base(emul_to_vcpu(ctxt), seg);
7988 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7989 struct desc_struct *desc, u32 *base3,
7992 struct kvm_segment var;
7994 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7995 *selector = var.selector;
7998 memset(desc, 0, sizeof(*desc));
8006 set_desc_limit(desc, var.limit);
8007 set_desc_base(desc, (unsigned long)var.base);
8008 #ifdef CONFIG_X86_64
8010 *base3 = var.base >> 32;
8012 desc->type = var.type;
8014 desc->dpl = var.dpl;
8015 desc->p = var.present;
8016 desc->avl = var.avl;
8024 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8025 struct desc_struct *desc, u32 base3,
8028 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8029 struct kvm_segment var;
8031 var.selector = selector;
8032 var.base = get_desc_base(desc);
8033 #ifdef CONFIG_X86_64
8034 var.base |= ((u64)base3) << 32;
8036 var.limit = get_desc_limit(desc);
8038 var.limit = (var.limit << 12) | 0xfff;
8039 var.type = desc->type;
8040 var.dpl = desc->dpl;
8045 var.avl = desc->avl;
8046 var.present = desc->p;
8047 var.unusable = !var.present;
8050 kvm_set_segment(vcpu, &var, seg);
8054 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8055 u32 msr_index, u64 *pdata)
8057 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8060 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8062 return X86EMUL_UNHANDLEABLE;
8065 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8066 complete_emulated_rdmsr, r))
8067 return X86EMUL_IO_NEEDED;
8069 trace_kvm_msr_read_ex(msr_index);
8070 return X86EMUL_PROPAGATE_FAULT;
8073 trace_kvm_msr_read(msr_index, *pdata);
8074 return X86EMUL_CONTINUE;
8077 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8078 u32 msr_index, u64 data)
8080 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8083 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8085 return X86EMUL_UNHANDLEABLE;
8088 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8089 complete_emulated_msr_access, r))
8090 return X86EMUL_IO_NEEDED;
8092 trace_kvm_msr_write_ex(msr_index, data);
8093 return X86EMUL_PROPAGATE_FAULT;
8096 trace_kvm_msr_write(msr_index, data);
8097 return X86EMUL_CONTINUE;
8100 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8101 u32 msr_index, u64 *pdata)
8103 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8106 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
8107 u32 msr_index, u64 data)
8109 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
8112 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
8114 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8116 return vcpu->arch.smbase;
8119 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
8121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8123 vcpu->arch.smbase = smbase;
8126 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8129 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8134 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8135 u32 pmc, u64 *pdata)
8137 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8140 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8142 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8145 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8146 struct x86_instruction_info *info,
8147 enum x86_intercept_stage stage)
8149 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8153 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8154 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8157 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8160 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8162 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8165 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8167 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8170 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8172 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8175 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8177 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8180 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8182 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8185 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8187 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8190 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8192 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8195 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
8197 return emul_to_vcpu(ctxt)->arch.hflags;
8200 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
8202 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8204 kvm_smm_changed(vcpu, false);
8207 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
8208 const char *smstate)
8210 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
8213 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8215 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8218 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8220 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8223 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8225 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8227 if (!kvm->vm_bugged)
8231 static const struct x86_emulate_ops emulate_ops = {
8232 .vm_bugged = emulator_vm_bugged,
8233 .read_gpr = emulator_read_gpr,
8234 .write_gpr = emulator_write_gpr,
8235 .read_std = emulator_read_std,
8236 .write_std = emulator_write_std,
8237 .read_phys = kvm_read_guest_phys_system,
8238 .fetch = kvm_fetch_guest_virt,
8239 .read_emulated = emulator_read_emulated,
8240 .write_emulated = emulator_write_emulated,
8241 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8242 .invlpg = emulator_invlpg,
8243 .pio_in_emulated = emulator_pio_in_emulated,
8244 .pio_out_emulated = emulator_pio_out_emulated,
8245 .get_segment = emulator_get_segment,
8246 .set_segment = emulator_set_segment,
8247 .get_cached_segment_base = emulator_get_cached_segment_base,
8248 .get_gdt = emulator_get_gdt,
8249 .get_idt = emulator_get_idt,
8250 .set_gdt = emulator_set_gdt,
8251 .set_idt = emulator_set_idt,
8252 .get_cr = emulator_get_cr,
8253 .set_cr = emulator_set_cr,
8254 .cpl = emulator_get_cpl,
8255 .get_dr = emulator_get_dr,
8256 .set_dr = emulator_set_dr,
8257 .get_smbase = emulator_get_smbase,
8258 .set_smbase = emulator_set_smbase,
8259 .set_msr_with_filter = emulator_set_msr_with_filter,
8260 .get_msr_with_filter = emulator_get_msr_with_filter,
8261 .set_msr = emulator_set_msr,
8262 .get_msr = emulator_get_msr,
8263 .check_pmc = emulator_check_pmc,
8264 .read_pmc = emulator_read_pmc,
8265 .halt = emulator_halt,
8266 .wbinvd = emulator_wbinvd,
8267 .fix_hypercall = emulator_fix_hypercall,
8268 .intercept = emulator_intercept,
8269 .get_cpuid = emulator_get_cpuid,
8270 .guest_has_long_mode = emulator_guest_has_long_mode,
8271 .guest_has_movbe = emulator_guest_has_movbe,
8272 .guest_has_fxsr = emulator_guest_has_fxsr,
8273 .guest_has_rdpid = emulator_guest_has_rdpid,
8274 .set_nmi_mask = emulator_set_nmi_mask,
8275 .get_hflags = emulator_get_hflags,
8276 .exiting_smm = emulator_exiting_smm,
8277 .leave_smm = emulator_leave_smm,
8278 .triple_fault = emulator_triple_fault,
8279 .set_xcr = emulator_set_xcr,
8282 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8284 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8286 * an sti; sti; sequence only disable interrupts for the first
8287 * instruction. So, if the last instruction, be it emulated or
8288 * not, left the system with the INT_STI flag enabled, it
8289 * means that the last instruction is an sti. We should not
8290 * leave the flag on in this case. The same goes for mov ss
8292 if (int_shadow & mask)
8294 if (unlikely(int_shadow || mask)) {
8295 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8297 kvm_make_request(KVM_REQ_EVENT, vcpu);
8301 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8303 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8305 if (ctxt->exception.vector == PF_VECTOR)
8306 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8307 else if (ctxt->exception.error_code_valid)
8308 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8309 ctxt->exception.error_code);
8311 kvm_queue_exception(vcpu, ctxt->exception.vector);
8314 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8316 struct x86_emulate_ctxt *ctxt;
8318 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8320 pr_err("kvm: failed to allocate vcpu's emulator\n");
8325 ctxt->ops = &emulate_ops;
8326 vcpu->arch.emulate_ctxt = ctxt;
8331 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8333 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8336 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8338 ctxt->gpa_available = false;
8339 ctxt->eflags = kvm_get_rflags(vcpu);
8340 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8342 ctxt->eip = kvm_rip_read(vcpu);
8343 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8344 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8345 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8346 cs_db ? X86EMUL_MODE_PROT32 :
8347 X86EMUL_MODE_PROT16;
8348 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
8349 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
8350 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
8352 ctxt->interruptibility = 0;
8353 ctxt->have_exception = false;
8354 ctxt->exception.vector = -1;
8355 ctxt->perm_ok = false;
8357 init_decode_cache(ctxt);
8358 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8361 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8363 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8366 init_emulate_ctxt(vcpu);
8370 ctxt->_eip = ctxt->eip + inc_eip;
8371 ret = emulate_int_real(ctxt, irq);
8373 if (ret != X86EMUL_CONTINUE) {
8374 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8376 ctxt->eip = ctxt->_eip;
8377 kvm_rip_write(vcpu, ctxt->eip);
8378 kvm_set_rflags(vcpu, ctxt->eflags);
8381 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8383 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8384 u8 ndata, u8 *insn_bytes, u8 insn_size)
8386 struct kvm_run *run = vcpu->run;
8391 * Zero the whole array used to retrieve the exit info, as casting to
8392 * u32 for select entries will leave some chunks uninitialized.
8394 memset(&info, 0, sizeof(info));
8396 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8397 &info[2], (u32 *)&info[3],
8400 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8401 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8404 * There's currently space for 13 entries, but 5 are used for the exit
8405 * reason and info. Restrict to 4 to reduce the maintenance burden
8406 * when expanding kvm_run.emulation_failure in the future.
8408 if (WARN_ON_ONCE(ndata > 4))
8411 /* Always include the flags as a 'data' entry. */
8413 run->emulation_failure.flags = 0;
8416 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8417 sizeof(run->emulation_failure.insn_bytes) != 16));
8419 run->emulation_failure.flags |=
8420 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8421 run->emulation_failure.insn_size = insn_size;
8422 memset(run->emulation_failure.insn_bytes, 0x90,
8423 sizeof(run->emulation_failure.insn_bytes));
8424 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8427 memcpy(&run->internal.data[info_start], info, sizeof(info));
8428 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8429 ndata * sizeof(data[0]));
8431 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8434 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8436 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8438 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8439 ctxt->fetch.end - ctxt->fetch.data);
8442 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8445 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8447 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8449 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8451 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8453 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8455 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8457 struct kvm *kvm = vcpu->kvm;
8459 ++vcpu->stat.insn_emulation_fail;
8460 trace_kvm_emulate_insn_failed(vcpu);
8462 if (emulation_type & EMULTYPE_VMWARE_GP) {
8463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8467 if (kvm->arch.exit_on_emulation_error ||
8468 (emulation_type & EMULTYPE_SKIP)) {
8469 prepare_emulation_ctxt_failure_exit(vcpu);
8473 kvm_queue_exception(vcpu, UD_VECTOR);
8475 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8476 prepare_emulation_ctxt_failure_exit(vcpu);
8483 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8484 bool write_fault_to_shadow_pgtable,
8487 gpa_t gpa = cr2_or_gpa;
8490 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8493 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8494 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8497 if (!vcpu->arch.mmu->root_role.direct) {
8499 * Write permission should be allowed since only
8500 * write access need to be emulated.
8502 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8505 * If the mapping is invalid in guest, let cpu retry
8506 * it to generate fault.
8508 if (gpa == INVALID_GPA)
8513 * Do not retry the unhandleable instruction if it faults on the
8514 * readonly host memory, otherwise it will goto a infinite loop:
8515 * retry instruction -> write #PF -> emulation fail -> retry
8516 * instruction -> ...
8518 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8521 * If the instruction failed on the error pfn, it can not be fixed,
8522 * report the error to userspace.
8524 if (is_error_noslot_pfn(pfn))
8527 kvm_release_pfn_clean(pfn);
8529 /* The instructions are well-emulated on direct mmu. */
8530 if (vcpu->arch.mmu->root_role.direct) {
8531 unsigned int indirect_shadow_pages;
8533 write_lock(&vcpu->kvm->mmu_lock);
8534 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8535 write_unlock(&vcpu->kvm->mmu_lock);
8537 if (indirect_shadow_pages)
8538 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8544 * if emulation was due to access to shadowed page table
8545 * and it failed try to unshadow page and re-enter the
8546 * guest to let CPU execute the instruction.
8548 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8551 * If the access faults on its page table, it can not
8552 * be fixed by unprotecting shadow page and it should
8553 * be reported to userspace.
8555 return !write_fault_to_shadow_pgtable;
8558 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8559 gpa_t cr2_or_gpa, int emulation_type)
8561 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8562 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8564 last_retry_eip = vcpu->arch.last_retry_eip;
8565 last_retry_addr = vcpu->arch.last_retry_addr;
8568 * If the emulation is caused by #PF and it is non-page_table
8569 * writing instruction, it means the VM-EXIT is caused by shadow
8570 * page protected, we can zap the shadow page and retry this
8571 * instruction directly.
8573 * Note: if the guest uses a non-page-table modifying instruction
8574 * on the PDE that points to the instruction, then we will unmap
8575 * the instruction and go to an infinite loop. So, we cache the
8576 * last retried eip and the last fault address, if we meet the eip
8577 * and the address again, we can break out of the potential infinite
8580 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8582 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8585 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8586 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8589 if (x86_page_table_writing_insn(ctxt))
8592 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8595 vcpu->arch.last_retry_eip = ctxt->eip;
8596 vcpu->arch.last_retry_addr = cr2_or_gpa;
8598 if (!vcpu->arch.mmu->root_role.direct)
8599 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8601 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8606 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8607 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8609 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8611 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8614 vcpu->arch.hflags |= HF_SMM_MASK;
8616 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8618 /* Process a latched INIT or SMI, if any. */
8619 kvm_make_request(KVM_REQ_EVENT, vcpu);
8622 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8623 * on SMM exit we still need to reload them from
8626 vcpu->arch.pdptrs_from_userspace = false;
8629 kvm_mmu_reset_context(vcpu);
8632 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8641 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8642 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8647 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8649 struct kvm_run *kvm_run = vcpu->run;
8651 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8652 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8653 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8654 kvm_run->debug.arch.exception = DB_VECTOR;
8655 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8658 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8662 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8664 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8667 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8671 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8674 * rflags is the old, "raw" value of the flags. The new value has
8675 * not been saved yet.
8677 * This is correct even for TF set by the guest, because "the
8678 * processor will not generate this exception after the instruction
8679 * that sets the TF flag".
8681 if (unlikely(rflags & X86_EFLAGS_TF))
8682 r = kvm_vcpu_do_singlestep(vcpu);
8685 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8687 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8691 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8695 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8696 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8697 * to avoid the relatively expensive CPUID lookup.
8699 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8700 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8701 guest_cpuid_is_intel(vcpu);
8704 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8705 int emulation_type, int *r)
8707 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8710 * Do not check for code breakpoints if hardware has already done the
8711 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8712 * the instruction has passed all exception checks, and all intercepted
8713 * exceptions that trigger emulation have lower priority than code
8714 * breakpoints, i.e. the fact that the intercepted exception occurred
8715 * means any code breakpoints have already been serviced.
8717 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8718 * hardware has checked the RIP of the magic prefix, but not the RIP of
8719 * the instruction being emulated. The intent of forced emulation is
8720 * to behave as if KVM intercepted the instruction without an exception
8721 * and without a prefix.
8723 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8724 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8727 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8728 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8729 struct kvm_run *kvm_run = vcpu->run;
8730 unsigned long eip = kvm_get_linear_rip(vcpu);
8731 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8732 vcpu->arch.guest_debug_dr7,
8736 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8737 kvm_run->debug.arch.pc = eip;
8738 kvm_run->debug.arch.exception = DB_VECTOR;
8739 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8745 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8746 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8747 unsigned long eip = kvm_get_linear_rip(vcpu);
8748 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8753 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8762 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8764 switch (ctxt->opcode_len) {
8771 case 0xe6: /* OUT */
8775 case 0x6c: /* INS */
8777 case 0x6e: /* OUTS */
8784 case 0x33: /* RDPMC */
8794 * Decode an instruction for emulation. The caller is responsible for handling
8795 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8796 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8797 * code breakpoints have higher priority and thus have already been done by
8800 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8801 * response to a machine check.
8803 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8804 void *insn, int insn_len)
8806 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8809 init_emulate_ctxt(vcpu);
8811 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8813 trace_kvm_emulate_insn_start(vcpu);
8814 ++vcpu->stat.insn_emulation;
8818 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8820 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8821 int emulation_type, void *insn, int insn_len)
8824 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8825 bool writeback = true;
8826 bool write_fault_to_spt;
8828 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8831 vcpu->arch.l1tf_flush_l1d = true;
8834 * Clear write_fault_to_shadow_pgtable here to ensure it is
8837 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8838 vcpu->arch.write_fault_to_shadow_pgtable = false;
8840 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8841 kvm_clear_exception_queue(vcpu);
8844 * Return immediately if RIP hits a code breakpoint, such #DBs
8845 * are fault-like and are higher priority than any faults on
8846 * the code fetch itself.
8848 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8851 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8853 if (r != EMULATION_OK) {
8854 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8855 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8856 kvm_queue_exception(vcpu, UD_VECTOR);
8859 if (reexecute_instruction(vcpu, cr2_or_gpa,
8864 if (ctxt->have_exception &&
8865 !(emulation_type & EMULTYPE_SKIP)) {
8867 * #UD should result in just EMULATION_FAILED, and trap-like
8868 * exception should not be encountered during decode.
8870 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8871 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8872 inject_emulated_exception(vcpu);
8875 return handle_emulation_failure(vcpu, emulation_type);
8879 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8880 !is_vmware_backdoor_opcode(ctxt)) {
8881 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8886 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8887 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8888 * The caller is responsible for updating interruptibility state and
8889 * injecting single-step #DBs.
8891 if (emulation_type & EMULTYPE_SKIP) {
8892 if (ctxt->mode != X86EMUL_MODE_PROT64)
8893 ctxt->eip = (u32)ctxt->_eip;
8895 ctxt->eip = ctxt->_eip;
8897 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8902 kvm_rip_write(vcpu, ctxt->eip);
8903 if (ctxt->eflags & X86_EFLAGS_RF)
8904 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8908 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8911 /* this is needed for vmware backdoor interface to work since it
8912 changes registers values during IO operation */
8913 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8914 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8915 emulator_invalidate_register_cache(ctxt);
8919 if (emulation_type & EMULTYPE_PF) {
8920 /* Save the faulting GPA (cr2) in the address field */
8921 ctxt->exception.address = cr2_or_gpa;
8923 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8924 if (vcpu->arch.mmu->root_role.direct) {
8925 ctxt->gpa_available = true;
8926 ctxt->gpa_val = cr2_or_gpa;
8929 /* Sanitize the address out of an abundance of paranoia. */
8930 ctxt->exception.address = 0;
8933 r = x86_emulate_insn(ctxt);
8935 if (r == EMULATION_INTERCEPTED)
8938 if (r == EMULATION_FAILED) {
8939 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8943 return handle_emulation_failure(vcpu, emulation_type);
8946 if (ctxt->have_exception) {
8948 inject_emulated_exception(vcpu);
8949 } else if (vcpu->arch.pio.count) {
8950 if (!vcpu->arch.pio.in) {
8951 /* FIXME: return into emulator if single-stepping. */
8952 vcpu->arch.pio.count = 0;
8955 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8958 } else if (vcpu->mmio_needed) {
8959 ++vcpu->stat.mmio_exits;
8961 if (!vcpu->mmio_is_write)
8964 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8965 } else if (vcpu->arch.complete_userspace_io) {
8968 } else if (r == EMULATION_RESTART)
8975 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8976 toggle_interruptibility(vcpu, ctxt->interruptibility);
8977 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8980 * Note, EXCPT_DB is assumed to be fault-like as the emulator
8981 * only supports code breakpoints and general detect #DB, both
8982 * of which are fault-like.
8984 if (!ctxt->have_exception ||
8985 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8986 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8987 if (ctxt->is_branch)
8988 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8989 kvm_rip_write(vcpu, ctxt->eip);
8990 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8991 r = kvm_vcpu_do_singlestep(vcpu);
8992 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8993 __kvm_set_rflags(vcpu, ctxt->eflags);
8997 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8998 * do nothing, and it will be requested again as soon as
8999 * the shadow expires. But we still need to check here,
9000 * because POPF has no interrupt shadow.
9002 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9003 kvm_make_request(KVM_REQ_EVENT, vcpu);
9005 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9010 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9012 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9014 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9016 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9017 void *insn, int insn_len)
9019 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9021 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9023 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9025 vcpu->arch.pio.count = 0;
9029 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9031 vcpu->arch.pio.count = 0;
9033 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9036 return kvm_skip_emulated_instruction(vcpu);
9039 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9040 unsigned short port)
9042 unsigned long val = kvm_rax_read(vcpu);
9043 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9049 * Workaround userspace that relies on old KVM behavior of %rip being
9050 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9053 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9054 vcpu->arch.complete_userspace_io =
9055 complete_fast_pio_out_port_0x7e;
9056 kvm_skip_emulated_instruction(vcpu);
9058 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9059 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9064 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9068 /* We should only ever be called with arch.pio.count equal to 1 */
9069 BUG_ON(vcpu->arch.pio.count != 1);
9071 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9072 vcpu->arch.pio.count = 0;
9076 /* For size less than 4 we merge, else we zero extend */
9077 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9079 complete_emulator_pio_in(vcpu, &val);
9080 kvm_rax_write(vcpu, val);
9082 return kvm_skip_emulated_instruction(vcpu);
9085 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9086 unsigned short port)
9091 /* For size less than 4 we merge, else we zero extend */
9092 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9094 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9096 kvm_rax_write(vcpu, val);
9100 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9101 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9106 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9111 ret = kvm_fast_pio_in(vcpu, size, port);
9113 ret = kvm_fast_pio_out(vcpu, size, port);
9114 return ret && kvm_skip_emulated_instruction(vcpu);
9116 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9118 static int kvmclock_cpu_down_prep(unsigned int cpu)
9120 __this_cpu_write(cpu_tsc_khz, 0);
9124 static void tsc_khz_changed(void *data)
9126 struct cpufreq_freqs *freq = data;
9127 unsigned long khz = 0;
9131 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
9132 khz = cpufreq_quick_get(raw_smp_processor_id());
9135 __this_cpu_write(cpu_tsc_khz, khz);
9138 #ifdef CONFIG_X86_64
9139 static void kvm_hyperv_tsc_notifier(void)
9144 mutex_lock(&kvm_lock);
9145 list_for_each_entry(kvm, &vm_list, vm_list)
9146 kvm_make_mclock_inprogress_request(kvm);
9148 /* no guest entries from this point */
9149 hyperv_stop_tsc_emulation();
9151 /* TSC frequency always matches when on Hyper-V */
9152 for_each_present_cpu(cpu)
9153 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9154 kvm_caps.max_guest_tsc_khz = tsc_khz;
9156 list_for_each_entry(kvm, &vm_list, vm_list) {
9157 __kvm_start_pvclock_update(kvm);
9158 pvclock_update_vm_gtod_copy(kvm);
9159 kvm_end_pvclock_update(kvm);
9162 mutex_unlock(&kvm_lock);
9166 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9169 struct kvm_vcpu *vcpu;
9174 * We allow guests to temporarily run on slowing clocks,
9175 * provided we notify them after, or to run on accelerating
9176 * clocks, provided we notify them before. Thus time never
9179 * However, we have a problem. We can't atomically update
9180 * the frequency of a given CPU from this function; it is
9181 * merely a notifier, which can be called from any CPU.
9182 * Changing the TSC frequency at arbitrary points in time
9183 * requires a recomputation of local variables related to
9184 * the TSC for each VCPU. We must flag these local variables
9185 * to be updated and be sure the update takes place with the
9186 * new frequency before any guests proceed.
9188 * Unfortunately, the combination of hotplug CPU and frequency
9189 * change creates an intractable locking scenario; the order
9190 * of when these callouts happen is undefined with respect to
9191 * CPU hotplug, and they can race with each other. As such,
9192 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9193 * undefined; you can actually have a CPU frequency change take
9194 * place in between the computation of X and the setting of the
9195 * variable. To protect against this problem, all updates of
9196 * the per_cpu tsc_khz variable are done in an interrupt
9197 * protected IPI, and all callers wishing to update the value
9198 * must wait for a synchronous IPI to complete (which is trivial
9199 * if the caller is on the CPU already). This establishes the
9200 * necessary total order on variable updates.
9202 * Note that because a guest time update may take place
9203 * anytime after the setting of the VCPU's request bit, the
9204 * correct TSC value must be set before the request. However,
9205 * to ensure the update actually makes it to any guest which
9206 * starts running in hardware virtualization between the set
9207 * and the acquisition of the spinlock, we must also ping the
9208 * CPU after setting the request bit.
9212 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9214 mutex_lock(&kvm_lock);
9215 list_for_each_entry(kvm, &vm_list, vm_list) {
9216 kvm_for_each_vcpu(i, vcpu, kvm) {
9217 if (vcpu->cpu != cpu)
9219 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9220 if (vcpu->cpu != raw_smp_processor_id())
9224 mutex_unlock(&kvm_lock);
9226 if (freq->old < freq->new && send_ipi) {
9228 * We upscale the frequency. Must make the guest
9229 * doesn't see old kvmclock values while running with
9230 * the new frequency, otherwise we risk the guest sees
9231 * time go backwards.
9233 * In case we update the frequency for another cpu
9234 * (which might be in guest context) send an interrupt
9235 * to kick the cpu out of guest context. Next time
9236 * guest context is entered kvmclock will be updated,
9237 * so the guest will not see stale values.
9239 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9243 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9246 struct cpufreq_freqs *freq = data;
9249 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9251 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9254 for_each_cpu(cpu, freq->policy->cpus)
9255 __kvmclock_cpufreq_notifier(freq, cpu);
9260 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9261 .notifier_call = kvmclock_cpufreq_notifier
9264 static int kvmclock_cpu_online(unsigned int cpu)
9266 tsc_khz_changed(NULL);
9270 static void kvm_timer_init(void)
9272 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9273 max_tsc_khz = tsc_khz;
9275 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9276 struct cpufreq_policy *policy;
9280 policy = cpufreq_cpu_get(cpu);
9282 if (policy->cpuinfo.max_freq)
9283 max_tsc_khz = policy->cpuinfo.max_freq;
9284 cpufreq_cpu_put(policy);
9288 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9289 CPUFREQ_TRANSITION_NOTIFIER);
9292 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9293 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9296 #ifdef CONFIG_X86_64
9297 static void pvclock_gtod_update_fn(struct work_struct *work)
9300 struct kvm_vcpu *vcpu;
9303 mutex_lock(&kvm_lock);
9304 list_for_each_entry(kvm, &vm_list, vm_list)
9305 kvm_for_each_vcpu(i, vcpu, kvm)
9306 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9307 atomic_set(&kvm_guest_has_master_clock, 0);
9308 mutex_unlock(&kvm_lock);
9311 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9314 * Indirection to move queue_work() out of the tk_core.seq write held
9315 * region to prevent possible deadlocks against time accessors which
9316 * are invoked with work related locks held.
9318 static void pvclock_irq_work_fn(struct irq_work *w)
9320 queue_work(system_long_wq, &pvclock_gtod_work);
9323 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9326 * Notification about pvclock gtod data update.
9328 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9331 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9332 struct timekeeper *tk = priv;
9334 update_pvclock_gtod(tk);
9337 * Disable master clock if host does not trust, or does not use,
9338 * TSC based clocksource. Delegate queue_work() to irq_work as
9339 * this is invoked with tk_core.seq write held.
9341 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9342 atomic_read(&kvm_guest_has_master_clock) != 0)
9343 irq_work_queue(&pvclock_irq_work);
9347 static struct notifier_block pvclock_gtod_notifier = {
9348 .notifier_call = pvclock_gtod_notify,
9352 int kvm_arch_init(void *opaque)
9357 void kvm_arch_exit(void)
9362 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9367 if (kvm_x86_ops.hardware_enable) {
9368 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
9372 if (!ops->cpu_has_kvm_support()) {
9373 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
9374 ops->runtime_ops->name);
9377 if (ops->disabled_by_bios()) {
9378 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
9379 ops->runtime_ops->name);
9384 * KVM explicitly assumes that the guest has an FPU and
9385 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9386 * vCPU's FPU state as a fxregs_state struct.
9388 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9389 printk(KERN_ERR "kvm: inadequate fpu\n");
9393 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9394 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9399 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9400 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9401 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9402 * with an exception. PAT[0] is set to WB on RESET and also by the
9403 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9405 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9406 (host_pat & GENMASK(2, 0)) != 6) {
9407 pr_err("kvm: host PAT[0] is not WB\n");
9411 x86_emulator_cache = kvm_alloc_emulator_cache();
9412 if (!x86_emulator_cache) {
9413 pr_err("kvm: failed to allocate cache for x86 emulator\n");
9417 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9418 if (!user_return_msrs) {
9419 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
9421 goto out_free_x86_emulator_cache;
9423 kvm_nr_uret_msrs = 0;
9425 r = kvm_mmu_vendor_module_init();
9427 goto out_free_percpu;
9431 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9432 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9433 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9436 if (pi_inject_timer == -1)
9437 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9438 #ifdef CONFIG_X86_64
9439 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9441 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9442 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9448 free_percpu(user_return_msrs);
9449 out_free_x86_emulator_cache:
9450 kmem_cache_destroy(x86_emulator_cache);
9453 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9455 void kvm_x86_vendor_exit(void)
9457 #ifdef CONFIG_X86_64
9458 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9459 clear_hv_tscchange_cb();
9463 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
9464 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9465 CPUFREQ_TRANSITION_NOTIFIER);
9466 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9467 #ifdef CONFIG_X86_64
9468 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9469 irq_work_sync(&pvclock_irq_work);
9470 cancel_work_sync(&pvclock_gtod_work);
9472 kvm_x86_ops.hardware_enable = NULL;
9473 kvm_mmu_vendor_module_exit();
9474 free_percpu(user_return_msrs);
9475 kmem_cache_destroy(x86_emulator_cache);
9476 #ifdef CONFIG_KVM_XEN
9477 static_key_deferred_flush(&kvm_xen_enabled);
9478 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9481 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9483 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9486 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9487 * local APIC is in-kernel, the run loop will detect the non-runnable
9488 * state and halt the vCPU. Exit to userspace if the local APIC is
9489 * managed by userspace, in which case userspace is responsible for
9490 * handling wake events.
9492 ++vcpu->stat.halt_exits;
9493 if (lapic_in_kernel(vcpu)) {
9494 vcpu->arch.mp_state = state;
9497 vcpu->run->exit_reason = reason;
9502 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9504 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9506 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9508 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9510 int ret = kvm_skip_emulated_instruction(vcpu);
9512 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9513 * KVM_EXIT_DEBUG here.
9515 return kvm_emulate_halt_noskip(vcpu) && ret;
9517 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9519 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9521 int ret = kvm_skip_emulated_instruction(vcpu);
9523 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9524 KVM_EXIT_AP_RESET_HOLD) && ret;
9526 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9528 #ifdef CONFIG_X86_64
9529 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9530 unsigned long clock_type)
9532 struct kvm_clock_pairing clock_pairing;
9533 struct timespec64 ts;
9537 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9538 return -KVM_EOPNOTSUPP;
9541 * When tsc is in permanent catchup mode guests won't be able to use
9542 * pvclock_read_retry loop to get consistent view of pvclock
9544 if (vcpu->arch.tsc_always_catchup)
9545 return -KVM_EOPNOTSUPP;
9547 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9548 return -KVM_EOPNOTSUPP;
9550 clock_pairing.sec = ts.tv_sec;
9551 clock_pairing.nsec = ts.tv_nsec;
9552 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9553 clock_pairing.flags = 0;
9554 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9557 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9558 sizeof(struct kvm_clock_pairing)))
9566 * kvm_pv_kick_cpu_op: Kick a vcpu.
9568 * @apicid - apicid of vcpu to be kicked.
9570 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9573 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9574 * common code, e.g. for tracing. Defer initialization to the compiler.
9576 struct kvm_lapic_irq lapic_irq = {
9577 .delivery_mode = APIC_DM_REMRD,
9578 .dest_mode = APIC_DEST_PHYSICAL,
9579 .shorthand = APIC_DEST_NOSHORT,
9583 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9586 bool kvm_apicv_activated(struct kvm *kvm)
9588 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9590 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9592 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9594 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9595 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9597 return (vm_reasons | vcpu_reasons) == 0;
9599 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9601 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9602 enum kvm_apicv_inhibit reason, bool set)
9605 __set_bit(reason, inhibits);
9607 __clear_bit(reason, inhibits);
9609 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9612 static void kvm_apicv_init(struct kvm *kvm)
9614 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9616 init_rwsem(&kvm->arch.apicv_update_lock);
9618 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9621 set_or_clear_apicv_inhibit(inhibits,
9622 APICV_INHIBIT_REASON_DISABLE, true);
9625 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9627 struct kvm_vcpu *target = NULL;
9628 struct kvm_apic_map *map;
9630 vcpu->stat.directed_yield_attempted++;
9632 if (single_task_running())
9636 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9638 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9639 target = map->phys_map[dest_id]->vcpu;
9643 if (!target || !READ_ONCE(target->ready))
9646 /* Ignore requests to yield to self */
9650 if (kvm_vcpu_yield_to(target) <= 0)
9653 vcpu->stat.directed_yield_successful++;
9659 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9661 u64 ret = vcpu->run->hypercall.ret;
9663 if (!is_64_bit_mode(vcpu))
9665 kvm_rax_write(vcpu, ret);
9666 ++vcpu->stat.hypercalls;
9667 return kvm_skip_emulated_instruction(vcpu);
9670 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9672 unsigned long nr, a0, a1, a2, a3, ret;
9675 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9676 return kvm_xen_hypercall(vcpu);
9678 if (kvm_hv_hypercall_enabled(vcpu))
9679 return kvm_hv_hypercall(vcpu);
9681 nr = kvm_rax_read(vcpu);
9682 a0 = kvm_rbx_read(vcpu);
9683 a1 = kvm_rcx_read(vcpu);
9684 a2 = kvm_rdx_read(vcpu);
9685 a3 = kvm_rsi_read(vcpu);
9687 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9689 op_64_bit = is_64_bit_hypercall(vcpu);
9698 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9706 case KVM_HC_VAPIC_POLL_IRQ:
9709 case KVM_HC_KICK_CPU:
9710 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9713 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9714 kvm_sched_yield(vcpu, a1);
9717 #ifdef CONFIG_X86_64
9718 case KVM_HC_CLOCK_PAIRING:
9719 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9722 case KVM_HC_SEND_IPI:
9723 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9726 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9728 case KVM_HC_SCHED_YIELD:
9729 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9732 kvm_sched_yield(vcpu, a0);
9735 case KVM_HC_MAP_GPA_RANGE: {
9736 u64 gpa = a0, npages = a1, attrs = a2;
9739 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9742 if (!PAGE_ALIGNED(gpa) || !npages ||
9743 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9748 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9749 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9750 vcpu->run->hypercall.args[0] = gpa;
9751 vcpu->run->hypercall.args[1] = npages;
9752 vcpu->run->hypercall.args[2] = attrs;
9753 vcpu->run->hypercall.longmode = op_64_bit;
9754 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9764 kvm_rax_write(vcpu, ret);
9766 ++vcpu->stat.hypercalls;
9767 return kvm_skip_emulated_instruction(vcpu);
9769 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9771 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9773 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9774 char instruction[3];
9775 unsigned long rip = kvm_rip_read(vcpu);
9778 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9781 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9782 ctxt->exception.error_code_valid = false;
9783 ctxt->exception.vector = UD_VECTOR;
9784 ctxt->have_exception = true;
9785 return X86EMUL_PROPAGATE_FAULT;
9788 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9790 return emulator_write_emulated(ctxt, rip, instruction, 3,
9794 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9796 return vcpu->run->request_interrupt_window &&
9797 likely(!pic_in_kernel(vcpu->kvm));
9800 /* Called within kvm->srcu read side. */
9801 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9803 struct kvm_run *kvm_run = vcpu->run;
9805 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9806 kvm_run->cr8 = kvm_get_cr8(vcpu);
9807 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9809 kvm_run->ready_for_interrupt_injection =
9810 pic_in_kernel(vcpu->kvm) ||
9811 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9814 kvm_run->flags |= KVM_RUN_X86_SMM;
9817 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9821 if (!kvm_x86_ops.update_cr8_intercept)
9824 if (!lapic_in_kernel(vcpu))
9827 if (vcpu->arch.apic->apicv_active)
9830 if (!vcpu->arch.apic->vapic_addr)
9831 max_irr = kvm_lapic_find_highest_irr(vcpu);
9838 tpr = kvm_lapic_get_cr8(vcpu);
9840 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9844 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9846 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9847 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9851 return kvm_x86_ops.nested_ops->check_events(vcpu);
9854 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9857 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
9858 * exceptions don't report error codes. The presence of an error code
9859 * is carried with the exception and only stripped when the exception
9860 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
9861 * report an error code despite the CPU being in Real Mode.
9863 vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
9865 trace_kvm_inj_exception(vcpu->arch.exception.vector,
9866 vcpu->arch.exception.has_error_code,
9867 vcpu->arch.exception.error_code,
9868 vcpu->arch.exception.injected);
9870 static_call(kvm_x86_inject_exception)(vcpu);
9874 * Check for any event (interrupt or exception) that is ready to be injected,
9875 * and if there is at least one event, inject the event with the highest
9876 * priority. This handles both "pending" events, i.e. events that have never
9877 * been injected into the guest, and "injected" events, i.e. events that were
9878 * injected as part of a previous VM-Enter, but weren't successfully delivered
9879 * and need to be re-injected.
9881 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
9882 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
9883 * be able to inject exceptions in the "middle" of an instruction, and so must
9884 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
9885 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
9886 * boundaries is necessary and correct.
9888 * For simplicity, KVM uses a single path to inject all events (except events
9889 * that are injected directly from L1 to L2) and doesn't explicitly track
9890 * instruction boundaries for asynchronous events. However, because VM-Exits
9891 * that can occur during instruction execution typically result in KVM skipping
9892 * the instruction or injecting an exception, e.g. instruction and exception
9893 * intercepts, and because pending exceptions have higher priority than pending
9894 * interrupts, KVM still honors instruction boundaries in most scenarios.
9896 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
9897 * the instruction or inject an exception, then KVM can incorrecty inject a new
9898 * asynchrounous event if the event became pending after the CPU fetched the
9899 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
9900 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
9901 * injected on the restarted instruction instead of being deferred until the
9902 * instruction completes.
9904 * In practice, this virtualization hole is unlikely to be observed by the
9905 * guest, and even less likely to cause functional problems. To detect the
9906 * hole, the guest would have to trigger an event on a side effect of an early
9907 * phase of instruction execution, e.g. on the instruction fetch from memory.
9908 * And for it to be a functional problem, the guest would need to depend on the
9909 * ordering between that side effect, the instruction completing, _and_ the
9910 * delivery of the asynchronous event.
9912 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
9913 bool *req_immediate_exit)
9919 * Process nested events first, as nested VM-Exit supercedes event
9920 * re-injection. If there's an event queued for re-injection, it will
9921 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
9923 if (is_guest_mode(vcpu))
9924 r = kvm_check_nested_events(vcpu);
9929 * Re-inject exceptions and events *especially* if immediate entry+exit
9930 * to/from L2 is needed, as any event that has already been injected
9931 * into L2 needs to complete its lifecycle before injecting a new event.
9933 * Don't re-inject an NMI or interrupt if there is a pending exception.
9934 * This collision arises if an exception occurred while vectoring the
9935 * injected event, KVM intercepted said exception, and KVM ultimately
9936 * determined the fault belongs to the guest and queues the exception
9937 * for injection back into the guest.
9939 * "Injected" interrupts can also collide with pending exceptions if
9940 * userspace ignores the "ready for injection" flag and blindly queues
9941 * an interrupt. In that case, prioritizing the exception is correct,
9942 * as the exception "occurred" before the exit to userspace. Trap-like
9943 * exceptions, e.g. most #DBs, have higher priority than interrupts.
9944 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
9945 * priority, they're only generated (pended) during instruction
9946 * execution, and interrupts are recognized at instruction boundaries.
9947 * Thus a pending fault-like exception means the fault occurred on the
9948 * *previous* instruction and must be serviced prior to recognizing any
9949 * new events in order to fully complete the previous instruction.
9951 if (vcpu->arch.exception.injected)
9952 kvm_inject_exception(vcpu);
9953 else if (kvm_is_exception_pending(vcpu))
9955 else if (vcpu->arch.nmi_injected)
9956 static_call(kvm_x86_inject_nmi)(vcpu);
9957 else if (vcpu->arch.interrupt.injected)
9958 static_call(kvm_x86_inject_irq)(vcpu, true);
9961 * Exceptions that morph to VM-Exits are handled above, and pending
9962 * exceptions on top of injected exceptions that do not VM-Exit should
9963 * either morph to #DF or, sadly, override the injected exception.
9965 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9966 vcpu->arch.exception.pending);
9969 * Bail if immediate entry+exit to/from the guest is needed to complete
9970 * nested VM-Enter or event re-injection so that a different pending
9971 * event can be serviced (or if KVM needs to exit to userspace).
9973 * Otherwise, continue processing events even if VM-Exit occurred. The
9974 * VM-Exit will have cleared exceptions that were meant for L2, but
9975 * there may now be events that can be injected into L1.
9981 * A pending exception VM-Exit should either result in nested VM-Exit
9982 * or force an immediate re-entry and exit to/from L2, and exception
9983 * VM-Exits cannot be injected (flag should _never_ be set).
9985 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
9986 vcpu->arch.exception_vmexit.pending);
9989 * New events, other than exceptions, cannot be injected if KVM needs
9990 * to re-inject a previous event. See above comments on re-injecting
9991 * for why pending exceptions get priority.
9993 can_inject = !kvm_event_needs_reinjection(vcpu);
9995 if (vcpu->arch.exception.pending) {
9997 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
9998 * value pushed on the stack. Trap-like exception and all #DBs
9999 * leave RF as-is (KVM follows Intel's behavior in this regard;
10000 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10002 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10003 * describe the behavior of General Detect #DBs, which are
10004 * fault-like. They do _not_ set RF, a la code breakpoints.
10006 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10007 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10010 if (vcpu->arch.exception.vector == DB_VECTOR) {
10011 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10012 if (vcpu->arch.dr7 & DR7_GD) {
10013 vcpu->arch.dr7 &= ~DR7_GD;
10014 kvm_update_dr7(vcpu);
10018 kvm_inject_exception(vcpu);
10020 vcpu->arch.exception.pending = false;
10021 vcpu->arch.exception.injected = true;
10023 can_inject = false;
10026 /* Don't inject interrupts if the user asked to avoid doing so */
10027 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10031 * Finally, inject interrupt events. If an event cannot be injected
10032 * due to architectural conditions (e.g. IF=0) a window-open exit
10033 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10034 * and can architecturally be injected, but we cannot do it right now:
10035 * an interrupt could have arrived just now and we have to inject it
10036 * as a vmexit, or there could already an event in the queue, which is
10037 * indicated by can_inject. In that case we request an immediate exit
10038 * in order to make progress and get back here for another iteration.
10039 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10041 if (vcpu->arch.smi_pending) {
10042 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10046 vcpu->arch.smi_pending = false;
10047 ++vcpu->arch.smi_count;
10049 can_inject = false;
10051 static_call(kvm_x86_enable_smi_window)(vcpu);
10054 if (vcpu->arch.nmi_pending) {
10055 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10059 --vcpu->arch.nmi_pending;
10060 vcpu->arch.nmi_injected = true;
10061 static_call(kvm_x86_inject_nmi)(vcpu);
10062 can_inject = false;
10063 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10065 if (vcpu->arch.nmi_pending)
10066 static_call(kvm_x86_enable_nmi_window)(vcpu);
10069 if (kvm_cpu_has_injectable_intr(vcpu)) {
10070 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10074 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
10075 static_call(kvm_x86_inject_irq)(vcpu, false);
10076 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10078 if (kvm_cpu_has_injectable_intr(vcpu))
10079 static_call(kvm_x86_enable_irq_window)(vcpu);
10082 if (is_guest_mode(vcpu) &&
10083 kvm_x86_ops.nested_ops->has_events &&
10084 kvm_x86_ops.nested_ops->has_events(vcpu))
10085 *req_immediate_exit = true;
10088 * KVM must never queue a new exception while injecting an event; KVM
10089 * is done emulating and should only propagate the to-be-injected event
10090 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10091 * infinite loop as KVM will bail from VM-Enter to inject the pending
10092 * exception and start the cycle all over.
10094 * Exempt triple faults as they have special handling and won't put the
10095 * vCPU into an infinite loop. Triple fault can be queued when running
10096 * VMX without unrestricted guest, as that requires KVM to emulate Real
10097 * Mode events (see kvm_inject_realmode_interrupt()).
10099 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10100 vcpu->arch.exception_vmexit.pending);
10105 *req_immediate_exit = true;
10111 static void process_nmi(struct kvm_vcpu *vcpu)
10113 unsigned limit = 2;
10116 * x86 is limited to one NMI running, and one NMI pending after it.
10117 * If an NMI is already in progress, limit further NMIs to just one.
10118 * Otherwise, allow two (and we'll inject the first one immediately).
10120 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10123 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10124 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10125 kvm_make_request(KVM_REQ_EVENT, vcpu);
10128 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
10131 flags |= seg->g << 23;
10132 flags |= seg->db << 22;
10133 flags |= seg->l << 21;
10134 flags |= seg->avl << 20;
10135 flags |= seg->present << 15;
10136 flags |= seg->dpl << 13;
10137 flags |= seg->s << 12;
10138 flags |= seg->type << 8;
10142 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
10144 struct kvm_segment seg;
10147 kvm_get_segment(vcpu, &seg, n);
10148 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
10151 offset = 0x7f84 + n * 12;
10153 offset = 0x7f2c + (n - 3) * 12;
10155 put_smstate(u32, buf, offset + 8, seg.base);
10156 put_smstate(u32, buf, offset + 4, seg.limit);
10157 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
10160 #ifdef CONFIG_X86_64
10161 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
10163 struct kvm_segment seg;
10167 kvm_get_segment(vcpu, &seg, n);
10168 offset = 0x7e00 + n * 16;
10170 flags = enter_smm_get_segment_flags(&seg) >> 8;
10171 put_smstate(u16, buf, offset, seg.selector);
10172 put_smstate(u16, buf, offset + 2, flags);
10173 put_smstate(u32, buf, offset + 4, seg.limit);
10174 put_smstate(u64, buf, offset + 8, seg.base);
10178 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
10180 struct desc_ptr dt;
10181 struct kvm_segment seg;
10185 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
10186 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
10187 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
10188 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
10190 for (i = 0; i < 8; i++)
10191 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
10193 kvm_get_dr(vcpu, 6, &val);
10194 put_smstate(u32, buf, 0x7fcc, (u32)val);
10195 kvm_get_dr(vcpu, 7, &val);
10196 put_smstate(u32, buf, 0x7fc8, (u32)val);
10198 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
10199 put_smstate(u32, buf, 0x7fc4, seg.selector);
10200 put_smstate(u32, buf, 0x7f64, seg.base);
10201 put_smstate(u32, buf, 0x7f60, seg.limit);
10202 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
10204 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
10205 put_smstate(u32, buf, 0x7fc0, seg.selector);
10206 put_smstate(u32, buf, 0x7f80, seg.base);
10207 put_smstate(u32, buf, 0x7f7c, seg.limit);
10208 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
10210 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10211 put_smstate(u32, buf, 0x7f74, dt.address);
10212 put_smstate(u32, buf, 0x7f70, dt.size);
10214 static_call(kvm_x86_get_idt)(vcpu, &dt);
10215 put_smstate(u32, buf, 0x7f58, dt.address);
10216 put_smstate(u32, buf, 0x7f54, dt.size);
10218 for (i = 0; i < 6; i++)
10219 enter_smm_save_seg_32(vcpu, buf, i);
10221 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
10224 put_smstate(u32, buf, 0x7efc, 0x00020000);
10225 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
10228 #ifdef CONFIG_X86_64
10229 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
10231 struct desc_ptr dt;
10232 struct kvm_segment seg;
10236 for (i = 0; i < 16; i++)
10237 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
10239 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
10240 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
10242 kvm_get_dr(vcpu, 6, &val);
10243 put_smstate(u64, buf, 0x7f68, val);
10244 kvm_get_dr(vcpu, 7, &val);
10245 put_smstate(u64, buf, 0x7f60, val);
10247 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
10248 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
10249 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
10251 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
10254 put_smstate(u32, buf, 0x7efc, 0x00020064);
10256 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
10258 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
10259 put_smstate(u16, buf, 0x7e90, seg.selector);
10260 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
10261 put_smstate(u32, buf, 0x7e94, seg.limit);
10262 put_smstate(u64, buf, 0x7e98, seg.base);
10264 static_call(kvm_x86_get_idt)(vcpu, &dt);
10265 put_smstate(u32, buf, 0x7e84, dt.size);
10266 put_smstate(u64, buf, 0x7e88, dt.address);
10268 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
10269 put_smstate(u16, buf, 0x7e70, seg.selector);
10270 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
10271 put_smstate(u32, buf, 0x7e74, seg.limit);
10272 put_smstate(u64, buf, 0x7e78, seg.base);
10274 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10275 put_smstate(u32, buf, 0x7e64, dt.size);
10276 put_smstate(u64, buf, 0x7e68, dt.address);
10278 for (i = 0; i < 6; i++)
10279 enter_smm_save_seg_64(vcpu, buf, i);
10283 static void enter_smm(struct kvm_vcpu *vcpu)
10285 struct kvm_segment cs, ds;
10286 struct desc_ptr dt;
10290 memset(buf, 0, 512);
10291 #ifdef CONFIG_X86_64
10292 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
10293 enter_smm_save_state_64(vcpu, buf);
10296 enter_smm_save_state_32(vcpu, buf);
10299 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
10300 * state (e.g. leave guest mode) after we've saved the state into the
10301 * SMM state-save area.
10303 static_call(kvm_x86_enter_smm)(vcpu, buf);
10305 kvm_smm_changed(vcpu, true);
10306 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
10308 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
10309 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
10311 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
10313 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
10314 kvm_rip_write(vcpu, 0x8000);
10316 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
10317 static_call(kvm_x86_set_cr0)(vcpu, cr0);
10318 vcpu->arch.cr0 = cr0;
10320 static_call(kvm_x86_set_cr4)(vcpu, 0);
10322 /* Undocumented: IDT limit is set to zero on entry to SMM. */
10323 dt.address = dt.size = 0;
10324 static_call(kvm_x86_set_idt)(vcpu, &dt);
10326 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
10328 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
10329 cs.base = vcpu->arch.smbase;
10334 cs.limit = ds.limit = 0xffffffff;
10335 cs.type = ds.type = 0x3;
10336 cs.dpl = ds.dpl = 0;
10341 cs.avl = ds.avl = 0;
10342 cs.present = ds.present = 1;
10343 cs.unusable = ds.unusable = 0;
10344 cs.padding = ds.padding = 0;
10346 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10347 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
10348 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
10349 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
10350 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
10351 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
10353 #ifdef CONFIG_X86_64
10354 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
10355 static_call(kvm_x86_set_efer)(vcpu, 0);
10358 kvm_update_cpuid_runtime(vcpu);
10359 kvm_mmu_reset_context(vcpu);
10362 static void process_smi(struct kvm_vcpu *vcpu)
10364 vcpu->arch.smi_pending = true;
10365 kvm_make_request(KVM_REQ_EVENT, vcpu);
10368 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10369 unsigned long *vcpu_bitmap)
10371 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10374 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10376 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10379 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10381 struct kvm_lapic *apic = vcpu->arch.apic;
10384 if (!lapic_in_kernel(vcpu))
10387 down_read(&vcpu->kvm->arch.apicv_update_lock);
10390 /* Do not activate APICV when APIC is disabled */
10391 activate = kvm_vcpu_apicv_activated(vcpu) &&
10392 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10394 if (apic->apicv_active == activate)
10397 apic->apicv_active = activate;
10398 kvm_apic_update_apicv(vcpu);
10399 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10402 * When APICv gets disabled, we may still have injected interrupts
10403 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10404 * still active when the interrupt got accepted. Make sure
10405 * kvm_check_and_inject_events() is called to check for that.
10407 if (!apic->apicv_active)
10408 kvm_make_request(KVM_REQ_EVENT, vcpu);
10412 up_read(&vcpu->kvm->arch.apicv_update_lock);
10414 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
10416 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10417 enum kvm_apicv_inhibit reason, bool set)
10419 unsigned long old, new;
10421 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10423 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
10426 old = new = kvm->arch.apicv_inhibit_reasons;
10428 set_or_clear_apicv_inhibit(&new, reason, set);
10430 if (!!old != !!new) {
10432 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10433 * false positives in the sanity check WARN in svm_vcpu_run().
10434 * This task will wait for all vCPUs to ack the kick IRQ before
10435 * updating apicv_inhibit_reasons, and all other vCPUs will
10436 * block on acquiring apicv_update_lock so that vCPUs can't
10437 * redo svm_vcpu_run() without seeing the new inhibit state.
10439 * Note, holding apicv_update_lock and taking it in the read
10440 * side (handling the request) also prevents other vCPUs from
10441 * servicing the request with a stale apicv_inhibit_reasons.
10443 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10444 kvm->arch.apicv_inhibit_reasons = new;
10446 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10447 int idx = srcu_read_lock(&kvm->srcu);
10449 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10450 srcu_read_unlock(&kvm->srcu, idx);
10453 kvm->arch.apicv_inhibit_reasons = new;
10457 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10458 enum kvm_apicv_inhibit reason, bool set)
10463 down_write(&kvm->arch.apicv_update_lock);
10464 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10465 up_write(&kvm->arch.apicv_update_lock);
10467 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10469 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10471 if (!kvm_apic_present(vcpu))
10474 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10476 if (irqchip_split(vcpu->kvm))
10477 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10479 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10480 if (ioapic_in_kernel(vcpu->kvm))
10481 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10484 if (is_guest_mode(vcpu))
10485 vcpu->arch.load_eoi_exitmap_pending = true;
10487 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10490 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10492 u64 eoi_exit_bitmap[4];
10494 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10497 if (to_hv_vcpu(vcpu)) {
10498 bitmap_or((ulong *)eoi_exit_bitmap,
10499 vcpu->arch.ioapic_handled_vectors,
10500 to_hv_synic(vcpu)->vec_bitmap, 256);
10501 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10505 static_call_cond(kvm_x86_load_eoi_exitmap)(
10506 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10509 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10510 unsigned long start, unsigned long end)
10512 unsigned long apic_address;
10515 * The physical address of apic access page is stored in the VMCS.
10516 * Update it when it becomes invalid.
10518 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10519 if (start <= apic_address && apic_address < end)
10520 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10523 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10525 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10528 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10530 if (!lapic_in_kernel(vcpu))
10533 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10536 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10538 smp_send_reschedule(vcpu->cpu);
10540 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10543 * Called within kvm->srcu read side.
10544 * Returns 1 to let vcpu_run() continue the guest execution loop without
10545 * exiting to the userspace. Otherwise, the value will be returned to the
10548 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10552 dm_request_for_irq_injection(vcpu) &&
10553 kvm_cpu_accept_dm_intr(vcpu);
10554 fastpath_t exit_fastpath;
10556 bool req_immediate_exit = false;
10558 /* Forbid vmenter if vcpu dirty ring is soft-full */
10559 if (unlikely(vcpu->kvm->dirty_ring_size &&
10560 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
10561 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
10562 trace_kvm_dirty_ring_exit(vcpu);
10567 if (kvm_request_pending(vcpu)) {
10568 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10572 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10573 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10578 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10579 kvm_mmu_free_obsolete_roots(vcpu);
10580 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10581 __kvm_migrate_timers(vcpu);
10582 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10583 kvm_update_masterclock(vcpu->kvm);
10584 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10585 kvm_gen_kvmclock_update(vcpu);
10586 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10587 r = kvm_guest_time_update(vcpu);
10591 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10592 kvm_mmu_sync_roots(vcpu);
10593 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10594 kvm_mmu_load_pgd(vcpu);
10595 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
10596 kvm_vcpu_flush_tlb_all(vcpu);
10598 /* Flushing all ASIDs flushes the current ASID... */
10599 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
10601 kvm_service_local_tlb_flush_requests(vcpu);
10603 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10604 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10608 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10609 if (is_guest_mode(vcpu))
10610 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10612 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10613 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10614 vcpu->mmio_needed = 0;
10619 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10620 /* Page is swapped out. Do synthetic halt */
10621 vcpu->arch.apf.halted = true;
10625 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10626 record_steal_time(vcpu);
10627 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10629 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10631 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10632 kvm_pmu_handle_event(vcpu);
10633 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10634 kvm_pmu_deliver_pmi(vcpu);
10635 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10636 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10637 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10638 vcpu->arch.ioapic_handled_vectors)) {
10639 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10640 vcpu->run->eoi.vector =
10641 vcpu->arch.pending_ioapic_eoi;
10646 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10647 vcpu_scan_ioapic(vcpu);
10648 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10649 vcpu_load_eoi_exitmap(vcpu);
10650 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10651 kvm_vcpu_reload_apic_access_page(vcpu);
10652 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10653 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10654 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10655 vcpu->run->system_event.ndata = 0;
10659 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10660 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10661 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10662 vcpu->run->system_event.ndata = 0;
10666 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10667 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10669 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10670 vcpu->run->hyperv = hv_vcpu->exit;
10676 * KVM_REQ_HV_STIMER has to be processed after
10677 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10678 * depend on the guest clock being up-to-date
10680 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10681 kvm_hv_process_stimers(vcpu);
10682 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10683 kvm_vcpu_update_apicv(vcpu);
10684 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10685 kvm_check_async_pf_completion(vcpu);
10686 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10687 static_call(kvm_x86_msr_filter_changed)(vcpu);
10689 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10690 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10693 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10694 kvm_xen_has_interrupt(vcpu)) {
10695 ++vcpu->stat.req_event;
10696 r = kvm_apic_accept_events(vcpu);
10701 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10706 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10712 static_call(kvm_x86_enable_irq_window)(vcpu);
10714 if (kvm_lapic_enabled(vcpu)) {
10715 update_cr8_intercept(vcpu);
10716 kvm_lapic_sync_to_vapic(vcpu);
10720 r = kvm_mmu_reload(vcpu);
10722 goto cancel_injection;
10727 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10730 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10731 * IPI are then delayed after guest entry, which ensures that they
10732 * result in virtual interrupt delivery.
10734 local_irq_disable();
10736 /* Store vcpu->apicv_active before vcpu->mode. */
10737 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10739 kvm_vcpu_srcu_read_unlock(vcpu);
10742 * 1) We should set ->mode before checking ->requests. Please see
10743 * the comment in kvm_vcpu_exiting_guest_mode().
10745 * 2) For APICv, we should set ->mode before checking PID.ON. This
10746 * pairs with the memory barrier implicit in pi_test_and_set_on
10747 * (see vmx_deliver_posted_interrupt).
10749 * 3) This also orders the write to mode from any reads to the page
10750 * tables done while the VCPU is running. Please see the comment
10751 * in kvm_flush_remote_tlbs.
10753 smp_mb__after_srcu_read_unlock();
10756 * Process pending posted interrupts to handle the case where the
10757 * notification IRQ arrived in the host, or was never sent (because the
10758 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10759 * status, KVM doesn't update assigned devices when APICv is inhibited,
10760 * i.e. they can post interrupts even if APICv is temporarily disabled.
10762 if (kvm_lapic_enabled(vcpu))
10763 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10765 if (kvm_vcpu_exit_request(vcpu)) {
10766 vcpu->mode = OUTSIDE_GUEST_MODE;
10768 local_irq_enable();
10770 kvm_vcpu_srcu_read_lock(vcpu);
10772 goto cancel_injection;
10775 if (req_immediate_exit) {
10776 kvm_make_request(KVM_REQ_EVENT, vcpu);
10777 static_call(kvm_x86_request_immediate_exit)(vcpu);
10780 fpregs_assert_state_consistent();
10781 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10782 switch_fpu_return();
10784 if (vcpu->arch.guest_fpu.xfd_err)
10785 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10787 if (unlikely(vcpu->arch.switch_db_regs)) {
10788 set_debugreg(0, 7);
10789 set_debugreg(vcpu->arch.eff_db[0], 0);
10790 set_debugreg(vcpu->arch.eff_db[1], 1);
10791 set_debugreg(vcpu->arch.eff_db[2], 2);
10792 set_debugreg(vcpu->arch.eff_db[3], 3);
10793 } else if (unlikely(hw_breakpoint_active())) {
10794 set_debugreg(0, 7);
10797 guest_timing_enter_irqoff();
10801 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10802 * update must kick and wait for all vCPUs before toggling the
10803 * per-VM state, and responsing vCPUs must wait for the update
10804 * to complete before servicing KVM_REQ_APICV_UPDATE.
10806 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10807 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10809 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10810 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10813 if (kvm_lapic_enabled(vcpu))
10814 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10816 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10817 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10823 * Do this here before restoring debug registers on the host. And
10824 * since we do this before handling the vmexit, a DR access vmexit
10825 * can (a) read the correct value of the debug registers, (b) set
10826 * KVM_DEBUGREG_WONT_EXIT again.
10828 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10829 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10830 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10831 kvm_update_dr0123(vcpu);
10832 kvm_update_dr7(vcpu);
10836 * If the guest has used debug registers, at least dr7
10837 * will be disabled while returning to the host.
10838 * If we don't have active breakpoints in the host, we don't
10839 * care about the messed up debug address registers. But if
10840 * we have some of them active, restore the old state.
10842 if (hw_breakpoint_active())
10843 hw_breakpoint_restore();
10845 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10846 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10848 vcpu->mode = OUTSIDE_GUEST_MODE;
10852 * Sync xfd before calling handle_exit_irqoff() which may
10853 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10854 * in #NM irqoff handler).
10856 if (vcpu->arch.xfd_no_write_intercept)
10857 fpu_sync_guest_vmexit_xfd_state();
10859 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10861 if (vcpu->arch.guest_fpu.xfd_err)
10862 wrmsrl(MSR_IA32_XFD_ERR, 0);
10865 * Consume any pending interrupts, including the possible source of
10866 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10867 * An instruction is required after local_irq_enable() to fully unblock
10868 * interrupts on processors that implement an interrupt shadow, the
10869 * stat.exits increment will do nicely.
10871 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10872 local_irq_enable();
10873 ++vcpu->stat.exits;
10874 local_irq_disable();
10875 kvm_after_interrupt(vcpu);
10878 * Wait until after servicing IRQs to account guest time so that any
10879 * ticks that occurred while running the guest are properly accounted
10880 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10881 * of accounting via context tracking, but the loss of accuracy is
10882 * acceptable for all known use cases.
10884 guest_timing_exit_irqoff();
10886 local_irq_enable();
10889 kvm_vcpu_srcu_read_lock(vcpu);
10892 * Profile KVM exit RIPs:
10894 if (unlikely(prof_on == KVM_PROFILING)) {
10895 unsigned long rip = kvm_rip_read(vcpu);
10896 profile_hit(KVM_PROFILING, (void *)rip);
10899 if (unlikely(vcpu->arch.tsc_always_catchup))
10900 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10902 if (vcpu->arch.apic_attention)
10903 kvm_lapic_sync_from_vapic(vcpu);
10905 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10909 if (req_immediate_exit)
10910 kvm_make_request(KVM_REQ_EVENT, vcpu);
10911 static_call(kvm_x86_cancel_injection)(vcpu);
10912 if (unlikely(vcpu->arch.apic_attention))
10913 kvm_lapic_sync_from_vapic(vcpu);
10918 /* Called within kvm->srcu read side. */
10919 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10923 if (!kvm_arch_vcpu_runnable(vcpu)) {
10925 * Switch to the software timer before halt-polling/blocking as
10926 * the guest's timer may be a break event for the vCPU, and the
10927 * hypervisor timer runs only when the CPU is in guest mode.
10928 * Switch before halt-polling so that KVM recognizes an expired
10929 * timer before blocking.
10931 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10933 kvm_lapic_switch_to_sw_timer(vcpu);
10935 kvm_vcpu_srcu_read_unlock(vcpu);
10936 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10937 kvm_vcpu_halt(vcpu);
10939 kvm_vcpu_block(vcpu);
10940 kvm_vcpu_srcu_read_lock(vcpu);
10943 kvm_lapic_switch_to_hv_timer(vcpu);
10946 * If the vCPU is not runnable, a signal or another host event
10947 * of some kind is pending; service it without changing the
10948 * vCPU's activity state.
10950 if (!kvm_arch_vcpu_runnable(vcpu))
10955 * Evaluate nested events before exiting the halted state. This allows
10956 * the halt state to be recorded properly in the VMCS12's activity
10957 * state field (AMD does not have a similar field and a VM-Exit always
10958 * causes a spurious wakeup from HLT).
10960 if (is_guest_mode(vcpu)) {
10961 if (kvm_check_nested_events(vcpu) < 0)
10965 if (kvm_apic_accept_events(vcpu) < 0)
10967 switch(vcpu->arch.mp_state) {
10968 case KVM_MP_STATE_HALTED:
10969 case KVM_MP_STATE_AP_RESET_HOLD:
10970 vcpu->arch.pv.pv_unhalted = false;
10971 vcpu->arch.mp_state =
10972 KVM_MP_STATE_RUNNABLE;
10974 case KVM_MP_STATE_RUNNABLE:
10975 vcpu->arch.apf.halted = false;
10977 case KVM_MP_STATE_INIT_RECEIVED:
10986 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10988 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10989 !vcpu->arch.apf.halted);
10992 /* Called within kvm->srcu read side. */
10993 static int vcpu_run(struct kvm_vcpu *vcpu)
10997 vcpu->arch.l1tf_flush_l1d = true;
11001 * If another guest vCPU requests a PV TLB flush in the middle
11002 * of instruction emulation, the rest of the emulation could
11003 * use a stale page translation. Assume that any code after
11004 * this point can start executing an instruction.
11006 vcpu->arch.at_instruction_boundary = false;
11007 if (kvm_vcpu_running(vcpu)) {
11008 r = vcpu_enter_guest(vcpu);
11010 r = vcpu_block(vcpu);
11016 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
11017 if (kvm_xen_has_pending_events(vcpu))
11018 kvm_xen_inject_pending_events(vcpu);
11020 if (kvm_cpu_has_pending_timer(vcpu))
11021 kvm_inject_pending_timer_irqs(vcpu);
11023 if (dm_request_for_irq_injection(vcpu) &&
11024 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
11026 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
11027 ++vcpu->stat.request_irq_exits;
11031 if (__xfer_to_guest_mode_work_pending()) {
11032 kvm_vcpu_srcu_read_unlock(vcpu);
11033 r = xfer_to_guest_mode_handle_work(vcpu);
11034 kvm_vcpu_srcu_read_lock(vcpu);
11043 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
11045 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
11048 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
11050 BUG_ON(!vcpu->arch.pio.count);
11052 return complete_emulated_io(vcpu);
11056 * Implements the following, as a state machine:
11059 * for each fragment
11060 * for each mmio piece in the fragment
11067 * for each fragment
11068 * for each mmio piece in the fragment
11073 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11075 struct kvm_run *run = vcpu->run;
11076 struct kvm_mmio_fragment *frag;
11079 BUG_ON(!vcpu->mmio_needed);
11081 /* Complete previous fragment */
11082 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11083 len = min(8u, frag->len);
11084 if (!vcpu->mmio_is_write)
11085 memcpy(frag->data, run->mmio.data, len);
11087 if (frag->len <= 8) {
11088 /* Switch to the next fragment. */
11090 vcpu->mmio_cur_fragment++;
11092 /* Go forward to the next mmio piece. */
11098 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11099 vcpu->mmio_needed = 0;
11101 /* FIXME: return into emulator if single-stepping. */
11102 if (vcpu->mmio_is_write)
11104 vcpu->mmio_read_completed = 1;
11105 return complete_emulated_io(vcpu);
11108 run->exit_reason = KVM_EXIT_MMIO;
11109 run->mmio.phys_addr = frag->gpa;
11110 if (vcpu->mmio_is_write)
11111 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11112 run->mmio.len = min(8u, frag->len);
11113 run->mmio.is_write = vcpu->mmio_is_write;
11114 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11118 /* Swap (qemu) user FPU context for the guest FPU context. */
11119 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11121 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11122 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11126 /* When vcpu_run ends, restore user space FPU context. */
11127 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11129 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11130 ++vcpu->stat.fpu_reload;
11134 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11136 struct kvm_queued_exception *ex = &vcpu->arch.exception;
11137 struct kvm_run *kvm_run = vcpu->run;
11141 kvm_sigset_activate(vcpu);
11142 kvm_run->flags = 0;
11143 kvm_load_guest_fpu(vcpu);
11145 kvm_vcpu_srcu_read_lock(vcpu);
11146 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11147 if (kvm_run->immediate_exit) {
11152 * It should be impossible for the hypervisor timer to be in
11153 * use before KVM has ever run the vCPU.
11155 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
11157 kvm_vcpu_srcu_read_unlock(vcpu);
11158 kvm_vcpu_block(vcpu);
11159 kvm_vcpu_srcu_read_lock(vcpu);
11161 if (kvm_apic_accept_events(vcpu) < 0) {
11166 if (signal_pending(current)) {
11168 kvm_run->exit_reason = KVM_EXIT_INTR;
11169 ++vcpu->stat.signal_exits;
11174 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11175 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11180 if (kvm_run->kvm_dirty_regs) {
11181 r = sync_regs(vcpu);
11186 /* re-sync apic's tpr */
11187 if (!lapic_in_kernel(vcpu)) {
11188 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11195 * If userspace set a pending exception and L2 is active, convert it to
11196 * a pending VM-Exit if L1 wants to intercept the exception.
11198 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11199 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11201 kvm_queue_exception_vmexit(vcpu, ex->vector,
11202 ex->has_error_code, ex->error_code,
11203 ex->has_payload, ex->payload);
11204 ex->injected = false;
11205 ex->pending = false;
11207 vcpu->arch.exception_from_userspace = false;
11209 if (unlikely(vcpu->arch.complete_userspace_io)) {
11210 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11211 vcpu->arch.complete_userspace_io = NULL;
11216 WARN_ON_ONCE(vcpu->arch.pio.count);
11217 WARN_ON_ONCE(vcpu->mmio_needed);
11220 if (kvm_run->immediate_exit) {
11225 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11229 r = vcpu_run(vcpu);
11232 kvm_put_guest_fpu(vcpu);
11233 if (kvm_run->kvm_valid_regs)
11235 post_kvm_run_save(vcpu);
11236 kvm_vcpu_srcu_read_unlock(vcpu);
11238 kvm_sigset_deactivate(vcpu);
11243 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11245 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11247 * We are here if userspace calls get_regs() in the middle of
11248 * instruction emulation. Registers state needs to be copied
11249 * back from emulation context to vcpu. Userspace shouldn't do
11250 * that usually, but some bad designed PV devices (vmware
11251 * backdoor interface) need this to work
11253 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11254 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11256 regs->rax = kvm_rax_read(vcpu);
11257 regs->rbx = kvm_rbx_read(vcpu);
11258 regs->rcx = kvm_rcx_read(vcpu);
11259 regs->rdx = kvm_rdx_read(vcpu);
11260 regs->rsi = kvm_rsi_read(vcpu);
11261 regs->rdi = kvm_rdi_read(vcpu);
11262 regs->rsp = kvm_rsp_read(vcpu);
11263 regs->rbp = kvm_rbp_read(vcpu);
11264 #ifdef CONFIG_X86_64
11265 regs->r8 = kvm_r8_read(vcpu);
11266 regs->r9 = kvm_r9_read(vcpu);
11267 regs->r10 = kvm_r10_read(vcpu);
11268 regs->r11 = kvm_r11_read(vcpu);
11269 regs->r12 = kvm_r12_read(vcpu);
11270 regs->r13 = kvm_r13_read(vcpu);
11271 regs->r14 = kvm_r14_read(vcpu);
11272 regs->r15 = kvm_r15_read(vcpu);
11275 regs->rip = kvm_rip_read(vcpu);
11276 regs->rflags = kvm_get_rflags(vcpu);
11279 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11282 __get_regs(vcpu, regs);
11287 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11289 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11290 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11292 kvm_rax_write(vcpu, regs->rax);
11293 kvm_rbx_write(vcpu, regs->rbx);
11294 kvm_rcx_write(vcpu, regs->rcx);
11295 kvm_rdx_write(vcpu, regs->rdx);
11296 kvm_rsi_write(vcpu, regs->rsi);
11297 kvm_rdi_write(vcpu, regs->rdi);
11298 kvm_rsp_write(vcpu, regs->rsp);
11299 kvm_rbp_write(vcpu, regs->rbp);
11300 #ifdef CONFIG_X86_64
11301 kvm_r8_write(vcpu, regs->r8);
11302 kvm_r9_write(vcpu, regs->r9);
11303 kvm_r10_write(vcpu, regs->r10);
11304 kvm_r11_write(vcpu, regs->r11);
11305 kvm_r12_write(vcpu, regs->r12);
11306 kvm_r13_write(vcpu, regs->r13);
11307 kvm_r14_write(vcpu, regs->r14);
11308 kvm_r15_write(vcpu, regs->r15);
11311 kvm_rip_write(vcpu, regs->rip);
11312 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11314 vcpu->arch.exception.pending = false;
11315 vcpu->arch.exception_vmexit.pending = false;
11317 kvm_make_request(KVM_REQ_EVENT, vcpu);
11320 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11323 __set_regs(vcpu, regs);
11328 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11330 struct desc_ptr dt;
11332 if (vcpu->arch.guest_state_protected)
11333 goto skip_protected_regs;
11335 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11336 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11337 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11338 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11339 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11340 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11342 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11343 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11345 static_call(kvm_x86_get_idt)(vcpu, &dt);
11346 sregs->idt.limit = dt.size;
11347 sregs->idt.base = dt.address;
11348 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11349 sregs->gdt.limit = dt.size;
11350 sregs->gdt.base = dt.address;
11352 sregs->cr2 = vcpu->arch.cr2;
11353 sregs->cr3 = kvm_read_cr3(vcpu);
11355 skip_protected_regs:
11356 sregs->cr0 = kvm_read_cr0(vcpu);
11357 sregs->cr4 = kvm_read_cr4(vcpu);
11358 sregs->cr8 = kvm_get_cr8(vcpu);
11359 sregs->efer = vcpu->arch.efer;
11360 sregs->apic_base = kvm_get_apic_base(vcpu);
11363 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11365 __get_sregs_common(vcpu, sregs);
11367 if (vcpu->arch.guest_state_protected)
11370 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11371 set_bit(vcpu->arch.interrupt.nr,
11372 (unsigned long *)sregs->interrupt_bitmap);
11375 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11379 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11381 if (vcpu->arch.guest_state_protected)
11384 if (is_pae_paging(vcpu)) {
11385 for (i = 0 ; i < 4 ; i++)
11386 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11387 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11391 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11392 struct kvm_sregs *sregs)
11395 __get_sregs(vcpu, sregs);
11400 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11401 struct kvm_mp_state *mp_state)
11406 if (kvm_mpx_supported())
11407 kvm_load_guest_fpu(vcpu);
11409 r = kvm_apic_accept_events(vcpu);
11414 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11415 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11416 vcpu->arch.pv.pv_unhalted)
11417 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11419 mp_state->mp_state = vcpu->arch.mp_state;
11422 if (kvm_mpx_supported())
11423 kvm_put_guest_fpu(vcpu);
11428 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11429 struct kvm_mp_state *mp_state)
11435 switch (mp_state->mp_state) {
11436 case KVM_MP_STATE_UNINITIALIZED:
11437 case KVM_MP_STATE_HALTED:
11438 case KVM_MP_STATE_AP_RESET_HOLD:
11439 case KVM_MP_STATE_INIT_RECEIVED:
11440 case KVM_MP_STATE_SIPI_RECEIVED:
11441 if (!lapic_in_kernel(vcpu))
11445 case KVM_MP_STATE_RUNNABLE:
11453 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11454 * forcing the guest into INIT/SIPI if those events are supposed to be
11455 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11456 * if an SMI is pending as well.
11458 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11459 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11460 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11463 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11464 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11465 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11467 vcpu->arch.mp_state = mp_state->mp_state;
11468 kvm_make_request(KVM_REQ_EVENT, vcpu);
11476 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11477 int reason, bool has_error_code, u32 error_code)
11479 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11482 init_emulate_ctxt(vcpu);
11484 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11485 has_error_code, error_code);
11487 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11488 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11489 vcpu->run->internal.ndata = 0;
11493 kvm_rip_write(vcpu, ctxt->eip);
11494 kvm_set_rflags(vcpu, ctxt->eflags);
11497 EXPORT_SYMBOL_GPL(kvm_task_switch);
11499 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11501 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11503 * When EFER.LME and CR0.PG are set, the processor is in
11504 * 64-bit mode (though maybe in a 32-bit code segment).
11505 * CR4.PAE and EFER.LMA must be set.
11507 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11509 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11513 * Not in 64-bit mode: EFER.LMA is clear and the code
11514 * segment cannot be 64-bit.
11516 if (sregs->efer & EFER_LMA || sregs->cs.l)
11520 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11523 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11524 int *mmu_reset_needed, bool update_pdptrs)
11526 struct msr_data apic_base_msr;
11528 struct desc_ptr dt;
11530 if (!kvm_is_valid_sregs(vcpu, sregs))
11533 apic_base_msr.data = sregs->apic_base;
11534 apic_base_msr.host_initiated = true;
11535 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11538 if (vcpu->arch.guest_state_protected)
11541 dt.size = sregs->idt.limit;
11542 dt.address = sregs->idt.base;
11543 static_call(kvm_x86_set_idt)(vcpu, &dt);
11544 dt.size = sregs->gdt.limit;
11545 dt.address = sregs->gdt.base;
11546 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11548 vcpu->arch.cr2 = sregs->cr2;
11549 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11550 vcpu->arch.cr3 = sregs->cr3;
11551 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11552 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11554 kvm_set_cr8(vcpu, sregs->cr8);
11556 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11557 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11559 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11560 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11561 vcpu->arch.cr0 = sregs->cr0;
11563 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11564 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11566 if (update_pdptrs) {
11567 idx = srcu_read_lock(&vcpu->kvm->srcu);
11568 if (is_pae_paging(vcpu)) {
11569 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11570 *mmu_reset_needed = 1;
11572 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11575 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11576 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11577 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11578 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11579 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11580 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11582 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11583 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11585 update_cr8_intercept(vcpu);
11587 /* Older userspace won't unhalt the vcpu on reset. */
11588 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11589 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11590 !is_protmode(vcpu))
11591 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11596 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11598 int pending_vec, max_bits;
11599 int mmu_reset_needed = 0;
11600 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11605 if (mmu_reset_needed)
11606 kvm_mmu_reset_context(vcpu);
11608 max_bits = KVM_NR_INTERRUPTS;
11609 pending_vec = find_first_bit(
11610 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11612 if (pending_vec < max_bits) {
11613 kvm_queue_interrupt(vcpu, pending_vec, false);
11614 pr_debug("Set back pending irq %d\n", pending_vec);
11615 kvm_make_request(KVM_REQ_EVENT, vcpu);
11620 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11622 int mmu_reset_needed = 0;
11623 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11624 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11625 !(sregs2->efer & EFER_LMA);
11628 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11631 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11634 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11635 &mmu_reset_needed, !valid_pdptrs);
11639 if (valid_pdptrs) {
11640 for (i = 0; i < 4 ; i++)
11641 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11643 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11644 mmu_reset_needed = 1;
11645 vcpu->arch.pdptrs_from_userspace = true;
11647 if (mmu_reset_needed)
11648 kvm_mmu_reset_context(vcpu);
11652 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11653 struct kvm_sregs *sregs)
11658 ret = __set_sregs(vcpu, sregs);
11663 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11666 struct kvm_vcpu *vcpu;
11672 down_write(&kvm->arch.apicv_update_lock);
11674 kvm_for_each_vcpu(i, vcpu, kvm) {
11675 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11680 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11681 up_write(&kvm->arch.apicv_update_lock);
11684 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11685 struct kvm_guest_debug *dbg)
11687 unsigned long rflags;
11690 if (vcpu->arch.guest_state_protected)
11695 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11697 if (kvm_is_exception_pending(vcpu))
11699 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11700 kvm_queue_exception(vcpu, DB_VECTOR);
11702 kvm_queue_exception(vcpu, BP_VECTOR);
11706 * Read rflags as long as potentially injected trace flags are still
11709 rflags = kvm_get_rflags(vcpu);
11711 vcpu->guest_debug = dbg->control;
11712 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11713 vcpu->guest_debug = 0;
11715 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11716 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11717 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11718 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11720 for (i = 0; i < KVM_NR_DB_REGS; i++)
11721 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11723 kvm_update_dr7(vcpu);
11725 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11726 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11729 * Trigger an rflags update that will inject or remove the trace
11732 kvm_set_rflags(vcpu, rflags);
11734 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11736 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11746 * Translate a guest virtual address to a guest physical address.
11748 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11749 struct kvm_translation *tr)
11751 unsigned long vaddr = tr->linear_address;
11757 idx = srcu_read_lock(&vcpu->kvm->srcu);
11758 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11759 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11760 tr->physical_address = gpa;
11761 tr->valid = gpa != INVALID_GPA;
11769 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11771 struct fxregs_state *fxsave;
11773 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11778 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11779 memcpy(fpu->fpr, fxsave->st_space, 128);
11780 fpu->fcw = fxsave->cwd;
11781 fpu->fsw = fxsave->swd;
11782 fpu->ftwx = fxsave->twd;
11783 fpu->last_opcode = fxsave->fop;
11784 fpu->last_ip = fxsave->rip;
11785 fpu->last_dp = fxsave->rdp;
11786 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11792 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11794 struct fxregs_state *fxsave;
11796 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11801 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11803 memcpy(fxsave->st_space, fpu->fpr, 128);
11804 fxsave->cwd = fpu->fcw;
11805 fxsave->swd = fpu->fsw;
11806 fxsave->twd = fpu->ftwx;
11807 fxsave->fop = fpu->last_opcode;
11808 fxsave->rip = fpu->last_ip;
11809 fxsave->rdp = fpu->last_dp;
11810 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11816 static void store_regs(struct kvm_vcpu *vcpu)
11818 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11820 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11821 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11823 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11824 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11826 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11827 kvm_vcpu_ioctl_x86_get_vcpu_events(
11828 vcpu, &vcpu->run->s.regs.events);
11831 static int sync_regs(struct kvm_vcpu *vcpu)
11833 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11834 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11835 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11837 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11838 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11840 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11842 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11843 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11844 vcpu, &vcpu->run->s.regs.events))
11846 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11852 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11854 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11855 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11856 "guest TSC will not be reliable\n");
11858 if (!kvm->arch.max_vcpu_ids)
11859 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11861 if (id >= kvm->arch.max_vcpu_ids)
11864 return static_call(kvm_x86_vcpu_precreate)(kvm);
11867 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11872 vcpu->arch.last_vmentry_cpu = -1;
11873 vcpu->arch.regs_avail = ~0;
11874 vcpu->arch.regs_dirty = ~0;
11876 kvm_gpc_init(&vcpu->arch.pv_time);
11878 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11879 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11881 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11883 r = kvm_mmu_create(vcpu);
11887 if (irqchip_in_kernel(vcpu->kvm)) {
11888 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11890 goto fail_mmu_destroy;
11893 * Defer evaluating inhibits until the vCPU is first run, as
11894 * this vCPU will not get notified of any changes until this
11895 * vCPU is visible to other vCPUs (marked online and added to
11896 * the set of vCPUs). Opportunistically mark APICv active as
11897 * VMX in particularly is highly unlikely to have inhibits.
11898 * Ignore the current per-VM APICv state so that vCPU creation
11899 * is guaranteed to run with a deterministic value, the request
11900 * will ensure the vCPU gets the correct state before VM-Entry.
11902 if (enable_apicv) {
11903 vcpu->arch.apic->apicv_active = true;
11904 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11907 static_branch_inc(&kvm_has_noapic_vcpu);
11911 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11913 goto fail_free_lapic;
11914 vcpu->arch.pio_data = page_address(page);
11916 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11917 GFP_KERNEL_ACCOUNT);
11918 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11919 GFP_KERNEL_ACCOUNT);
11920 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11921 goto fail_free_mce_banks;
11922 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11924 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11925 GFP_KERNEL_ACCOUNT))
11926 goto fail_free_mce_banks;
11928 if (!alloc_emulate_ctxt(vcpu))
11929 goto free_wbinvd_dirty_mask;
11931 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11932 pr_err("kvm: failed to allocate vcpu's fpu\n");
11933 goto free_emulate_ctxt;
11936 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11937 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11939 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11941 kvm_async_pf_hash_reset(vcpu);
11942 kvm_pmu_init(vcpu);
11944 vcpu->arch.pending_external_vector = -1;
11945 vcpu->arch.preempted_in_kernel = false;
11947 #if IS_ENABLED(CONFIG_HYPERV)
11948 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11951 r = static_call(kvm_x86_vcpu_create)(vcpu);
11953 goto free_guest_fpu;
11955 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11956 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11957 kvm_xen_init_vcpu(vcpu);
11958 kvm_vcpu_mtrr_init(vcpu);
11960 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11961 kvm_vcpu_reset(vcpu, false);
11962 kvm_init_mmu(vcpu);
11967 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11969 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11970 free_wbinvd_dirty_mask:
11971 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11972 fail_free_mce_banks:
11973 kfree(vcpu->arch.mce_banks);
11974 kfree(vcpu->arch.mci_ctl2_banks);
11975 free_page((unsigned long)vcpu->arch.pio_data);
11977 kvm_free_lapic(vcpu);
11979 kvm_mmu_destroy(vcpu);
11983 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11985 struct kvm *kvm = vcpu->kvm;
11987 if (mutex_lock_killable(&vcpu->mutex))
11990 kvm_synchronize_tsc(vcpu, 0);
11993 /* poll control enabled by default */
11994 vcpu->arch.msr_kvm_poll_control = 1;
11996 mutex_unlock(&vcpu->mutex);
11998 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11999 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
12000 KVMCLOCK_SYNC_PERIOD);
12003 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
12007 kvmclock_reset(vcpu);
12009 static_call(kvm_x86_vcpu_free)(vcpu);
12011 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12012 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12013 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12015 kvm_xen_destroy_vcpu(vcpu);
12016 kvm_hv_vcpu_uninit(vcpu);
12017 kvm_pmu_destroy(vcpu);
12018 kfree(vcpu->arch.mce_banks);
12019 kfree(vcpu->arch.mci_ctl2_banks);
12020 kvm_free_lapic(vcpu);
12021 idx = srcu_read_lock(&vcpu->kvm->srcu);
12022 kvm_mmu_destroy(vcpu);
12023 srcu_read_unlock(&vcpu->kvm->srcu, idx);
12024 free_page((unsigned long)vcpu->arch.pio_data);
12025 kvfree(vcpu->arch.cpuid_entries);
12026 if (!lapic_in_kernel(vcpu))
12027 static_branch_dec(&kvm_has_noapic_vcpu);
12030 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
12032 struct kvm_cpuid_entry2 *cpuid_0x1;
12033 unsigned long old_cr0 = kvm_read_cr0(vcpu);
12034 unsigned long new_cr0;
12037 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12038 * to handle side effects. RESET emulation hits those flows and relies
12039 * on emulated/virtualized registers, including those that are loaded
12040 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
12041 * to detect improper or missing initialization.
12043 WARN_ON_ONCE(!init_event &&
12044 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
12047 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
12048 * possible to INIT the vCPU while L2 is active. Force the vCPU back
12049 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
12050 * bits), i.e. virtualization is disabled.
12052 if (is_guest_mode(vcpu))
12053 kvm_leave_nested(vcpu);
12055 kvm_lapic_reset(vcpu, init_event);
12057 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12058 vcpu->arch.hflags = 0;
12060 vcpu->arch.smi_pending = 0;
12061 vcpu->arch.smi_count = 0;
12062 atomic_set(&vcpu->arch.nmi_queued, 0);
12063 vcpu->arch.nmi_pending = 0;
12064 vcpu->arch.nmi_injected = false;
12065 kvm_clear_interrupt_queue(vcpu);
12066 kvm_clear_exception_queue(vcpu);
12068 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12069 kvm_update_dr0123(vcpu);
12070 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12071 vcpu->arch.dr7 = DR7_FIXED_1;
12072 kvm_update_dr7(vcpu);
12074 vcpu->arch.cr2 = 0;
12076 kvm_make_request(KVM_REQ_EVENT, vcpu);
12077 vcpu->arch.apf.msr_en_val = 0;
12078 vcpu->arch.apf.msr_int_val = 0;
12079 vcpu->arch.st.msr_val = 0;
12081 kvmclock_reset(vcpu);
12083 kvm_clear_async_pf_completion_queue(vcpu);
12084 kvm_async_pf_hash_reset(vcpu);
12085 vcpu->arch.apf.halted = false;
12087 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12088 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12091 * All paths that lead to INIT are required to load the guest's
12092 * FPU state (because most paths are buried in KVM_RUN).
12095 kvm_put_guest_fpu(vcpu);
12097 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12098 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12101 kvm_load_guest_fpu(vcpu);
12105 kvm_pmu_reset(vcpu);
12106 vcpu->arch.smbase = 0x30000;
12108 vcpu->arch.msr_misc_features_enables = 0;
12109 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12110 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12112 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12113 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12116 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12117 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12118 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12121 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12122 * if no CPUID match is found. Note, it's impossible to get a match at
12123 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12124 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12125 * on RESET. But, go through the motions in case that's ever remedied.
12127 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12128 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12130 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12132 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12133 kvm_rip_write(vcpu, 0xfff0);
12135 vcpu->arch.cr3 = 0;
12136 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12139 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12140 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12141 * (or qualify) that with a footnote stating that CD/NW are preserved.
12143 new_cr0 = X86_CR0_ET;
12145 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12147 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12149 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12150 static_call(kvm_x86_set_cr4)(vcpu, 0);
12151 static_call(kvm_x86_set_efer)(vcpu, 0);
12152 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12155 * On the standard CR0/CR4/EFER modification paths, there are several
12156 * complex conditions determining whether the MMU has to be reset and/or
12157 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12158 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12159 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12160 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12162 if (old_cr0 & X86_CR0_PG) {
12163 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12164 kvm_mmu_reset_context(vcpu);
12168 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12169 * APM states the TLBs are untouched by INIT, but it also states that
12170 * the TLBs are flushed on "External initialization of the processor."
12171 * Flush the guest TLB regardless of vendor, there is no meaningful
12172 * benefit in relying on the guest to flush the TLB immediately after
12173 * INIT. A spurious TLB flush is benign and likely negligible from a
12174 * performance perspective.
12177 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12179 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12181 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12183 struct kvm_segment cs;
12185 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12186 cs.selector = vector << 8;
12187 cs.base = vector << 12;
12188 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12189 kvm_rip_write(vcpu, 0);
12191 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12193 int kvm_arch_hardware_enable(void)
12196 struct kvm_vcpu *vcpu;
12201 bool stable, backwards_tsc = false;
12203 kvm_user_return_msr_cpu_online();
12204 ret = static_call(kvm_x86_hardware_enable)();
12208 local_tsc = rdtsc();
12209 stable = !kvm_check_tsc_unstable();
12210 list_for_each_entry(kvm, &vm_list, vm_list) {
12211 kvm_for_each_vcpu(i, vcpu, kvm) {
12212 if (!stable && vcpu->cpu == smp_processor_id())
12213 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12214 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12215 backwards_tsc = true;
12216 if (vcpu->arch.last_host_tsc > max_tsc)
12217 max_tsc = vcpu->arch.last_host_tsc;
12223 * Sometimes, even reliable TSCs go backwards. This happens on
12224 * platforms that reset TSC during suspend or hibernate actions, but
12225 * maintain synchronization. We must compensate. Fortunately, we can
12226 * detect that condition here, which happens early in CPU bringup,
12227 * before any KVM threads can be running. Unfortunately, we can't
12228 * bring the TSCs fully up to date with real time, as we aren't yet far
12229 * enough into CPU bringup that we know how much real time has actually
12230 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12231 * variables that haven't been updated yet.
12233 * So we simply find the maximum observed TSC above, then record the
12234 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12235 * the adjustment will be applied. Note that we accumulate
12236 * adjustments, in case multiple suspend cycles happen before some VCPU
12237 * gets a chance to run again. In the event that no KVM threads get a
12238 * chance to run, we will miss the entire elapsed period, as we'll have
12239 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12240 * loose cycle time. This isn't too big a deal, since the loss will be
12241 * uniform across all VCPUs (not to mention the scenario is extremely
12242 * unlikely). It is possible that a second hibernate recovery happens
12243 * much faster than a first, causing the observed TSC here to be
12244 * smaller; this would require additional padding adjustment, which is
12245 * why we set last_host_tsc to the local tsc observed here.
12247 * N.B. - this code below runs only on platforms with reliable TSC,
12248 * as that is the only way backwards_tsc is set above. Also note
12249 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12250 * have the same delta_cyc adjustment applied if backwards_tsc
12251 * is detected. Note further, this adjustment is only done once,
12252 * as we reset last_host_tsc on all VCPUs to stop this from being
12253 * called multiple times (one for each physical CPU bringup).
12255 * Platforms with unreliable TSCs don't have to deal with this, they
12256 * will be compensated by the logic in vcpu_load, which sets the TSC to
12257 * catchup mode. This will catchup all VCPUs to real time, but cannot
12258 * guarantee that they stay in perfect synchronization.
12260 if (backwards_tsc) {
12261 u64 delta_cyc = max_tsc - local_tsc;
12262 list_for_each_entry(kvm, &vm_list, vm_list) {
12263 kvm->arch.backwards_tsc_observed = true;
12264 kvm_for_each_vcpu(i, vcpu, kvm) {
12265 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12266 vcpu->arch.last_host_tsc = local_tsc;
12267 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12271 * We have to disable TSC offset matching.. if you were
12272 * booting a VM while issuing an S4 host suspend....
12273 * you may have some problem. Solving this issue is
12274 * left as an exercise to the reader.
12276 kvm->arch.last_tsc_nsec = 0;
12277 kvm->arch.last_tsc_write = 0;
12284 void kvm_arch_hardware_disable(void)
12286 static_call(kvm_x86_hardware_disable)();
12287 drop_user_return_notifiers();
12290 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
12292 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
12294 #define __KVM_X86_OP(func) \
12295 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
12296 #define KVM_X86_OP(func) \
12297 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
12298 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
12299 #define KVM_X86_OP_OPTIONAL_RET0(func) \
12300 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
12301 (void *)__static_call_return0);
12302 #include <asm/kvm-x86-ops.h>
12303 #undef __KVM_X86_OP
12305 kvm_pmu_ops_update(ops->pmu_ops);
12308 int kvm_arch_hardware_setup(void *opaque)
12310 struct kvm_x86_init_ops *ops = opaque;
12313 rdmsrl_safe(MSR_EFER, &host_efer);
12315 if (boot_cpu_has(X86_FEATURE_XSAVES))
12316 rdmsrl(MSR_IA32_XSS, host_xss);
12318 kvm_init_pmu_capability();
12320 r = ops->hardware_setup();
12324 kvm_ops_update(ops);
12326 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
12328 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
12329 kvm_caps.supported_xss = 0;
12331 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
12332 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
12333 #undef __kvm_cpu_cap_has
12335 if (kvm_caps.has_tsc_control) {
12337 * Make sure the user can only configure tsc_khz values that
12338 * fit into a signed integer.
12339 * A min value is not calculated because it will always
12340 * be 1 on all machines.
12342 u64 max = min(0x7fffffffULL,
12343 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
12344 kvm_caps.max_guest_tsc_khz = max;
12346 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
12347 kvm_init_msr_list();
12351 void kvm_arch_hardware_unsetup(void)
12353 kvm_unregister_perf_callbacks();
12355 static_call(kvm_x86_hardware_unsetup)();
12358 int kvm_arch_check_processor_compat(void *opaque)
12360 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
12361 struct kvm_x86_init_ops *ops = opaque;
12363 WARN_ON(!irqs_disabled());
12365 if (__cr4_reserved_bits(cpu_has, c) !=
12366 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
12369 return ops->check_processor_compatibility();
12372 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12374 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12376 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
12378 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12380 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12383 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12384 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12386 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12388 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12390 vcpu->arch.l1tf_flush_l1d = true;
12391 if (pmu->version && unlikely(pmu->event_count)) {
12392 pmu->need_cleanup = true;
12393 kvm_make_request(KVM_REQ_PMU, vcpu);
12395 static_call(kvm_x86_sched_in)(vcpu, cpu);
12398 void kvm_arch_free_vm(struct kvm *kvm)
12400 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12401 __kvm_arch_free_vm(kvm);
12405 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12408 unsigned long flags;
12413 ret = kvm_page_track_init(kvm);
12417 ret = kvm_mmu_init_vm(kvm);
12419 goto out_page_track;
12421 ret = static_call(kvm_x86_vm_init)(kvm);
12423 goto out_uninit_mmu;
12425 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12426 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12427 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12429 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12430 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12431 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12432 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12433 &kvm->arch.irq_sources_bitmap);
12435 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12436 mutex_init(&kvm->arch.apic_map_lock);
12437 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12438 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12440 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12441 pvclock_update_vm_gtod_copy(kvm);
12442 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12444 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12445 kvm->arch.guest_can_read_msr_platform_info = true;
12446 kvm->arch.enable_pmu = enable_pmu;
12448 #if IS_ENABLED(CONFIG_HYPERV)
12449 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12450 kvm->arch.hv_root_tdp = INVALID_PAGE;
12453 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12454 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12456 kvm_apicv_init(kvm);
12457 kvm_hv_init_vm(kvm);
12458 kvm_xen_init_vm(kvm);
12463 kvm_mmu_uninit_vm(kvm);
12465 kvm_page_track_cleanup(kvm);
12470 int kvm_arch_post_init_vm(struct kvm *kvm)
12472 return kvm_mmu_post_init_vm(kvm);
12475 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12478 kvm_mmu_unload(vcpu);
12482 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12485 struct kvm_vcpu *vcpu;
12487 kvm_for_each_vcpu(i, vcpu, kvm) {
12488 kvm_clear_async_pf_completion_queue(vcpu);
12489 kvm_unload_vcpu_mmu(vcpu);
12493 void kvm_arch_sync_events(struct kvm *kvm)
12495 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12496 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12501 * __x86_set_memory_region: Setup KVM internal memory slot
12503 * @kvm: the kvm pointer to the VM.
12504 * @id: the slot ID to setup.
12505 * @gpa: the GPA to install the slot (unused when @size == 0).
12506 * @size: the size of the slot. Set to zero to uninstall a slot.
12508 * This function helps to setup a KVM internal memory slot. Specify
12509 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12510 * slot. The return code can be one of the following:
12512 * HVA: on success (uninstall will return a bogus HVA)
12515 * The caller should always use IS_ERR() to check the return value
12516 * before use. Note, the KVM internal memory slots are guaranteed to
12517 * remain valid and unchanged until the VM is destroyed, i.e., the
12518 * GPA->HVA translation will not change. However, the HVA is a user
12519 * address, i.e. its accessibility is not guaranteed, and must be
12520 * accessed via __copy_{to,from}_user().
12522 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12526 unsigned long hva, old_npages;
12527 struct kvm_memslots *slots = kvm_memslots(kvm);
12528 struct kvm_memory_slot *slot;
12530 /* Called with kvm->slots_lock held. */
12531 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12532 return ERR_PTR_USR(-EINVAL);
12534 slot = id_to_memslot(slots, id);
12536 if (slot && slot->npages)
12537 return ERR_PTR_USR(-EEXIST);
12540 * MAP_SHARED to prevent internal slot pages from being moved
12543 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12544 MAP_SHARED | MAP_ANONYMOUS, 0);
12545 if (IS_ERR((void *)hva))
12546 return (void __user *)hva;
12548 if (!slot || !slot->npages)
12551 old_npages = slot->npages;
12552 hva = slot->userspace_addr;
12555 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12556 struct kvm_userspace_memory_region m;
12558 m.slot = id | (i << 16);
12560 m.guest_phys_addr = gpa;
12561 m.userspace_addr = hva;
12562 m.memory_size = size;
12563 r = __kvm_set_memory_region(kvm, &m);
12565 return ERR_PTR_USR(r);
12569 vm_munmap(hva, old_npages * PAGE_SIZE);
12571 return (void __user *)hva;
12573 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12575 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12577 kvm_mmu_pre_destroy_vm(kvm);
12580 void kvm_arch_destroy_vm(struct kvm *kvm)
12582 if (current->mm == kvm->mm) {
12584 * Free memory regions allocated on behalf of userspace,
12585 * unless the memory map has changed due to process exit
12588 mutex_lock(&kvm->slots_lock);
12589 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12591 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12593 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12594 mutex_unlock(&kvm->slots_lock);
12596 kvm_unload_vcpu_mmus(kvm);
12597 static_call_cond(kvm_x86_vm_destroy)(kvm);
12598 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12599 kvm_pic_destroy(kvm);
12600 kvm_ioapic_destroy(kvm);
12601 kvm_destroy_vcpus(kvm);
12602 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12603 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12604 kvm_mmu_uninit_vm(kvm);
12605 kvm_page_track_cleanup(kvm);
12606 kvm_xen_destroy_vm(kvm);
12607 kvm_hv_destroy_vm(kvm);
12610 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12614 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12615 kvfree(slot->arch.rmap[i]);
12616 slot->arch.rmap[i] = NULL;
12620 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12624 memslot_rmap_free(slot);
12626 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12627 kvfree(slot->arch.lpage_info[i - 1]);
12628 slot->arch.lpage_info[i - 1] = NULL;
12631 kvm_page_track_free_memslot(slot);
12634 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12636 const int sz = sizeof(*slot->arch.rmap[0]);
12639 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12641 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12643 if (slot->arch.rmap[i])
12646 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12647 if (!slot->arch.rmap[i]) {
12648 memslot_rmap_free(slot);
12656 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12657 struct kvm_memory_slot *slot)
12659 unsigned long npages = slot->npages;
12663 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12664 * old arrays will be freed by __kvm_set_memory_region() if installing
12665 * the new memslot is successful.
12667 memset(&slot->arch, 0, sizeof(slot->arch));
12669 if (kvm_memslots_have_rmaps(kvm)) {
12670 r = memslot_rmap_alloc(slot, npages);
12675 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12676 struct kvm_lpage_info *linfo;
12677 unsigned long ugfn;
12681 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12683 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12687 slot->arch.lpage_info[i - 1] = linfo;
12689 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12690 linfo[0].disallow_lpage = 1;
12691 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12692 linfo[lpages - 1].disallow_lpage = 1;
12693 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12695 * If the gfn and userspace address are not aligned wrt each
12696 * other, disable large page support for this slot.
12698 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12701 for (j = 0; j < lpages; ++j)
12702 linfo[j].disallow_lpage = 1;
12706 if (kvm_page_track_create_memslot(kvm, slot, npages))
12712 memslot_rmap_free(slot);
12714 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12715 kvfree(slot->arch.lpage_info[i - 1]);
12716 slot->arch.lpage_info[i - 1] = NULL;
12721 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12723 struct kvm_vcpu *vcpu;
12727 * memslots->generation has been incremented.
12728 * mmio generation may have reached its maximum value.
12730 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12732 /* Force re-initialization of steal_time cache */
12733 kvm_for_each_vcpu(i, vcpu, kvm)
12734 kvm_vcpu_kick(vcpu);
12737 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12738 const struct kvm_memory_slot *old,
12739 struct kvm_memory_slot *new,
12740 enum kvm_mr_change change)
12742 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12743 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12746 return kvm_alloc_memslot_metadata(kvm, new);
12749 if (change == KVM_MR_FLAGS_ONLY)
12750 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12751 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12758 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12760 struct kvm_arch *ka = &kvm->arch;
12762 if (!kvm_x86_ops.cpu_dirty_log_size)
12765 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12766 (!enable && --ka->cpu_dirty_logging_count == 0))
12767 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12769 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12772 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12773 struct kvm_memory_slot *old,
12774 const struct kvm_memory_slot *new,
12775 enum kvm_mr_change change)
12777 u32 old_flags = old ? old->flags : 0;
12778 u32 new_flags = new ? new->flags : 0;
12779 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12782 * Update CPU dirty logging if dirty logging is being toggled. This
12783 * applies to all operations.
12785 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12786 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12789 * Nothing more to do for RO slots (which can't be dirtied and can't be
12790 * made writable) or CREATE/MOVE/DELETE of a slot.
12792 * For a memslot with dirty logging disabled:
12793 * CREATE: No dirty mappings will already exist.
12794 * MOVE/DELETE: The old mappings will already have been cleaned up by
12795 * kvm_arch_flush_shadow_memslot()
12797 * For a memslot with dirty logging enabled:
12798 * CREATE: No shadow pages exist, thus nothing to write-protect
12799 * and no dirty bits to clear.
12800 * MOVE/DELETE: The old mappings will already have been cleaned up by
12801 * kvm_arch_flush_shadow_memslot().
12803 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12807 * READONLY and non-flags changes were filtered out above, and the only
12808 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12809 * logging isn't being toggled on or off.
12811 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12814 if (!log_dirty_pages) {
12816 * Dirty logging tracks sptes in 4k granularity, meaning that
12817 * large sptes have to be split. If live migration succeeds,
12818 * the guest in the source machine will be destroyed and large
12819 * sptes will be created in the destination. However, if the
12820 * guest continues to run in the source machine (for example if
12821 * live migration fails), small sptes will remain around and
12822 * cause bad performance.
12824 * Scan sptes if dirty logging has been stopped, dropping those
12825 * which can be collapsed into a single large-page spte. Later
12826 * page faults will create the large-page sptes.
12828 kvm_mmu_zap_collapsible_sptes(kvm, new);
12831 * Initially-all-set does not require write protecting any page,
12832 * because they're all assumed to be dirty.
12834 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12837 if (READ_ONCE(eager_page_split))
12838 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12840 if (kvm_x86_ops.cpu_dirty_log_size) {
12841 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12842 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12844 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12848 * Unconditionally flush the TLBs after enabling dirty logging.
12849 * A flush is almost always going to be necessary (see below),
12850 * and unconditionally flushing allows the helpers to omit
12851 * the subtly complex checks when removing write access.
12853 * Do the flush outside of mmu_lock to reduce the amount of
12854 * time mmu_lock is held. Flushing after dropping mmu_lock is
12855 * safe as KVM only needs to guarantee the slot is fully
12856 * write-protected before returning to userspace, i.e. before
12857 * userspace can consume the dirty status.
12859 * Flushing outside of mmu_lock requires KVM to be careful when
12860 * making decisions based on writable status of an SPTE, e.g. a
12861 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12863 * Specifically, KVM also write-protects guest page tables to
12864 * monitor changes when using shadow paging, and must guarantee
12865 * no CPUs can write to those page before mmu_lock is dropped.
12866 * Because CPUs may have stale TLB entries at this point, a
12867 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12869 * KVM also allows making SPTES writable outside of mmu_lock,
12870 * e.g. to allow dirty logging without taking mmu_lock.
12872 * To handle these scenarios, KVM uses a separate software-only
12873 * bit (MMU-writable) to track if a SPTE is !writable due to
12874 * a guest page table being write-protected (KVM clears the
12875 * MMU-writable flag when write-protecting for shadow paging).
12877 * The use of MMU-writable is also the primary motivation for
12878 * the unconditional flush. Because KVM must guarantee that a
12879 * CPU doesn't contain stale, writable TLB entries for a
12880 * !MMU-writable SPTE, KVM must flush if it encounters any
12881 * MMU-writable SPTE regardless of whether the actual hardware
12882 * writable bit was set. I.e. KVM is almost guaranteed to need
12883 * to flush, while unconditionally flushing allows the "remove
12884 * write access" helpers to ignore MMU-writable entirely.
12886 * See is_writable_pte() for more details (the case involving
12887 * access-tracked SPTEs is particularly relevant).
12889 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
12893 void kvm_arch_commit_memory_region(struct kvm *kvm,
12894 struct kvm_memory_slot *old,
12895 const struct kvm_memory_slot *new,
12896 enum kvm_mr_change change)
12898 if (!kvm->arch.n_requested_mmu_pages &&
12899 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12900 unsigned long nr_mmu_pages;
12902 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12903 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12904 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12907 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12909 /* Free the arrays associated with the old memslot. */
12910 if (change == KVM_MR_MOVE)
12911 kvm_arch_free_memslot(kvm, old);
12914 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12916 kvm_mmu_zap_all(kvm);
12919 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12920 struct kvm_memory_slot *slot)
12922 kvm_page_track_flush_slot(kvm, slot);
12925 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12927 return (is_guest_mode(vcpu) &&
12928 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12931 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12933 if (!list_empty_careful(&vcpu->async_pf.done))
12936 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12937 kvm_apic_init_sipi_allowed(vcpu))
12940 if (vcpu->arch.pv.pv_unhalted)
12943 if (kvm_is_exception_pending(vcpu))
12946 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12947 (vcpu->arch.nmi_pending &&
12948 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12951 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12952 (vcpu->arch.smi_pending &&
12953 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12956 if (kvm_arch_interrupt_allowed(vcpu) &&
12957 (kvm_cpu_has_interrupt(vcpu) ||
12958 kvm_guest_apic_has_interrupt(vcpu)))
12961 if (kvm_hv_has_stimer_pending(vcpu))
12964 if (is_guest_mode(vcpu) &&
12965 kvm_x86_ops.nested_ops->has_events &&
12966 kvm_x86_ops.nested_ops->has_events(vcpu))
12969 if (kvm_xen_has_pending_events(vcpu))
12975 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12977 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12980 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12982 if (kvm_vcpu_apicv_active(vcpu) &&
12983 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12989 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12991 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12994 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12995 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12996 kvm_test_request(KVM_REQ_EVENT, vcpu))
12999 return kvm_arch_dy_has_pending_interrupt(vcpu);
13002 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
13004 if (vcpu->arch.guest_state_protected)
13007 return vcpu->arch.preempted_in_kernel;
13010 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
13012 return kvm_rip_read(vcpu);
13015 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
13017 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
13020 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
13022 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
13025 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
13027 /* Can't read the RIP when guest state is protected, just return 0 */
13028 if (vcpu->arch.guest_state_protected)
13031 if (is_64_bit_mode(vcpu))
13032 return kvm_rip_read(vcpu);
13033 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
13034 kvm_rip_read(vcpu));
13036 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
13038 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
13040 return kvm_get_linear_rip(vcpu) == linear_rip;
13042 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
13044 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
13046 unsigned long rflags;
13048 rflags = static_call(kvm_x86_get_rflags)(vcpu);
13049 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
13050 rflags &= ~X86_EFLAGS_TF;
13053 EXPORT_SYMBOL_GPL(kvm_get_rflags);
13055 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13057 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
13058 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
13059 rflags |= X86_EFLAGS_TF;
13060 static_call(kvm_x86_set_rflags)(vcpu, rflags);
13063 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13065 __kvm_set_rflags(vcpu, rflags);
13066 kvm_make_request(KVM_REQ_EVENT, vcpu);
13068 EXPORT_SYMBOL_GPL(kvm_set_rflags);
13070 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
13072 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
13074 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
13077 static inline u32 kvm_async_pf_next_probe(u32 key)
13079 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
13082 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13084 u32 key = kvm_async_pf_hash_fn(gfn);
13086 while (vcpu->arch.apf.gfns[key] != ~0)
13087 key = kvm_async_pf_next_probe(key);
13089 vcpu->arch.apf.gfns[key] = gfn;
13092 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
13095 u32 key = kvm_async_pf_hash_fn(gfn);
13097 for (i = 0; i < ASYNC_PF_PER_VCPU &&
13098 (vcpu->arch.apf.gfns[key] != gfn &&
13099 vcpu->arch.apf.gfns[key] != ~0); i++)
13100 key = kvm_async_pf_next_probe(key);
13105 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13107 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
13110 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13114 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
13116 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
13120 vcpu->arch.apf.gfns[i] = ~0;
13122 j = kvm_async_pf_next_probe(j);
13123 if (vcpu->arch.apf.gfns[j] == ~0)
13125 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
13127 * k lies cyclically in ]i,j]
13129 * |....j i.k.| or |.k..j i...|
13131 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13132 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13137 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13139 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13141 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13145 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13147 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13149 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13150 &token, offset, sizeof(token));
13153 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13155 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13158 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13159 &val, offset, sizeof(val)))
13165 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13168 if (!kvm_pv_async_pf_enabled(vcpu))
13171 if (vcpu->arch.apf.send_user_only &&
13172 static_call(kvm_x86_get_cpl)(vcpu) == 0)
13175 if (is_guest_mode(vcpu)) {
13177 * L1 needs to opt into the special #PF vmexits that are
13178 * used to deliver async page faults.
13180 return vcpu->arch.apf.delivery_as_pf_vmexit;
13183 * Play it safe in case the guest temporarily disables paging.
13184 * The real mode IDT in particular is unlikely to have a #PF
13187 return is_paging(vcpu);
13191 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13193 if (unlikely(!lapic_in_kernel(vcpu) ||
13194 kvm_event_needs_reinjection(vcpu) ||
13195 kvm_is_exception_pending(vcpu)))
13198 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13202 * If interrupts are off we cannot even use an artificial
13205 return kvm_arch_interrupt_allowed(vcpu);
13208 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13209 struct kvm_async_pf *work)
13211 struct x86_exception fault;
13213 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13214 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13216 if (kvm_can_deliver_async_pf(vcpu) &&
13217 !apf_put_user_notpresent(vcpu)) {
13218 fault.vector = PF_VECTOR;
13219 fault.error_code_valid = true;
13220 fault.error_code = 0;
13221 fault.nested_page_fault = false;
13222 fault.address = work->arch.token;
13223 fault.async_page_fault = true;
13224 kvm_inject_page_fault(vcpu, &fault);
13228 * It is not possible to deliver a paravirtualized asynchronous
13229 * page fault, but putting the guest in an artificial halt state
13230 * can be beneficial nevertheless: if an interrupt arrives, we
13231 * can deliver it timely and perhaps the guest will schedule
13232 * another process. When the instruction that triggered a page
13233 * fault is retried, hopefully the page will be ready in the host.
13235 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13240 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13241 struct kvm_async_pf *work)
13243 struct kvm_lapic_irq irq = {
13244 .delivery_mode = APIC_DM_FIXED,
13245 .vector = vcpu->arch.apf.vec
13248 if (work->wakeup_all)
13249 work->arch.token = ~0; /* broadcast wakeup */
13251 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13252 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13254 if ((work->wakeup_all || work->notpresent_injected) &&
13255 kvm_pv_async_pf_enabled(vcpu) &&
13256 !apf_put_user_ready(vcpu, work->arch.token)) {
13257 vcpu->arch.apf.pageready_pending = true;
13258 kvm_apic_set_irq(vcpu, &irq, NULL);
13261 vcpu->arch.apf.halted = false;
13262 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13265 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13267 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13268 if (!vcpu->arch.apf.pageready_pending)
13269 kvm_vcpu_kick(vcpu);
13272 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13274 if (!kvm_pv_async_pf_enabled(vcpu))
13277 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13280 void kvm_arch_start_assignment(struct kvm *kvm)
13282 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13283 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13285 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13287 void kvm_arch_end_assignment(struct kvm *kvm)
13289 atomic_dec(&kvm->arch.assigned_device_count);
13291 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13293 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13295 return arch_atomic_read(&kvm->arch.assigned_device_count);
13297 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13299 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13301 atomic_inc(&kvm->arch.noncoherent_dma_count);
13303 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13305 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13307 atomic_dec(&kvm->arch.noncoherent_dma_count);
13309 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13311 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13313 return atomic_read(&kvm->arch.noncoherent_dma_count);
13315 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13317 bool kvm_arch_has_irq_bypass(void)
13322 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13323 struct irq_bypass_producer *prod)
13325 struct kvm_kernel_irqfd *irqfd =
13326 container_of(cons, struct kvm_kernel_irqfd, consumer);
13329 irqfd->producer = prod;
13330 kvm_arch_start_assignment(irqfd->kvm);
13331 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13332 prod->irq, irqfd->gsi, 1);
13335 kvm_arch_end_assignment(irqfd->kvm);
13340 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13341 struct irq_bypass_producer *prod)
13344 struct kvm_kernel_irqfd *irqfd =
13345 container_of(cons, struct kvm_kernel_irqfd, consumer);
13347 WARN_ON(irqfd->producer != prod);
13348 irqfd->producer = NULL;
13351 * When producer of consumer is unregistered, we change back to
13352 * remapped mode, so we can re-use the current implementation
13353 * when the irq is masked/disabled or the consumer side (KVM
13354 * int this case doesn't want to receive the interrupts.
13356 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13358 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13359 " fails: %d\n", irqfd->consumer.token, ret);
13361 kvm_arch_end_assignment(irqfd->kvm);
13364 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13365 uint32_t guest_irq, bool set)
13367 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13370 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13371 struct kvm_kernel_irq_routing_entry *new)
13373 if (new->type != KVM_IRQ_ROUTING_MSI)
13376 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13379 bool kvm_vector_hashing_enabled(void)
13381 return vector_hashing;
13384 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13386 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13388 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13391 int kvm_spec_ctrl_test_value(u64 value)
13394 * test that setting IA32_SPEC_CTRL to given value
13395 * is allowed by the host processor
13399 unsigned long flags;
13402 local_irq_save(flags);
13404 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13406 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13409 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13411 local_irq_restore(flags);
13415 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13417 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13419 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13420 struct x86_exception fault;
13421 u64 access = error_code &
13422 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13424 if (!(error_code & PFERR_PRESENT_MASK) ||
13425 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13427 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13428 * tables probably do not match the TLB. Just proceed
13429 * with the error code that the processor gave.
13431 fault.vector = PF_VECTOR;
13432 fault.error_code_valid = true;
13433 fault.error_code = error_code;
13434 fault.nested_page_fault = false;
13435 fault.address = gva;
13436 fault.async_page_fault = false;
13438 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13440 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13443 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13444 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13445 * indicates whether exit to userspace is needed.
13447 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13448 struct x86_exception *e)
13450 if (r == X86EMUL_PROPAGATE_FAULT) {
13451 kvm_inject_emulated_page_fault(vcpu, e);
13456 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13457 * while handling a VMX instruction KVM could've handled the request
13458 * correctly by exiting to userspace and performing I/O but there
13459 * doesn't seem to be a real use-case behind such requests, just return
13460 * KVM_EXIT_INTERNAL_ERROR for now.
13462 kvm_prepare_emulation_failure_exit(vcpu);
13466 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13468 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13471 struct x86_exception e;
13478 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13479 if (r != X86EMUL_CONTINUE)
13480 return kvm_handle_memory_failure(vcpu, r, &e);
13482 if (operand.pcid >> 12 != 0) {
13483 kvm_inject_gp(vcpu, 0);
13487 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
13490 case INVPCID_TYPE_INDIV_ADDR:
13491 if ((!pcid_enabled && (operand.pcid != 0)) ||
13492 is_noncanonical_address(operand.gla, vcpu)) {
13493 kvm_inject_gp(vcpu, 0);
13496 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13497 return kvm_skip_emulated_instruction(vcpu);
13499 case INVPCID_TYPE_SINGLE_CTXT:
13500 if (!pcid_enabled && (operand.pcid != 0)) {
13501 kvm_inject_gp(vcpu, 0);
13505 kvm_invalidate_pcid(vcpu, operand.pcid);
13506 return kvm_skip_emulated_instruction(vcpu);
13508 case INVPCID_TYPE_ALL_NON_GLOBAL:
13510 * Currently, KVM doesn't mark global entries in the shadow
13511 * page tables, so a non-global flush just degenerates to a
13512 * global flush. If needed, we could optimize this later by
13513 * keeping track of global entries in shadow page tables.
13517 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13518 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13519 return kvm_skip_emulated_instruction(vcpu);
13522 kvm_inject_gp(vcpu, 0);
13526 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13528 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13530 struct kvm_run *run = vcpu->run;
13531 struct kvm_mmio_fragment *frag;
13534 BUG_ON(!vcpu->mmio_needed);
13536 /* Complete previous fragment */
13537 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13538 len = min(8u, frag->len);
13539 if (!vcpu->mmio_is_write)
13540 memcpy(frag->data, run->mmio.data, len);
13542 if (frag->len <= 8) {
13543 /* Switch to the next fragment. */
13545 vcpu->mmio_cur_fragment++;
13547 /* Go forward to the next mmio piece. */
13553 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13554 vcpu->mmio_needed = 0;
13556 // VMG change, at this point, we're always done
13557 // RIP has already been advanced
13561 // More MMIO is needed
13562 run->mmio.phys_addr = frag->gpa;
13563 run->mmio.len = min(8u, frag->len);
13564 run->mmio.is_write = vcpu->mmio_is_write;
13565 if (run->mmio.is_write)
13566 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13567 run->exit_reason = KVM_EXIT_MMIO;
13569 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13574 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13578 struct kvm_mmio_fragment *frag;
13583 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13584 if (handled == bytes)
13591 /*TODO: Check if need to increment number of frags */
13592 frag = vcpu->mmio_fragments;
13593 vcpu->mmio_nr_fragments = 1;
13598 vcpu->mmio_needed = 1;
13599 vcpu->mmio_cur_fragment = 0;
13601 vcpu->run->mmio.phys_addr = gpa;
13602 vcpu->run->mmio.len = min(8u, frag->len);
13603 vcpu->run->mmio.is_write = 1;
13604 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13605 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13607 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13611 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13613 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13617 struct kvm_mmio_fragment *frag;
13622 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13623 if (handled == bytes)
13630 /*TODO: Check if need to increment number of frags */
13631 frag = vcpu->mmio_fragments;
13632 vcpu->mmio_nr_fragments = 1;
13637 vcpu->mmio_needed = 1;
13638 vcpu->mmio_cur_fragment = 0;
13640 vcpu->run->mmio.phys_addr = gpa;
13641 vcpu->run->mmio.len = min(8u, frag->len);
13642 vcpu->run->mmio.is_write = 0;
13643 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13645 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13649 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13651 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13653 vcpu->arch.sev_pio_count -= count;
13654 vcpu->arch.sev_pio_data += count * size;
13657 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13658 unsigned int port);
13660 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13662 int size = vcpu->arch.pio.size;
13663 int port = vcpu->arch.pio.port;
13665 vcpu->arch.pio.count = 0;
13666 if (vcpu->arch.sev_pio_count)
13667 return kvm_sev_es_outs(vcpu, size, port);
13671 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13675 unsigned int count =
13676 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13677 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13679 /* memcpy done already by emulator_pio_out. */
13680 advance_sev_es_emulated_pio(vcpu, count, size);
13684 /* Emulation done by the kernel. */
13685 if (!vcpu->arch.sev_pio_count)
13689 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13693 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13694 unsigned int port);
13696 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13698 unsigned count = vcpu->arch.pio.count;
13699 int size = vcpu->arch.pio.size;
13700 int port = vcpu->arch.pio.port;
13702 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13703 advance_sev_es_emulated_pio(vcpu, count, size);
13704 if (vcpu->arch.sev_pio_count)
13705 return kvm_sev_es_ins(vcpu, size, port);
13709 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13713 unsigned int count =
13714 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13715 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13718 /* Emulation done by the kernel. */
13719 advance_sev_es_emulated_pio(vcpu, count, size);
13720 if (!vcpu->arch.sev_pio_count)
13724 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13728 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13729 unsigned int port, void *data, unsigned int count,
13732 vcpu->arch.sev_pio_data = data;
13733 vcpu->arch.sev_pio_count = count;
13734 return in ? kvm_sev_es_ins(vcpu, size, port)
13735 : kvm_sev_es_outs(vcpu, size, port);
13737 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13739 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13740 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13741 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13742 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13743 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13744 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13745 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13746 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13747 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13748 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13749 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13750 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13751 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13752 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13753 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13754 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13755 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13756 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13757 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13758 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13759 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13760 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13761 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13762 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13763 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13764 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13765 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13766 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13767 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13769 static int __init kvm_x86_init(void)
13771 kvm_mmu_x86_module_init();
13772 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13775 module_init(kvm_x86_init);
13777 static void __exit kvm_x86_exit(void)
13780 * If module_init() is implemented, module_exit() must also be
13781 * implemented to allow module unload.
13784 module_exit(kvm_x86_exit);