2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/sched/smt.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mod_devicetable.h>
33 #include <linux/trace_events.h>
34 #include <linux/slab.h>
35 #include <linux/tboot.h>
36 #include <linux/hrtimer.h>
37 #include <linux/frame.h>
38 #include <linux/nospec.h>
39 #include "kvm_cache_regs.h"
43 #include <asm/cpu_device_id.h>
47 #include <asm/virtext.h>
49 #include <asm/fpu/internal.h>
50 #include <asm/perf_event.h>
51 #include <asm/debugreg.h>
52 #include <asm/kexec.h>
54 #include <asm/irq_remapping.h>
55 #include <asm/mmu_context.h>
56 #include <asm/microcode.h>
57 #include <asm/spec-ctrl.h>
62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
63 #define __ex_clear(x, reg) \
64 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
66 MODULE_AUTHOR("Qumranet");
67 MODULE_LICENSE("GPL");
69 static const struct x86_cpu_id vmx_cpu_id[] = {
70 X86_FEATURE_MATCH(X86_FEATURE_VMX),
73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75 static bool __read_mostly enable_vpid = 1;
76 module_param_named(vpid, enable_vpid, bool, 0444);
78 static bool __read_mostly flexpriority_enabled = 1;
79 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
81 static bool __read_mostly enable_ept = 1;
82 module_param_named(ept, enable_ept, bool, S_IRUGO);
84 static bool __read_mostly enable_unrestricted_guest = 1;
85 module_param_named(unrestricted_guest,
86 enable_unrestricted_guest, bool, S_IRUGO);
88 static bool __read_mostly enable_ept_ad_bits = 1;
89 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
91 static bool __read_mostly emulate_invalid_guest_state = true;
92 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
94 static bool __read_mostly fasteoi = 1;
95 module_param(fasteoi, bool, S_IRUGO);
97 static bool __read_mostly enable_apicv = 1;
98 module_param(enable_apicv, bool, S_IRUGO);
100 static bool __read_mostly enable_shadow_vmcs = 1;
101 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
103 * If nested=1, nested virtualization is supported, i.e., guests may use
104 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
105 * use VMX instructions.
107 static bool __read_mostly nested = 0;
108 module_param(nested, bool, S_IRUGO);
110 static u64 __read_mostly host_xss;
112 static bool __read_mostly enable_pml = 1;
113 module_param_named(pml, enable_pml, bool, S_IRUGO);
117 #define MSR_TYPE_RW 3
119 #define MSR_BITMAP_MODE_X2APIC 1
120 #define MSR_BITMAP_MODE_X2APIC_APICV 2
121 #define MSR_BITMAP_MODE_LM 4
123 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
125 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126 static int __read_mostly cpu_preemption_timer_multi;
127 static bool __read_mostly enable_preemption_timer = 1;
129 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
132 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
133 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
134 #define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
136 #define KVM_CR4_GUEST_OWNED_BITS \
137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
140 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
141 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
143 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
145 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
148 * Hyper-V requires all of these, so mark them as supported even though
149 * they are just treated the same as all-context.
151 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
152 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
153 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
154 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
155 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
158 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
159 * ple_gap: upper bound on the amount of time between two successive
160 * executions of PAUSE in a loop. Also indicate if ple enabled.
161 * According to test, this time is usually smaller than 128 cycles.
162 * ple_window: upper bound on the amount of time a guest is allowed to execute
163 * in a PAUSE loop. Tests indicate that most spinlocks are held for
164 * less than 2^12 cycles
165 * Time is measured based on a counter that runs at the same rate as the TSC,
166 * refer SDM volume 3b section 21.6.13 & 22.1.3.
168 #define KVM_VMX_DEFAULT_PLE_GAP 128
169 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
170 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
171 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
172 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
173 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
175 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
176 module_param(ple_gap, int, S_IRUGO);
178 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
179 module_param(ple_window, int, S_IRUGO);
181 /* Default doubles per-vcpu window every exit. */
182 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
183 module_param(ple_window_grow, int, S_IRUGO);
185 /* Default resets per-vcpu window every exit to ple_window. */
186 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
187 module_param(ple_window_shrink, int, S_IRUGO);
189 /* Default is to compute the maximum so we can never overflow. */
190 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
191 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
192 module_param(ple_window_max, int, S_IRUGO);
194 extern const ulong vmx_return;
196 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
197 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
198 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
200 /* Storage for pre module init parameter parsing */
201 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
203 static const struct {
206 } vmentry_l1d_param[] = {
207 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
208 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
209 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
210 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
211 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
212 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
215 #define L1D_CACHE_ORDER 4
216 static void *vmx_l1d_flush_pages;
218 /* Control for disabling CPU Fill buffer clear */
219 static bool __read_mostly vmx_fb_clear_ctrl_available;
221 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
231 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
234 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
235 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
236 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
241 /* If set to auto use the default l1tf mitigation method */
242 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
243 switch (l1tf_mitigation) {
244 case L1TF_MITIGATION_OFF:
245 l1tf = VMENTER_L1D_FLUSH_NEVER;
247 case L1TF_MITIGATION_FLUSH_NOWARN:
248 case L1TF_MITIGATION_FLUSH:
249 case L1TF_MITIGATION_FLUSH_NOSMT:
250 l1tf = VMENTER_L1D_FLUSH_COND;
252 case L1TF_MITIGATION_FULL:
253 case L1TF_MITIGATION_FULL_FORCE:
254 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
257 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
258 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
261 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
262 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
263 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
266 vmx_l1d_flush_pages = page_address(page);
269 * Initialize each page with a different pattern in
270 * order to protect against KSM in the nested
271 * virtualization case.
273 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
274 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
279 l1tf_vmx_mitigation = l1tf;
281 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
282 static_branch_enable(&vmx_l1d_should_flush);
284 static_branch_disable(&vmx_l1d_should_flush);
286 if (l1tf == VMENTER_L1D_FLUSH_COND)
287 static_branch_enable(&vmx_l1d_flush_cond);
289 static_branch_disable(&vmx_l1d_flush_cond);
293 static int vmentry_l1d_flush_parse(const char *s)
298 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
299 if (vmentry_l1d_param[i].for_parse &&
300 sysfs_streq(s, vmentry_l1d_param[i].option))
307 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
311 l1tf = vmentry_l1d_flush_parse(s);
315 if (!boot_cpu_has(X86_BUG_L1TF))
319 * Has vmx_init() run already? If not then this is the pre init
320 * parameter parsing. In that case just store the value and let
321 * vmx_init() do the proper setup after enable_ept has been
324 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
325 vmentry_l1d_flush_param = l1tf;
329 mutex_lock(&vmx_l1d_flush_mutex);
330 ret = vmx_setup_l1d_flush(l1tf);
331 mutex_unlock(&vmx_l1d_flush_mutex);
335 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
337 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
338 return sprintf(s, "???\n");
340 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
343 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
344 .set = vmentry_l1d_flush_set,
345 .get = vmentry_l1d_flush_get,
347 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
349 #define NR_AUTOLOAD_MSRS 8
358 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
359 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
360 * loaded on this CPU (so we can clear them if the CPU goes down).
364 struct vmcs *shadow_vmcs;
367 bool nmi_known_unmasked;
368 unsigned long vmcs_host_cr3; /* May not match real cr3 */
369 unsigned long vmcs_host_cr4; /* May not match real cr4 */
370 /* Support for vnmi-less CPUs */
371 int soft_vnmi_blocked;
373 s64 vnmi_blocked_time;
374 unsigned long *msr_bitmap;
375 struct list_head loaded_vmcss_on_cpu_link;
378 struct shared_msr_entry {
385 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
386 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
387 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
388 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
389 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
390 * More than one of these structures may exist, if L1 runs multiple L2 guests.
391 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
392 * underlying hardware which will be used to run L2.
393 * This structure is packed to ensure that its layout is identical across
394 * machines (necessary for live migration).
395 * If there are changes in this struct, VMCS12_REVISION must be changed.
397 typedef u64 natural_width;
398 struct __packed vmcs12 {
399 /* According to the Intel spec, a VMCS region must start with the
400 * following two fields. Then follow implementation-specific data.
405 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
406 u32 padding[7]; /* room for future expansion */
411 u64 vm_exit_msr_store_addr;
412 u64 vm_exit_msr_load_addr;
413 u64 vm_entry_msr_load_addr;
415 u64 virtual_apic_page_addr;
416 u64 apic_access_addr;
417 u64 posted_intr_desc_addr;
418 u64 vm_function_control;
420 u64 eoi_exit_bitmap0;
421 u64 eoi_exit_bitmap1;
422 u64 eoi_exit_bitmap2;
423 u64 eoi_exit_bitmap3;
424 u64 eptp_list_address;
426 u64 guest_physical_address;
427 u64 vmcs_link_pointer;
429 u64 guest_ia32_debugctl;
432 u64 guest_ia32_perf_global_ctrl;
440 u64 host_ia32_perf_global_ctrl;
441 u64 padding64[8]; /* room for future expansion */
443 * To allow migration of L1 (complete with its L2 guests) between
444 * machines of different natural widths (32 or 64 bit), we cannot have
445 * unsigned long fields with no explict size. We use u64 (aliased
446 * natural_width) instead. Luckily, x86 is little-endian.
448 natural_width cr0_guest_host_mask;
449 natural_width cr4_guest_host_mask;
450 natural_width cr0_read_shadow;
451 natural_width cr4_read_shadow;
452 natural_width cr3_target_value0;
453 natural_width cr3_target_value1;
454 natural_width cr3_target_value2;
455 natural_width cr3_target_value3;
456 natural_width exit_qualification;
457 natural_width guest_linear_address;
458 natural_width guest_cr0;
459 natural_width guest_cr3;
460 natural_width guest_cr4;
461 natural_width guest_es_base;
462 natural_width guest_cs_base;
463 natural_width guest_ss_base;
464 natural_width guest_ds_base;
465 natural_width guest_fs_base;
466 natural_width guest_gs_base;
467 natural_width guest_ldtr_base;
468 natural_width guest_tr_base;
469 natural_width guest_gdtr_base;
470 natural_width guest_idtr_base;
471 natural_width guest_dr7;
472 natural_width guest_rsp;
473 natural_width guest_rip;
474 natural_width guest_rflags;
475 natural_width guest_pending_dbg_exceptions;
476 natural_width guest_sysenter_esp;
477 natural_width guest_sysenter_eip;
478 natural_width host_cr0;
479 natural_width host_cr3;
480 natural_width host_cr4;
481 natural_width host_fs_base;
482 natural_width host_gs_base;
483 natural_width host_tr_base;
484 natural_width host_gdtr_base;
485 natural_width host_idtr_base;
486 natural_width host_ia32_sysenter_esp;
487 natural_width host_ia32_sysenter_eip;
488 natural_width host_rsp;
489 natural_width host_rip;
490 natural_width paddingl[8]; /* room for future expansion */
491 u32 pin_based_vm_exec_control;
492 u32 cpu_based_vm_exec_control;
493 u32 exception_bitmap;
494 u32 page_fault_error_code_mask;
495 u32 page_fault_error_code_match;
496 u32 cr3_target_count;
497 u32 vm_exit_controls;
498 u32 vm_exit_msr_store_count;
499 u32 vm_exit_msr_load_count;
500 u32 vm_entry_controls;
501 u32 vm_entry_msr_load_count;
502 u32 vm_entry_intr_info_field;
503 u32 vm_entry_exception_error_code;
504 u32 vm_entry_instruction_len;
506 u32 secondary_vm_exec_control;
507 u32 vm_instruction_error;
509 u32 vm_exit_intr_info;
510 u32 vm_exit_intr_error_code;
511 u32 idt_vectoring_info_field;
512 u32 idt_vectoring_error_code;
513 u32 vm_exit_instruction_len;
514 u32 vmx_instruction_info;
521 u32 guest_ldtr_limit;
523 u32 guest_gdtr_limit;
524 u32 guest_idtr_limit;
525 u32 guest_es_ar_bytes;
526 u32 guest_cs_ar_bytes;
527 u32 guest_ss_ar_bytes;
528 u32 guest_ds_ar_bytes;
529 u32 guest_fs_ar_bytes;
530 u32 guest_gs_ar_bytes;
531 u32 guest_ldtr_ar_bytes;
532 u32 guest_tr_ar_bytes;
533 u32 guest_interruptibility_info;
534 u32 guest_activity_state;
535 u32 guest_sysenter_cs;
536 u32 host_ia32_sysenter_cs;
537 u32 vmx_preemption_timer_value;
538 u32 padding32[7]; /* room for future expansion */
539 u16 virtual_processor_id;
541 u16 guest_es_selector;
542 u16 guest_cs_selector;
543 u16 guest_ss_selector;
544 u16 guest_ds_selector;
545 u16 guest_fs_selector;
546 u16 guest_gs_selector;
547 u16 guest_ldtr_selector;
548 u16 guest_tr_selector;
549 u16 guest_intr_status;
551 u16 host_es_selector;
552 u16 host_cs_selector;
553 u16 host_ss_selector;
554 u16 host_ds_selector;
555 u16 host_fs_selector;
556 u16 host_gs_selector;
557 u16 host_tr_selector;
561 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
562 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
563 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
565 #define VMCS12_REVISION 0x11e57ed0
568 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
569 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
570 * current implementation, 4K are reserved to avoid future complications.
572 #define VMCS12_SIZE 0x1000
575 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
576 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
579 /* Has the level1 guest done vmxon? */
584 /* The guest-physical address of the current VMCS L1 keeps for L2 */
587 * Cache of the guest's VMCS, existing outside of guest memory.
588 * Loaded from guest memory during VMPTRLD. Flushed to guest
589 * memory during VMCLEAR and VMPTRLD.
591 struct vmcs12 *cached_vmcs12;
593 * Indicates if the shadow vmcs must be updated with the
594 * data hold by vmcs12
596 bool sync_shadow_vmcs;
598 bool change_vmcs01_virtual_apic_mode;
600 /* L2 must run next, and mustn't decide to exit to L1. */
601 bool nested_run_pending;
603 struct loaded_vmcs vmcs02;
606 * Guest pages referred to in the vmcs02 with host-physical
607 * pointers, so we must keep them pinned while L2 runs.
609 struct page *apic_access_page;
610 struct page *virtual_apic_page;
611 struct page *pi_desc_page;
612 struct pi_desc *pi_desc;
616 struct hrtimer preemption_timer;
617 bool preemption_timer_expired;
619 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
626 * We only store the "true" versions of the VMX capability MSRs. We
627 * generate the "non-true" versions by setting the must-be-1 bits
628 * according to the SDM.
630 u32 nested_vmx_procbased_ctls_low;
631 u32 nested_vmx_procbased_ctls_high;
632 u32 nested_vmx_secondary_ctls_low;
633 u32 nested_vmx_secondary_ctls_high;
634 u32 nested_vmx_pinbased_ctls_low;
635 u32 nested_vmx_pinbased_ctls_high;
636 u32 nested_vmx_exit_ctls_low;
637 u32 nested_vmx_exit_ctls_high;
638 u32 nested_vmx_entry_ctls_low;
639 u32 nested_vmx_entry_ctls_high;
640 u32 nested_vmx_misc_low;
641 u32 nested_vmx_misc_high;
642 u32 nested_vmx_ept_caps;
643 u32 nested_vmx_vpid_caps;
644 u64 nested_vmx_basic;
645 u64 nested_vmx_cr0_fixed0;
646 u64 nested_vmx_cr0_fixed1;
647 u64 nested_vmx_cr4_fixed0;
648 u64 nested_vmx_cr4_fixed1;
649 u64 nested_vmx_vmcs_enum;
650 u64 nested_vmx_vmfunc_controls;
653 #define POSTED_INTR_ON 0
654 #define POSTED_INTR_SN 1
656 /* Posted-Interrupt Descriptor */
658 u32 pir[8]; /* Posted interrupt requested */
661 /* bit 256 - Outstanding Notification */
663 /* bit 257 - Suppress Notification */
665 /* bit 271:258 - Reserved */
667 /* bit 279:272 - Notification Vector */
669 /* bit 287:280 - Reserved */
671 /* bit 319:288 - Notification Destination */
679 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
681 return test_and_set_bit(POSTED_INTR_ON,
682 (unsigned long *)&pi_desc->control);
685 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
687 return test_and_clear_bit(POSTED_INTR_ON,
688 (unsigned long *)&pi_desc->control);
691 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
693 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
696 static inline void pi_clear_sn(struct pi_desc *pi_desc)
698 return clear_bit(POSTED_INTR_SN,
699 (unsigned long *)&pi_desc->control);
702 static inline void pi_set_sn(struct pi_desc *pi_desc)
704 return set_bit(POSTED_INTR_SN,
705 (unsigned long *)&pi_desc->control);
708 static inline void pi_clear_on(struct pi_desc *pi_desc)
710 clear_bit(POSTED_INTR_ON,
711 (unsigned long *)&pi_desc->control);
714 static inline int pi_test_on(struct pi_desc *pi_desc)
716 return test_bit(POSTED_INTR_ON,
717 (unsigned long *)&pi_desc->control);
720 static inline int pi_test_sn(struct pi_desc *pi_desc)
722 return test_bit(POSTED_INTR_SN,
723 (unsigned long *)&pi_desc->control);
728 struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
732 struct kvm_vcpu vcpu;
733 unsigned long host_rsp;
737 u32 idt_vectoring_info;
739 struct shared_msr_entry *guest_msrs;
742 unsigned long host_idt_base;
744 u64 msr_host_kernel_gs_base;
745 u64 msr_guest_kernel_gs_base;
750 u32 vm_entry_controls_shadow;
751 u32 vm_exit_controls_shadow;
752 u32 secondary_exec_control;
755 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
756 * non-nested (L1) guest, it always points to vmcs01. For a nested
757 * guest (L2), it points to a different VMCS. loaded_cpu_state points
758 * to the VMCS whose state is loaded into the CPU registers that only
759 * need to be switched when transitioning to/from the kernel; a NULL
760 * value indicates that host state is loaded.
762 struct loaded_vmcs vmcs01;
763 struct loaded_vmcs *loaded_vmcs;
764 struct loaded_vmcs *loaded_cpu_state;
765 bool __launched; /* temporary, used in vmx_vcpu_run */
766 struct msr_autoload {
767 struct vmx_msrs guest;
768 struct vmx_msrs host;
772 u16 fs_sel, gs_sel, ldt_sel;
776 int gs_ldt_reload_needed;
777 int fs_reload_needed;
778 u64 msr_host_bndcfgs;
783 struct kvm_segment segs[8];
786 u32 bitmask; /* 4 bits per segment (1 bit per field) */
787 struct kvm_save_segment {
795 bool emulation_required;
799 /* Posted interrupt descriptor */
800 struct pi_desc pi_desc;
802 /* Support for a guest hypervisor (nested VMX) */
803 struct nested_vmx nested;
805 /* Dynamic PLE window. */
807 bool ple_window_dirty;
809 /* Support for PML */
810 #define PML_ENTITY_NUM 512
813 /* apic deadline value in host tsc */
816 u64 current_tsc_ratio;
821 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
822 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
823 * in msr_ia32_feature_control_valid_bits.
825 u64 msr_ia32_feature_control;
826 u64 msr_ia32_feature_control_valid_bits;
827 u64 msr_ia32_mcu_opt_ctrl;
828 bool disable_fb_clear;
831 enum segment_cache_field {
840 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
842 return container_of(vcpu, struct vcpu_vmx, vcpu);
845 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
847 return &(to_vmx(vcpu)->pi_desc);
850 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
851 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
852 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
853 [number##_HIGH] = VMCS12_OFFSET(name)+4
856 static unsigned long shadow_read_only_fields[] = {
858 * We do NOT shadow fields that are modified when L0
859 * traps and emulates any vmx instruction (e.g. VMPTRLD,
860 * VMXON...) executed by L1.
861 * For example, VM_INSTRUCTION_ERROR is read
862 * by L1 if a vmx instruction fails (part of the error path).
863 * Note the code assumes this logic. If for some reason
864 * we start shadowing these fields then we need to
865 * force a shadow sync when L0 emulates vmx instructions
866 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
867 * by nested_vmx_failValid)
871 VM_EXIT_INSTRUCTION_LEN,
872 IDT_VECTORING_INFO_FIELD,
873 IDT_VECTORING_ERROR_CODE,
874 VM_EXIT_INTR_ERROR_CODE,
876 GUEST_LINEAR_ADDRESS,
877 GUEST_PHYSICAL_ADDRESS
879 static int max_shadow_read_only_fields =
880 ARRAY_SIZE(shadow_read_only_fields);
882 static unsigned long shadow_read_write_fields[] = {
889 GUEST_INTERRUPTIBILITY_INFO,
902 CPU_BASED_VM_EXEC_CONTROL,
903 VM_ENTRY_EXCEPTION_ERROR_CODE,
904 VM_ENTRY_INTR_INFO_FIELD,
905 VM_ENTRY_INSTRUCTION_LEN,
906 VM_ENTRY_EXCEPTION_ERROR_CODE,
912 static int max_shadow_read_write_fields =
913 ARRAY_SIZE(shadow_read_write_fields);
915 static const unsigned short vmcs_field_to_offset_table[] = {
916 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
917 FIELD(POSTED_INTR_NV, posted_intr_nv),
918 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
919 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
920 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
921 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
922 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
923 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
924 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
925 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
926 FIELD(GUEST_INTR_STATUS, guest_intr_status),
927 FIELD(GUEST_PML_INDEX, guest_pml_index),
928 FIELD(HOST_ES_SELECTOR, host_es_selector),
929 FIELD(HOST_CS_SELECTOR, host_cs_selector),
930 FIELD(HOST_SS_SELECTOR, host_ss_selector),
931 FIELD(HOST_DS_SELECTOR, host_ds_selector),
932 FIELD(HOST_FS_SELECTOR, host_fs_selector),
933 FIELD(HOST_GS_SELECTOR, host_gs_selector),
934 FIELD(HOST_TR_SELECTOR, host_tr_selector),
935 FIELD64(IO_BITMAP_A, io_bitmap_a),
936 FIELD64(IO_BITMAP_B, io_bitmap_b),
937 FIELD64(MSR_BITMAP, msr_bitmap),
938 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
939 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
940 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
941 FIELD64(TSC_OFFSET, tsc_offset),
942 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
943 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
944 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
945 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
946 FIELD64(EPT_POINTER, ept_pointer),
947 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
948 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
949 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
950 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
951 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
952 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
953 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
954 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
955 FIELD64(PML_ADDRESS, pml_address),
956 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
957 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
958 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
959 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
960 FIELD64(GUEST_PDPTR0, guest_pdptr0),
961 FIELD64(GUEST_PDPTR1, guest_pdptr1),
962 FIELD64(GUEST_PDPTR2, guest_pdptr2),
963 FIELD64(GUEST_PDPTR3, guest_pdptr3),
964 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
965 FIELD64(HOST_IA32_PAT, host_ia32_pat),
966 FIELD64(HOST_IA32_EFER, host_ia32_efer),
967 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
968 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
969 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
970 FIELD(EXCEPTION_BITMAP, exception_bitmap),
971 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
972 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
973 FIELD(CR3_TARGET_COUNT, cr3_target_count),
974 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
975 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
976 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
977 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
978 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
979 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
980 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
981 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
982 FIELD(TPR_THRESHOLD, tpr_threshold),
983 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
984 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
985 FIELD(VM_EXIT_REASON, vm_exit_reason),
986 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
987 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
988 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
989 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
990 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
991 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
992 FIELD(GUEST_ES_LIMIT, guest_es_limit),
993 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
994 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
995 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
996 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
997 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
998 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
999 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1000 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1001 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1002 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1003 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1004 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1005 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1006 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1007 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1008 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1009 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1010 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1011 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1012 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1013 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1014 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1015 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1016 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1017 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1018 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1019 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1020 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1021 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1022 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1023 FIELD(EXIT_QUALIFICATION, exit_qualification),
1024 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1025 FIELD(GUEST_CR0, guest_cr0),
1026 FIELD(GUEST_CR3, guest_cr3),
1027 FIELD(GUEST_CR4, guest_cr4),
1028 FIELD(GUEST_ES_BASE, guest_es_base),
1029 FIELD(GUEST_CS_BASE, guest_cs_base),
1030 FIELD(GUEST_SS_BASE, guest_ss_base),
1031 FIELD(GUEST_DS_BASE, guest_ds_base),
1032 FIELD(GUEST_FS_BASE, guest_fs_base),
1033 FIELD(GUEST_GS_BASE, guest_gs_base),
1034 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1035 FIELD(GUEST_TR_BASE, guest_tr_base),
1036 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1037 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1038 FIELD(GUEST_DR7, guest_dr7),
1039 FIELD(GUEST_RSP, guest_rsp),
1040 FIELD(GUEST_RIP, guest_rip),
1041 FIELD(GUEST_RFLAGS, guest_rflags),
1042 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1043 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1044 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1045 FIELD(HOST_CR0, host_cr0),
1046 FIELD(HOST_CR3, host_cr3),
1047 FIELD(HOST_CR4, host_cr4),
1048 FIELD(HOST_FS_BASE, host_fs_base),
1049 FIELD(HOST_GS_BASE, host_gs_base),
1050 FIELD(HOST_TR_BASE, host_tr_base),
1051 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1052 FIELD(HOST_IDTR_BASE, host_idtr_base),
1053 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1054 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1055 FIELD(HOST_RSP, host_rsp),
1056 FIELD(HOST_RIP, host_rip),
1059 static inline short vmcs_field_to_offset(unsigned long field)
1061 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1062 unsigned short offset;
1064 BUILD_BUG_ON(size > SHRT_MAX);
1068 field = array_index_nospec(field, size);
1069 offset = vmcs_field_to_offset_table[field];
1075 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1077 return to_vmx(vcpu)->nested.cached_vmcs12;
1080 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1081 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1082 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1083 static bool vmx_xsaves_supported(void);
1084 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
1085 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1086 struct kvm_segment *var, int seg);
1087 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1088 struct kvm_segment *var, int seg);
1089 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1090 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1091 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
1092 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1093 static int alloc_identity_pagetable(struct kvm *kvm);
1094 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1095 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1096 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1098 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1099 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1102 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1103 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1105 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1106 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1108 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1111 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1112 * can find which vCPU should be waken up.
1114 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1115 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1125 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1127 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
1128 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
1129 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1130 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1132 static bool cpu_has_load_ia32_efer;
1133 static bool cpu_has_load_perf_global_ctrl;
1135 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1136 static DEFINE_SPINLOCK(vmx_vpid_lock);
1138 static struct vmcs_config {
1143 u32 pin_based_exec_ctrl;
1144 u32 cpu_based_exec_ctrl;
1145 u32 cpu_based_2nd_exec_ctrl;
1150 static struct vmx_capability {
1155 #define VMX_SEGMENT_FIELD(seg) \
1156 [VCPU_SREG_##seg] = { \
1157 .selector = GUEST_##seg##_SELECTOR, \
1158 .base = GUEST_##seg##_BASE, \
1159 .limit = GUEST_##seg##_LIMIT, \
1160 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1163 static const struct kvm_vmx_segment_field {
1168 } kvm_vmx_segment_fields[] = {
1169 VMX_SEGMENT_FIELD(CS),
1170 VMX_SEGMENT_FIELD(DS),
1171 VMX_SEGMENT_FIELD(ES),
1172 VMX_SEGMENT_FIELD(FS),
1173 VMX_SEGMENT_FIELD(GS),
1174 VMX_SEGMENT_FIELD(SS),
1175 VMX_SEGMENT_FIELD(TR),
1176 VMX_SEGMENT_FIELD(LDTR),
1179 static u64 host_efer;
1181 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1184 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1185 * away by decrementing the array size.
1187 static const u32 vmx_msr_index[] = {
1188 #ifdef CONFIG_X86_64
1189 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1191 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1194 static inline bool is_exception_n(u32 intr_info, u8 vector)
1196 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1197 INTR_INFO_VALID_MASK)) ==
1198 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1201 static inline bool is_debug(u32 intr_info)
1203 return is_exception_n(intr_info, DB_VECTOR);
1206 static inline bool is_breakpoint(u32 intr_info)
1208 return is_exception_n(intr_info, BP_VECTOR);
1211 static inline bool is_page_fault(u32 intr_info)
1213 return is_exception_n(intr_info, PF_VECTOR);
1216 static inline bool is_no_device(u32 intr_info)
1218 return is_exception_n(intr_info, NM_VECTOR);
1221 static inline bool is_invalid_opcode(u32 intr_info)
1223 return is_exception_n(intr_info, UD_VECTOR);
1226 static inline bool is_external_interrupt(u32 intr_info)
1228 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1229 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1232 static inline bool is_machine_check(u32 intr_info)
1234 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1235 INTR_INFO_VALID_MASK)) ==
1236 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1239 /* Undocumented: icebp/int1 */
1240 static inline bool is_icebp(u32 intr_info)
1242 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1243 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1246 static inline bool cpu_has_vmx_msr_bitmap(void)
1248 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1251 static inline bool cpu_has_vmx_tpr_shadow(void)
1253 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1256 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1258 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1261 static inline bool cpu_has_secondary_exec_ctrls(void)
1263 return vmcs_config.cpu_based_exec_ctrl &
1264 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1267 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1269 return vmcs_config.cpu_based_2nd_exec_ctrl &
1270 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1273 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1275 return vmcs_config.cpu_based_2nd_exec_ctrl &
1276 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1279 static inline bool cpu_has_vmx_apic_register_virt(void)
1281 return vmcs_config.cpu_based_2nd_exec_ctrl &
1282 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1285 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1287 return vmcs_config.cpu_based_2nd_exec_ctrl &
1288 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1292 * Comment's format: document - errata name - stepping - processor name.
1294 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1296 static u32 vmx_preemption_cpu_tfms[] = {
1297 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1299 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1300 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1301 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1303 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1305 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1306 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1308 * 320767.pdf - AAP86 - B1 -
1309 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1312 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1314 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1316 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1318 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1319 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1320 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1324 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1326 u32 eax = cpuid_eax(0x00000001), i;
1328 /* Clear the reserved bits */
1329 eax &= ~(0x3U << 14 | 0xfU << 28);
1330 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1331 if (eax == vmx_preemption_cpu_tfms[i])
1337 static inline bool cpu_has_vmx_preemption_timer(void)
1339 return vmcs_config.pin_based_exec_ctrl &
1340 PIN_BASED_VMX_PREEMPTION_TIMER;
1343 static inline bool cpu_has_vmx_posted_intr(void)
1345 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1346 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1349 static inline bool cpu_has_vmx_apicv(void)
1351 return cpu_has_vmx_apic_register_virt() &&
1352 cpu_has_vmx_virtual_intr_delivery() &&
1353 cpu_has_vmx_posted_intr();
1356 static inline bool cpu_has_vmx_flexpriority(void)
1358 return cpu_has_vmx_tpr_shadow() &&
1359 cpu_has_vmx_virtualize_apic_accesses();
1362 static inline bool cpu_has_vmx_ept_execute_only(void)
1364 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1367 static inline bool cpu_has_vmx_ept_2m_page(void)
1369 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1372 static inline bool cpu_has_vmx_ept_1g_page(void)
1374 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1377 static inline bool cpu_has_vmx_ept_4levels(void)
1379 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1382 static inline bool cpu_has_vmx_ept_mt_wb(void)
1384 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1387 static inline bool cpu_has_vmx_ept_5levels(void)
1389 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1392 static inline bool cpu_has_vmx_ept_ad_bits(void)
1394 return vmx_capability.ept & VMX_EPT_AD_BIT;
1397 static inline bool cpu_has_vmx_invept_context(void)
1399 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1402 static inline bool cpu_has_vmx_invept_global(void)
1404 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1407 static inline bool cpu_has_vmx_invvpid_single(void)
1409 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1412 static inline bool cpu_has_vmx_invvpid_global(void)
1414 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1417 static inline bool cpu_has_vmx_invvpid(void)
1419 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1422 static inline bool cpu_has_vmx_ept(void)
1424 return vmcs_config.cpu_based_2nd_exec_ctrl &
1425 SECONDARY_EXEC_ENABLE_EPT;
1428 static inline bool cpu_has_vmx_unrestricted_guest(void)
1430 return vmcs_config.cpu_based_2nd_exec_ctrl &
1431 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1434 static inline bool cpu_has_vmx_ple(void)
1436 return vmcs_config.cpu_based_2nd_exec_ctrl &
1437 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1440 static inline bool cpu_has_vmx_basic_inout(void)
1442 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1445 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1447 return flexpriority_enabled && lapic_in_kernel(vcpu);
1450 static inline bool cpu_has_vmx_vpid(void)
1452 return vmcs_config.cpu_based_2nd_exec_ctrl &
1453 SECONDARY_EXEC_ENABLE_VPID;
1456 static inline bool cpu_has_vmx_rdtscp(void)
1458 return vmcs_config.cpu_based_2nd_exec_ctrl &
1459 SECONDARY_EXEC_RDTSCP;
1462 static inline bool cpu_has_vmx_invpcid(void)
1464 return vmcs_config.cpu_based_2nd_exec_ctrl &
1465 SECONDARY_EXEC_ENABLE_INVPCID;
1468 static inline bool cpu_has_virtual_nmis(void)
1470 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1473 static inline bool cpu_has_vmx_wbinvd_exit(void)
1475 return vmcs_config.cpu_based_2nd_exec_ctrl &
1476 SECONDARY_EXEC_WBINVD_EXITING;
1479 static inline bool cpu_has_vmx_shadow_vmcs(void)
1482 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1483 /* check if the cpu supports writing r/o exit information fields */
1484 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1487 return vmcs_config.cpu_based_2nd_exec_ctrl &
1488 SECONDARY_EXEC_SHADOW_VMCS;
1491 static inline bool cpu_has_vmx_pml(void)
1493 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1496 static inline bool cpu_has_vmx_tsc_scaling(void)
1498 return vmcs_config.cpu_based_2nd_exec_ctrl &
1499 SECONDARY_EXEC_TSC_SCALING;
1502 static inline bool cpu_has_vmx_vmfunc(void)
1504 return vmcs_config.cpu_based_2nd_exec_ctrl &
1505 SECONDARY_EXEC_ENABLE_VMFUNC;
1508 static inline bool report_flexpriority(void)
1510 return flexpriority_enabled;
1513 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1515 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1518 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1520 return vmcs12->cpu_based_vm_exec_control & bit;
1523 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1525 return (vmcs12->cpu_based_vm_exec_control &
1526 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1527 (vmcs12->secondary_vm_exec_control & bit);
1530 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1532 return vmcs12->pin_based_vm_exec_control &
1533 PIN_BASED_VMX_PREEMPTION_TIMER;
1536 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1538 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1541 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1543 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1546 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1548 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1551 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1553 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1556 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1558 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1561 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1563 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1566 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1568 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1571 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1573 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1576 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1578 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1581 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1583 return nested_cpu_has_vmfunc(vmcs12) &&
1584 (vmcs12->vm_function_control &
1585 VMX_VMFUNC_EPTP_SWITCHING);
1588 static inline bool is_nmi(u32 intr_info)
1590 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1591 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1594 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1596 unsigned long exit_qualification);
1597 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1598 struct vmcs12 *vmcs12,
1599 u32 reason, unsigned long qualification);
1601 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1605 for (i = 0; i < vmx->nmsrs; ++i)
1606 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1611 static inline void __invvpid(unsigned long ext, u16 vpid, gva_t gva)
1617 } operand = { vpid, 0, gva };
1619 asm volatile (__ex(ASM_VMX_INVVPID)
1620 /* CF==1 or ZF==1 --> rc = -1 */
1621 "; ja 1f ; ud2 ; 1:"
1622 : : "a"(&operand), "c"(ext) : "cc", "memory");
1625 static inline void __invept(unsigned long ext, u64 eptp, gpa_t gpa)
1629 } operand = {eptp, gpa};
1631 asm volatile (__ex(ASM_VMX_INVEPT)
1632 /* CF==1 or ZF==1 --> rc = -1 */
1633 "; ja 1f ; ud2 ; 1:\n"
1634 : : "a" (&operand), "c" (ext) : "cc", "memory");
1637 static void vmx_setup_fb_clear_ctrl(void)
1641 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES) &&
1642 !boot_cpu_has_bug(X86_BUG_MDS) &&
1643 !boot_cpu_has_bug(X86_BUG_TAA)) {
1644 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
1645 if (msr & ARCH_CAP_FB_CLEAR_CTRL)
1646 vmx_fb_clear_ctrl_available = true;
1650 static __always_inline void vmx_disable_fb_clear(struct vcpu_vmx *vmx)
1654 if (!vmx->disable_fb_clear)
1657 rdmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
1658 msr |= FB_CLEAR_DIS;
1659 wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
1660 /* Cache the MSR value to avoid reading it later */
1661 vmx->msr_ia32_mcu_opt_ctrl = msr;
1664 static __always_inline void vmx_enable_fb_clear(struct vcpu_vmx *vmx)
1666 if (!vmx->disable_fb_clear)
1669 vmx->msr_ia32_mcu_opt_ctrl &= ~FB_CLEAR_DIS;
1670 wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);
1673 static void vmx_update_fb_clear_dis(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx)
1675 vmx->disable_fb_clear = vmx_fb_clear_ctrl_available;
1678 * If guest will not execute VERW, there is no need to set FB_CLEAR_DIS
1679 * at VMEntry. Skip the MSR read/write when a guest has no use case to
1682 if ((vcpu->arch.arch_capabilities & ARCH_CAP_FB_CLEAR) ||
1683 ((vcpu->arch.arch_capabilities & ARCH_CAP_MDS_NO) &&
1684 (vcpu->arch.arch_capabilities & ARCH_CAP_TAA_NO) &&
1685 (vcpu->arch.arch_capabilities & ARCH_CAP_PSDP_NO) &&
1686 (vcpu->arch.arch_capabilities & ARCH_CAP_FBSDP_NO) &&
1687 (vcpu->arch.arch_capabilities & ARCH_CAP_SBDR_SSDP_NO)))
1688 vmx->disable_fb_clear = false;
1691 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1695 i = __find_msr_index(vmx, msr);
1697 return &vmx->guest_msrs[i];
1701 static void vmcs_clear(struct vmcs *vmcs)
1703 u64 phys_addr = __pa(vmcs);
1706 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1707 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1710 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1714 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1716 vmcs_clear(loaded_vmcs->vmcs);
1717 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1718 vmcs_clear(loaded_vmcs->shadow_vmcs);
1719 loaded_vmcs->cpu = -1;
1720 loaded_vmcs->launched = 0;
1723 static void vmcs_load(struct vmcs *vmcs)
1725 u64 phys_addr = __pa(vmcs);
1728 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1729 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1732 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1736 #ifdef CONFIG_KEXEC_CORE
1737 static void crash_vmclear_local_loaded_vmcss(void)
1739 int cpu = raw_smp_processor_id();
1740 struct loaded_vmcs *v;
1742 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1743 loaded_vmcss_on_cpu_link)
1744 vmcs_clear(v->vmcs);
1746 #endif /* CONFIG_KEXEC_CORE */
1748 static void __loaded_vmcs_clear(void *arg)
1750 struct loaded_vmcs *loaded_vmcs = arg;
1751 int cpu = raw_smp_processor_id();
1753 if (loaded_vmcs->cpu != cpu)
1754 return; /* vcpu migration can race with cpu offline */
1755 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1756 per_cpu(current_vmcs, cpu) = NULL;
1758 vmcs_clear(loaded_vmcs->vmcs);
1759 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1760 vmcs_clear(loaded_vmcs->shadow_vmcs);
1762 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1765 * Ensure all writes to loaded_vmcs, including deleting it from its
1766 * current percpu list, complete before setting loaded_vmcs->vcpu to
1767 * -1, otherwise a different cpu can see vcpu == -1 first and add
1768 * loaded_vmcs to its percpu list before it's deleted from this cpu's
1769 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
1773 loaded_vmcs->cpu = -1;
1774 loaded_vmcs->launched = 0;
1777 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1779 int cpu = loaded_vmcs->cpu;
1782 smp_call_function_single(cpu,
1783 __loaded_vmcs_clear, loaded_vmcs, 1);
1786 static inline void vpid_sync_vcpu_single(int vpid)
1791 if (cpu_has_vmx_invvpid_single())
1792 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1795 static inline void vpid_sync_vcpu_global(void)
1797 if (cpu_has_vmx_invvpid_global())
1798 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1801 static inline void vpid_sync_context(int vpid)
1803 if (cpu_has_vmx_invvpid_single())
1804 vpid_sync_vcpu_single(vpid);
1806 vpid_sync_vcpu_global();
1809 static inline void ept_sync_global(void)
1811 if (cpu_has_vmx_invept_global())
1812 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1815 static inline void ept_sync_context(u64 eptp)
1818 if (cpu_has_vmx_invept_context())
1819 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1825 static __always_inline void vmcs_check16(unsigned long field)
1827 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1828 "16-bit accessor invalid for 64-bit field");
1829 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1830 "16-bit accessor invalid for 64-bit high field");
1831 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1832 "16-bit accessor invalid for 32-bit high field");
1833 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1834 "16-bit accessor invalid for natural width field");
1837 static __always_inline void vmcs_check32(unsigned long field)
1839 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1840 "32-bit accessor invalid for 16-bit field");
1841 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1842 "32-bit accessor invalid for natural width field");
1845 static __always_inline void vmcs_check64(unsigned long field)
1847 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1848 "64-bit accessor invalid for 16-bit field");
1849 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1850 "64-bit accessor invalid for 64-bit high field");
1851 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1852 "64-bit accessor invalid for 32-bit field");
1853 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1854 "64-bit accessor invalid for natural width field");
1857 static __always_inline void vmcs_checkl(unsigned long field)
1859 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1860 "Natural width accessor invalid for 16-bit field");
1861 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1862 "Natural width accessor invalid for 64-bit field");
1863 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1864 "Natural width accessor invalid for 64-bit high field");
1865 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1866 "Natural width accessor invalid for 32-bit field");
1869 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1871 unsigned long value;
1873 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1874 : "=a"(value) : "d"(field) : "cc");
1878 static __always_inline u16 vmcs_read16(unsigned long field)
1880 vmcs_check16(field);
1881 return __vmcs_readl(field);
1884 static __always_inline u32 vmcs_read32(unsigned long field)
1886 vmcs_check32(field);
1887 return __vmcs_readl(field);
1890 static __always_inline u64 vmcs_read64(unsigned long field)
1892 vmcs_check64(field);
1893 #ifdef CONFIG_X86_64
1894 return __vmcs_readl(field);
1896 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1900 static __always_inline unsigned long vmcs_readl(unsigned long field)
1903 return __vmcs_readl(field);
1906 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1908 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1909 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1913 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1917 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1918 : "=q"(error) : "a"(value), "d"(field) : "cc");
1919 if (unlikely(error))
1920 vmwrite_error(field, value);
1923 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1925 vmcs_check16(field);
1926 __vmcs_writel(field, value);
1929 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1931 vmcs_check32(field);
1932 __vmcs_writel(field, value);
1935 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1937 vmcs_check64(field);
1938 __vmcs_writel(field, value);
1939 #ifndef CONFIG_X86_64
1941 __vmcs_writel(field+1, value >> 32);
1945 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1948 __vmcs_writel(field, value);
1951 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1953 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1954 "vmcs_clear_bits does not support 64-bit fields");
1955 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1958 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1960 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1961 "vmcs_set_bits does not support 64-bit fields");
1962 __vmcs_writel(field, __vmcs_readl(field) | mask);
1965 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1967 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1970 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1972 vmcs_write32(VM_ENTRY_CONTROLS, val);
1973 vmx->vm_entry_controls_shadow = val;
1976 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1978 if (vmx->vm_entry_controls_shadow != val)
1979 vm_entry_controls_init(vmx, val);
1982 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1984 return vmx->vm_entry_controls_shadow;
1988 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1990 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1993 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1995 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1998 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2000 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2003 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2005 vmcs_write32(VM_EXIT_CONTROLS, val);
2006 vmx->vm_exit_controls_shadow = val;
2009 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2011 if (vmx->vm_exit_controls_shadow != val)
2012 vm_exit_controls_init(vmx, val);
2015 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2017 return vmx->vm_exit_controls_shadow;
2021 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2023 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2026 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2028 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2031 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2033 vmx->segment_cache.bitmask = 0;
2036 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2040 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2042 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2043 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2044 vmx->segment_cache.bitmask = 0;
2046 ret = vmx->segment_cache.bitmask & mask;
2047 vmx->segment_cache.bitmask |= mask;
2051 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2053 u16 *p = &vmx->segment_cache.seg[seg].selector;
2055 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2056 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2060 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2062 ulong *p = &vmx->segment_cache.seg[seg].base;
2064 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2065 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2069 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2071 u32 *p = &vmx->segment_cache.seg[seg].limit;
2073 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2074 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2078 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2080 u32 *p = &vmx->segment_cache.seg[seg].ar;
2082 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2083 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2087 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2091 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2092 (1u << DB_VECTOR) | (1u << AC_VECTOR);
2093 if ((vcpu->guest_debug &
2094 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2095 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2096 eb |= 1u << BP_VECTOR;
2097 if (to_vmx(vcpu)->rmode.vm86_active)
2100 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2102 /* When we are running a nested L2 guest and L1 specified for it a
2103 * certain exception bitmap, we must trap the same exceptions and pass
2104 * them to L1. When running L2, we will only handle the exceptions
2105 * specified above if L1 did not want them.
2107 if (is_guest_mode(vcpu))
2108 eb |= get_vmcs12(vcpu)->exception_bitmap;
2110 vmcs_write32(EXCEPTION_BITMAP, eb);
2114 * Check if MSR is intercepted for currently loaded MSR bitmap.
2116 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2118 unsigned long *msr_bitmap;
2119 int f = sizeof(unsigned long);
2121 if (!cpu_has_vmx_msr_bitmap())
2124 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2126 if (msr <= 0x1fff) {
2127 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2128 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2130 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2137 * Check if MSR is intercepted for L01 MSR bitmap.
2139 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2141 unsigned long *msr_bitmap;
2142 int f = sizeof(unsigned long);
2144 if (!cpu_has_vmx_msr_bitmap())
2147 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2149 if (msr <= 0x1fff) {
2150 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2151 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2153 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2159 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2160 unsigned long entry, unsigned long exit)
2162 vm_entry_controls_clearbit(vmx, entry);
2163 vm_exit_controls_clearbit(vmx, exit);
2166 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2170 for (i = 0; i < m->nr; ++i) {
2171 if (m->val[i].index == msr)
2177 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2180 struct msr_autoload *m = &vmx->msr_autoload;
2184 if (cpu_has_load_ia32_efer) {
2185 clear_atomic_switch_msr_special(vmx,
2186 VM_ENTRY_LOAD_IA32_EFER,
2187 VM_EXIT_LOAD_IA32_EFER);
2191 case MSR_CORE_PERF_GLOBAL_CTRL:
2192 if (cpu_has_load_perf_global_ctrl) {
2193 clear_atomic_switch_msr_special(vmx,
2194 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2195 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2200 i = find_msr(&m->guest, msr);
2204 m->guest.val[i] = m->guest.val[m->guest.nr];
2205 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2208 i = find_msr(&m->host, msr);
2213 m->host.val[i] = m->host.val[m->host.nr];
2214 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2217 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2218 unsigned long entry, unsigned long exit,
2219 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2220 u64 guest_val, u64 host_val)
2222 vmcs_write64(guest_val_vmcs, guest_val);
2223 vmcs_write64(host_val_vmcs, host_val);
2224 vm_entry_controls_setbit(vmx, entry);
2225 vm_exit_controls_setbit(vmx, exit);
2228 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2229 u64 guest_val, u64 host_val, bool entry_only)
2232 struct msr_autoload *m = &vmx->msr_autoload;
2236 if (cpu_has_load_ia32_efer) {
2237 add_atomic_switch_msr_special(vmx,
2238 VM_ENTRY_LOAD_IA32_EFER,
2239 VM_EXIT_LOAD_IA32_EFER,
2242 guest_val, host_val);
2246 case MSR_CORE_PERF_GLOBAL_CTRL:
2247 if (cpu_has_load_perf_global_ctrl) {
2248 add_atomic_switch_msr_special(vmx,
2249 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2250 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2251 GUEST_IA32_PERF_GLOBAL_CTRL,
2252 HOST_IA32_PERF_GLOBAL_CTRL,
2253 guest_val, host_val);
2257 case MSR_IA32_PEBS_ENABLE:
2258 /* PEBS needs a quiescent period after being disabled (to write
2259 * a record). Disabling PEBS through VMX MSR swapping doesn't
2260 * provide that period, so a CPU could write host's record into
2263 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2266 i = find_msr(&m->guest, msr);
2268 j = find_msr(&m->host, msr);
2270 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
2271 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
2272 printk_once(KERN_WARNING "Not enough msr switch entries. "
2273 "Can't add msr %x\n", msr);
2278 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2280 m->guest.val[i].index = msr;
2281 m->guest.val[i].value = guest_val;
2288 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2290 m->host.val[j].index = msr;
2291 m->host.val[j].value = host_val;
2294 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2296 u64 guest_efer = vmx->vcpu.arch.efer;
2297 u64 ignore_bits = 0;
2299 /* Shadow paging assumes NX to be available. */
2301 guest_efer |= EFER_NX;
2304 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2306 ignore_bits |= EFER_SCE;
2307 #ifdef CONFIG_X86_64
2308 ignore_bits |= EFER_LMA | EFER_LME;
2309 /* SCE is meaningful only in long mode on Intel */
2310 if (guest_efer & EFER_LMA)
2311 ignore_bits &= ~(u64)EFER_SCE;
2314 clear_atomic_switch_msr(vmx, MSR_EFER);
2317 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2318 * On CPUs that support "load IA32_EFER", always switch EFER
2319 * atomically, since it's faster than switching it manually.
2321 if (cpu_has_load_ia32_efer ||
2322 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2323 if (!(guest_efer & EFER_LMA))
2324 guest_efer &= ~EFER_LME;
2325 if (guest_efer != host_efer)
2326 add_atomic_switch_msr(vmx, MSR_EFER,
2327 guest_efer, host_efer, false);
2330 guest_efer &= ~ignore_bits;
2331 guest_efer |= host_efer & ignore_bits;
2333 vmx->guest_msrs[efer_offset].data = guest_efer;
2334 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2340 #ifdef CONFIG_X86_32
2342 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2343 * VMCS rather than the segment table. KVM uses this helper to figure
2344 * out the current bases to poke them into the VMCS before entry.
2346 static unsigned long segment_base(u16 selector)
2348 struct desc_struct *table;
2351 if (!(selector & ~SEGMENT_RPL_MASK))
2354 table = get_current_gdt_ro();
2356 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2357 u16 ldt_selector = kvm_read_ldt();
2359 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2362 table = (struct desc_struct *)segment_base(ldt_selector);
2364 v = get_desc_base(&table[selector >> 3]);
2369 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2371 struct vcpu_vmx *vmx = to_vmx(vcpu);
2374 if (vmx->loaded_cpu_state)
2377 vmx->loaded_cpu_state = vmx->loaded_vmcs;
2380 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2381 * allow segment selectors with cpl > 0 or ti == 1.
2383 vmx->host_state.ldt_sel = kvm_read_ldt();
2384 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2385 savesegment(fs, vmx->host_state.fs_sel);
2386 if (!(vmx->host_state.fs_sel & 7)) {
2387 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2388 vmx->host_state.fs_reload_needed = 0;
2390 vmcs_write16(HOST_FS_SELECTOR, 0);
2391 vmx->host_state.fs_reload_needed = 1;
2393 savesegment(gs, vmx->host_state.gs_sel);
2394 if (!(vmx->host_state.gs_sel & 7))
2395 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2397 vmcs_write16(HOST_GS_SELECTOR, 0);
2398 vmx->host_state.gs_ldt_reload_needed = 1;
2401 #ifdef CONFIG_X86_64
2402 savesegment(ds, vmx->host_state.ds_sel);
2403 savesegment(es, vmx->host_state.es_sel);
2406 #ifdef CONFIG_X86_64
2407 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2408 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2410 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2411 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2414 #ifdef CONFIG_X86_64
2415 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2416 if (is_long_mode(&vmx->vcpu))
2417 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2419 if (boot_cpu_has(X86_FEATURE_MPX))
2420 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2421 for (i = 0; i < vmx->save_nmsrs; ++i)
2422 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2423 vmx->guest_msrs[i].data,
2424 vmx->guest_msrs[i].mask);
2427 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2429 if (!vmx->loaded_cpu_state)
2432 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
2434 ++vmx->vcpu.stat.host_state_reload;
2435 vmx->loaded_cpu_state = NULL;
2437 #ifdef CONFIG_X86_64
2438 if (is_long_mode(&vmx->vcpu))
2439 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2441 if (vmx->host_state.gs_ldt_reload_needed) {
2442 kvm_load_ldt(vmx->host_state.ldt_sel);
2443 #ifdef CONFIG_X86_64
2444 load_gs_index(vmx->host_state.gs_sel);
2446 loadsegment(gs, vmx->host_state.gs_sel);
2449 if (vmx->host_state.fs_reload_needed)
2450 loadsegment(fs, vmx->host_state.fs_sel);
2451 #ifdef CONFIG_X86_64
2452 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2453 loadsegment(ds, vmx->host_state.ds_sel);
2454 loadsegment(es, vmx->host_state.es_sel);
2457 invalidate_tss_limit();
2458 #ifdef CONFIG_X86_64
2459 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2461 if (vmx->host_state.msr_host_bndcfgs)
2462 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2463 load_fixmap_gdt(raw_smp_processor_id());
2466 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2469 __vmx_load_host_state(vmx);
2473 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2475 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2476 struct pi_desc old, new;
2480 * In case of hot-plug or hot-unplug, we may have to undo
2481 * vmx_vcpu_pi_put even if there is no assigned device. And we
2482 * always keep PI.NDST up to date for simplicity: it makes the
2483 * code easier, and CPU migration is not a fast path.
2485 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2489 * First handle the simple case where no cmpxchg is necessary; just
2490 * allow posting non-urgent interrupts.
2492 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2493 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2494 * expects the VCPU to be on the blocked_vcpu_list that matches
2497 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2499 pi_clear_sn(pi_desc);
2503 /* The full case. */
2505 old.control = new.control = pi_desc->control;
2507 dest = cpu_physical_id(cpu);
2509 if (x2apic_enabled())
2512 new.ndst = (dest << 8) & 0xFF00;
2515 } while (cmpxchg64(&pi_desc->control, old.control,
2516 new.control) != old.control);
2519 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2521 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2522 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2526 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2527 * vcpu mutex is already taken.
2529 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2531 struct vcpu_vmx *vmx = to_vmx(vcpu);
2532 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2534 if (!already_loaded) {
2535 loaded_vmcs_clear(vmx->loaded_vmcs);
2536 local_irq_disable();
2539 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
2540 * this cpu's percpu list, otherwise it may not yet be deleted
2541 * from its previous cpu's percpu list. Pairs with the
2542 * smb_wmb() in __loaded_vmcs_clear().
2546 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2547 &per_cpu(loaded_vmcss_on_cpu, cpu));
2551 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2552 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2553 vmcs_load(vmx->loaded_vmcs->vmcs);
2554 indirect_branch_prediction_barrier();
2557 if (!already_loaded) {
2558 void *gdt = get_current_gdt_ro();
2559 unsigned long sysenter_esp;
2561 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2564 * Linux uses per-cpu TSS and GDT, so set these when switching
2565 * processors. See 22.2.4.
2567 vmcs_writel(HOST_TR_BASE,
2568 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2569 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2572 * VM exits change the host TR limit to 0x67 after a VM
2573 * exit. This is okay, since 0x67 covers everything except
2574 * the IO bitmap and have have code to handle the IO bitmap
2575 * being lost after a VM exit.
2577 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2579 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2580 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2582 vmx->loaded_vmcs->cpu = cpu;
2585 /* Setup TSC multiplier */
2586 if (kvm_has_tsc_control &&
2587 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2588 decache_tsc_multiplier(vmx);
2590 vmx_vcpu_pi_load(vcpu, cpu);
2591 vmx->host_pkru = read_pkru();
2594 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2596 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2598 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2599 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2600 !kvm_vcpu_apicv_active(vcpu))
2603 /* Set SN when the vCPU is preempted */
2604 if (vcpu->preempted)
2608 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2610 vmx_vcpu_pi_put(vcpu);
2612 __vmx_load_host_state(to_vmx(vcpu));
2615 static bool emulation_required(struct kvm_vcpu *vcpu)
2617 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2620 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2623 * Return the cr0 value that a nested guest would read. This is a combination
2624 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2625 * its hypervisor (cr0_read_shadow).
2627 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2629 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2630 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2632 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2634 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2635 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2638 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2640 unsigned long rflags, save_rflags;
2642 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2643 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2644 rflags = vmcs_readl(GUEST_RFLAGS);
2645 if (to_vmx(vcpu)->rmode.vm86_active) {
2646 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2647 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2648 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2650 to_vmx(vcpu)->rflags = rflags;
2652 return to_vmx(vcpu)->rflags;
2655 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2657 unsigned long old_rflags = vmx_get_rflags(vcpu);
2659 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2660 to_vmx(vcpu)->rflags = rflags;
2661 if (to_vmx(vcpu)->rmode.vm86_active) {
2662 to_vmx(vcpu)->rmode.save_rflags = rflags;
2663 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2665 vmcs_writel(GUEST_RFLAGS, rflags);
2667 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2668 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2671 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2673 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2676 if (interruptibility & GUEST_INTR_STATE_STI)
2677 ret |= KVM_X86_SHADOW_INT_STI;
2678 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2679 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2684 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2686 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2687 u32 interruptibility = interruptibility_old;
2689 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2691 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2692 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2693 else if (mask & KVM_X86_SHADOW_INT_STI)
2694 interruptibility |= GUEST_INTR_STATE_STI;
2696 if ((interruptibility != interruptibility_old))
2697 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2700 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2704 rip = kvm_rip_read(vcpu);
2705 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2706 kvm_rip_write(vcpu, rip);
2708 /* skipping an emulated instruction also counts */
2709 vmx_set_interrupt_shadow(vcpu, 0);
2712 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2713 unsigned long exit_qual)
2715 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2716 unsigned int nr = vcpu->arch.exception.nr;
2717 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2719 if (vcpu->arch.exception.has_error_code) {
2720 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2721 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2724 if (kvm_exception_is_soft(nr))
2725 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2727 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2729 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2730 vmx_get_nmi_mask(vcpu))
2731 intr_info |= INTR_INFO_UNBLOCK_NMI;
2733 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2737 * KVM wants to inject page-faults which it got to the guest. This function
2738 * checks whether in a nested guest, we need to inject them to L1 or L2.
2740 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2742 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2743 unsigned int nr = vcpu->arch.exception.nr;
2745 if (nr == PF_VECTOR) {
2746 if (vcpu->arch.exception.nested_apf) {
2747 *exit_qual = vcpu->arch.apf.nested_apf_token;
2751 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2752 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2753 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2754 * can be written only when inject_pending_event runs. This should be
2755 * conditional on a new capability---if the capability is disabled,
2756 * kvm_multiple_exception would write the ancillary information to
2757 * CR2 or DR6, for backwards ABI-compatibility.
2759 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2760 vcpu->arch.exception.error_code)) {
2761 *exit_qual = vcpu->arch.cr2;
2765 if (vmcs12->exception_bitmap & (1u << nr)) {
2766 if (nr == DB_VECTOR) {
2767 *exit_qual = vcpu->arch.dr6;
2768 *exit_qual &= ~(DR6_FIXED_1 | DR6_BT);
2769 *exit_qual ^= DR6_RTM;
2780 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2782 struct vcpu_vmx *vmx = to_vmx(vcpu);
2783 unsigned nr = vcpu->arch.exception.nr;
2784 bool has_error_code = vcpu->arch.exception.has_error_code;
2785 u32 error_code = vcpu->arch.exception.error_code;
2786 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2788 if (has_error_code) {
2789 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2790 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2793 if (vmx->rmode.vm86_active) {
2795 if (kvm_exception_is_soft(nr))
2796 inc_eip = vcpu->arch.event_exit_inst_len;
2797 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2798 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2802 WARN_ON_ONCE(vmx->emulation_required);
2804 if (kvm_exception_is_soft(nr)) {
2805 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2806 vmx->vcpu.arch.event_exit_inst_len);
2807 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2809 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2811 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2814 static bool vmx_rdtscp_supported(void)
2816 return cpu_has_vmx_rdtscp();
2819 static bool vmx_invpcid_supported(void)
2821 return cpu_has_vmx_invpcid() && enable_ept;
2825 * Swap MSR entry in host/guest MSR entry array.
2827 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2829 struct shared_msr_entry tmp;
2831 tmp = vmx->guest_msrs[to];
2832 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2833 vmx->guest_msrs[from] = tmp;
2837 * Set up the vmcs to automatically save and restore system
2838 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2839 * mode, as fiddling with msrs is very expensive.
2841 static void setup_msrs(struct vcpu_vmx *vmx)
2843 int save_nmsrs, index;
2846 #ifdef CONFIG_X86_64
2847 if (is_long_mode(&vmx->vcpu)) {
2848 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2850 move_msr_up(vmx, index, save_nmsrs++);
2851 index = __find_msr_index(vmx, MSR_LSTAR);
2853 move_msr_up(vmx, index, save_nmsrs++);
2854 index = __find_msr_index(vmx, MSR_CSTAR);
2856 move_msr_up(vmx, index, save_nmsrs++);
2858 * MSR_STAR is only needed on long mode guests, and only
2859 * if efer.sce is enabled.
2861 index = __find_msr_index(vmx, MSR_STAR);
2862 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2863 move_msr_up(vmx, index, save_nmsrs++);
2866 index = __find_msr_index(vmx, MSR_EFER);
2867 if (index >= 0 && update_transition_efer(vmx, index))
2868 move_msr_up(vmx, index, save_nmsrs++);
2869 index = __find_msr_index(vmx, MSR_TSC_AUX);
2870 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2871 move_msr_up(vmx, index, save_nmsrs++);
2873 vmx->save_nmsrs = save_nmsrs;
2875 if (cpu_has_vmx_msr_bitmap())
2876 vmx_update_msr_bitmap(&vmx->vcpu);
2880 * reads and returns guest's timestamp counter "register"
2881 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2882 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2884 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2886 u64 host_tsc, tsc_offset;
2889 tsc_offset = vmcs_read64(TSC_OFFSET);
2890 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2894 * writes 'offset' into guest's timestamp counter offset register
2896 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2898 if (is_guest_mode(vcpu)) {
2900 * We're here if L1 chose not to trap WRMSR to TSC. According
2901 * to the spec, this should set L1's TSC; The offset that L1
2902 * set for L2 remains unchanged, and still needs to be added
2903 * to the newly set TSC to get L2's TSC.
2905 struct vmcs12 *vmcs12;
2906 /* recalculate vmcs02.TSC_OFFSET: */
2907 vmcs12 = get_vmcs12(vcpu);
2908 vmcs_write64(TSC_OFFSET, offset +
2909 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2910 vmcs12->tsc_offset : 0));
2912 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2913 vmcs_read64(TSC_OFFSET), offset);
2914 vmcs_write64(TSC_OFFSET, offset);
2919 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2920 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2921 * all guests if the "nested" module option is off, and can also be disabled
2922 * for a single guest by disabling its VMX cpuid bit.
2924 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2926 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2930 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2931 * returned for the various VMX controls MSRs when nested VMX is enabled.
2932 * The same values should also be used to verify that vmcs12 control fields are
2933 * valid during nested entry from L1 to L2.
2934 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2935 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2936 * bit in the high half is on if the corresponding bit in the control field
2937 * may be on. See also vmx_control_verify().
2939 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2942 * Note that as a general rule, the high half of the MSRs (bits in
2943 * the control fields which may be 1) should be initialized by the
2944 * intersection of the underlying hardware's MSR (i.e., features which
2945 * can be supported) and the list of features we want to expose -
2946 * because they are known to be properly supported in our code.
2947 * Also, usually, the low half of the MSRs (bits which must be 1) can
2948 * be set to 0, meaning that L1 may turn off any of these bits. The
2949 * reason is that if one of these bits is necessary, it will appear
2950 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2951 * fields of vmcs01 and vmcs02, will turn these bits off - and
2952 * nested_vmx_exit_reflected() will not pass related exits to L1.
2953 * These rules have exceptions below.
2956 /* pin-based controls */
2957 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2958 vmx->nested.nested_vmx_pinbased_ctls_low,
2959 vmx->nested.nested_vmx_pinbased_ctls_high);
2960 vmx->nested.nested_vmx_pinbased_ctls_low |=
2961 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2962 vmx->nested.nested_vmx_pinbased_ctls_high &=
2963 PIN_BASED_EXT_INTR_MASK |
2964 PIN_BASED_NMI_EXITING |
2965 PIN_BASED_VIRTUAL_NMIS;
2966 vmx->nested.nested_vmx_pinbased_ctls_high |=
2967 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2968 PIN_BASED_VMX_PREEMPTION_TIMER;
2969 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2970 vmx->nested.nested_vmx_pinbased_ctls_high |=
2971 PIN_BASED_POSTED_INTR;
2974 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2975 vmx->nested.nested_vmx_exit_ctls_low,
2976 vmx->nested.nested_vmx_exit_ctls_high);
2977 vmx->nested.nested_vmx_exit_ctls_low =
2978 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2980 vmx->nested.nested_vmx_exit_ctls_high &=
2981 #ifdef CONFIG_X86_64
2982 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2984 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2985 vmx->nested.nested_vmx_exit_ctls_high |=
2986 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2987 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2988 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2990 if (kvm_mpx_supported())
2991 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2993 /* We support free control of debug control saving. */
2994 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996 /* entry controls */
2997 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2998 vmx->nested.nested_vmx_entry_ctls_low,
2999 vmx->nested.nested_vmx_entry_ctls_high);
3000 vmx->nested.nested_vmx_entry_ctls_low =
3001 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3002 vmx->nested.nested_vmx_entry_ctls_high &=
3003 #ifdef CONFIG_X86_64
3004 VM_ENTRY_IA32E_MODE |
3006 VM_ENTRY_LOAD_IA32_PAT;
3007 vmx->nested.nested_vmx_entry_ctls_high |=
3008 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3009 if (kvm_mpx_supported())
3010 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3012 /* We support free control of debug control loading. */
3013 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3015 /* cpu-based controls */
3016 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3017 vmx->nested.nested_vmx_procbased_ctls_low,
3018 vmx->nested.nested_vmx_procbased_ctls_high);
3019 vmx->nested.nested_vmx_procbased_ctls_low =
3020 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3021 vmx->nested.nested_vmx_procbased_ctls_high &=
3022 CPU_BASED_VIRTUAL_INTR_PENDING |
3023 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3024 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3025 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3026 CPU_BASED_CR3_STORE_EXITING |
3027 #ifdef CONFIG_X86_64
3028 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3030 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3031 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3032 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3033 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3034 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3036 * We can allow some features even when not supported by the
3037 * hardware. For example, L1 can specify an MSR bitmap - and we
3038 * can use it to avoid exits to L1 - even when L0 runs L2
3039 * without MSR bitmaps.
3041 vmx->nested.nested_vmx_procbased_ctls_high |=
3042 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3043 CPU_BASED_USE_MSR_BITMAPS;
3045 /* We support free control of CR3 access interception. */
3046 vmx->nested.nested_vmx_procbased_ctls_low &=
3047 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3050 * secondary cpu-based controls. Do not include those that
3051 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3053 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3054 vmx->nested.nested_vmx_secondary_ctls_low,
3055 vmx->nested.nested_vmx_secondary_ctls_high);
3056 vmx->nested.nested_vmx_secondary_ctls_low = 0;
3057 vmx->nested.nested_vmx_secondary_ctls_high &=
3058 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3059 SECONDARY_EXEC_DESC |
3060 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3061 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3062 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3063 SECONDARY_EXEC_WBINVD_EXITING;
3066 /* nested EPT: emulate EPT also to L1 */
3067 vmx->nested.nested_vmx_secondary_ctls_high |=
3068 SECONDARY_EXEC_ENABLE_EPT;
3069 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3070 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3071 if (cpu_has_vmx_ept_execute_only())
3072 vmx->nested.nested_vmx_ept_caps |=
3073 VMX_EPT_EXECUTE_ONLY_BIT;
3074 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
3075 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3076 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3077 VMX_EPT_1GB_PAGE_BIT;
3078 if (enable_ept_ad_bits) {
3079 vmx->nested.nested_vmx_secondary_ctls_high |=
3080 SECONDARY_EXEC_ENABLE_PML;
3081 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
3084 vmx->nested.nested_vmx_ept_caps = 0;
3086 if (cpu_has_vmx_vmfunc()) {
3087 vmx->nested.nested_vmx_secondary_ctls_high |=
3088 SECONDARY_EXEC_ENABLE_VMFUNC;
3090 * Advertise EPTP switching unconditionally
3091 * since we emulate it
3094 vmx->nested.nested_vmx_vmfunc_controls =
3095 VMX_VMFUNC_EPTP_SWITCHING;
3099 * Old versions of KVM use the single-context version without
3100 * checking for support, so declare that it is supported even
3101 * though it is treated as global context. The alternative is
3102 * not failing the single-context invvpid, and it is worse.
3105 vmx->nested.nested_vmx_secondary_ctls_high |=
3106 SECONDARY_EXEC_ENABLE_VPID;
3107 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
3108 VMX_VPID_EXTENT_SUPPORTED_MASK;
3110 vmx->nested.nested_vmx_vpid_caps = 0;
3112 if (enable_unrestricted_guest)
3113 vmx->nested.nested_vmx_secondary_ctls_high |=
3114 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3116 /* miscellaneous data */
3117 rdmsr(MSR_IA32_VMX_MISC,
3118 vmx->nested.nested_vmx_misc_low,
3119 vmx->nested.nested_vmx_misc_high);
3120 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
3121 vmx->nested.nested_vmx_misc_low |=
3122 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3123 VMX_MISC_ACTIVITY_HLT;
3124 vmx->nested.nested_vmx_misc_high = 0;
3127 * This MSR reports some information about VMX support. We
3128 * should return information about the VMX we emulate for the
3129 * guest, and the VMCS structure we give it - not about the
3130 * VMX support of the underlying hardware.
3132 vmx->nested.nested_vmx_basic =
3134 VMX_BASIC_TRUE_CTLS |
3135 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3136 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3138 if (cpu_has_vmx_basic_inout())
3139 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
3142 * These MSRs specify bits which the guest must keep fixed on
3143 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3144 * We picked the standard core2 setting.
3146 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3147 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3148 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
3149 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
3151 /* These MSRs specify bits which the guest must keep fixed off. */
3152 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
3153 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
3155 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3156 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
3160 * if fixed0[i] == 1: val[i] must be 1
3161 * if fixed1[i] == 0: val[i] must be 0
3163 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3165 return ((val & fixed1) | fixed0) == val;
3168 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3170 return fixed_bits_valid(control, low, high);
3173 static inline u64 vmx_control_msr(u32 low, u32 high)
3175 return low | ((u64)high << 32);
3178 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3183 return (superset | subset) == superset;
3186 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3188 const u64 feature_and_reserved =
3189 /* feature (except bit 48; see below) */
3190 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3192 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3193 u64 vmx_basic = vmx->nested.nested_vmx_basic;
3195 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3199 * KVM does not emulate a version of VMX that constrains physical
3200 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3202 if (data & BIT_ULL(48))
3205 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3206 vmx_basic_vmcs_revision_id(data))
3209 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3212 vmx->nested.nested_vmx_basic = data;
3217 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3222 switch (msr_index) {
3223 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3224 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
3225 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
3227 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3228 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
3229 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
3231 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3232 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
3233 highp = &vmx->nested.nested_vmx_exit_ctls_high;
3235 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3236 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
3237 highp = &vmx->nested.nested_vmx_entry_ctls_high;
3239 case MSR_IA32_VMX_PROCBASED_CTLS2:
3240 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
3241 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
3247 supported = vmx_control_msr(*lowp, *highp);
3249 /* Check must-be-1 bits are still 1. */
3250 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3253 /* Check must-be-0 bits are still 0. */
3254 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3258 *highp = data >> 32;
3262 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3264 const u64 feature_and_reserved_bits =
3266 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3267 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3269 GENMASK_ULL(13, 9) | BIT_ULL(31);
3272 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3273 vmx->nested.nested_vmx_misc_high);
3275 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3278 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3279 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3280 vmx_misc_preemption_timer_rate(data) !=
3281 vmx_misc_preemption_timer_rate(vmx_misc))
3284 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3287 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3290 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3293 vmx->nested.nested_vmx_misc_low = data;
3294 vmx->nested.nested_vmx_misc_high = data >> 32;
3298 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3300 u64 vmx_ept_vpid_cap;
3302 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3303 vmx->nested.nested_vmx_vpid_caps);
3305 /* Every bit is either reserved or a feature bit. */
3306 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3309 vmx->nested.nested_vmx_ept_caps = data;
3310 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3314 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3318 switch (msr_index) {
3319 case MSR_IA32_VMX_CR0_FIXED0:
3320 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3322 case MSR_IA32_VMX_CR4_FIXED0:
3323 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3330 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3331 * must be 1 in the restored value.
3333 if (!is_bitwise_subset(data, *msr, -1ULL))
3341 * Called when userspace is restoring VMX MSRs.
3343 * Returns 0 on success, non-0 otherwise.
3345 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3347 struct vcpu_vmx *vmx = to_vmx(vcpu);
3349 switch (msr_index) {
3350 case MSR_IA32_VMX_BASIC:
3351 return vmx_restore_vmx_basic(vmx, data);
3352 case MSR_IA32_VMX_PINBASED_CTLS:
3353 case MSR_IA32_VMX_PROCBASED_CTLS:
3354 case MSR_IA32_VMX_EXIT_CTLS:
3355 case MSR_IA32_VMX_ENTRY_CTLS:
3357 * The "non-true" VMX capability MSRs are generated from the
3358 * "true" MSRs, so we do not support restoring them directly.
3360 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3361 * should restore the "true" MSRs with the must-be-1 bits
3362 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3363 * DEFAULT SETTINGS".
3366 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3367 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3368 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3369 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3370 case MSR_IA32_VMX_PROCBASED_CTLS2:
3371 return vmx_restore_control_msr(vmx, msr_index, data);
3372 case MSR_IA32_VMX_MISC:
3373 return vmx_restore_vmx_misc(vmx, data);
3374 case MSR_IA32_VMX_CR0_FIXED0:
3375 case MSR_IA32_VMX_CR4_FIXED0:
3376 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3377 case MSR_IA32_VMX_CR0_FIXED1:
3378 case MSR_IA32_VMX_CR4_FIXED1:
3380 * These MSRs are generated based on the vCPU's CPUID, so we
3381 * do not support restoring them directly.
3384 case MSR_IA32_VMX_EPT_VPID_CAP:
3385 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3386 case MSR_IA32_VMX_VMCS_ENUM:
3387 vmx->nested.nested_vmx_vmcs_enum = data;
3391 * The rest of the VMX capability MSRs do not support restore.
3397 /* Returns 0 on success, non-0 otherwise. */
3398 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3400 struct vcpu_vmx *vmx = to_vmx(vcpu);
3402 switch (msr_index) {
3403 case MSR_IA32_VMX_BASIC:
3404 *pdata = vmx->nested.nested_vmx_basic;
3406 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3407 case MSR_IA32_VMX_PINBASED_CTLS:
3408 *pdata = vmx_control_msr(
3409 vmx->nested.nested_vmx_pinbased_ctls_low,
3410 vmx->nested.nested_vmx_pinbased_ctls_high);
3411 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3412 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3414 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3415 case MSR_IA32_VMX_PROCBASED_CTLS:
3416 *pdata = vmx_control_msr(
3417 vmx->nested.nested_vmx_procbased_ctls_low,
3418 vmx->nested.nested_vmx_procbased_ctls_high);
3419 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3420 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3422 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3423 case MSR_IA32_VMX_EXIT_CTLS:
3424 *pdata = vmx_control_msr(
3425 vmx->nested.nested_vmx_exit_ctls_low,
3426 vmx->nested.nested_vmx_exit_ctls_high);
3427 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3428 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3430 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3431 case MSR_IA32_VMX_ENTRY_CTLS:
3432 *pdata = vmx_control_msr(
3433 vmx->nested.nested_vmx_entry_ctls_low,
3434 vmx->nested.nested_vmx_entry_ctls_high);
3435 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3436 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3438 case MSR_IA32_VMX_MISC:
3439 *pdata = vmx_control_msr(
3440 vmx->nested.nested_vmx_misc_low,
3441 vmx->nested.nested_vmx_misc_high);
3443 case MSR_IA32_VMX_CR0_FIXED0:
3444 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3446 case MSR_IA32_VMX_CR0_FIXED1:
3447 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3449 case MSR_IA32_VMX_CR4_FIXED0:
3450 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3452 case MSR_IA32_VMX_CR4_FIXED1:
3453 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3455 case MSR_IA32_VMX_VMCS_ENUM:
3456 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3458 case MSR_IA32_VMX_PROCBASED_CTLS2:
3459 *pdata = vmx_control_msr(
3460 vmx->nested.nested_vmx_secondary_ctls_low,
3461 vmx->nested.nested_vmx_secondary_ctls_high);
3463 case MSR_IA32_VMX_EPT_VPID_CAP:
3464 *pdata = vmx->nested.nested_vmx_ept_caps |
3465 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3467 case MSR_IA32_VMX_VMFUNC:
3468 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3477 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3480 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3482 return !(val & ~valid_bits);
3485 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3491 * Reads an msr value (of 'msr_index') into 'pdata'.
3492 * Returns 0 on success, non-0 otherwise.
3493 * Assumes vcpu_load() was already called.
3495 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3497 struct shared_msr_entry *msr;
3499 switch (msr_info->index) {
3500 #ifdef CONFIG_X86_64
3502 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3505 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3507 case MSR_KERNEL_GS_BASE:
3508 vmx_load_host_state(to_vmx(vcpu));
3509 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3513 return kvm_get_msr_common(vcpu, msr_info);
3515 msr_info->data = guest_read_tsc(vcpu);
3517 case MSR_IA32_SPEC_CTRL:
3518 if (!msr_info->host_initiated &&
3519 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3522 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3524 case MSR_IA32_SYSENTER_CS:
3525 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3527 case MSR_IA32_SYSENTER_EIP:
3528 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3530 case MSR_IA32_SYSENTER_ESP:
3531 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3533 case MSR_IA32_BNDCFGS:
3534 if (!kvm_mpx_supported() ||
3535 (!msr_info->host_initiated &&
3536 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3538 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3540 case MSR_IA32_MCG_EXT_CTL:
3541 if (!msr_info->host_initiated &&
3542 !(to_vmx(vcpu)->msr_ia32_feature_control &
3543 FEATURE_CONTROL_LMCE))
3545 msr_info->data = vcpu->arch.mcg_ext_ctl;
3547 case MSR_IA32_FEATURE_CONTROL:
3548 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3550 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3551 if (!nested_vmx_allowed(vcpu))
3553 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3555 if (!vmx_xsaves_supported())
3557 msr_info->data = vcpu->arch.ia32_xss;
3560 if (!msr_info->host_initiated &&
3561 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3563 /* Otherwise falls through */
3565 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3567 msr_info->data = msr->data;
3570 return kvm_get_msr_common(vcpu, msr_info);
3576 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3579 * Writes msr value into into the appropriate "register".
3580 * Returns 0 on success, non-0 otherwise.
3581 * Assumes vcpu_load() was already called.
3583 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3585 struct vcpu_vmx *vmx = to_vmx(vcpu);
3586 struct shared_msr_entry *msr;
3588 u32 msr_index = msr_info->index;
3589 u64 data = msr_info->data;
3591 switch (msr_index) {
3593 ret = kvm_set_msr_common(vcpu, msr_info);
3595 #ifdef CONFIG_X86_64
3597 vmx_segment_cache_clear(vmx);
3598 vmcs_writel(GUEST_FS_BASE, data);
3601 vmx_segment_cache_clear(vmx);
3602 vmcs_writel(GUEST_GS_BASE, data);
3604 case MSR_KERNEL_GS_BASE:
3605 vmx_load_host_state(vmx);
3606 vmx->msr_guest_kernel_gs_base = data;
3609 case MSR_IA32_SYSENTER_CS:
3610 vmcs_write32(GUEST_SYSENTER_CS, data);
3612 case MSR_IA32_SYSENTER_EIP:
3613 vmcs_writel(GUEST_SYSENTER_EIP, data);
3615 case MSR_IA32_SYSENTER_ESP:
3616 vmcs_writel(GUEST_SYSENTER_ESP, data);
3618 case MSR_IA32_BNDCFGS:
3619 if (!kvm_mpx_supported() ||
3620 (!msr_info->host_initiated &&
3621 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3623 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3624 (data & MSR_IA32_BNDCFGS_RSVD))
3626 vmcs_write64(GUEST_BNDCFGS, data);
3629 kvm_write_tsc(vcpu, msr_info);
3631 case MSR_IA32_SPEC_CTRL:
3632 if (!msr_info->host_initiated &&
3633 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3636 /* The STIBP bit doesn't fault even if it's not advertised */
3637 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3640 vmx->spec_ctrl = data;
3647 * When it's written (to non-zero) for the first time, pass
3651 * The handling of the MSR bitmap for L2 guests is done in
3652 * nested_vmx_merge_msr_bitmap. We should not touch the
3653 * vmcs02.msr_bitmap here since it gets completely overwritten
3654 * in the merging. We update the vmcs01 here for L1 as well
3655 * since it will end up touching the MSR anyway now.
3657 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3661 case MSR_IA32_PRED_CMD:
3662 if (!msr_info->host_initiated &&
3663 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3666 if (data & ~PRED_CMD_IBPB)
3672 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3676 * When it's written (to non-zero) for the first time, pass
3680 * The handling of the MSR bitmap for L2 guests is done in
3681 * nested_vmx_merge_msr_bitmap. We should not touch the
3682 * vmcs02.msr_bitmap here since it gets completely overwritten
3685 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3688 case MSR_IA32_CR_PAT:
3689 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3690 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3692 vmcs_write64(GUEST_IA32_PAT, data);
3693 vcpu->arch.pat = data;
3696 ret = kvm_set_msr_common(vcpu, msr_info);
3698 case MSR_IA32_TSC_ADJUST:
3699 ret = kvm_set_msr_common(vcpu, msr_info);
3701 case MSR_IA32_MCG_EXT_CTL:
3702 if ((!msr_info->host_initiated &&
3703 !(to_vmx(vcpu)->msr_ia32_feature_control &
3704 FEATURE_CONTROL_LMCE)) ||
3705 (data & ~MCG_EXT_CTL_LMCE_EN))
3707 vcpu->arch.mcg_ext_ctl = data;
3709 case MSR_IA32_FEATURE_CONTROL:
3710 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3711 (to_vmx(vcpu)->msr_ia32_feature_control &
3712 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3714 vmx->msr_ia32_feature_control = data;
3715 if (msr_info->host_initiated && data == 0)
3716 vmx_leave_nested(vcpu);
3718 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3719 if (!msr_info->host_initiated)
3720 return 1; /* they are read-only */
3721 if (!nested_vmx_allowed(vcpu))
3723 return vmx_set_vmx_msr(vcpu, msr_index, data);
3725 if (!vmx_xsaves_supported())
3728 * The only supported bit as of Skylake is bit 8, but
3729 * it is not supported on KVM.
3733 vcpu->arch.ia32_xss = data;
3734 if (vcpu->arch.ia32_xss != host_xss)
3735 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3736 vcpu->arch.ia32_xss, host_xss, false);
3738 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3741 if (!msr_info->host_initiated &&
3742 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3744 /* Check reserved bit, higher 32 bits should be zero */
3745 if ((data >> 32) != 0)
3747 /* Otherwise falls through */
3749 msr = find_msr_entry(vmx, msr_index);
3751 u64 old_msr_data = msr->data;
3753 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3755 ret = kvm_set_shared_msr(msr->index, msr->data,
3759 msr->data = old_msr_data;
3763 ret = kvm_set_msr_common(vcpu, msr_info);
3766 /* FB_CLEAR may have changed, also update the FB_CLEAR_DIS behavior */
3767 if (msr_index == MSR_IA32_ARCH_CAPABILITIES)
3768 vmx_update_fb_clear_dis(vcpu, vmx);
3773 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3775 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3778 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3781 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3783 case VCPU_EXREG_PDPTR:
3785 ept_save_pdptrs(vcpu);
3792 static __init int cpu_has_kvm_support(void)
3794 return cpu_has_vmx();
3797 static __init int vmx_disabled_by_bios(void)
3801 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3802 if (msr & FEATURE_CONTROL_LOCKED) {
3803 /* launched w/ TXT and VMX disabled */
3804 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3807 /* launched w/o TXT and VMX only enabled w/ TXT */
3808 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3809 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3810 && !tboot_enabled()) {
3811 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3812 "activate TXT before enabling KVM\n");
3815 /* launched w/o TXT and VMX disabled */
3816 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3817 && !tboot_enabled())
3824 static void kvm_cpu_vmxon(u64 addr)
3826 cr4_set_bits(X86_CR4_VMXE);
3827 intel_pt_handle_vmx(1);
3829 asm volatile (ASM_VMX_VMXON_RAX
3830 : : "a"(&addr), "m"(addr)
3834 static int hardware_enable(void)
3836 int cpu = raw_smp_processor_id();
3837 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3840 if (cr4_read_shadow() & X86_CR4_VMXE)
3843 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3845 test_bits = FEATURE_CONTROL_LOCKED;
3846 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3847 if (tboot_enabled())
3848 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3850 if ((old & test_bits) != test_bits) {
3851 /* enable and lock */
3852 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3854 kvm_cpu_vmxon(phys_addr);
3860 static void vmclear_local_loaded_vmcss(void)
3862 int cpu = raw_smp_processor_id();
3863 struct loaded_vmcs *v, *n;
3865 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3866 loaded_vmcss_on_cpu_link)
3867 __loaded_vmcs_clear(v);
3871 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3874 static void kvm_cpu_vmxoff(void)
3876 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3878 intel_pt_handle_vmx(0);
3879 cr4_clear_bits(X86_CR4_VMXE);
3882 static void hardware_disable(void)
3884 vmclear_local_loaded_vmcss();
3888 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3889 u32 msr, u32 *result)
3891 u32 vmx_msr_low, vmx_msr_high;
3892 u32 ctl = ctl_min | ctl_opt;
3894 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3896 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3897 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3899 /* Ensure minimum (required) set of control bits are supported. */
3907 static __init bool allow_1_setting(u32 msr, u32 ctl)
3909 u32 vmx_msr_low, vmx_msr_high;
3911 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3912 return vmx_msr_high & ctl;
3915 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3917 u32 vmx_msr_low, vmx_msr_high;
3918 u32 min, opt, min2, opt2;
3919 u32 _pin_based_exec_control = 0;
3920 u32 _cpu_based_exec_control = 0;
3921 u32 _cpu_based_2nd_exec_control = 0;
3922 u32 _vmexit_control = 0;
3923 u32 _vmentry_control = 0;
3925 min = CPU_BASED_HLT_EXITING |
3926 #ifdef CONFIG_X86_64
3927 CPU_BASED_CR8_LOAD_EXITING |
3928 CPU_BASED_CR8_STORE_EXITING |
3930 CPU_BASED_CR3_LOAD_EXITING |
3931 CPU_BASED_CR3_STORE_EXITING |
3932 CPU_BASED_USE_IO_BITMAPS |
3933 CPU_BASED_MOV_DR_EXITING |
3934 CPU_BASED_USE_TSC_OFFSETING |
3935 CPU_BASED_INVLPG_EXITING |
3936 CPU_BASED_RDPMC_EXITING;
3938 if (!kvm_mwait_in_guest())
3939 min |= CPU_BASED_MWAIT_EXITING |
3940 CPU_BASED_MONITOR_EXITING;
3942 opt = CPU_BASED_TPR_SHADOW |
3943 CPU_BASED_USE_MSR_BITMAPS |
3944 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3945 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3946 &_cpu_based_exec_control) < 0)
3948 #ifdef CONFIG_X86_64
3949 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3950 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3951 ~CPU_BASED_CR8_STORE_EXITING;
3953 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3955 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3956 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3957 SECONDARY_EXEC_WBINVD_EXITING |
3958 SECONDARY_EXEC_ENABLE_VPID |
3959 SECONDARY_EXEC_ENABLE_EPT |
3960 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3961 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3962 SECONDARY_EXEC_RDTSCP |
3963 SECONDARY_EXEC_ENABLE_INVPCID |
3964 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3965 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3966 SECONDARY_EXEC_SHADOW_VMCS |
3967 SECONDARY_EXEC_XSAVES |
3968 SECONDARY_EXEC_RDSEED |
3969 SECONDARY_EXEC_RDRAND |
3970 SECONDARY_EXEC_ENABLE_PML |
3971 SECONDARY_EXEC_TSC_SCALING |
3972 SECONDARY_EXEC_ENABLE_VMFUNC;
3973 if (adjust_vmx_controls(min2, opt2,
3974 MSR_IA32_VMX_PROCBASED_CTLS2,
3975 &_cpu_based_2nd_exec_control) < 0)
3978 #ifndef CONFIG_X86_64
3979 if (!(_cpu_based_2nd_exec_control &
3980 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3981 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3984 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3985 _cpu_based_2nd_exec_control &= ~(
3986 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3987 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3988 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3990 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3991 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3993 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3994 CPU_BASED_CR3_STORE_EXITING |
3995 CPU_BASED_INVLPG_EXITING);
3996 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3997 vmx_capability.ept, vmx_capability.vpid);
4000 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4001 #ifdef CONFIG_X86_64
4002 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4004 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4005 VM_EXIT_CLEAR_BNDCFGS;
4006 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4007 &_vmexit_control) < 0)
4010 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4011 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4012 PIN_BASED_VMX_PREEMPTION_TIMER;
4013 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4014 &_pin_based_exec_control) < 0)
4017 if (cpu_has_broken_vmx_preemption_timer())
4018 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4019 if (!(_cpu_based_2nd_exec_control &
4020 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4021 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4023 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4024 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4025 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4026 &_vmentry_control) < 0)
4029 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4031 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4032 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4035 #ifdef CONFIG_X86_64
4036 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4037 if (vmx_msr_high & (1u<<16))
4041 /* Require Write-Back (WB) memory type for VMCS accesses. */
4042 if (((vmx_msr_high >> 18) & 15) != 6)
4045 vmcs_conf->size = vmx_msr_high & 0x1fff;
4046 vmcs_conf->order = get_order(vmcs_conf->size);
4047 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4048 vmcs_conf->revision_id = vmx_msr_low;
4050 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4051 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4052 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4053 vmcs_conf->vmexit_ctrl = _vmexit_control;
4054 vmcs_conf->vmentry_ctrl = _vmentry_control;
4056 cpu_has_load_ia32_efer =
4057 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4058 VM_ENTRY_LOAD_IA32_EFER)
4059 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4060 VM_EXIT_LOAD_IA32_EFER);
4062 cpu_has_load_perf_global_ctrl =
4063 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4064 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4065 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4066 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4069 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4070 * but due to errata below it can't be used. Workaround is to use
4071 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4073 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4078 * BC86,AAY89,BD102 (model 44)
4082 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4083 switch (boot_cpu_data.x86_model) {
4089 cpu_has_load_perf_global_ctrl = false;
4090 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4091 "does not work properly. Using workaround\n");
4098 if (boot_cpu_has(X86_FEATURE_XSAVES))
4099 rdmsrl(MSR_IA32_XSS, host_xss);
4104 static struct vmcs *alloc_vmcs_cpu(int cpu)
4106 int node = cpu_to_node(cpu);
4110 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4113 vmcs = page_address(pages);
4114 memset(vmcs, 0, vmcs_config.size);
4115 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4119 static void free_vmcs(struct vmcs *vmcs)
4121 free_pages((unsigned long)vmcs, vmcs_config.order);
4125 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4127 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4129 if (!loaded_vmcs->vmcs)
4131 loaded_vmcs_clear(loaded_vmcs);
4132 free_vmcs(loaded_vmcs->vmcs);
4133 loaded_vmcs->vmcs = NULL;
4134 if (loaded_vmcs->msr_bitmap)
4135 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4136 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4139 static struct vmcs *alloc_vmcs(void)
4141 return alloc_vmcs_cpu(raw_smp_processor_id());
4144 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4146 loaded_vmcs->vmcs = alloc_vmcs();
4147 if (!loaded_vmcs->vmcs)
4150 loaded_vmcs->shadow_vmcs = NULL;
4151 loaded_vmcs_init(loaded_vmcs);
4153 if (cpu_has_vmx_msr_bitmap()) {
4154 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4155 if (!loaded_vmcs->msr_bitmap)
4157 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4162 free_loaded_vmcs(loaded_vmcs);
4166 static void free_kvm_area(void)
4170 for_each_possible_cpu(cpu) {
4171 free_vmcs(per_cpu(vmxarea, cpu));
4172 per_cpu(vmxarea, cpu) = NULL;
4176 enum vmcs_field_type {
4177 VMCS_FIELD_TYPE_U16 = 0,
4178 VMCS_FIELD_TYPE_U64 = 1,
4179 VMCS_FIELD_TYPE_U32 = 2,
4180 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
4183 static inline int vmcs_field_type(unsigned long field)
4185 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4186 return VMCS_FIELD_TYPE_U32;
4187 return (field >> 13) & 0x3 ;
4190 static inline int vmcs_field_readonly(unsigned long field)
4192 return (((field >> 10) & 0x3) == 1);
4195 static void init_vmcs_shadow_fields(void)
4199 /* No checks for read only fields yet */
4201 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4202 switch (shadow_read_write_fields[i]) {
4204 if (!kvm_mpx_supported())
4212 shadow_read_write_fields[j] =
4213 shadow_read_write_fields[i];
4216 max_shadow_read_write_fields = j;
4218 /* shadowed fields guest access without vmexit */
4219 for (i = 0; i < max_shadow_read_write_fields; i++) {
4220 unsigned long field = shadow_read_write_fields[i];
4222 clear_bit(field, vmx_vmwrite_bitmap);
4223 clear_bit(field, vmx_vmread_bitmap);
4224 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
4225 clear_bit(field + 1, vmx_vmwrite_bitmap);
4226 clear_bit(field + 1, vmx_vmread_bitmap);
4229 for (i = 0; i < max_shadow_read_only_fields; i++) {
4230 unsigned long field = shadow_read_only_fields[i];
4232 clear_bit(field, vmx_vmread_bitmap);
4233 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
4234 clear_bit(field + 1, vmx_vmread_bitmap);
4238 static __init int alloc_kvm_area(void)
4242 for_each_possible_cpu(cpu) {
4245 vmcs = alloc_vmcs_cpu(cpu);
4251 per_cpu(vmxarea, cpu) = vmcs;
4256 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4257 struct kvm_segment *save)
4259 if (!emulate_invalid_guest_state) {
4261 * CS and SS RPL should be equal during guest entry according
4262 * to VMX spec, but in reality it is not always so. Since vcpu
4263 * is in the middle of the transition from real mode to
4264 * protected mode it is safe to assume that RPL 0 is a good
4267 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4268 save->selector &= ~SEGMENT_RPL_MASK;
4269 save->dpl = save->selector & SEGMENT_RPL_MASK;
4272 vmx_set_segment(vcpu, save, seg);
4275 static void enter_pmode(struct kvm_vcpu *vcpu)
4277 unsigned long flags;
4278 struct vcpu_vmx *vmx = to_vmx(vcpu);
4281 * Update real mode segment cache. It may be not up-to-date if sement
4282 * register was written while vcpu was in a guest mode.
4284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4287 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4289 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4291 vmx->rmode.vm86_active = 0;
4293 vmx_segment_cache_clear(vmx);
4295 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4297 flags = vmcs_readl(GUEST_RFLAGS);
4298 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4299 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4300 vmcs_writel(GUEST_RFLAGS, flags);
4302 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4303 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4305 update_exception_bitmap(vcpu);
4307 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4308 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4309 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4310 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4311 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4312 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4315 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4317 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4318 struct kvm_segment var = *save;
4321 if (seg == VCPU_SREG_CS)
4324 if (!emulate_invalid_guest_state) {
4325 var.selector = var.base >> 4;
4326 var.base = var.base & 0xffff0;
4336 if (save->base & 0xf)
4337 printk_once(KERN_WARNING "kvm: segment base is not "
4338 "paragraph aligned when entering "
4339 "protected mode (seg=%d)", seg);
4342 vmcs_write16(sf->selector, var.selector);
4343 vmcs_writel(sf->base, var.base);
4344 vmcs_write32(sf->limit, var.limit);
4345 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4348 static void enter_rmode(struct kvm_vcpu *vcpu)
4350 unsigned long flags;
4351 struct vcpu_vmx *vmx = to_vmx(vcpu);
4353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4359 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4361 vmx->rmode.vm86_active = 1;
4364 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4365 * vcpu. Warn the user that an update is overdue.
4367 if (!vcpu->kvm->arch.tss_addr)
4368 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4369 "called before entering vcpu\n");
4371 vmx_segment_cache_clear(vmx);
4373 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4374 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4375 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4377 flags = vmcs_readl(GUEST_RFLAGS);
4378 vmx->rmode.save_rflags = flags;
4380 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4382 vmcs_writel(GUEST_RFLAGS, flags);
4383 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4384 update_exception_bitmap(vcpu);
4386 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4387 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4388 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4389 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4390 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4391 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4393 kvm_mmu_reset_context(vcpu);
4396 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4398 struct vcpu_vmx *vmx = to_vmx(vcpu);
4399 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4405 * Force kernel_gs_base reloading before EFER changes, as control
4406 * of this msr depends on is_long_mode().
4408 vmx_load_host_state(to_vmx(vcpu));
4409 vcpu->arch.efer = efer;
4410 if (efer & EFER_LMA) {
4411 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4414 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4416 msr->data = efer & ~EFER_LME;
4421 #ifdef CONFIG_X86_64
4423 static void enter_lmode(struct kvm_vcpu *vcpu)
4427 vmx_segment_cache_clear(to_vmx(vcpu));
4429 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4430 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4431 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4433 vmcs_write32(GUEST_TR_AR_BYTES,
4434 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4435 | VMX_AR_TYPE_BUSY_64_TSS);
4437 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4440 static void exit_lmode(struct kvm_vcpu *vcpu)
4442 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4443 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4448 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4449 bool invalidate_gpa)
4451 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4452 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4454 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4456 vpid_sync_context(vpid);
4460 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4462 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4465 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4467 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4469 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4470 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4473 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4475 if (enable_ept && is_paging(vcpu))
4476 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4477 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4480 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4482 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4484 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4485 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4488 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4490 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4492 if (!test_bit(VCPU_EXREG_PDPTR,
4493 (unsigned long *)&vcpu->arch.regs_dirty))
4496 if (is_pae_paging(vcpu)) {
4497 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4498 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4499 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4500 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4504 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4506 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4508 if (is_pae_paging(vcpu)) {
4509 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4510 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4511 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4512 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4515 __set_bit(VCPU_EXREG_PDPTR,
4516 (unsigned long *)&vcpu->arch.regs_avail);
4517 __set_bit(VCPU_EXREG_PDPTR,
4518 (unsigned long *)&vcpu->arch.regs_dirty);
4521 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4523 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4524 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4525 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4527 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4528 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4529 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4530 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4532 return fixed_bits_valid(val, fixed0, fixed1);
4535 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4537 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4538 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4540 return fixed_bits_valid(val, fixed0, fixed1);
4543 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4545 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4546 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4548 return fixed_bits_valid(val, fixed0, fixed1);
4551 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4552 #define nested_guest_cr4_valid nested_cr4_valid
4553 #define nested_host_cr4_valid nested_cr4_valid
4555 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4557 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4559 struct kvm_vcpu *vcpu)
4561 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4562 vmx_decache_cr3(vcpu);
4563 if (!(cr0 & X86_CR0_PG)) {
4564 /* From paging/starting to nonpaging */
4565 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4566 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4567 (CPU_BASED_CR3_LOAD_EXITING |
4568 CPU_BASED_CR3_STORE_EXITING));
4569 vcpu->arch.cr0 = cr0;
4570 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4571 } else if (!is_paging(vcpu)) {
4572 /* From nonpaging to paging */
4573 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4574 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4575 ~(CPU_BASED_CR3_LOAD_EXITING |
4576 CPU_BASED_CR3_STORE_EXITING));
4577 vcpu->arch.cr0 = cr0;
4578 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4581 if (!(cr0 & X86_CR0_WP))
4582 *hw_cr0 &= ~X86_CR0_WP;
4585 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4587 struct vcpu_vmx *vmx = to_vmx(vcpu);
4588 unsigned long hw_cr0;
4590 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4591 if (enable_unrestricted_guest)
4592 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4594 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4596 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4599 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4603 #ifdef CONFIG_X86_64
4604 if (vcpu->arch.efer & EFER_LME) {
4605 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4607 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4613 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4615 vmcs_writel(CR0_READ_SHADOW, cr0);
4616 vmcs_writel(GUEST_CR0, hw_cr0);
4617 vcpu->arch.cr0 = cr0;
4619 /* depends on vcpu->arch.cr0 to be set to a new value */
4620 vmx->emulation_required = emulation_required(vcpu);
4623 static int get_ept_level(struct kvm_vcpu *vcpu)
4625 /* Nested EPT currently only supports 4-level walks. */
4626 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
4628 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4633 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4635 u64 eptp = VMX_EPTP_MT_WB;
4637 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4639 if (enable_ept_ad_bits &&
4640 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4641 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4642 eptp |= (root_hpa & PAGE_MASK);
4647 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4649 unsigned long guest_cr3;
4654 eptp = construct_eptp(vcpu, cr3);
4655 vmcs_write64(EPT_POINTER, eptp);
4656 if (is_paging(vcpu) || is_guest_mode(vcpu))
4657 guest_cr3 = kvm_read_cr3(vcpu);
4659 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4660 ept_load_pdptrs(vcpu);
4663 vmx_flush_tlb(vcpu, true);
4664 vmcs_writel(GUEST_CR3, guest_cr3);
4667 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4670 * Pass through host's Machine Check Enable value to hw_cr4, which
4671 * is in force while we are in guest mode. Do not let guests control
4672 * this bit, even if host CR4.MCE == 0.
4674 unsigned long hw_cr4 =
4675 (cr4_read_shadow() & X86_CR4_MCE) |
4676 (cr4 & ~X86_CR4_MCE) |
4677 (to_vmx(vcpu)->rmode.vm86_active ?
4678 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4680 if (cr4 & X86_CR4_VMXE) {
4682 * To use VMXON (and later other VMX instructions), a guest
4683 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4684 * So basically the check on whether to allow nested VMX
4687 if (!nested_vmx_allowed(vcpu))
4691 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4694 vcpu->arch.cr4 = cr4;
4696 if (!is_paging(vcpu)) {
4697 hw_cr4 &= ~X86_CR4_PAE;
4698 hw_cr4 |= X86_CR4_PSE;
4699 } else if (!(cr4 & X86_CR4_PAE)) {
4700 hw_cr4 &= ~X86_CR4_PAE;
4704 if (!enable_unrestricted_guest && !is_paging(vcpu))
4706 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4707 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4708 * to be manually disabled when guest switches to non-paging
4711 * If !enable_unrestricted_guest, the CPU is always running
4712 * with CR0.PG=1 and CR4 needs to be modified.
4713 * If enable_unrestricted_guest, the CPU automatically
4714 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4716 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4718 vmcs_writel(CR4_READ_SHADOW, cr4);
4719 vmcs_writel(GUEST_CR4, hw_cr4);
4723 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4724 struct kvm_segment *var, int seg)
4726 struct vcpu_vmx *vmx = to_vmx(vcpu);
4729 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4730 *var = vmx->rmode.segs[seg];
4731 if (seg == VCPU_SREG_TR
4732 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4734 var->base = vmx_read_guest_seg_base(vmx, seg);
4735 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4738 var->base = vmx_read_guest_seg_base(vmx, seg);
4739 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4740 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4741 ar = vmx_read_guest_seg_ar(vmx, seg);
4742 var->unusable = (ar >> 16) & 1;
4743 var->type = ar & 15;
4744 var->s = (ar >> 4) & 1;
4745 var->dpl = (ar >> 5) & 3;
4747 * Some userspaces do not preserve unusable property. Since usable
4748 * segment has to be present according to VMX spec we can use present
4749 * property to amend userspace bug by making unusable segment always
4750 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4751 * segment as unusable.
4753 var->present = !var->unusable;
4754 var->avl = (ar >> 12) & 1;
4755 var->l = (ar >> 13) & 1;
4756 var->db = (ar >> 14) & 1;
4757 var->g = (ar >> 15) & 1;
4760 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4762 struct kvm_segment s;
4764 if (to_vmx(vcpu)->rmode.vm86_active) {
4765 vmx_get_segment(vcpu, &s, seg);
4768 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4771 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4773 struct vcpu_vmx *vmx = to_vmx(vcpu);
4775 if (unlikely(vmx->rmode.vm86_active))
4778 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4779 return VMX_AR_DPL(ar);
4783 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4787 if (var->unusable || !var->present)
4790 ar = var->type & 15;
4791 ar |= (var->s & 1) << 4;
4792 ar |= (var->dpl & 3) << 5;
4793 ar |= (var->present & 1) << 7;
4794 ar |= (var->avl & 1) << 12;
4795 ar |= (var->l & 1) << 13;
4796 ar |= (var->db & 1) << 14;
4797 ar |= (var->g & 1) << 15;
4803 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4804 struct kvm_segment *var, int seg)
4806 struct vcpu_vmx *vmx = to_vmx(vcpu);
4807 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4809 vmx_segment_cache_clear(vmx);
4811 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4812 vmx->rmode.segs[seg] = *var;
4813 if (seg == VCPU_SREG_TR)
4814 vmcs_write16(sf->selector, var->selector);
4816 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4820 vmcs_writel(sf->base, var->base);
4821 vmcs_write32(sf->limit, var->limit);
4822 vmcs_write16(sf->selector, var->selector);
4825 * Fix the "Accessed" bit in AR field of segment registers for older
4827 * IA32 arch specifies that at the time of processor reset the
4828 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4829 * is setting it to 0 in the userland code. This causes invalid guest
4830 * state vmexit when "unrestricted guest" mode is turned on.
4831 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4832 * tree. Newer qemu binaries with that qemu fix would not need this
4835 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4836 var->type |= 0x1; /* Accessed */
4838 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4841 vmx->emulation_required = emulation_required(vcpu);
4844 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4846 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4848 *db = (ar >> 14) & 1;
4849 *l = (ar >> 13) & 1;
4852 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4854 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4855 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4858 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4860 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4861 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4864 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4866 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4867 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4870 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4872 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4873 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4876 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4878 struct kvm_segment var;
4881 vmx_get_segment(vcpu, &var, seg);
4883 if (seg == VCPU_SREG_CS)
4885 ar = vmx_segment_access_rights(&var);
4887 if (var.base != (var.selector << 4))
4889 if (var.limit != 0xffff)
4897 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4899 struct kvm_segment cs;
4900 unsigned int cs_rpl;
4902 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4903 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4907 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4911 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4912 if (cs.dpl > cs_rpl)
4915 if (cs.dpl != cs_rpl)
4921 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4925 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4927 struct kvm_segment ss;
4928 unsigned int ss_rpl;
4930 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4931 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4935 if (ss.type != 3 && ss.type != 7)
4939 if (ss.dpl != ss_rpl) /* DPL != RPL */
4947 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4949 struct kvm_segment var;
4952 vmx_get_segment(vcpu, &var, seg);
4953 rpl = var.selector & SEGMENT_RPL_MASK;
4961 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4962 if (var.dpl < rpl) /* DPL < RPL */
4966 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4972 static bool tr_valid(struct kvm_vcpu *vcpu)
4974 struct kvm_segment tr;
4976 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4980 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4982 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4990 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4992 struct kvm_segment ldtr;
4994 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4998 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5008 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5010 struct kvm_segment cs, ss;
5012 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5013 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5015 return ((cs.selector & SEGMENT_RPL_MASK) ==
5016 (ss.selector & SEGMENT_RPL_MASK));
5019 static bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu,
5020 unsigned int port, int size);
5021 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5022 struct vmcs12 *vmcs12)
5024 unsigned long exit_qualification;
5025 unsigned short port;
5028 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5029 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5031 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5033 port = exit_qualification >> 16;
5034 size = (exit_qualification & 7) + 1;
5036 return nested_vmx_check_io_bitmaps(vcpu, port, size);
5040 * Check if guest state is valid. Returns true if valid, false if
5042 * We assume that registers are always usable
5044 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5046 if (enable_unrestricted_guest)
5049 /* real mode guest state checks */
5050 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5051 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5053 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5055 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5057 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5059 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5061 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5064 /* protected mode guest state checks */
5065 if (!cs_ss_rpl_check(vcpu))
5067 if (!code_segment_valid(vcpu))
5069 if (!stack_segment_valid(vcpu))
5071 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5073 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5075 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5077 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5079 if (!tr_valid(vcpu))
5081 if (!ldtr_valid(vcpu))
5085 * - Add checks on RIP
5086 * - Add checks on RFLAGS
5092 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5094 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5097 static int init_rmode_tss(struct kvm *kvm)
5103 idx = srcu_read_lock(&kvm->srcu);
5104 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
5105 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5108 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5109 r = kvm_write_guest_page(kvm, fn++, &data,
5110 TSS_IOPB_BASE_OFFSET, sizeof(u16));
5113 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5116 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5120 r = kvm_write_guest_page(kvm, fn, &data,
5121 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5124 srcu_read_unlock(&kvm->srcu, idx);
5128 static int init_rmode_identity_map(struct kvm *kvm)
5131 kvm_pfn_t identity_map_pfn;
5137 /* Protect kvm->arch.ept_identity_pagetable_done. */
5138 mutex_lock(&kvm->slots_lock);
5140 if (likely(kvm->arch.ept_identity_pagetable_done))
5143 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
5145 r = alloc_identity_pagetable(kvm);
5149 idx = srcu_read_lock(&kvm->srcu);
5150 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5153 /* Set up identity-mapping pagetable for EPT in real mode */
5154 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5155 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5156 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5157 r = kvm_write_guest_page(kvm, identity_map_pfn,
5158 &tmp, i * sizeof(tmp), sizeof(tmp));
5162 kvm->arch.ept_identity_pagetable_done = true;
5165 srcu_read_unlock(&kvm->srcu, idx);
5168 mutex_unlock(&kvm->slots_lock);
5172 static void seg_setup(int seg)
5174 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5177 vmcs_write16(sf->selector, 0);
5178 vmcs_writel(sf->base, 0);
5179 vmcs_write32(sf->limit, 0xffff);
5181 if (seg == VCPU_SREG_CS)
5182 ar |= 0x08; /* code segment */
5184 vmcs_write32(sf->ar_bytes, ar);
5187 static int alloc_apic_access_page(struct kvm *kvm)
5192 mutex_lock(&kvm->slots_lock);
5193 if (kvm->arch.apic_access_page_done)
5195 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5196 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5200 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5201 if (is_error_page(page)) {
5207 * Do not pin the page in memory, so that memory hot-unplug
5208 * is able to migrate it.
5211 kvm->arch.apic_access_page_done = true;
5213 mutex_unlock(&kvm->slots_lock);
5217 static int alloc_identity_pagetable(struct kvm *kvm)
5219 /* Called with kvm->slots_lock held. */
5223 BUG_ON(kvm->arch.ept_identity_pagetable_done);
5225 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5226 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
5231 static int allocate_vpid(void)
5237 spin_lock(&vmx_vpid_lock);
5238 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5239 if (vpid < VMX_NR_VPIDS)
5240 __set_bit(vpid, vmx_vpid_bitmap);
5243 spin_unlock(&vmx_vpid_lock);
5247 static void free_vpid(int vpid)
5249 if (!enable_vpid || vpid == 0)
5251 spin_lock(&vmx_vpid_lock);
5252 __clear_bit(vpid, vmx_vpid_bitmap);
5253 spin_unlock(&vmx_vpid_lock);
5256 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5259 int f = sizeof(unsigned long);
5261 if (!cpu_has_vmx_msr_bitmap())
5265 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5266 * have the write-low and read-high bitmap offsets the wrong way round.
5267 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5269 if (msr <= 0x1fff) {
5270 if (type & MSR_TYPE_R)
5272 __clear_bit(msr, msr_bitmap + 0x000 / f);
5274 if (type & MSR_TYPE_W)
5276 __clear_bit(msr, msr_bitmap + 0x800 / f);
5278 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5280 if (type & MSR_TYPE_R)
5282 __clear_bit(msr, msr_bitmap + 0x400 / f);
5284 if (type & MSR_TYPE_W)
5286 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5291 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5294 int f = sizeof(unsigned long);
5296 if (!cpu_has_vmx_msr_bitmap())
5300 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5301 * have the write-low and read-high bitmap offsets the wrong way round.
5302 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5304 if (msr <= 0x1fff) {
5305 if (type & MSR_TYPE_R)
5307 __set_bit(msr, msr_bitmap + 0x000 / f);
5309 if (type & MSR_TYPE_W)
5311 __set_bit(msr, msr_bitmap + 0x800 / f);
5313 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5315 if (type & MSR_TYPE_R)
5317 __set_bit(msr, msr_bitmap + 0x400 / f);
5319 if (type & MSR_TYPE_W)
5321 __set_bit(msr, msr_bitmap + 0xc00 / f);
5326 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5327 u32 msr, int type, bool value)
5330 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5332 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5336 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5337 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5339 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5340 unsigned long *msr_bitmap_nested,
5343 int f = sizeof(unsigned long);
5345 if (!cpu_has_vmx_msr_bitmap()) {
5351 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5352 * have the write-low and read-high bitmap offsets the wrong way round.
5353 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5355 if (msr <= 0x1fff) {
5356 if (type & MSR_TYPE_R &&
5357 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5359 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5361 if (type & MSR_TYPE_W &&
5362 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5364 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5366 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5368 if (type & MSR_TYPE_R &&
5369 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5371 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5373 if (type & MSR_TYPE_W &&
5374 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5376 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5381 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5385 if (cpu_has_secondary_exec_ctrls() &&
5386 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5387 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5388 mode |= MSR_BITMAP_MODE_X2APIC;
5389 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5390 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5393 if (is_long_mode(vcpu))
5394 mode |= MSR_BITMAP_MODE_LM;
5399 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5401 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5406 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5407 unsigned word = msr / BITS_PER_LONG;
5408 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5409 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5412 if (mode & MSR_BITMAP_MODE_X2APIC) {
5414 * TPR reads and writes can be virtualized even if virtual interrupt
5415 * delivery is not in use.
5417 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5418 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5419 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5420 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5421 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5426 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5428 struct vcpu_vmx *vmx = to_vmx(vcpu);
5429 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5430 u8 mode = vmx_msr_bitmap_mode(vcpu);
5431 u8 changed = mode ^ vmx->msr_bitmap_mode;
5436 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5437 !(mode & MSR_BITMAP_MODE_LM));
5439 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5440 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5442 vmx->msr_bitmap_mode = mode;
5445 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5447 return enable_apicv;
5450 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5452 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5456 * Don't need to mark the APIC access page dirty; it is never
5457 * written to by the CPU during APIC virtualization.
5460 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5461 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5462 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5465 if (nested_cpu_has_posted_intr(vmcs12)) {
5466 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5467 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5472 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5474 struct vcpu_vmx *vmx = to_vmx(vcpu);
5479 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5482 vmx->nested.pi_pending = false;
5483 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5486 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5487 if (max_irr != 256) {
5488 vapic_page = kmap(vmx->nested.virtual_apic_page);
5489 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5490 kunmap(vmx->nested.virtual_apic_page);
5492 status = vmcs_read16(GUEST_INTR_STATUS);
5493 if ((u8)max_irr > ((u8)status & 0xff)) {
5495 status |= (u8)max_irr;
5496 vmcs_write16(GUEST_INTR_STATUS, status);
5500 nested_mark_vmcs12_pages_dirty(vcpu);
5503 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5507 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5509 if (vcpu->mode == IN_GUEST_MODE) {
5511 * The vector of interrupt to be delivered to vcpu had
5512 * been set in PIR before this function.
5514 * Following cases will be reached in this block, and
5515 * we always send a notification event in all cases as
5518 * Case 1: vcpu keeps in non-root mode. Sending a
5519 * notification event posts the interrupt to vcpu.
5521 * Case 2: vcpu exits to root mode and is still
5522 * runnable. PIR will be synced to vIRR before the
5523 * next vcpu entry. Sending a notification event in
5524 * this case has no effect, as vcpu is not in root
5527 * Case 3: vcpu exits to root mode and is blocked.
5528 * vcpu_block() has already synced PIR to vIRR and
5529 * never blocks vcpu if vIRR is not cleared. Therefore,
5530 * a blocked vcpu here does not wait for any requested
5531 * interrupts in PIR, and sending a notification event
5532 * which has no effect is safe here.
5535 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5542 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5545 struct vcpu_vmx *vmx = to_vmx(vcpu);
5547 if (is_guest_mode(vcpu) &&
5548 vector == vmx->nested.posted_intr_nv) {
5550 * If a posted intr is not recognized by hardware,
5551 * we will accomplish it in the next vmentry.
5553 vmx->nested.pi_pending = true;
5554 kvm_make_request(KVM_REQ_EVENT, vcpu);
5555 /* the PIR and ON have been set by L1. */
5556 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5557 kvm_vcpu_kick(vcpu);
5563 * Send interrupt to vcpu via posted interrupt way.
5564 * 1. If target vcpu is running(non-root mode), send posted interrupt
5565 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5566 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5567 * interrupt from PIR in next vmentry.
5569 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5571 struct vcpu_vmx *vmx = to_vmx(vcpu);
5574 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5578 if (!vcpu->arch.apicv_active)
5581 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5584 /* If a previous notification has sent the IPI, nothing to do. */
5585 if (pi_test_and_set_on(&vmx->pi_desc))
5588 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5589 kvm_vcpu_kick(vcpu);
5595 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5596 * will not change in the lifetime of the guest.
5597 * Note that host-state that does change is set elsewhere. E.g., host-state
5598 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5600 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5605 unsigned long cr0, cr3, cr4;
5608 WARN_ON(cr0 & X86_CR0_TS);
5609 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5612 * Save the most likely value for this task's CR3 in the VMCS.
5613 * We can't use __get_current_cr3_fast() because we're not atomic.
5616 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5617 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5619 /* Save the most likely value for this task's CR4 in the VMCS. */
5620 cr4 = cr4_read_shadow();
5621 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5622 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5624 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5625 #ifdef CONFIG_X86_64
5627 * Load null selectors, so we can avoid reloading them in
5628 * __vmx_load_host_state(), in case userspace uses the null selectors
5629 * too (the expected case).
5631 vmcs_write16(HOST_DS_SELECTOR, 0);
5632 vmcs_write16(HOST_ES_SELECTOR, 0);
5634 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5635 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5637 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5638 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5641 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5642 vmx->host_idt_base = dt.address;
5644 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5646 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5647 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5648 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5649 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5651 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5652 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5653 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5657 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5659 BUILD_BUG_ON(KVM_CR4_GUEST_OWNED_BITS & ~KVM_POSSIBLE_CR4_GUEST_BITS);
5661 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5663 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5664 if (is_guest_mode(&vmx->vcpu))
5665 vmx->vcpu.arch.cr4_guest_owned_bits &=
5666 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5667 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5670 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5672 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5674 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5675 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5676 /* Enable the preemption timer dynamically */
5677 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5678 return pin_based_exec_ctrl;
5681 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5683 struct vcpu_vmx *vmx = to_vmx(vcpu);
5685 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5686 if (cpu_has_secondary_exec_ctrls()) {
5687 if (kvm_vcpu_apicv_active(vcpu))
5688 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5689 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5690 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5692 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5693 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5694 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5697 if (cpu_has_vmx_msr_bitmap())
5698 vmx_update_msr_bitmap(vcpu);
5701 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5703 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5705 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5706 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5708 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5709 exec_control &= ~CPU_BASED_TPR_SHADOW;
5710 #ifdef CONFIG_X86_64
5711 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5712 CPU_BASED_CR8_LOAD_EXITING;
5716 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5717 CPU_BASED_CR3_LOAD_EXITING |
5718 CPU_BASED_INVLPG_EXITING;
5719 return exec_control;
5722 static bool vmx_rdrand_supported(void)
5724 return vmcs_config.cpu_based_2nd_exec_ctrl &
5725 SECONDARY_EXEC_RDRAND;
5728 static bool vmx_rdseed_supported(void)
5730 return vmcs_config.cpu_based_2nd_exec_ctrl &
5731 SECONDARY_EXEC_RDSEED;
5734 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5736 struct kvm_vcpu *vcpu = &vmx->vcpu;
5738 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5739 if (!cpu_need_virtualize_apic_accesses(vcpu))
5740 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5742 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5744 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5745 enable_unrestricted_guest = 0;
5746 /* Enable INVPCID for non-ept guests may cause performance regression. */
5747 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5749 if (!enable_unrestricted_guest)
5750 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5752 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5753 if (!kvm_vcpu_apicv_active(vcpu))
5754 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5755 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5756 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5757 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5759 We can NOT enable shadow_vmcs here because we don't have yet
5762 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5765 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5767 if (vmx_xsaves_supported()) {
5768 /* Exposing XSAVES only when XSAVE is exposed */
5769 bool xsaves_enabled =
5770 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5771 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5773 if (!xsaves_enabled)
5774 exec_control &= ~SECONDARY_EXEC_XSAVES;
5778 vmx->nested.nested_vmx_secondary_ctls_high |=
5779 SECONDARY_EXEC_XSAVES;
5781 vmx->nested.nested_vmx_secondary_ctls_high &=
5782 ~SECONDARY_EXEC_XSAVES;
5786 if (vmx_rdtscp_supported()) {
5787 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5788 if (!rdtscp_enabled)
5789 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5793 vmx->nested.nested_vmx_secondary_ctls_high |=
5794 SECONDARY_EXEC_RDTSCP;
5796 vmx->nested.nested_vmx_secondary_ctls_high &=
5797 ~SECONDARY_EXEC_RDTSCP;
5801 if (vmx_invpcid_supported()) {
5802 /* Exposing INVPCID only when PCID is exposed */
5803 bool invpcid_enabled =
5804 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5805 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5807 if (!invpcid_enabled) {
5808 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5809 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5813 if (invpcid_enabled)
5814 vmx->nested.nested_vmx_secondary_ctls_high |=
5815 SECONDARY_EXEC_ENABLE_INVPCID;
5817 vmx->nested.nested_vmx_secondary_ctls_high &=
5818 ~SECONDARY_EXEC_ENABLE_INVPCID;
5822 if (vmx_rdrand_supported()) {
5823 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5825 exec_control &= ~SECONDARY_EXEC_RDRAND;
5829 vmx->nested.nested_vmx_secondary_ctls_high |=
5830 SECONDARY_EXEC_RDRAND;
5832 vmx->nested.nested_vmx_secondary_ctls_high &=
5833 ~SECONDARY_EXEC_RDRAND;
5837 if (vmx_rdseed_supported()) {
5838 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5840 exec_control &= ~SECONDARY_EXEC_RDSEED;
5844 vmx->nested.nested_vmx_secondary_ctls_high |=
5845 SECONDARY_EXEC_RDSEED;
5847 vmx->nested.nested_vmx_secondary_ctls_high &=
5848 ~SECONDARY_EXEC_RDSEED;
5852 vmx->secondary_exec_control = exec_control;
5855 static void ept_set_mmio_spte_mask(void)
5858 * EPT Misconfigurations can be generated if the value of bits 2:0
5859 * of an EPT paging-structure entry is 110b (write/execute).
5861 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5862 VMX_EPT_MISCONFIG_WX_VALUE);
5865 #define VMX_XSS_EXIT_BITMAP 0
5867 * Sets up the vmcs for emulated real mode.
5869 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5871 #ifdef CONFIG_X86_64
5877 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5878 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5880 if (enable_shadow_vmcs) {
5881 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5882 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5884 if (cpu_has_vmx_msr_bitmap())
5885 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5887 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5890 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5891 vmx->hv_deadline_tsc = -1;
5893 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5895 if (cpu_has_secondary_exec_ctrls()) {
5896 vmx_compute_secondary_exec_control(vmx);
5897 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5898 vmx->secondary_exec_control);
5901 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5902 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5903 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5904 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5905 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5907 vmcs_write16(GUEST_INTR_STATUS, 0);
5909 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5910 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5914 vmcs_write32(PLE_GAP, ple_gap);
5915 vmx->ple_window = ple_window;
5916 vmx->ple_window_dirty = true;
5919 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5920 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5921 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5923 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5924 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5925 vmx_set_constant_host_state(vmx);
5926 #ifdef CONFIG_X86_64
5927 rdmsrl(MSR_FS_BASE, a);
5928 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5929 rdmsrl(MSR_GS_BASE, a);
5930 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5932 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5933 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5936 if (cpu_has_vmx_vmfunc())
5937 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5939 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5940 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5941 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
5942 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5943 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
5945 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5946 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5948 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5949 u32 index = vmx_msr_index[i];
5950 u32 data_low, data_high;
5953 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5955 if (wrmsr_safe(index, data_low, data_high) < 0)
5957 vmx->guest_msrs[j].index = i;
5958 vmx->guest_msrs[j].data = 0;
5959 vmx->guest_msrs[j].mask = -1ull;
5963 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5965 /* 22.2.1, 20.8.1 */
5966 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5968 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5969 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5971 set_cr4_guest_host_mask(vmx);
5973 if (vmx_xsaves_supported())
5974 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5977 ASSERT(vmx->pml_pg);
5978 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5979 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5985 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5987 struct vcpu_vmx *vmx = to_vmx(vcpu);
5988 struct msr_data apic_base_msr;
5991 vmx->rmode.vm86_active = 0;
5994 vcpu->arch.microcode_version = 0x100000000ULL;
5995 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5996 kvm_set_cr8(vcpu, 0);
5999 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6000 MSR_IA32_APICBASE_ENABLE;
6001 if (kvm_vcpu_is_reset_bsp(vcpu))
6002 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6003 apic_base_msr.host_initiated = true;
6004 kvm_set_apic_base(vcpu, &apic_base_msr);
6007 vmx_segment_cache_clear(vmx);
6009 seg_setup(VCPU_SREG_CS);
6010 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6011 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6013 seg_setup(VCPU_SREG_DS);
6014 seg_setup(VCPU_SREG_ES);
6015 seg_setup(VCPU_SREG_FS);
6016 seg_setup(VCPU_SREG_GS);
6017 seg_setup(VCPU_SREG_SS);
6019 vmcs_write16(GUEST_TR_SELECTOR, 0);
6020 vmcs_writel(GUEST_TR_BASE, 0);
6021 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6022 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6024 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6025 vmcs_writel(GUEST_LDTR_BASE, 0);
6026 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6027 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6030 vmcs_write32(GUEST_SYSENTER_CS, 0);
6031 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6032 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6033 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6036 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6037 kvm_rip_write(vcpu, 0xfff0);
6039 vmcs_writel(GUEST_GDTR_BASE, 0);
6040 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6042 vmcs_writel(GUEST_IDTR_BASE, 0);
6043 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6045 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6046 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6047 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
6053 if (cpu_has_vmx_tpr_shadow() && !init_event) {
6054 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6055 if (cpu_need_tpr_shadow(vcpu))
6056 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6057 __pa(vcpu->arch.apic->regs));
6058 vmcs_write32(TPR_THRESHOLD, 0);
6061 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6064 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6066 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6067 vmx->vcpu.arch.cr0 = cr0;
6068 vmx_set_cr0(vcpu, cr0); /* enter rmode */
6069 vmx_set_cr4(vcpu, 0);
6070 vmx_set_efer(vcpu, 0);
6072 update_exception_bitmap(vcpu);
6074 vpid_sync_context(vmx->vpid);
6076 vmx_update_fb_clear_dis(vcpu, vmx);
6080 * In nested virtualization, check if L1 asked to exit on external interrupts.
6081 * For most existing hypervisors, this will always return true.
6083 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6085 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6086 PIN_BASED_EXT_INTR_MASK;
6090 * In nested virtualization, check if L1 has set
6091 * VM_EXIT_ACK_INTR_ON_EXIT
6093 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6095 return get_vmcs12(vcpu)->vm_exit_controls &
6096 VM_EXIT_ACK_INTR_ON_EXIT;
6099 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6101 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6102 PIN_BASED_NMI_EXITING;
6105 static void enable_irq_window(struct kvm_vcpu *vcpu)
6107 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6108 CPU_BASED_VIRTUAL_INTR_PENDING);
6111 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6113 if (!cpu_has_virtual_nmis() ||
6114 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6115 enable_irq_window(vcpu);
6119 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6120 CPU_BASED_VIRTUAL_NMI_PENDING);
6123 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6125 struct vcpu_vmx *vmx = to_vmx(vcpu);
6127 int irq = vcpu->arch.interrupt.nr;
6129 trace_kvm_inj_virq(irq);
6131 ++vcpu->stat.irq_injections;
6132 if (vmx->rmode.vm86_active) {
6134 if (vcpu->arch.interrupt.soft)
6135 inc_eip = vcpu->arch.event_exit_inst_len;
6136 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6137 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6140 intr = irq | INTR_INFO_VALID_MASK;
6141 if (vcpu->arch.interrupt.soft) {
6142 intr |= INTR_TYPE_SOFT_INTR;
6143 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6144 vmx->vcpu.arch.event_exit_inst_len);
6146 intr |= INTR_TYPE_EXT_INTR;
6147 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6150 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6152 struct vcpu_vmx *vmx = to_vmx(vcpu);
6154 if (!cpu_has_virtual_nmis()) {
6156 * Tracking the NMI-blocked state in software is built upon
6157 * finding the next open IRQ window. This, in turn, depends on
6158 * well-behaving guests: They have to keep IRQs disabled at
6159 * least as long as the NMI handler runs. Otherwise we may
6160 * cause NMI nesting, maybe breaking the guest. But as this is
6161 * highly unlikely, we can live with the residual risk.
6163 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6164 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6167 ++vcpu->stat.nmi_injections;
6168 vmx->loaded_vmcs->nmi_known_unmasked = false;
6170 if (vmx->rmode.vm86_active) {
6171 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6172 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6176 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6177 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6180 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6182 struct vcpu_vmx *vmx = to_vmx(vcpu);
6185 if (!cpu_has_virtual_nmis())
6186 return vmx->loaded_vmcs->soft_vnmi_blocked;
6187 if (vmx->loaded_vmcs->nmi_known_unmasked)
6189 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6190 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6194 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6196 struct vcpu_vmx *vmx = to_vmx(vcpu);
6198 if (!cpu_has_virtual_nmis()) {
6199 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6200 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6201 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6204 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6206 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6207 GUEST_INTR_STATE_NMI);
6209 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6210 GUEST_INTR_STATE_NMI);
6214 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6216 if (to_vmx(vcpu)->nested.nested_run_pending)
6219 if (!cpu_has_virtual_nmis() &&
6220 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6223 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6224 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6225 | GUEST_INTR_STATE_NMI));
6228 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6230 if (to_vmx(vcpu)->nested.nested_run_pending)
6233 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
6236 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6237 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6238 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6241 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6245 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6249 kvm->arch.tss_addr = addr;
6250 return init_rmode_tss(kvm);
6253 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6258 * Update instruction length as we may reinject the exception
6259 * from user space while in guest debugging mode.
6261 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6262 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6263 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6267 if (vcpu->guest_debug &
6268 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6285 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6286 int vec, u32 err_code)
6289 * Instruction with address size override prefix opcode 0x67
6290 * Cause the #SS fault with 0 error code in VM86 mode.
6292 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6293 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6294 if (vcpu->arch.halt_request) {
6295 vcpu->arch.halt_request = 0;
6296 return kvm_vcpu_halt(vcpu);
6304 * Forward all other exceptions that are valid in real mode.
6305 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6306 * the required debugging infrastructure rework.
6308 kvm_queue_exception(vcpu, vec);
6313 * Trigger machine check on the host. We assume all the MSRs are already set up
6314 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6315 * We pass a fake environment to the machine check handler because we want
6316 * the guest to be always treated like user space, no matter what context
6317 * it used internally.
6319 static void kvm_machine_check(void)
6321 #if defined(CONFIG_X86_MCE)
6322 struct pt_regs regs = {
6323 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6324 .flags = X86_EFLAGS_IF,
6327 do_machine_check(®s, 0);
6331 static int handle_machine_check(struct kvm_vcpu *vcpu)
6333 /* already handled by vcpu_run */
6337 static int handle_exception(struct kvm_vcpu *vcpu)
6339 struct vcpu_vmx *vmx = to_vmx(vcpu);
6340 struct kvm_run *kvm_run = vcpu->run;
6341 u32 intr_info, ex_no, error_code;
6342 unsigned long cr2, rip, dr6;
6344 enum emulation_result er;
6346 vect_info = vmx->idt_vectoring_info;
6347 intr_info = vmx->exit_intr_info;
6349 if (is_machine_check(intr_info))
6350 return handle_machine_check(vcpu);
6352 if (is_nmi(intr_info))
6353 return 1; /* already handled by vmx_vcpu_run() */
6355 if (is_invalid_opcode(intr_info)) {
6356 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
6357 if (er == EMULATE_USER_EXIT)
6359 if (er != EMULATE_DONE)
6360 kvm_queue_exception(vcpu, UD_VECTOR);
6365 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6366 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6369 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6370 * MMIO, it is better to report an internal error.
6371 * See the comments in vmx_handle_exit.
6373 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6374 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6375 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6376 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6377 vcpu->run->internal.ndata = 3;
6378 vcpu->run->internal.data[0] = vect_info;
6379 vcpu->run->internal.data[1] = intr_info;
6380 vcpu->run->internal.data[2] = error_code;
6384 if (is_page_fault(intr_info)) {
6385 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6386 /* EPT won't cause page fault directly */
6387 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6388 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
6392 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6394 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6395 return handle_rmode_exception(vcpu, ex_no, error_code);
6399 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6402 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6403 if (!(vcpu->guest_debug &
6404 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6405 vcpu->arch.dr6 &= ~15;
6406 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6407 if (is_icebp(intr_info))
6408 skip_emulated_instruction(vcpu);
6410 kvm_queue_exception(vcpu, DB_VECTOR);
6413 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6414 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6418 * Update instruction length as we may reinject #BP from
6419 * user space while in guest debugging mode. Reading it for
6420 * #DB as well causes no harm, it is not used in that case.
6422 vmx->vcpu.arch.event_exit_inst_len =
6423 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6424 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6425 rip = kvm_rip_read(vcpu);
6426 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6427 kvm_run->debug.arch.exception = ex_no;
6430 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6431 kvm_run->ex.exception = ex_no;
6432 kvm_run->ex.error_code = error_code;
6438 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6440 ++vcpu->stat.irq_exits;
6444 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6446 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6447 vcpu->mmio_needed = 0;
6451 static int handle_io(struct kvm_vcpu *vcpu)
6453 unsigned long exit_qualification;
6454 int size, in, string, ret;
6457 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6458 string = (exit_qualification & 16) != 0;
6459 in = (exit_qualification & 8) != 0;
6461 ++vcpu->stat.io_exits;
6464 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6466 port = exit_qualification >> 16;
6467 size = (exit_qualification & 7) + 1;
6469 ret = kvm_skip_emulated_instruction(vcpu);
6472 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6473 * KVM_EXIT_DEBUG here.
6475 return kvm_fast_pio_out(vcpu, size, port) && ret;
6479 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6482 * Patch in the VMCALL instruction:
6484 hypercall[0] = 0x0f;
6485 hypercall[1] = 0x01;
6486 hypercall[2] = 0xc1;
6489 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6490 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6492 if (is_guest_mode(vcpu)) {
6493 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6494 unsigned long orig_val = val;
6497 * We get here when L2 changed cr0 in a way that did not change
6498 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6499 * but did change L0 shadowed bits. So we first calculate the
6500 * effective cr0 value that L1 would like to write into the
6501 * hardware. It consists of the L2-owned bits from the new
6502 * value combined with the L1-owned bits from L1's guest_cr0.
6504 val = (val & ~vmcs12->cr0_guest_host_mask) |
6505 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6507 if (!nested_guest_cr0_valid(vcpu, val))
6510 if (kvm_set_cr0(vcpu, val))
6512 vmcs_writel(CR0_READ_SHADOW, orig_val);
6515 if (to_vmx(vcpu)->nested.vmxon &&
6516 !nested_host_cr0_valid(vcpu, val))
6519 return kvm_set_cr0(vcpu, val);
6523 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6525 if (is_guest_mode(vcpu)) {
6526 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6527 unsigned long orig_val = val;
6529 /* analogously to handle_set_cr0 */
6530 val = (val & ~vmcs12->cr4_guest_host_mask) |
6531 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6532 if (kvm_set_cr4(vcpu, val))
6534 vmcs_writel(CR4_READ_SHADOW, orig_val);
6537 return kvm_set_cr4(vcpu, val);
6540 static int handle_cr(struct kvm_vcpu *vcpu)
6542 unsigned long exit_qualification, val;
6548 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6549 cr = exit_qualification & 15;
6550 reg = (exit_qualification >> 8) & 15;
6551 switch ((exit_qualification >> 4) & 3) {
6552 case 0: /* mov to cr */
6553 val = kvm_register_readl(vcpu, reg);
6554 trace_kvm_cr_write(cr, val);
6557 err = handle_set_cr0(vcpu, val);
6558 return kvm_complete_insn_gp(vcpu, err);
6560 err = kvm_set_cr3(vcpu, val);
6561 return kvm_complete_insn_gp(vcpu, err);
6563 err = handle_set_cr4(vcpu, val);
6564 return kvm_complete_insn_gp(vcpu, err);
6566 u8 cr8_prev = kvm_get_cr8(vcpu);
6568 err = kvm_set_cr8(vcpu, cr8);
6569 ret = kvm_complete_insn_gp(vcpu, err);
6570 if (lapic_in_kernel(vcpu))
6572 if (cr8_prev <= cr8)
6575 * TODO: we might be squashing a
6576 * KVM_GUESTDBG_SINGLESTEP-triggered
6577 * KVM_EXIT_DEBUG here.
6579 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6585 WARN_ONCE(1, "Guest should always own CR0.TS");
6586 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6587 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6588 return kvm_skip_emulated_instruction(vcpu);
6589 case 1: /*mov from cr*/
6592 val = kvm_read_cr3(vcpu);
6593 kvm_register_write(vcpu, reg, val);
6594 trace_kvm_cr_read(cr, val);
6595 return kvm_skip_emulated_instruction(vcpu);
6597 val = kvm_get_cr8(vcpu);
6598 kvm_register_write(vcpu, reg, val);
6599 trace_kvm_cr_read(cr, val);
6600 return kvm_skip_emulated_instruction(vcpu);
6604 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6605 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6606 kvm_lmsw(vcpu, val);
6608 return kvm_skip_emulated_instruction(vcpu);
6612 vcpu->run->exit_reason = 0;
6613 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6614 (int)(exit_qualification >> 4) & 3, cr);
6618 static int handle_dr(struct kvm_vcpu *vcpu)
6620 unsigned long exit_qualification;
6623 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6624 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6626 /* First, if DR does not exist, trigger UD */
6627 if (!kvm_require_dr(vcpu, dr))
6630 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6631 if (!kvm_require_cpl(vcpu, 0))
6633 dr7 = vmcs_readl(GUEST_DR7);
6636 * As the vm-exit takes precedence over the debug trap, we
6637 * need to emulate the latter, either for the host or the
6638 * guest debugging itself.
6640 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6641 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6642 vcpu->run->debug.arch.dr7 = dr7;
6643 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6644 vcpu->run->debug.arch.exception = DB_VECTOR;
6645 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6648 vcpu->arch.dr6 &= ~15;
6649 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6650 kvm_queue_exception(vcpu, DB_VECTOR);
6655 if (vcpu->guest_debug == 0) {
6656 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6657 CPU_BASED_MOV_DR_EXITING);
6660 * No more DR vmexits; force a reload of the debug registers
6661 * and reenter on this instruction. The next vmexit will
6662 * retrieve the full state of the debug registers.
6664 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6668 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6669 if (exit_qualification & TYPE_MOV_FROM_DR) {
6672 if (kvm_get_dr(vcpu, dr, &val))
6674 kvm_register_write(vcpu, reg, val);
6676 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6679 return kvm_skip_emulated_instruction(vcpu);
6682 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6684 return vcpu->arch.dr6;
6687 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6691 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6693 get_debugreg(vcpu->arch.db[0], 0);
6694 get_debugreg(vcpu->arch.db[1], 1);
6695 get_debugreg(vcpu->arch.db[2], 2);
6696 get_debugreg(vcpu->arch.db[3], 3);
6697 get_debugreg(vcpu->arch.dr6, 6);
6698 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6700 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6701 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6704 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6706 vmcs_writel(GUEST_DR7, val);
6709 static int handle_cpuid(struct kvm_vcpu *vcpu)
6711 return kvm_emulate_cpuid(vcpu);
6714 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6716 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6717 struct msr_data msr_info;
6719 msr_info.index = ecx;
6720 msr_info.host_initiated = false;
6721 if (vmx_get_msr(vcpu, &msr_info)) {
6722 trace_kvm_msr_read_ex(ecx);
6723 kvm_inject_gp(vcpu, 0);
6727 trace_kvm_msr_read(ecx, msr_info.data);
6729 /* FIXME: handling of bits 32:63 of rax, rdx */
6730 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6731 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6732 return kvm_skip_emulated_instruction(vcpu);
6735 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6737 struct msr_data msr;
6738 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6739 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6740 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6744 msr.host_initiated = false;
6745 if (kvm_set_msr(vcpu, &msr) != 0) {
6746 trace_kvm_msr_write_ex(ecx, data);
6747 kvm_inject_gp(vcpu, 0);
6751 trace_kvm_msr_write(ecx, data);
6752 return kvm_skip_emulated_instruction(vcpu);
6755 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6757 kvm_apic_update_ppr(vcpu);
6761 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6763 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6764 CPU_BASED_VIRTUAL_INTR_PENDING);
6766 kvm_make_request(KVM_REQ_EVENT, vcpu);
6768 ++vcpu->stat.irq_window_exits;
6772 static int handle_halt(struct kvm_vcpu *vcpu)
6774 return kvm_emulate_halt(vcpu);
6777 static int handle_vmcall(struct kvm_vcpu *vcpu)
6779 return kvm_emulate_hypercall(vcpu);
6782 static int handle_invd(struct kvm_vcpu *vcpu)
6784 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6787 static int handle_invlpg(struct kvm_vcpu *vcpu)
6789 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6791 kvm_mmu_invlpg(vcpu, exit_qualification);
6792 return kvm_skip_emulated_instruction(vcpu);
6795 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6799 err = kvm_rdpmc(vcpu);
6800 return kvm_complete_insn_gp(vcpu, err);
6803 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6805 return kvm_emulate_wbinvd(vcpu);
6808 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6810 u64 new_bv = kvm_read_edx_eax(vcpu);
6811 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6813 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6814 return kvm_skip_emulated_instruction(vcpu);
6818 static int handle_xsaves(struct kvm_vcpu *vcpu)
6820 kvm_skip_emulated_instruction(vcpu);
6821 WARN(1, "this should never happen\n");
6825 static int handle_xrstors(struct kvm_vcpu *vcpu)
6827 kvm_skip_emulated_instruction(vcpu);
6828 WARN(1, "this should never happen\n");
6832 static int handle_apic_access(struct kvm_vcpu *vcpu)
6834 if (likely(fasteoi)) {
6835 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6836 int access_type, offset;
6838 access_type = exit_qualification & APIC_ACCESS_TYPE;
6839 offset = exit_qualification & APIC_ACCESS_OFFSET;
6841 * Sane guest uses MOV to write EOI, with written value
6842 * not cared. So make a short-circuit here by avoiding
6843 * heavy instruction emulation.
6845 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6846 (offset == APIC_EOI)) {
6847 kvm_lapic_set_eoi(vcpu);
6848 return kvm_skip_emulated_instruction(vcpu);
6851 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6854 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6856 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6857 int vector = exit_qualification & 0xff;
6859 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6860 kvm_apic_set_eoi_accelerated(vcpu, vector);
6864 static int handle_apic_write(struct kvm_vcpu *vcpu)
6866 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6867 u32 offset = exit_qualification & 0xfff;
6869 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6870 kvm_apic_write_nodecode(vcpu, offset);
6874 static int handle_task_switch(struct kvm_vcpu *vcpu)
6876 struct vcpu_vmx *vmx = to_vmx(vcpu);
6877 unsigned long exit_qualification;
6878 bool has_error_code = false;
6881 int reason, type, idt_v, idt_index;
6883 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6884 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6885 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6887 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6889 reason = (u32)exit_qualification >> 30;
6890 if (reason == TASK_SWITCH_GATE && idt_v) {
6892 case INTR_TYPE_NMI_INTR:
6893 vcpu->arch.nmi_injected = false;
6894 vmx_set_nmi_mask(vcpu, true);
6896 case INTR_TYPE_EXT_INTR:
6897 case INTR_TYPE_SOFT_INTR:
6898 kvm_clear_interrupt_queue(vcpu);
6900 case INTR_TYPE_HARD_EXCEPTION:
6901 if (vmx->idt_vectoring_info &
6902 VECTORING_INFO_DELIVER_CODE_MASK) {
6903 has_error_code = true;
6905 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6908 case INTR_TYPE_SOFT_EXCEPTION:
6909 kvm_clear_exception_queue(vcpu);
6915 tss_selector = exit_qualification;
6917 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6918 type != INTR_TYPE_EXT_INTR &&
6919 type != INTR_TYPE_NMI_INTR))
6920 skip_emulated_instruction(vcpu);
6922 if (kvm_task_switch(vcpu, tss_selector,
6923 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6924 has_error_code, error_code) == EMULATE_FAIL) {
6925 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6926 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6927 vcpu->run->internal.ndata = 0;
6932 * TODO: What about debug traps on tss switch?
6933 * Are we supposed to inject them and update dr6?
6939 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6941 unsigned long exit_qualification;
6945 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6948 * EPT violation happened while executing iret from NMI,
6949 * "blocked by NMI" bit has to be set before next VM entry.
6950 * There are errata that may cause this bit to not be set:
6953 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6954 cpu_has_virtual_nmis() &&
6955 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6956 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6958 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6959 trace_kvm_page_fault(gpa, exit_qualification);
6961 /* Is it a read fault? */
6962 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6963 ? PFERR_USER_MASK : 0;
6964 /* Is it a write fault? */
6965 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6966 ? PFERR_WRITE_MASK : 0;
6967 /* Is it a fetch fault? */
6968 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6969 ? PFERR_FETCH_MASK : 0;
6970 /* ept page table entry is present? */
6971 error_code |= (exit_qualification &
6972 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6973 EPT_VIOLATION_EXECUTABLE))
6974 ? PFERR_PRESENT_MASK : 0;
6976 error_code |= (exit_qualification & 0x100) != 0 ?
6977 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6979 vcpu->arch.exit_qualification = exit_qualification;
6980 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6983 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6989 * A nested guest cannot optimize MMIO vmexits, because we have an
6990 * nGPA here instead of the required GPA.
6992 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6993 if (!is_guest_mode(vcpu) &&
6994 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6995 trace_kvm_fast_mmio(gpa);
6997 * Doing kvm_skip_emulated_instruction() depends on undefined
6998 * behavior: Intel's manual doesn't mandate
6999 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7000 * occurs and while on real hardware it was observed to be set,
7001 * other hypervisors (namely Hyper-V) don't set it, we end up
7002 * advancing IP with some random value. Disable fast mmio when
7003 * running nested and keep it for real hardware in hope that
7004 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7006 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7007 return kvm_skip_emulated_instruction(vcpu);
7009 return emulate_instruction(vcpu, EMULTYPE_SKIP) ==
7013 ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7017 /* It is the real ept misconfig */
7020 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7021 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7026 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7028 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7029 CPU_BASED_VIRTUAL_NMI_PENDING);
7030 ++vcpu->stat.nmi_window_exits;
7031 kvm_make_request(KVM_REQ_EVENT, vcpu);
7036 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7038 struct vcpu_vmx *vmx = to_vmx(vcpu);
7039 enum emulation_result err = EMULATE_DONE;
7042 bool intr_window_requested;
7043 unsigned count = 130;
7045 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7046 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7048 while (vmx->emulation_required && count-- != 0) {
7049 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7050 return handle_interrupt_window(&vmx->vcpu);
7052 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7055 err = emulate_instruction(vcpu, 0);
7057 if (err == EMULATE_USER_EXIT) {
7058 ++vcpu->stat.mmio_exits;
7063 if (err != EMULATE_DONE)
7064 goto emulation_error;
7066 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7067 vcpu->arch.exception.pending)
7068 goto emulation_error;
7070 if (vcpu->arch.halt_request) {
7071 vcpu->arch.halt_request = 0;
7072 ret = kvm_vcpu_halt(vcpu);
7076 if (signal_pending(current))
7086 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7087 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7088 vcpu->run->internal.ndata = 0;
7092 static int __grow_ple_window(int val)
7094 if (ple_window_grow < 1)
7097 val = min(val, ple_window_actual_max);
7099 if (ple_window_grow < ple_window)
7100 val *= ple_window_grow;
7102 val += ple_window_grow;
7107 static int __shrink_ple_window(int val, int modifier, int minimum)
7112 if (modifier < ple_window)
7117 return max(val, minimum);
7120 static void grow_ple_window(struct kvm_vcpu *vcpu)
7122 struct vcpu_vmx *vmx = to_vmx(vcpu);
7123 int old = vmx->ple_window;
7125 vmx->ple_window = __grow_ple_window(old);
7127 if (vmx->ple_window != old)
7128 vmx->ple_window_dirty = true;
7130 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7133 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7135 struct vcpu_vmx *vmx = to_vmx(vcpu);
7136 int old = vmx->ple_window;
7138 vmx->ple_window = __shrink_ple_window(old,
7139 ple_window_shrink, ple_window);
7141 if (vmx->ple_window != old)
7142 vmx->ple_window_dirty = true;
7144 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7148 * ple_window_actual_max is computed to be one grow_ple_window() below
7149 * ple_window_max. (See __grow_ple_window for the reason.)
7150 * This prevents overflows, because ple_window_max is int.
7151 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
7153 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
7155 static void update_ple_window_actual_max(void)
7157 ple_window_actual_max =
7158 __shrink_ple_window(max(ple_window_max, ple_window),
7159 ple_window_grow, INT_MIN);
7163 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7165 static void wakeup_handler(void)
7167 struct kvm_vcpu *vcpu;
7168 int cpu = smp_processor_id();
7170 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7171 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7172 blocked_vcpu_list) {
7173 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7175 if (pi_test_on(pi_desc) == 1)
7176 kvm_vcpu_kick(vcpu);
7178 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7181 void vmx_enable_tdp(void)
7183 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7184 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7185 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7186 0ull, VMX_EPT_EXECUTABLE_MASK,
7187 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7188 VMX_EPT_RWX_MASK, 0ull);
7190 ept_set_mmio_spte_mask();
7194 static __init int hardware_setup(void)
7198 rdmsrl_safe(MSR_EFER, &host_efer);
7200 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7201 kvm_define_shared_msr(i, vmx_msr_index[i]);
7203 for (i = 0; i < VMX_BITMAP_NR; i++) {
7204 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7209 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7210 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7212 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7214 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7216 if (setup_vmcs_config(&vmcs_config) < 0) {
7221 if (boot_cpu_has(X86_FEATURE_NX))
7222 kvm_enable_efer_bits(EFER_NX);
7224 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7225 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7228 if (!cpu_has_vmx_shadow_vmcs())
7229 enable_shadow_vmcs = 0;
7230 if (enable_shadow_vmcs)
7231 init_vmcs_shadow_fields();
7233 if (!cpu_has_vmx_ept() ||
7234 !cpu_has_vmx_ept_4levels() ||
7235 !cpu_has_vmx_ept_mt_wb()) {
7237 enable_unrestricted_guest = 0;
7238 enable_ept_ad_bits = 0;
7241 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7242 enable_ept_ad_bits = 0;
7244 if (!cpu_has_vmx_unrestricted_guest())
7245 enable_unrestricted_guest = 0;
7247 if (!cpu_has_vmx_flexpriority())
7248 flexpriority_enabled = 0;
7251 * set_apic_access_page_addr() is used to reload apic access
7252 * page upon invalidation. No need to do anything if not
7253 * using the APIC_ACCESS_ADDR VMCS field.
7255 if (!flexpriority_enabled)
7256 kvm_x86_ops->set_apic_access_page_addr = NULL;
7258 if (!cpu_has_vmx_tpr_shadow())
7259 kvm_x86_ops->update_cr8_intercept = NULL;
7261 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7262 kvm_disable_largepages();
7264 if (!cpu_has_vmx_ple())
7267 if (!cpu_has_vmx_apicv()) {
7269 kvm_x86_ops->sync_pir_to_irr = NULL;
7272 if (cpu_has_vmx_tsc_scaling()) {
7273 kvm_has_tsc_control = true;
7274 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7275 kvm_tsc_scaling_ratio_frac_bits = 48;
7278 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7285 update_ple_window_actual_max();
7288 * Only enable PML when hardware supports PML feature, and both EPT
7289 * and EPT A/D bit features are enabled -- PML depends on them to work.
7291 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7295 kvm_x86_ops->slot_enable_log_dirty = NULL;
7296 kvm_x86_ops->slot_disable_log_dirty = NULL;
7297 kvm_x86_ops->flush_log_dirty = NULL;
7298 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7301 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7304 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7305 cpu_preemption_timer_multi =
7306 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7308 kvm_x86_ops->set_hv_timer = NULL;
7309 kvm_x86_ops->cancel_hv_timer = NULL;
7312 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7314 kvm_mce_cap_supported |= MCG_LMCE_P;
7316 r = alloc_kvm_area();
7322 for (i = 0; i < VMX_BITMAP_NR; i++)
7323 free_page((unsigned long)vmx_bitmap[i]);
7328 static __exit void hardware_unsetup(void)
7332 for (i = 0; i < VMX_BITMAP_NR; i++)
7333 free_page((unsigned long)vmx_bitmap[i]);
7339 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7340 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7342 static int handle_pause(struct kvm_vcpu *vcpu)
7345 grow_ple_window(vcpu);
7348 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7349 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7350 * never set PAUSE_EXITING and just set PLE if supported,
7351 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7353 kvm_vcpu_on_spin(vcpu, true);
7354 return kvm_skip_emulated_instruction(vcpu);
7357 static int handle_nop(struct kvm_vcpu *vcpu)
7359 return kvm_skip_emulated_instruction(vcpu);
7362 static int handle_mwait(struct kvm_vcpu *vcpu)
7364 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7365 return handle_nop(vcpu);
7368 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7370 kvm_queue_exception(vcpu, UD_VECTOR);
7374 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7379 static int handle_monitor(struct kvm_vcpu *vcpu)
7381 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7382 return handle_nop(vcpu);
7386 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7387 * set the success or error code of an emulated VMX instruction, as specified
7388 * by Vol 2B, VMX Instruction Reference, "Conventions".
7390 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7392 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7393 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7394 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7397 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7399 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7400 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7401 X86_EFLAGS_SF | X86_EFLAGS_OF))
7405 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7406 u32 vm_instruction_error)
7408 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7410 * failValid writes the error number to the current VMCS, which
7411 * can't be done there isn't a current VMCS.
7413 nested_vmx_failInvalid(vcpu);
7416 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7417 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7418 X86_EFLAGS_SF | X86_EFLAGS_OF))
7420 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7422 * We don't need to force a shadow sync because
7423 * VM_INSTRUCTION_ERROR is not shadowed
7427 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7429 /* TODO: not to reset guest simply here. */
7430 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7431 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7434 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7436 struct vcpu_vmx *vmx =
7437 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7439 vmx->nested.preemption_timer_expired = true;
7440 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7441 kvm_vcpu_kick(&vmx->vcpu);
7443 return HRTIMER_NORESTART;
7447 * Decode the memory-address operand of a vmx instruction, as recorded on an
7448 * exit caused by such an instruction (run by a guest hypervisor).
7449 * On success, returns 0. When the operand is invalid, returns 1 and throws
7452 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7453 unsigned long exit_qualification,
7454 u32 vmx_instruction_info, bool wr, gva_t *ret)
7458 struct kvm_segment s;
7461 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7462 * Execution", on an exit, vmx_instruction_info holds most of the
7463 * addressing components of the operand. Only the displacement part
7464 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7465 * For how an actual address is calculated from all these components,
7466 * refer to Vol. 1, "Operand Addressing".
7468 int scaling = vmx_instruction_info & 3;
7469 int addr_size = (vmx_instruction_info >> 7) & 7;
7470 bool is_reg = vmx_instruction_info & (1u << 10);
7471 int seg_reg = (vmx_instruction_info >> 15) & 7;
7472 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7473 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7474 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7475 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7478 kvm_queue_exception(vcpu, UD_VECTOR);
7482 /* Addr = segment_base + offset */
7483 /* offset = base + [index * scale] + displacement */
7484 off = exit_qualification; /* holds the displacement */
7486 off = (gva_t)sign_extend64(off, 31);
7487 else if (addr_size == 0)
7488 off = (gva_t)sign_extend64(off, 15);
7490 off += kvm_register_read(vcpu, base_reg);
7492 off += kvm_register_read(vcpu, index_reg)<<scaling;
7493 vmx_get_segment(vcpu, &s, seg_reg);
7496 * The effective address, i.e. @off, of a memory operand is truncated
7497 * based on the address size of the instruction. Note that this is
7498 * the *effective address*, i.e. the address prior to accounting for
7499 * the segment's base.
7501 if (addr_size == 1) /* 32 bit */
7503 else if (addr_size == 0) /* 16 bit */
7506 /* Checks for #GP/#SS exceptions. */
7508 if (is_long_mode(vcpu)) {
7510 * The virtual/linear address is never truncated in 64-bit
7511 * mode, e.g. a 32-bit address size can yield a 64-bit virtual
7512 * address when using FS/GS with a non-zero base.
7514 *ret = s.base + off;
7516 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7517 * non-canonical form. This is the only check on the memory
7518 * destination for long mode!
7520 exn = is_noncanonical_address(*ret, vcpu);
7521 } else if (is_protmode(vcpu)) {
7523 * When not in long mode, the virtual/linear address is
7524 * unconditionally truncated to 32 bits regardless of the
7527 *ret = (s.base + off) & 0xffffffff;
7529 /* Protected mode: apply checks for segment validity in the
7531 * - segment type check (#GP(0) may be thrown)
7532 * - usability check (#GP(0)/#SS(0))
7533 * - limit check (#GP(0)/#SS(0))
7536 /* #GP(0) if the destination operand is located in a
7537 * read-only data segment or any code segment.
7539 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7541 /* #GP(0) if the source operand is located in an
7542 * execute-only code segment
7544 exn = ((s.type & 0xa) == 8);
7546 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7549 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7551 exn = (s.unusable != 0);
7554 * Protected mode: #GP(0)/#SS(0) if the memory operand is
7555 * outside the segment limit. All CPUs that support VMX ignore
7556 * limit checks for flat segments, i.e. segments with base==0,
7557 * limit==0xffffffff and of type expand-up data or code.
7559 if (!(s.base == 0 && s.limit == 0xffffffff &&
7560 ((s.type & 8) || !(s.type & 4))))
7561 exn = exn || (off + sizeof(u64) > s.limit);
7564 kvm_queue_exception_e(vcpu,
7565 seg_reg == VCPU_SREG_SS ?
7566 SS_VECTOR : GP_VECTOR,
7574 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7577 struct x86_exception e;
7579 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7580 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7583 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7584 kvm_inject_page_fault(vcpu, &e);
7591 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7593 struct vcpu_vmx *vmx = to_vmx(vcpu);
7594 struct vmcs *shadow_vmcs;
7597 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7601 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7602 if (!vmx->nested.cached_vmcs12)
7603 goto out_cached_vmcs12;
7605 if (enable_shadow_vmcs) {
7606 shadow_vmcs = alloc_vmcs();
7608 goto out_shadow_vmcs;
7609 /* mark vmcs as shadow */
7610 shadow_vmcs->revision_id |= (1u << 31);
7611 /* init shadow vmcs */
7612 vmcs_clear(shadow_vmcs);
7613 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7616 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7617 HRTIMER_MODE_REL_PINNED);
7618 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7620 vmx->nested.vpid02 = allocate_vpid();
7622 vmx->nested.vmxon = true;
7626 kfree(vmx->nested.cached_vmcs12);
7629 free_loaded_vmcs(&vmx->nested.vmcs02);
7636 * Emulate the VMXON instruction.
7637 * Currently, we just remember that VMX is active, and do not save or even
7638 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7639 * do not currently need to store anything in that guest-allocated memory
7640 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7641 * argument is different from the VMXON pointer (which the spec says they do).
7643 static int handle_vmon(struct kvm_vcpu *vcpu)
7648 struct vcpu_vmx *vmx = to_vmx(vcpu);
7649 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7650 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7653 * The Intel VMX Instruction Reference lists a bunch of bits that are
7654 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7655 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7656 * Otherwise, we should fail with #UD. But most faulting conditions
7657 * have already been checked by hardware, prior to the VM-exit for
7658 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7659 * that bit set to 1 in non-root mode.
7661 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7662 kvm_queue_exception(vcpu, UD_VECTOR);
7666 /* CPL=0 must be checked manually. */
7667 if (vmx_get_cpl(vcpu)) {
7668 kvm_inject_gp(vcpu, 0);
7672 if (vmx->nested.vmxon) {
7673 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7674 return kvm_skip_emulated_instruction(vcpu);
7677 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7678 != VMXON_NEEDED_FEATURES) {
7679 kvm_inject_gp(vcpu, 0);
7683 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7688 * The first 4 bytes of VMXON region contain the supported
7689 * VMCS revision identifier
7691 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7692 * which replaces physical address width with 32
7694 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7695 nested_vmx_failInvalid(vcpu);
7696 return kvm_skip_emulated_instruction(vcpu);
7699 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7700 if (is_error_page(page)) {
7701 nested_vmx_failInvalid(vcpu);
7702 return kvm_skip_emulated_instruction(vcpu);
7704 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7706 kvm_release_page_clean(page);
7707 nested_vmx_failInvalid(vcpu);
7708 return kvm_skip_emulated_instruction(vcpu);
7711 kvm_release_page_clean(page);
7713 vmx->nested.vmxon_ptr = vmptr;
7714 ret = enter_vmx_operation(vcpu);
7718 nested_vmx_succeed(vcpu);
7719 return kvm_skip_emulated_instruction(vcpu);
7723 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7724 * for running VMX instructions (except VMXON, whose prerequisites are
7725 * slightly different). It also specifies what exception to inject otherwise.
7726 * Note that many of these exceptions have priority over VM exits, so they
7727 * don't have to be checked again here.
7729 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7731 if (vmx_get_cpl(vcpu)) {
7732 kvm_inject_gp(vcpu, 0);
7736 if (!to_vmx(vcpu)->nested.vmxon) {
7737 kvm_queue_exception(vcpu, UD_VECTOR);
7743 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7745 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7746 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7747 vmx->nested.sync_shadow_vmcs = false;
7750 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7752 if (vmx->nested.current_vmptr == -1ull)
7755 if (enable_shadow_vmcs) {
7756 /* copy to memory all shadowed fields in case
7757 they were modified */
7758 copy_shadow_to_vmcs12(vmx);
7759 vmx_disable_shadow_vmcs(vmx);
7761 vmx->nested.posted_intr_nv = -1;
7763 /* Flush VMCS12 to guest memory */
7764 kvm_vcpu_write_guest_page(&vmx->vcpu,
7765 vmx->nested.current_vmptr >> PAGE_SHIFT,
7766 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7768 vmx->nested.current_vmptr = -1ull;
7772 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7773 * just stops using VMX.
7775 static void free_nested(struct vcpu_vmx *vmx)
7777 if (!vmx->nested.vmxon)
7780 hrtimer_cancel(&vmx->nested.preemption_timer);
7781 vmx->nested.vmxon = false;
7782 free_vpid(vmx->nested.vpid02);
7783 vmx->nested.posted_intr_nv = -1;
7784 vmx->nested.current_vmptr = -1ull;
7785 if (enable_shadow_vmcs) {
7786 vmx_disable_shadow_vmcs(vmx);
7787 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7788 free_vmcs(vmx->vmcs01.shadow_vmcs);
7789 vmx->vmcs01.shadow_vmcs = NULL;
7791 kfree(vmx->nested.cached_vmcs12);
7792 /* Unpin physical memory we referred to in the vmcs02 */
7793 if (vmx->nested.apic_access_page) {
7794 kvm_release_page_dirty(vmx->nested.apic_access_page);
7795 vmx->nested.apic_access_page = NULL;
7797 if (vmx->nested.virtual_apic_page) {
7798 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7799 vmx->nested.virtual_apic_page = NULL;
7801 if (vmx->nested.pi_desc_page) {
7802 kunmap(vmx->nested.pi_desc_page);
7803 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7804 vmx->nested.pi_desc_page = NULL;
7805 vmx->nested.pi_desc = NULL;
7808 free_loaded_vmcs(&vmx->nested.vmcs02);
7811 /* Emulate the VMXOFF instruction */
7812 static int handle_vmoff(struct kvm_vcpu *vcpu)
7814 if (!nested_vmx_check_permission(vcpu))
7816 free_nested(to_vmx(vcpu));
7817 nested_vmx_succeed(vcpu);
7818 return kvm_skip_emulated_instruction(vcpu);
7821 /* Emulate the VMCLEAR instruction */
7822 static int handle_vmclear(struct kvm_vcpu *vcpu)
7824 struct vcpu_vmx *vmx = to_vmx(vcpu);
7828 if (!nested_vmx_check_permission(vcpu))
7831 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7834 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7835 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7836 return kvm_skip_emulated_instruction(vcpu);
7839 if (vmptr == vmx->nested.vmxon_ptr) {
7840 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7841 return kvm_skip_emulated_instruction(vcpu);
7844 if (vmptr == vmx->nested.current_vmptr)
7845 nested_release_vmcs12(vmx);
7847 kvm_vcpu_write_guest(vcpu,
7848 vmptr + offsetof(struct vmcs12, launch_state),
7849 &zero, sizeof(zero));
7851 nested_vmx_succeed(vcpu);
7852 return kvm_skip_emulated_instruction(vcpu);
7855 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7857 /* Emulate the VMLAUNCH instruction */
7858 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7860 return nested_vmx_run(vcpu, true);
7863 /* Emulate the VMRESUME instruction */
7864 static int handle_vmresume(struct kvm_vcpu *vcpu)
7867 return nested_vmx_run(vcpu, false);
7871 * Read a vmcs12 field. Since these can have varying lengths and we return
7872 * one type, we chose the biggest type (u64) and zero-extend the return value
7873 * to that size. Note that the caller, handle_vmread, might need to use only
7874 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7875 * 64-bit fields are to be returned).
7877 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7878 unsigned long field, u64 *ret)
7880 short offset = vmcs_field_to_offset(field);
7886 p = ((char *)(get_vmcs12(vcpu))) + offset;
7888 switch (vmcs_field_type(field)) {
7889 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7890 *ret = *((natural_width *)p);
7892 case VMCS_FIELD_TYPE_U16:
7895 case VMCS_FIELD_TYPE_U32:
7898 case VMCS_FIELD_TYPE_U64:
7908 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7909 unsigned long field, u64 field_value){
7910 short offset = vmcs_field_to_offset(field);
7911 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7915 switch (vmcs_field_type(field)) {
7916 case VMCS_FIELD_TYPE_U16:
7917 *(u16 *)p = field_value;
7919 case VMCS_FIELD_TYPE_U32:
7920 *(u32 *)p = field_value;
7922 case VMCS_FIELD_TYPE_U64:
7923 *(u64 *)p = field_value;
7925 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7926 *(natural_width *)p = field_value;
7935 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7938 unsigned long field;
7940 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7941 const unsigned long *fields = shadow_read_write_fields;
7942 const int num_fields = max_shadow_read_write_fields;
7944 if (WARN_ON(!shadow_vmcs))
7949 vmcs_load(shadow_vmcs);
7951 for (i = 0; i < num_fields; i++) {
7953 switch (vmcs_field_type(field)) {
7954 case VMCS_FIELD_TYPE_U16:
7955 field_value = vmcs_read16(field);
7957 case VMCS_FIELD_TYPE_U32:
7958 field_value = vmcs_read32(field);
7960 case VMCS_FIELD_TYPE_U64:
7961 field_value = vmcs_read64(field);
7963 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7964 field_value = vmcs_readl(field);
7970 vmcs12_write_any(&vmx->vcpu, field, field_value);
7973 vmcs_clear(shadow_vmcs);
7974 vmcs_load(vmx->loaded_vmcs->vmcs);
7979 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7981 const unsigned long *fields[] = {
7982 shadow_read_write_fields,
7983 shadow_read_only_fields
7985 const int max_fields[] = {
7986 max_shadow_read_write_fields,
7987 max_shadow_read_only_fields
7990 unsigned long field;
7991 u64 field_value = 0;
7992 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7994 if (WARN_ON(!shadow_vmcs))
7997 vmcs_load(shadow_vmcs);
7999 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8000 for (i = 0; i < max_fields[q]; i++) {
8001 field = fields[q][i];
8002 vmcs12_read_any(&vmx->vcpu, field, &field_value);
8004 switch (vmcs_field_type(field)) {
8005 case VMCS_FIELD_TYPE_U16:
8006 vmcs_write16(field, (u16)field_value);
8008 case VMCS_FIELD_TYPE_U32:
8009 vmcs_write32(field, (u32)field_value);
8011 case VMCS_FIELD_TYPE_U64:
8012 vmcs_write64(field, (u64)field_value);
8014 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
8015 vmcs_writel(field, (long)field_value);
8024 vmcs_clear(shadow_vmcs);
8025 vmcs_load(vmx->loaded_vmcs->vmcs);
8029 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8030 * used before) all generate the same failure when it is missing.
8032 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8034 struct vcpu_vmx *vmx = to_vmx(vcpu);
8035 if (vmx->nested.current_vmptr == -1ull) {
8036 nested_vmx_failInvalid(vcpu);
8042 static int handle_vmread(struct kvm_vcpu *vcpu)
8044 unsigned long field;
8046 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8047 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8049 struct x86_exception e;
8051 if (!nested_vmx_check_permission(vcpu))
8054 if (!nested_vmx_check_vmcs12(vcpu))
8055 return kvm_skip_emulated_instruction(vcpu);
8057 /* Decode instruction info and find the field to read */
8058 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8059 /* Read the field, zero-extended to a u64 field_value */
8060 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8061 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8062 return kvm_skip_emulated_instruction(vcpu);
8065 * Now copy part of this value to register or memory, as requested.
8066 * Note that the number of bits actually copied is 32 or 64 depending
8067 * on the guest's mode (32 or 64 bit), not on the given field's length.
8069 if (vmx_instruction_info & (1u << 10)) {
8070 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8073 if (get_vmx_mem_address(vcpu, exit_qualification,
8074 vmx_instruction_info, true, &gva))
8076 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8077 if (kvm_write_guest_virt_system(vcpu, gva, &field_value,
8078 (is_long_mode(vcpu) ? 8 : 4),
8080 kvm_inject_page_fault(vcpu, &e);
8085 nested_vmx_succeed(vcpu);
8086 return kvm_skip_emulated_instruction(vcpu);
8090 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8092 unsigned long field;
8094 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8095 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8096 /* The value to write might be 32 or 64 bits, depending on L1's long
8097 * mode, and eventually we need to write that into a field of several
8098 * possible lengths. The code below first zero-extends the value to 64
8099 * bit (field_value), and then copies only the appropriate number of
8100 * bits into the vmcs12 field.
8102 u64 field_value = 0;
8103 struct x86_exception e;
8105 if (!nested_vmx_check_permission(vcpu))
8108 if (!nested_vmx_check_vmcs12(vcpu))
8109 return kvm_skip_emulated_instruction(vcpu);
8111 if (vmx_instruction_info & (1u << 10))
8112 field_value = kvm_register_readl(vcpu,
8113 (((vmx_instruction_info) >> 3) & 0xf));
8115 if (get_vmx_mem_address(vcpu, exit_qualification,
8116 vmx_instruction_info, false, &gva))
8118 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8119 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8120 kvm_inject_page_fault(vcpu, &e);
8126 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8127 if (vmcs_field_readonly(field)) {
8128 nested_vmx_failValid(vcpu,
8129 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8130 return kvm_skip_emulated_instruction(vcpu);
8133 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8134 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8135 return kvm_skip_emulated_instruction(vcpu);
8138 nested_vmx_succeed(vcpu);
8139 return kvm_skip_emulated_instruction(vcpu);
8142 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8144 vmx->nested.current_vmptr = vmptr;
8145 if (enable_shadow_vmcs) {
8146 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8147 SECONDARY_EXEC_SHADOW_VMCS);
8148 vmcs_write64(VMCS_LINK_POINTER,
8149 __pa(vmx->vmcs01.shadow_vmcs));
8150 vmx->nested.sync_shadow_vmcs = true;
8154 /* Emulate the VMPTRLD instruction */
8155 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8157 struct vcpu_vmx *vmx = to_vmx(vcpu);
8160 if (!nested_vmx_check_permission(vcpu))
8163 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8166 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8167 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8168 return kvm_skip_emulated_instruction(vcpu);
8171 if (vmptr == vmx->nested.vmxon_ptr) {
8172 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8173 return kvm_skip_emulated_instruction(vcpu);
8176 if (vmx->nested.current_vmptr != vmptr) {
8177 struct vmcs12 *new_vmcs12;
8179 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8180 if (is_error_page(page)) {
8181 nested_vmx_failInvalid(vcpu);
8182 return kvm_skip_emulated_instruction(vcpu);
8184 new_vmcs12 = kmap(page);
8185 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8187 kvm_release_page_clean(page);
8188 nested_vmx_failValid(vcpu,
8189 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8190 return kvm_skip_emulated_instruction(vcpu);
8193 nested_release_vmcs12(vmx);
8195 * Load VMCS12 from guest memory since it is not already
8198 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8200 kvm_release_page_clean(page);
8202 set_current_vmptr(vmx, vmptr);
8205 nested_vmx_succeed(vcpu);
8206 return kvm_skip_emulated_instruction(vcpu);
8209 /* Emulate the VMPTRST instruction */
8210 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8212 unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
8213 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8214 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
8215 struct x86_exception e;
8218 if (!nested_vmx_check_permission(vcpu))
8221 if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva))
8223 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8224 if (kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr,
8225 sizeof(gpa_t), &e)) {
8226 kvm_inject_page_fault(vcpu, &e);
8229 nested_vmx_succeed(vcpu);
8230 return kvm_skip_emulated_instruction(vcpu);
8233 /* Emulate the INVEPT instruction */
8234 static int handle_invept(struct kvm_vcpu *vcpu)
8236 struct vcpu_vmx *vmx = to_vmx(vcpu);
8237 u32 vmx_instruction_info, types;
8240 struct x86_exception e;
8245 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
8246 SECONDARY_EXEC_ENABLE_EPT) ||
8247 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
8248 kvm_queue_exception(vcpu, UD_VECTOR);
8252 if (!nested_vmx_check_permission(vcpu))
8255 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8256 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8258 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8260 if (type >= 32 || !(types & (1 << type))) {
8261 nested_vmx_failValid(vcpu,
8262 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8263 return kvm_skip_emulated_instruction(vcpu);
8266 /* According to the Intel VMX instruction reference, the memory
8267 * operand is read even if it isn't needed (e.g., for type==global)
8269 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8270 vmx_instruction_info, false, &gva))
8272 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8273 kvm_inject_page_fault(vcpu, &e);
8278 case VMX_EPT_EXTENT_GLOBAL:
8280 * TODO: track mappings and invalidate
8281 * single context requests appropriately
8283 case VMX_EPT_EXTENT_CONTEXT:
8284 kvm_mmu_sync_roots(vcpu);
8285 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8286 nested_vmx_succeed(vcpu);
8293 return kvm_skip_emulated_instruction(vcpu);
8296 static int handle_invvpid(struct kvm_vcpu *vcpu)
8298 struct vcpu_vmx *vmx = to_vmx(vcpu);
8299 u32 vmx_instruction_info;
8300 unsigned long type, types;
8302 struct x86_exception e;
8308 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
8309 SECONDARY_EXEC_ENABLE_VPID) ||
8310 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
8311 kvm_queue_exception(vcpu, UD_VECTOR);
8315 if (!nested_vmx_check_permission(vcpu))
8318 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8319 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8321 types = (vmx->nested.nested_vmx_vpid_caps &
8322 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8324 if (type >= 32 || !(types & (1 << type))) {
8325 nested_vmx_failValid(vcpu,
8326 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8327 return kvm_skip_emulated_instruction(vcpu);
8330 /* according to the intel vmx instruction reference, the memory
8331 * operand is read even if it isn't needed (e.g., for type==global)
8333 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8334 vmx_instruction_info, false, &gva))
8336 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8337 kvm_inject_page_fault(vcpu, &e);
8340 if (operand.vpid >> 16) {
8341 nested_vmx_failValid(vcpu,
8342 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8343 return kvm_skip_emulated_instruction(vcpu);
8347 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8348 if (is_noncanonical_address(operand.gla, vcpu)) {
8349 nested_vmx_failValid(vcpu,
8350 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8351 return kvm_skip_emulated_instruction(vcpu);
8354 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8355 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8356 if (!operand.vpid) {
8357 nested_vmx_failValid(vcpu,
8358 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8359 return kvm_skip_emulated_instruction(vcpu);
8362 case VMX_VPID_EXTENT_ALL_CONTEXT:
8366 return kvm_skip_emulated_instruction(vcpu);
8369 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8370 nested_vmx_succeed(vcpu);
8372 return kvm_skip_emulated_instruction(vcpu);
8375 static int handle_pml_full(struct kvm_vcpu *vcpu)
8377 unsigned long exit_qualification;
8379 trace_kvm_pml_full(vcpu->vcpu_id);
8381 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8384 * PML buffer FULL happened while executing iret from NMI,
8385 * "blocked by NMI" bit has to be set before next VM entry.
8387 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8388 cpu_has_virtual_nmis() &&
8389 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8390 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8391 GUEST_INTR_STATE_NMI);
8394 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8395 * here.., and there's no userspace involvement needed for PML.
8400 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8402 kvm_lapic_expired_hv_timer(vcpu);
8406 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8408 struct vcpu_vmx *vmx = to_vmx(vcpu);
8409 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8411 /* Check for memory type validity */
8412 switch (address & VMX_EPTP_MT_MASK) {
8413 case VMX_EPTP_MT_UC:
8414 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8417 case VMX_EPTP_MT_WB:
8418 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8425 /* only 4 levels page-walk length are valid */
8426 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8429 /* Reserved bits should not be set */
8430 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8433 /* AD, if set, should be supported */
8434 if (address & VMX_EPTP_AD_ENABLE_BIT) {
8435 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8442 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8443 struct vmcs12 *vmcs12)
8445 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8447 bool accessed_dirty;
8448 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8450 if (!nested_cpu_has_eptp_switching(vmcs12) ||
8451 !nested_cpu_has_ept(vmcs12))
8454 if (index >= VMFUNC_EPTP_ENTRIES)
8458 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8459 &address, index * 8, 8))
8462 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8465 * If the (L2) guest does a vmfunc to the currently
8466 * active ept pointer, we don't have to do anything else
8468 if (vmcs12->ept_pointer != address) {
8469 if (!valid_ept_address(vcpu, address))
8472 kvm_mmu_unload(vcpu);
8473 mmu->ept_ad = accessed_dirty;
8474 mmu->base_role.ad_disabled = !accessed_dirty;
8475 vmcs12->ept_pointer = address;
8477 * TODO: Check what's the correct approach in case
8478 * mmu reload fails. Currently, we just let the next
8479 * reload potentially fail
8481 kvm_mmu_reload(vcpu);
8487 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8489 struct vcpu_vmx *vmx = to_vmx(vcpu);
8490 struct vmcs12 *vmcs12;
8491 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8494 * VMFUNC is only supported for nested guests, but we always enable the
8495 * secondary control for simplicity; for non-nested mode, fake that we
8496 * didn't by injecting #UD.
8498 if (!is_guest_mode(vcpu)) {
8499 kvm_queue_exception(vcpu, UD_VECTOR);
8503 vmcs12 = get_vmcs12(vcpu);
8504 if ((vmcs12->vm_function_control & (1 << function)) == 0)
8509 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8515 return kvm_skip_emulated_instruction(vcpu);
8518 nested_vmx_vmexit(vcpu, vmx->exit_reason,
8519 vmcs_read32(VM_EXIT_INTR_INFO),
8520 vmcs_readl(EXIT_QUALIFICATION));
8525 * The exit handlers return 1 if the exit was handled fully and guest execution
8526 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8527 * to be done to userspace and return 0.
8529 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8530 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
8531 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
8532 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
8533 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
8534 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
8535 [EXIT_REASON_CR_ACCESS] = handle_cr,
8536 [EXIT_REASON_DR_ACCESS] = handle_dr,
8537 [EXIT_REASON_CPUID] = handle_cpuid,
8538 [EXIT_REASON_MSR_READ] = handle_rdmsr,
8539 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
8540 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
8541 [EXIT_REASON_HLT] = handle_halt,
8542 [EXIT_REASON_INVD] = handle_invd,
8543 [EXIT_REASON_INVLPG] = handle_invlpg,
8544 [EXIT_REASON_RDPMC] = handle_rdpmc,
8545 [EXIT_REASON_VMCALL] = handle_vmcall,
8546 [EXIT_REASON_VMCLEAR] = handle_vmclear,
8547 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
8548 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
8549 [EXIT_REASON_VMPTRST] = handle_vmptrst,
8550 [EXIT_REASON_VMREAD] = handle_vmread,
8551 [EXIT_REASON_VMRESUME] = handle_vmresume,
8552 [EXIT_REASON_VMWRITE] = handle_vmwrite,
8553 [EXIT_REASON_VMOFF] = handle_vmoff,
8554 [EXIT_REASON_VMON] = handle_vmon,
8555 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8556 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
8557 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
8558 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
8559 [EXIT_REASON_WBINVD] = handle_wbinvd,
8560 [EXIT_REASON_XSETBV] = handle_xsetbv,
8561 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
8562 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
8563 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8564 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
8565 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
8566 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
8567 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
8568 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
8569 [EXIT_REASON_INVEPT] = handle_invept,
8570 [EXIT_REASON_INVVPID] = handle_invvpid,
8571 [EXIT_REASON_RDRAND] = handle_invalid_op,
8572 [EXIT_REASON_RDSEED] = handle_invalid_op,
8573 [EXIT_REASON_XSAVES] = handle_xsaves,
8574 [EXIT_REASON_XRSTORS] = handle_xrstors,
8575 [EXIT_REASON_PML_FULL] = handle_pml_full,
8576 [EXIT_REASON_VMFUNC] = handle_vmfunc,
8577 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
8580 static const int kvm_vmx_max_exit_handlers =
8581 ARRAY_SIZE(kvm_vmx_exit_handlers);
8584 * Return true if an IO instruction with the specified port and size should cause
8585 * a VM-exit into L1.
8587 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
8590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8591 gpa_t bitmap, last_bitmap;
8594 last_bitmap = (gpa_t)-1;
8599 bitmap = vmcs12->io_bitmap_a;
8600 else if (port < 0x10000)
8601 bitmap = vmcs12->io_bitmap_b;
8604 bitmap += (port & 0x7fff) / 8;
8606 if (last_bitmap != bitmap)
8607 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8609 if (b & (1 << (port & 7)))
8614 last_bitmap = bitmap;
8621 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8622 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8623 * disinterest in the current event (read or write a specific MSR) by using an
8624 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8626 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8627 struct vmcs12 *vmcs12, u32 exit_reason)
8629 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8632 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8636 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8637 * for the four combinations of read/write and low/high MSR numbers.
8638 * First we need to figure out which of the four to use:
8640 bitmap = vmcs12->msr_bitmap;
8641 if (exit_reason == EXIT_REASON_MSR_WRITE)
8643 if (msr_index >= 0xc0000000) {
8644 msr_index -= 0xc0000000;
8648 /* Then read the msr_index'th bit from this bitmap: */
8649 if (msr_index < 1024*8) {
8651 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8653 return 1 & (b >> (msr_index & 7));
8655 return true; /* let L1 handle the wrong parameter */
8659 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8660 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8661 * intercept (via guest_host_mask etc.) the current event.
8663 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8664 struct vmcs12 *vmcs12)
8666 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8667 int cr = exit_qualification & 15;
8671 switch ((exit_qualification >> 4) & 3) {
8672 case 0: /* mov to cr */
8673 reg = (exit_qualification >> 8) & 15;
8674 val = kvm_register_readl(vcpu, reg);
8677 if (vmcs12->cr0_guest_host_mask &
8678 (val ^ vmcs12->cr0_read_shadow))
8682 if ((vmcs12->cr3_target_count >= 1 &&
8683 vmcs12->cr3_target_value0 == val) ||
8684 (vmcs12->cr3_target_count >= 2 &&
8685 vmcs12->cr3_target_value1 == val) ||
8686 (vmcs12->cr3_target_count >= 3 &&
8687 vmcs12->cr3_target_value2 == val) ||
8688 (vmcs12->cr3_target_count >= 4 &&
8689 vmcs12->cr3_target_value3 == val))
8691 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8695 if (vmcs12->cr4_guest_host_mask &
8696 (vmcs12->cr4_read_shadow ^ val))
8700 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8706 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8707 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8710 case 1: /* mov from cr */
8713 if (vmcs12->cpu_based_vm_exec_control &
8714 CPU_BASED_CR3_STORE_EXITING)
8718 if (vmcs12->cpu_based_vm_exec_control &
8719 CPU_BASED_CR8_STORE_EXITING)
8726 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8727 * cr0. Other attempted changes are ignored, with no exit.
8729 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8730 if (vmcs12->cr0_guest_host_mask & 0xe &
8731 (val ^ vmcs12->cr0_read_shadow))
8733 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8734 !(vmcs12->cr0_read_shadow & 0x1) &&
8743 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8744 * should handle it ourselves in L0 (and then continue L2). Only call this
8745 * when in is_guest_mode (L2).
8747 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8749 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8750 struct vcpu_vmx *vmx = to_vmx(vcpu);
8751 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8753 if (vmx->nested.nested_run_pending)
8756 if (unlikely(vmx->fail)) {
8757 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8758 vmcs_read32(VM_INSTRUCTION_ERROR));
8763 * The host physical addresses of some pages of guest memory
8764 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8765 * Page). The CPU may write to these pages via their host
8766 * physical address while L2 is running, bypassing any
8767 * address-translation-based dirty tracking (e.g. EPT write
8770 * Mark them dirty on every exit from L2 to prevent them from
8771 * getting out of sync with dirty tracking.
8773 nested_mark_vmcs12_pages_dirty(vcpu);
8775 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8776 vmcs_readl(EXIT_QUALIFICATION),
8777 vmx->idt_vectoring_info,
8779 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8782 switch ((u16)exit_reason) {
8783 case EXIT_REASON_EXCEPTION_NMI:
8784 if (is_nmi(intr_info))
8786 else if (is_page_fault(intr_info))
8787 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8788 else if (is_no_device(intr_info) &&
8789 !(vmcs12->guest_cr0 & X86_CR0_TS))
8791 else if (is_debug(intr_info) &&
8793 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8795 else if (is_breakpoint(intr_info) &&
8796 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8798 return vmcs12->exception_bitmap &
8799 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8800 case EXIT_REASON_EXTERNAL_INTERRUPT:
8802 case EXIT_REASON_TRIPLE_FAULT:
8804 case EXIT_REASON_PENDING_INTERRUPT:
8805 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8806 case EXIT_REASON_NMI_WINDOW:
8807 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8808 case EXIT_REASON_TASK_SWITCH:
8810 case EXIT_REASON_CPUID:
8812 case EXIT_REASON_HLT:
8813 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8814 case EXIT_REASON_INVD:
8816 case EXIT_REASON_INVLPG:
8817 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8818 case EXIT_REASON_RDPMC:
8819 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8820 case EXIT_REASON_RDRAND:
8821 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8822 case EXIT_REASON_RDSEED:
8823 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8824 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8825 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8826 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8827 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8828 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8829 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8830 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8831 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8833 * VMX instructions trap unconditionally. This allows L1 to
8834 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8837 case EXIT_REASON_CR_ACCESS:
8838 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8839 case EXIT_REASON_DR_ACCESS:
8840 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8841 case EXIT_REASON_IO_INSTRUCTION:
8842 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8843 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8844 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8845 case EXIT_REASON_MSR_READ:
8846 case EXIT_REASON_MSR_WRITE:
8847 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8848 case EXIT_REASON_INVALID_STATE:
8850 case EXIT_REASON_MWAIT_INSTRUCTION:
8851 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8852 case EXIT_REASON_MONITOR_TRAP_FLAG:
8853 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8854 case EXIT_REASON_MONITOR_INSTRUCTION:
8855 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8856 case EXIT_REASON_PAUSE_INSTRUCTION:
8857 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8858 nested_cpu_has2(vmcs12,
8859 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8860 case EXIT_REASON_MCE_DURING_VMENTRY:
8862 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8863 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8864 case EXIT_REASON_APIC_ACCESS:
8865 return nested_cpu_has2(vmcs12,
8866 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8867 case EXIT_REASON_APIC_WRITE:
8868 case EXIT_REASON_EOI_INDUCED:
8869 /* apic_write and eoi_induced should exit unconditionally. */
8871 case EXIT_REASON_EPT_VIOLATION:
8873 * L0 always deals with the EPT violation. If nested EPT is
8874 * used, and the nested mmu code discovers that the address is
8875 * missing in the guest EPT table (EPT12), the EPT violation
8876 * will be injected with nested_ept_inject_page_fault()
8879 case EXIT_REASON_EPT_MISCONFIG:
8881 * L2 never uses directly L1's EPT, but rather L0's own EPT
8882 * table (shadow on EPT) or a merged EPT table that L0 built
8883 * (EPT on EPT). So any problems with the structure of the
8884 * table is L0's fault.
8887 case EXIT_REASON_INVPCID:
8889 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8890 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8891 case EXIT_REASON_WBINVD:
8892 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8893 case EXIT_REASON_XSETBV:
8895 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8897 * This should never happen, since it is not possible to
8898 * set XSS to a non-zero value---neither in L1 nor in L2.
8899 * If if it were, XSS would have to be checked against
8900 * the XSS exit bitmap in vmcs12.
8902 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8903 case EXIT_REASON_PREEMPTION_TIMER:
8905 case EXIT_REASON_PML_FULL:
8906 /* We emulate PML support to L1. */
8908 case EXIT_REASON_VMFUNC:
8909 /* VM functions are emulated through L2->L0 vmexits. */
8916 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8918 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8921 * At this point, the exit interruption info in exit_intr_info
8922 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8923 * we need to query the in-kernel LAPIC.
8925 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8926 if ((exit_intr_info &
8927 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8928 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8929 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8930 vmcs12->vm_exit_intr_error_code =
8931 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8934 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8935 vmcs_readl(EXIT_QUALIFICATION));
8939 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8941 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8942 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8945 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8948 __free_page(vmx->pml_pg);
8953 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8955 struct vcpu_vmx *vmx = to_vmx(vcpu);
8959 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8961 /* Do nothing if PML buffer is empty */
8962 if (pml_idx == (PML_ENTITY_NUM - 1))
8965 /* PML index always points to next available PML buffer entity */
8966 if (pml_idx >= PML_ENTITY_NUM)
8971 pml_buf = page_address(vmx->pml_pg);
8972 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8975 gpa = pml_buf[pml_idx];
8976 WARN_ON(gpa & (PAGE_SIZE - 1));
8977 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8980 /* reset PML index */
8981 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8985 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8986 * Called before reporting dirty_bitmap to userspace.
8988 static void kvm_flush_pml_buffers(struct kvm *kvm)
8991 struct kvm_vcpu *vcpu;
8993 * We only need to kick vcpu out of guest mode here, as PML buffer
8994 * is flushed at beginning of all VMEXITs, and it's obvious that only
8995 * vcpus running in guest are possible to have unflushed GPAs in PML
8998 kvm_for_each_vcpu(i, vcpu, kvm)
8999 kvm_vcpu_kick(vcpu);
9002 static void vmx_dump_sel(char *name, uint32_t sel)
9004 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9005 name, vmcs_read16(sel),
9006 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9007 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9008 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9011 static void vmx_dump_dtsel(char *name, uint32_t limit)
9013 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9014 name, vmcs_read32(limit),
9015 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9018 static void dump_vmcs(void)
9020 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9021 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9022 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9023 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9024 u32 secondary_exec_control = 0;
9025 unsigned long cr4 = vmcs_readl(GUEST_CR4);
9026 u64 efer = vmcs_read64(GUEST_IA32_EFER);
9029 if (cpu_has_secondary_exec_ctrls())
9030 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9032 pr_err("*** Guest State ***\n");
9033 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9034 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9035 vmcs_readl(CR0_GUEST_HOST_MASK));
9036 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9037 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9038 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9039 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9040 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9042 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9043 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9044 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9045 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9047 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9048 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9049 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9050 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9051 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9052 vmcs_readl(GUEST_SYSENTER_ESP),
9053 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9054 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
9055 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
9056 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
9057 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
9058 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
9059 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
9060 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9061 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9062 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9063 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
9064 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9065 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9066 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9067 efer, vmcs_read64(GUEST_IA32_PAT));
9068 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9069 vmcs_read64(GUEST_IA32_DEBUGCTL),
9070 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9071 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9072 pr_err("PerfGlobCtl = 0x%016llx\n",
9073 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9074 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9075 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9076 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9077 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9078 vmcs_read32(GUEST_ACTIVITY_STATE));
9079 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9080 pr_err("InterruptStatus = %04x\n",
9081 vmcs_read16(GUEST_INTR_STATUS));
9083 pr_err("*** Host State ***\n");
9084 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9085 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9086 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9087 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9088 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9089 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9090 vmcs_read16(HOST_TR_SELECTOR));
9091 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9092 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9093 vmcs_readl(HOST_TR_BASE));
9094 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9095 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9096 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9097 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9098 vmcs_readl(HOST_CR4));
9099 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9100 vmcs_readl(HOST_IA32_SYSENTER_ESP),
9101 vmcs_read32(HOST_IA32_SYSENTER_CS),
9102 vmcs_readl(HOST_IA32_SYSENTER_EIP));
9103 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9104 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9105 vmcs_read64(HOST_IA32_EFER),
9106 vmcs_read64(HOST_IA32_PAT));
9107 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9108 pr_err("PerfGlobCtl = 0x%016llx\n",
9109 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9111 pr_err("*** Control State ***\n");
9112 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9113 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9114 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9115 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9116 vmcs_read32(EXCEPTION_BITMAP),
9117 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9118 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9119 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9120 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9121 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9122 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9123 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9124 vmcs_read32(VM_EXIT_INTR_INFO),
9125 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9126 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9127 pr_err(" reason=%08x qualification=%016lx\n",
9128 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9129 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9130 vmcs_read32(IDT_VECTORING_INFO_FIELD),
9131 vmcs_read32(IDT_VECTORING_ERROR_CODE));
9132 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9133 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9134 pr_err("TSC Multiplier = 0x%016llx\n",
9135 vmcs_read64(TSC_MULTIPLIER));
9136 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9137 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9138 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9139 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9140 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9141 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9142 n = vmcs_read32(CR3_TARGET_COUNT);
9143 for (i = 0; i + 1 < n; i += 4)
9144 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9145 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9146 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9148 pr_err("CR3 target%u=%016lx\n",
9149 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9150 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9151 pr_err("PLE Gap=%08x Window=%08x\n",
9152 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9153 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9154 pr_err("Virtual processor ID = 0x%04x\n",
9155 vmcs_read16(VIRTUAL_PROCESSOR_ID));
9159 * The guest has exited. See if we can fix it or if we need userspace
9162 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9164 struct vcpu_vmx *vmx = to_vmx(vcpu);
9165 u32 exit_reason = vmx->exit_reason;
9166 u32 vectoring_info = vmx->idt_vectoring_info;
9168 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9171 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9172 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9173 * querying dirty_bitmap, we only need to kick all vcpus out of guest
9174 * mode as if vcpus is in root mode, the PML buffer must has been
9178 vmx_flush_pml_buffer(vcpu);
9180 /* If guest state is invalid, start emulating */
9181 if (vmx->emulation_required)
9182 return handle_invalid_guest_state(vcpu);
9184 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9185 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9187 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9189 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9190 vcpu->run->fail_entry.hardware_entry_failure_reason
9195 if (unlikely(vmx->fail)) {
9196 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9197 vcpu->run->fail_entry.hardware_entry_failure_reason
9198 = vmcs_read32(VM_INSTRUCTION_ERROR);
9204 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9205 * delivery event since it indicates guest is accessing MMIO.
9206 * The vm-exit can be triggered again after return to guest that
9207 * will cause infinite loop.
9209 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9210 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9211 exit_reason != EXIT_REASON_EPT_VIOLATION &&
9212 exit_reason != EXIT_REASON_PML_FULL &&
9213 exit_reason != EXIT_REASON_APIC_ACCESS &&
9214 exit_reason != EXIT_REASON_TASK_SWITCH)) {
9215 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9216 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9217 vcpu->run->internal.ndata = 3;
9218 vcpu->run->internal.data[0] = vectoring_info;
9219 vcpu->run->internal.data[1] = exit_reason;
9220 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9221 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9222 vcpu->run->internal.ndata++;
9223 vcpu->run->internal.data[3] =
9224 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9229 if (unlikely(!cpu_has_virtual_nmis() &&
9230 vmx->loaded_vmcs->soft_vnmi_blocked)) {
9231 if (vmx_interrupt_allowed(vcpu)) {
9232 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9233 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9234 vcpu->arch.nmi_pending) {
9236 * This CPU don't support us in finding the end of an
9237 * NMI-blocked window if the guest runs with IRQs
9238 * disabled. So we pull the trigger after 1 s of
9239 * futile waiting, but inform the user about this.
9241 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9242 "state on VCPU %d after 1 s timeout\n",
9243 __func__, vcpu->vcpu_id);
9244 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9248 if (exit_reason < kvm_vmx_max_exit_handlers
9249 && kvm_vmx_exit_handlers[exit_reason])
9250 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9252 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9254 kvm_queue_exception(vcpu, UD_VECTOR);
9260 * Software based L1D cache flush which is used when microcode providing
9261 * the cache control MSR is not loaded.
9263 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
9264 * flush it is required to read in 64 KiB because the replacement algorithm
9265 * is not exactly LRU. This could be sized at runtime via topology
9266 * information but as all relevant affected CPUs have 32KiB L1D cache size
9267 * there is no point in doing so.
9269 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
9271 int size = PAGE_SIZE << L1D_CACHE_ORDER;
9274 * This code is only executed when the the flush mode is 'cond' or
9277 if (static_branch_likely(&vmx_l1d_flush_cond)) {
9281 * Clear the per-vcpu flush bit, it gets set again
9282 * either from vcpu_run() or from one of the unsafe
9285 flush_l1d = vcpu->arch.l1tf_flush_l1d;
9286 vcpu->arch.l1tf_flush_l1d = false;
9289 * Clear the per-cpu flush bit, it gets set again from
9290 * the interrupt handlers.
9292 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
9293 kvm_clear_cpu_l1tf_flush_l1d();
9299 vcpu->stat.l1d_flush++;
9301 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
9302 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
9307 /* First ensure the pages are in the TLB */
9308 "xorl %%eax, %%eax\n"
9309 ".Lpopulate_tlb:\n\t"
9310 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
9311 "addl $4096, %%eax\n\t"
9312 "cmpl %%eax, %[size]\n\t"
9313 "jne .Lpopulate_tlb\n\t"
9314 "xorl %%eax, %%eax\n\t"
9316 /* Now fill the cache */
9317 "xorl %%eax, %%eax\n"
9319 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
9320 "addl $64, %%eax\n\t"
9321 "cmpl %%eax, %[size]\n\t"
9322 "jne .Lfill_cache\n\t"
9324 :: [flush_pages] "r" (vmx_l1d_flush_pages),
9326 : "eax", "ebx", "ecx", "edx");
9329 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9331 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9333 if (is_guest_mode(vcpu) &&
9334 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9337 if (irr == -1 || tpr < irr) {
9338 vmcs_write32(TPR_THRESHOLD, 0);
9342 vmcs_write32(TPR_THRESHOLD, irr);
9345 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
9347 u32 sec_exec_control;
9349 if (!lapic_in_kernel(vcpu))
9352 if (!flexpriority_enabled &&
9353 !cpu_has_vmx_virtualize_x2apic_mode())
9356 /* Postpone execution until vmcs01 is the current VMCS. */
9357 if (is_guest_mode(vcpu)) {
9358 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
9362 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9363 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9364 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
9366 switch (kvm_get_apic_mode(vcpu)) {
9367 case LAPIC_MODE_INVALID:
9368 WARN_ONCE(true, "Invalid local APIC state");
9369 case LAPIC_MODE_DISABLED:
9371 case LAPIC_MODE_XAPIC:
9372 if (flexpriority_enabled) {
9374 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9375 vmx_flush_tlb(vcpu, true);
9378 case LAPIC_MODE_X2APIC:
9379 if (cpu_has_vmx_virtualize_x2apic_mode())
9381 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9384 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9386 vmx_update_msr_bitmap(vcpu);
9389 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9391 struct vcpu_vmx *vmx = to_vmx(vcpu);
9394 * Currently we do not handle the nested case where L2 has an
9395 * APIC access page of its own; that page is still pinned.
9396 * Hence, we skip the case where the VCPU is in guest mode _and_
9397 * L1 prepared an APIC access page for L2.
9399 * For the case where L1 and L2 share the same APIC access page
9400 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9401 * in the vmcs12), this function will only update either the vmcs01
9402 * or the vmcs02. If the former, the vmcs02 will be updated by
9403 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
9404 * the next L2->L1 exit.
9406 if (!is_guest_mode(vcpu) ||
9407 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9408 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9409 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9410 vmx_flush_tlb(vcpu, true);
9414 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9422 status = vmcs_read16(GUEST_INTR_STATUS);
9424 if (max_isr != old) {
9426 status |= max_isr << 8;
9427 vmcs_write16(GUEST_INTR_STATUS, status);
9431 static void vmx_set_rvi(int vector)
9439 status = vmcs_read16(GUEST_INTR_STATUS);
9440 old = (u8)status & 0xff;
9441 if ((u8)vector != old) {
9443 status |= (u8)vector;
9444 vmcs_write16(GUEST_INTR_STATUS, status);
9448 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9450 if (!is_guest_mode(vcpu)) {
9451 vmx_set_rvi(max_irr);
9459 * In guest mode. If a vmexit is needed, vmx_check_nested_events
9462 if (nested_exit_on_intr(vcpu))
9466 * Else, fall back to pre-APICv interrupt injection since L2
9467 * is run without virtual interrupt delivery.
9469 if (!kvm_event_needs_reinjection(vcpu) &&
9470 vmx_interrupt_allowed(vcpu)) {
9471 kvm_queue_interrupt(vcpu, max_irr, false);
9472 vmx_inject_irq(vcpu);
9476 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9478 struct vcpu_vmx *vmx = to_vmx(vcpu);
9481 WARN_ON(!vcpu->arch.apicv_active);
9482 if (pi_test_on(&vmx->pi_desc)) {
9483 pi_clear_on(&vmx->pi_desc);
9485 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9486 * But on x86 this is just a compiler barrier anyway.
9488 smp_mb__after_atomic();
9489 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
9491 max_irr = kvm_lapic_find_highest_irr(vcpu);
9493 vmx_hwapic_irr_update(vcpu, max_irr);
9497 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
9499 return pi_test_on(vcpu_to_pi_desc(vcpu));
9502 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9504 if (!kvm_vcpu_apicv_active(vcpu))
9507 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9508 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9509 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9510 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9513 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9515 struct vcpu_vmx *vmx = to_vmx(vcpu);
9517 pi_clear_on(&vmx->pi_desc);
9518 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9521 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9523 u32 exit_intr_info = 0;
9524 u16 basic_exit_reason = (u16)vmx->exit_reason;
9526 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9527 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9530 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9531 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9532 vmx->exit_intr_info = exit_intr_info;
9534 /* if exit due to PF check for async PF */
9535 if (is_page_fault(exit_intr_info))
9536 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9538 /* Handle machine checks before interrupts are enabled */
9539 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9540 is_machine_check(exit_intr_info))
9541 kvm_machine_check();
9543 /* We need to handle NMIs before interrupts are enabled */
9544 if (is_nmi(exit_intr_info)) {
9545 kvm_before_handle_nmi(&vmx->vcpu);
9547 kvm_after_handle_nmi(&vmx->vcpu);
9551 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9553 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9555 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9556 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9557 unsigned int vector;
9558 unsigned long entry;
9560 struct vcpu_vmx *vmx = to_vmx(vcpu);
9561 #ifdef CONFIG_X86_64
9565 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9566 desc = (gate_desc *)vmx->host_idt_base + vector;
9567 entry = gate_offset(desc);
9569 #ifdef CONFIG_X86_64
9570 "mov %%" _ASM_SP ", %[sp]\n\t"
9571 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9576 __ASM_SIZE(push) " $%c[cs]\n\t"
9579 #ifdef CONFIG_X86_64
9584 THUNK_TARGET(entry),
9585 [ss]"i"(__KERNEL_DS),
9586 [cs]"i"(__KERNEL_CS)
9590 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9592 static bool vmx_has_emulated_msr(int index)
9595 case MSR_IA32_SMBASE:
9597 * We cannot do SMM unless we can run the guest in big
9600 return enable_unrestricted_guest || emulate_invalid_guest_state;
9601 case MSR_AMD64_VIRT_SPEC_CTRL:
9602 /* This is AMD only. */
9609 static bool vmx_mpx_supported(void)
9611 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9612 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9615 static bool vmx_xsaves_supported(void)
9617 return vmcs_config.cpu_based_2nd_exec_ctrl &
9618 SECONDARY_EXEC_XSAVES;
9621 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9626 bool idtv_info_valid;
9628 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9630 if (cpu_has_virtual_nmis()) {
9631 if (vmx->loaded_vmcs->nmi_known_unmasked)
9634 * Can't use vmx->exit_intr_info since we're not sure what
9635 * the exit reason is.
9637 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9638 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9639 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9641 * SDM 3: 27.7.1.2 (September 2008)
9642 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9643 * a guest IRET fault.
9644 * SDM 3: 23.2.2 (September 2008)
9645 * Bit 12 is undefined in any of the following cases:
9646 * If the VM exit sets the valid bit in the IDT-vectoring
9647 * information field.
9648 * If the VM exit is due to a double fault.
9650 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9651 vector != DF_VECTOR && !idtv_info_valid)
9652 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9653 GUEST_INTR_STATE_NMI);
9655 vmx->loaded_vmcs->nmi_known_unmasked =
9656 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9657 & GUEST_INTR_STATE_NMI);
9658 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9659 vmx->loaded_vmcs->vnmi_blocked_time +=
9660 ktime_to_ns(ktime_sub(ktime_get(),
9661 vmx->loaded_vmcs->entry_time));
9664 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9665 u32 idt_vectoring_info,
9666 int instr_len_field,
9667 int error_code_field)
9671 bool idtv_info_valid;
9673 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9675 vcpu->arch.nmi_injected = false;
9676 kvm_clear_exception_queue(vcpu);
9677 kvm_clear_interrupt_queue(vcpu);
9679 if (!idtv_info_valid)
9682 kvm_make_request(KVM_REQ_EVENT, vcpu);
9684 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9685 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9688 case INTR_TYPE_NMI_INTR:
9689 vcpu->arch.nmi_injected = true;
9691 * SDM 3: 27.7.1.2 (September 2008)
9692 * Clear bit "block by NMI" before VM entry if a NMI
9695 vmx_set_nmi_mask(vcpu, false);
9697 case INTR_TYPE_SOFT_EXCEPTION:
9698 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9700 case INTR_TYPE_HARD_EXCEPTION:
9701 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9702 u32 err = vmcs_read32(error_code_field);
9703 kvm_requeue_exception_e(vcpu, vector, err);
9705 kvm_requeue_exception(vcpu, vector);
9707 case INTR_TYPE_SOFT_INTR:
9708 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9710 case INTR_TYPE_EXT_INTR:
9711 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9718 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9720 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9721 VM_EXIT_INSTRUCTION_LEN,
9722 IDT_VECTORING_ERROR_CODE);
9725 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9727 __vmx_complete_interrupts(vcpu,
9728 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9729 VM_ENTRY_INSTRUCTION_LEN,
9730 VM_ENTRY_EXCEPTION_ERROR_CODE);
9732 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9735 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9738 struct perf_guest_switch_msr *msrs;
9740 msrs = perf_guest_get_msrs(&nr_msrs);
9745 for (i = 0; i < nr_msrs; i++)
9746 if (msrs[i].host == msrs[i].guest)
9747 clear_atomic_switch_msr(vmx, msrs[i].msr);
9749 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9750 msrs[i].host, false);
9753 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9755 struct vcpu_vmx *vmx = to_vmx(vcpu);
9759 if (vmx->hv_deadline_tsc == -1)
9763 if (vmx->hv_deadline_tsc > tscl)
9764 /* sure to be 32 bit only because checked on set_hv_timer */
9765 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9766 cpu_preemption_timer_multi);
9770 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9773 u64 __always_inline vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx)
9775 u64 guestval, hostval = this_cpu_read(x86_spec_ctrl_current);
9777 if (!cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL))
9780 guestval = __rdmsr(MSR_IA32_SPEC_CTRL);
9783 * If the guest/host SPEC_CTRL values differ, restore the host value.
9785 * For legacy IBRS, the IBRS bit always needs to be written after
9786 * transitioning from a less privileged predictor mode, regardless of
9787 * whether the guest/host values differ.
9789 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) ||
9790 guestval != hostval)
9791 native_wrmsrl(MSR_IA32_SPEC_CTRL, hostval);
9798 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9800 struct vcpu_vmx *vmx = to_vmx(vcpu);
9801 unsigned long debugctlmsr, cr3, cr4;
9804 /* Record the guest's net vcpu time for enforced NMI injections. */
9805 if (unlikely(!cpu_has_virtual_nmis() &&
9806 vmx->loaded_vmcs->soft_vnmi_blocked))
9807 vmx->loaded_vmcs->entry_time = ktime_get();
9809 /* Don't enter VMX if guest state is invalid, let the exit handler
9810 start emulation until we arrive back to a valid state */
9811 if (vmx->emulation_required)
9814 if (vmx->ple_window_dirty) {
9815 vmx->ple_window_dirty = false;
9816 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9819 if (vmx->nested.sync_shadow_vmcs) {
9820 copy_vmcs12_to_shadow(vmx);
9821 vmx->nested.sync_shadow_vmcs = false;
9824 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9825 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9826 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9827 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9829 cr3 = __get_current_cr3_fast();
9830 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9831 vmcs_writel(HOST_CR3, cr3);
9832 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9835 cr4 = cr4_read_shadow();
9836 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9837 vmcs_writel(HOST_CR4, cr4);
9838 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9841 /* When single-stepping over STI and MOV SS, we must clear the
9842 * corresponding interruptibility bits in the guest state. Otherwise
9843 * vmentry fails as it then expects bit 14 (BS) in pending debug
9844 * exceptions being set, but that's not correct for the guest debugging
9846 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9847 vmx_set_interrupt_shadow(vcpu, 0);
9849 if (static_cpu_has(X86_FEATURE_PKU) &&
9850 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9851 vcpu->arch.pkru != vmx->host_pkru)
9852 __write_pkru(vcpu->arch.pkru);
9854 atomic_switch_perf_msrs(vmx);
9855 debugctlmsr = get_debugctlmsr();
9857 vmx_arm_hv_timer(vcpu);
9860 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9861 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9862 * is no need to worry about the conditional branch over the wrmsr
9863 * being speculatively taken.
9865 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
9867 vmx->__launched = vmx->loaded_vmcs->launched;
9869 /* L1D Flush includes CPU buffer clear to mitigate MDS */
9870 if (static_branch_unlikely(&vmx_l1d_should_flush))
9871 vmx_l1d_flush(vcpu);
9872 else if (static_branch_unlikely(&mds_user_clear))
9873 mds_clear_cpu_buffers();
9874 else if (static_branch_unlikely(&mmio_stale_data_clear) &&
9875 kvm_arch_has_assigned_device(vcpu->kvm))
9876 mds_clear_cpu_buffers();
9878 vmx_disable_fb_clear(vmx);
9881 /* Store host registers */
9882 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9883 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9884 "push %%" _ASM_CX " \n\t"
9885 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9887 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9888 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9890 /* Reload cr2 if changed */
9891 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9892 "mov %%cr2, %%" _ASM_DX " \n\t"
9893 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9895 "mov %%" _ASM_AX", %%cr2 \n\t"
9897 /* Check if vmlaunch of vmresume is needed */
9898 "cmpl $0, %c[launched](%0) \n\t"
9899 /* Load guest registers. Don't clobber flags. */
9900 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9901 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9902 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9903 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9904 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9905 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9906 #ifdef CONFIG_X86_64
9907 "mov %c[r8](%0), %%r8 \n\t"
9908 "mov %c[r9](%0), %%r9 \n\t"
9909 "mov %c[r10](%0), %%r10 \n\t"
9910 "mov %c[r11](%0), %%r11 \n\t"
9911 "mov %c[r12](%0), %%r12 \n\t"
9912 "mov %c[r13](%0), %%r13 \n\t"
9913 "mov %c[r14](%0), %%r14 \n\t"
9914 "mov %c[r15](%0), %%r15 \n\t"
9916 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9918 /* Enter guest mode */
9920 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9922 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9924 /* Save guest registers, load host registers, keep flags */
9925 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9927 "setbe %c[fail](%0)\n\t"
9928 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9929 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9930 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9931 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9932 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9933 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9934 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9935 #ifdef CONFIG_X86_64
9936 "mov %%r8, %c[r8](%0) \n\t"
9937 "mov %%r9, %c[r9](%0) \n\t"
9938 "mov %%r10, %c[r10](%0) \n\t"
9939 "mov %%r11, %c[r11](%0) \n\t"
9940 "mov %%r12, %c[r12](%0) \n\t"
9941 "mov %%r13, %c[r13](%0) \n\t"
9942 "mov %%r14, %c[r14](%0) \n\t"
9943 "mov %%r15, %c[r15](%0) \n\t"
9944 "xor %%r8d, %%r8d \n\t"
9945 "xor %%r9d, %%r9d \n\t"
9946 "xor %%r10d, %%r10d \n\t"
9947 "xor %%r11d, %%r11d \n\t"
9948 "xor %%r12d, %%r12d \n\t"
9949 "xor %%r13d, %%r13d \n\t"
9950 "xor %%r14d, %%r14d \n\t"
9951 "xor %%r15d, %%r15d \n\t"
9953 "mov %%cr2, %%" _ASM_AX " \n\t"
9954 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9956 "xor %%eax, %%eax \n\t"
9957 "xor %%ebx, %%ebx \n\t"
9958 "xor %%esi, %%esi \n\t"
9959 "xor %%edi, %%edi \n\t"
9960 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
9961 ".pushsection .rodata \n\t"
9962 ".global vmx_return \n\t"
9963 "vmx_return: " _ASM_PTR " 2b \n\t"
9965 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9966 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9967 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9968 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9969 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9970 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9971 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9972 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9973 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9974 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9975 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9976 #ifdef CONFIG_X86_64
9977 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9978 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9979 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9980 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9981 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9982 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9983 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9984 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9986 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9987 [wordsize]"i"(sizeof(ulong))
9989 #ifdef CONFIG_X86_64
9990 , "rax", "rbx", "rdi", "rsi"
9991 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9993 , "eax", "ebx", "edi", "esi"
9997 * IMPORTANT: RSB filling and SPEC_CTRL handling must be done before
9998 * the first unbalanced RET after vmexit!
10000 * For retpoline or IBRS, RSB filling is needed to prevent poisoned RSB
10001 * entries and (in some cases) RSB underflow.
10003 * eIBRS has its own protection against poisoned RSB, so it doesn't
10004 * need the RSB filling sequence. But it does need to be enabled, and a
10005 * single call to retire, before the first unbalanced RET.
10007 * So no RETs before vmx_spec_ctrl_restore_host() below.
10011 /* Save this for below */
10012 spec_ctrl = vmx_spec_ctrl_restore_host(vmx);
10014 vmx_enable_fb_clear(vmx);
10017 * We do not use IBRS in the kernel. If this vCPU has used the
10018 * SPEC_CTRL MSR it may have left it on; save the value and
10019 * turn it off. This is much more efficient than blindly adding
10020 * it to the atomic save/restore list. Especially as the former
10021 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10023 * For non-nested case:
10024 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10028 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10031 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10032 vmx->spec_ctrl = spec_ctrl;
10034 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10036 update_debugctlmsr(debugctlmsr);
10038 #ifndef CONFIG_X86_64
10040 * The sysexit path does not restore ds/es, so we must set them to
10041 * a reasonable value ourselves.
10043 * We can't defer this to vmx_load_host_state() since that function
10044 * may be executed in interrupt context, which saves and restore segments
10045 * around it, nullifying its effect.
10047 loadsegment(ds, __USER_DS);
10048 loadsegment(es, __USER_DS);
10051 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10052 | (1 << VCPU_EXREG_RFLAGS)
10053 | (1 << VCPU_EXREG_PDPTR)
10054 | (1 << VCPU_EXREG_SEGMENTS)
10055 | (1 << VCPU_EXREG_CR3));
10056 vcpu->arch.regs_dirty = 0;
10059 * eager fpu is enabled if PKEY is supported and CR4 is switched
10060 * back on host, so it is safe to read guest PKRU from current
10063 if (static_cpu_has(X86_FEATURE_PKU) &&
10064 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10065 vcpu->arch.pkru = __read_pkru();
10066 if (vcpu->arch.pkru != vmx->host_pkru)
10067 __write_pkru(vmx->host_pkru);
10071 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
10072 * we did not inject a still-pending event to L1 now because of
10073 * nested_run_pending, we need to re-enable this bit.
10075 if (vmx->nested.nested_run_pending)
10076 kvm_make_request(KVM_REQ_EVENT, vcpu);
10078 vmx->nested.nested_run_pending = 0;
10079 vmx->idt_vectoring_info = 0;
10081 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10082 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10085 vmx->loaded_vmcs->launched = 1;
10086 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10088 vmx_complete_atomic_exit(vmx);
10089 vmx_recover_nmi_blocking(vmx);
10090 vmx_complete_interrupts(vmx);
10092 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10094 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10096 struct vcpu_vmx *vmx = to_vmx(vcpu);
10099 if (vmx->loaded_vmcs == vmcs)
10103 vmx_vcpu_put(vcpu);
10104 vmx->loaded_vmcs = vmcs;
10105 vmx_vcpu_load(vcpu, cpu);
10111 * Ensure that the current vmcs of the logical processor is the
10112 * vmcs01 of the vcpu before calling free_nested().
10114 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10116 struct vcpu_vmx *vmx = to_vmx(vcpu);
10119 r = vcpu_load(vcpu);
10121 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10126 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10128 struct vcpu_vmx *vmx = to_vmx(vcpu);
10131 vmx_destroy_pml_buffer(vmx);
10132 free_vpid(vmx->vpid);
10133 leave_guest_mode(vcpu);
10134 vmx_free_vcpu_nested(vcpu);
10135 free_loaded_vmcs(vmx->loaded_vmcs);
10136 kfree(vmx->guest_msrs);
10137 kvm_vcpu_uninit(vcpu);
10138 kmem_cache_free(kvm_vcpu_cache, vmx);
10141 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10144 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10145 unsigned long *msr_bitmap;
10149 return ERR_PTR(-ENOMEM);
10151 vmx->vpid = allocate_vpid();
10153 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10160 * If PML is turned on, failure on enabling PML just results in failure
10161 * of creating the vcpu, therefore we can simplify PML logic (by
10162 * avoiding dealing with cases, such as enabling PML partially on vcpus
10163 * for the guest, etc.
10166 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10171 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10172 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10175 if (!vmx->guest_msrs)
10178 err = alloc_loaded_vmcs(&vmx->vmcs01);
10182 msr_bitmap = vmx->vmcs01.msr_bitmap;
10183 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10184 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10185 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10186 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10187 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10188 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10189 vmx->msr_bitmap_mode = 0;
10191 vmx->loaded_vmcs = &vmx->vmcs01;
10193 vmx_vcpu_load(&vmx->vcpu, cpu);
10194 vmx->vcpu.cpu = cpu;
10195 err = vmx_vcpu_setup(vmx);
10196 vmx_vcpu_put(&vmx->vcpu);
10200 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10201 err = alloc_apic_access_page(kvm);
10207 if (!kvm->arch.ept_identity_map_addr)
10208 kvm->arch.ept_identity_map_addr =
10209 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
10210 err = init_rmode_identity_map(kvm);
10216 nested_vmx_setup_ctls_msrs(vmx);
10218 vmx->nested.posted_intr_nv = -1;
10219 vmx->nested.current_vmptr = -1ull;
10221 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10224 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10225 * or POSTED_INTR_WAKEUP_VECTOR.
10227 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10228 vmx->pi_desc.sn = 1;
10233 free_loaded_vmcs(vmx->loaded_vmcs);
10235 kfree(vmx->guest_msrs);
10237 vmx_destroy_pml_buffer(vmx);
10239 kvm_vcpu_uninit(&vmx->vcpu);
10241 free_vpid(vmx->vpid);
10242 kmem_cache_free(kvm_vcpu_cache, vmx);
10243 return ERR_PTR(err);
10246 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
10247 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
10249 static int vmx_vm_init(struct kvm *kvm)
10251 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
10252 switch (l1tf_mitigation) {
10253 case L1TF_MITIGATION_OFF:
10254 case L1TF_MITIGATION_FLUSH_NOWARN:
10255 /* 'I explicitly don't care' is set */
10257 case L1TF_MITIGATION_FLUSH:
10258 case L1TF_MITIGATION_FLUSH_NOSMT:
10259 case L1TF_MITIGATION_FULL:
10261 * Warn upon starting the first VM in a potentially
10262 * insecure environment.
10264 if (sched_smt_active())
10265 pr_warn_once(L1TF_MSG_SMT);
10266 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
10267 pr_warn_once(L1TF_MSG_L1D);
10269 case L1TF_MITIGATION_FULL_FORCE:
10270 /* Flush is enforced */
10277 static void __init vmx_check_processor_compat(void *rtn)
10279 struct vmcs_config vmcs_conf;
10282 if (setup_vmcs_config(&vmcs_conf) < 0)
10283 *(int *)rtn = -EIO;
10284 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10285 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10286 smp_processor_id());
10287 *(int *)rtn = -EIO;
10291 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10296 /* For VT-d and EPT combination
10297 * 1. MMIO: always map as UC
10298 * 2. EPT with VT-d:
10299 * a. VT-d without snooping control feature: can't guarantee the
10300 * result, try to trust guest.
10301 * b. VT-d with snooping control feature: snooping control feature of
10302 * VT-d engine can guarantee the cache correctness. Just set it
10303 * to WB to keep consistent with host. So the same as item 3.
10304 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10305 * consistent with host MTRR
10308 cache = MTRR_TYPE_UNCACHABLE;
10312 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10313 ipat = VMX_EPT_IPAT_BIT;
10314 cache = MTRR_TYPE_WRBACK;
10318 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10319 ipat = VMX_EPT_IPAT_BIT;
10320 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10321 cache = MTRR_TYPE_WRBACK;
10323 cache = MTRR_TYPE_UNCACHABLE;
10327 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10330 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10333 static int vmx_get_lpage_level(void)
10335 if (enable_ept && !cpu_has_vmx_ept_1g_page())
10336 return PT_DIRECTORY_LEVEL;
10338 /* For shadow and EPT supported 1GB page */
10339 return PT_PDPE_LEVEL;
10342 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10345 * These bits in the secondary execution controls field
10346 * are dynamic, the others are mostly based on the hypervisor
10347 * architecture and the guest's CPUID. Do not touch the
10351 SECONDARY_EXEC_SHADOW_VMCS |
10352 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10353 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10355 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10357 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10358 (new_ctl & ~mask) | (cur_ctl & mask));
10362 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10363 * (indicating "allowed-1") if they are supported in the guest's CPUID.
10365 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10367 struct vcpu_vmx *vmx = to_vmx(vcpu);
10368 struct kvm_cpuid_entry2 *entry;
10370 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
10371 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
10373 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
10374 if (entry && (entry->_reg & (_cpuid_mask))) \
10375 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
10378 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10379 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
10380 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
10381 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
10382 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
10383 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
10384 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
10385 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
10386 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
10387 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
10388 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10389 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
10390 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
10391 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
10392 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
10394 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10395 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
10396 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
10397 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
10398 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
10399 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
10400 cr4_fixed1_update(bit(11), ecx, bit(2));
10402 #undef cr4_fixed1_update
10405 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10407 struct vcpu_vmx *vmx = to_vmx(vcpu);
10409 if (cpu_has_secondary_exec_ctrls()) {
10410 vmx_compute_secondary_exec_control(vmx);
10411 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10414 if (nested_vmx_allowed(vcpu))
10415 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10416 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10418 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10419 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10421 if (nested_vmx_allowed(vcpu))
10422 nested_vmx_cr_fixed1_bits_update(vcpu);
10425 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10427 if (func == 1 && nested)
10428 entry->ecx |= bit(X86_FEATURE_VMX);
10431 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10432 struct x86_exception *fault)
10434 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10435 struct vcpu_vmx *vmx = to_vmx(vcpu);
10437 unsigned long exit_qualification = vcpu->arch.exit_qualification;
10439 if (vmx->nested.pml_full) {
10440 exit_reason = EXIT_REASON_PML_FULL;
10441 vmx->nested.pml_full = false;
10442 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10443 } else if (fault->error_code & PFERR_RSVD_MASK)
10444 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10446 exit_reason = EXIT_REASON_EPT_VIOLATION;
10448 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10449 vmcs12->guest_physical_address = fault->address;
10452 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10454 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10457 /* Callbacks for nested_ept_init_mmu_context: */
10459 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10461 /* return the page table to be shadowed - in our case, EPT12 */
10462 return get_vmcs12(vcpu)->ept_pointer;
10465 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10467 WARN_ON(mmu_is_nested(vcpu));
10468 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10471 kvm_mmu_unload(vcpu);
10472 kvm_init_shadow_ept_mmu(vcpu,
10473 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
10474 VMX_EPT_EXECUTE_ONLY_BIT,
10475 nested_ept_ad_enabled(vcpu));
10476 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
10477 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
10478 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10480 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
10484 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10486 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10489 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10492 bool inequality, bit;
10494 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10496 (error_code & vmcs12->page_fault_error_code_mask) !=
10497 vmcs12->page_fault_error_code_match;
10498 return inequality ^ bit;
10501 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10502 struct x86_exception *fault)
10504 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10506 WARN_ON(!is_guest_mode(vcpu));
10508 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10509 !to_vmx(vcpu)->nested.nested_run_pending) {
10510 vmcs12->vm_exit_intr_error_code = fault->error_code;
10511 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10512 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10513 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10516 kvm_inject_page_fault(vcpu, fault);
10520 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10521 struct vmcs12 *vmcs12);
10523 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10524 struct vmcs12 *vmcs12)
10526 struct vcpu_vmx *vmx = to_vmx(vcpu);
10530 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10532 * Translate L1 physical address to host physical
10533 * address for vmcs02. Keep the page pinned, so this
10534 * physical address remains valid. We keep a reference
10535 * to it so we can release it later.
10537 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10538 kvm_release_page_dirty(vmx->nested.apic_access_page);
10539 vmx->nested.apic_access_page = NULL;
10541 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10543 * If translation failed, no matter: This feature asks
10544 * to exit when accessing the given address, and if it
10545 * can never be accessed, this feature won't do
10548 if (!is_error_page(page)) {
10549 vmx->nested.apic_access_page = page;
10550 hpa = page_to_phys(vmx->nested.apic_access_page);
10551 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10553 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10554 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10556 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10557 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10558 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10559 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10560 kvm_vcpu_reload_apic_access_page(vcpu);
10563 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10564 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10565 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10566 vmx->nested.virtual_apic_page = NULL;
10568 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10571 * If translation failed, VM entry will fail because
10572 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10573 * Failing the vm entry is _not_ what the processor
10574 * does but it's basically the only possibility we
10575 * have. We could still enter the guest if CR8 load
10576 * exits are enabled, CR8 store exits are enabled, and
10577 * virtualize APIC access is disabled; in this case
10578 * the processor would never use the TPR shadow and we
10579 * could simply clear the bit from the execution
10580 * control. But such a configuration is useless, so
10581 * let's keep the code simple.
10583 if (!is_error_page(page)) {
10584 vmx->nested.virtual_apic_page = page;
10585 hpa = page_to_phys(vmx->nested.virtual_apic_page);
10586 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10590 if (nested_cpu_has_posted_intr(vmcs12)) {
10591 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10592 kunmap(vmx->nested.pi_desc_page);
10593 kvm_release_page_dirty(vmx->nested.pi_desc_page);
10594 vmx->nested.pi_desc_page = NULL;
10595 vmx->nested.pi_desc = NULL;
10596 vmcs_write64(POSTED_INTR_DESC_ADDR, -1ull);
10598 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10599 if (is_error_page(page))
10601 vmx->nested.pi_desc_page = page;
10602 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10603 vmx->nested.pi_desc =
10604 (struct pi_desc *)((void *)vmx->nested.pi_desc +
10605 (unsigned long)(vmcs12->posted_intr_desc_addr &
10607 vmcs_write64(POSTED_INTR_DESC_ADDR,
10608 page_to_phys(vmx->nested.pi_desc_page) +
10609 (unsigned long)(vmcs12->posted_intr_desc_addr &
10612 if (cpu_has_vmx_msr_bitmap() &&
10613 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
10614 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10615 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10616 CPU_BASED_USE_MSR_BITMAPS);
10618 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10619 CPU_BASED_USE_MSR_BITMAPS);
10622 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10624 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10625 struct vcpu_vmx *vmx = to_vmx(vcpu);
10627 if (vcpu->arch.virtual_tsc_khz == 0)
10630 /* Make sure short timeouts reliably trigger an immediate vmexit.
10631 * hrtimer_start does not guarantee this. */
10632 if (preemption_timeout <= 1) {
10633 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10637 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10638 preemption_timeout *= 1000000;
10639 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10640 hrtimer_start(&vmx->nested.preemption_timer,
10641 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10644 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10645 struct vmcs12 *vmcs12)
10647 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10650 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10651 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10657 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10658 struct vmcs12 *vmcs12)
10660 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10663 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10669 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10670 struct vmcs12 *vmcs12)
10672 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10675 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10682 * Merge L0's and L1's MSR bitmap, return false to indicate that
10683 * we do not use the hardware.
10685 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10686 struct vmcs12 *vmcs12)
10690 unsigned long *msr_bitmap_l1;
10691 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10693 * pred_cmd & spec_ctrl are trying to verify two things:
10695 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10696 * ensures that we do not accidentally generate an L02 MSR bitmap
10697 * from the L12 MSR bitmap that is too permissive.
10698 * 2. That L1 or L2s have actually used the MSR. This avoids
10699 * unnecessarily merging of the bitmap if the MSR is unused. This
10700 * works properly because we only update the L01 MSR bitmap lazily.
10701 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10702 * updated to reflect this when L1 (or its L2s) actually write to
10705 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10706 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10708 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10709 !pred_cmd && !spec_ctrl)
10712 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10713 if (is_error_page(page))
10715 msr_bitmap_l1 = (unsigned long *)kmap(page);
10717 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
10719 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
10720 if (nested_cpu_has_apic_reg_virt(vmcs12))
10721 for (msr = 0x800; msr <= 0x8ff; msr++)
10722 nested_vmx_disable_intercept_for_msr(
10723 msr_bitmap_l1, msr_bitmap_l0,
10726 nested_vmx_disable_intercept_for_msr(
10727 msr_bitmap_l1, msr_bitmap_l0,
10728 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
10729 MSR_TYPE_R | MSR_TYPE_W);
10731 if (nested_cpu_has_vid(vmcs12)) {
10732 nested_vmx_disable_intercept_for_msr(
10733 msr_bitmap_l1, msr_bitmap_l0,
10734 APIC_BASE_MSR + (APIC_EOI >> 4),
10736 nested_vmx_disable_intercept_for_msr(
10737 msr_bitmap_l1, msr_bitmap_l0,
10738 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
10744 nested_vmx_disable_intercept_for_msr(
10745 msr_bitmap_l1, msr_bitmap_l0,
10746 MSR_IA32_SPEC_CTRL,
10747 MSR_TYPE_R | MSR_TYPE_W);
10750 nested_vmx_disable_intercept_for_msr(
10751 msr_bitmap_l1, msr_bitmap_l0,
10756 kvm_release_page_clean(page);
10761 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10762 struct vmcs12 *vmcs12)
10764 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10765 !page_address_valid(vcpu, vmcs12->apic_access_addr))
10771 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10772 struct vmcs12 *vmcs12)
10774 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10775 !nested_cpu_has_apic_reg_virt(vmcs12) &&
10776 !nested_cpu_has_vid(vmcs12) &&
10777 !nested_cpu_has_posted_intr(vmcs12))
10781 * If virtualize x2apic mode is enabled,
10782 * virtualize apic access must be disabled.
10784 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10785 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10789 * If virtual interrupt delivery is enabled,
10790 * we must exit on external interrupts.
10792 if (nested_cpu_has_vid(vmcs12) &&
10793 !nested_exit_on_intr(vcpu))
10797 * bits 15:8 should be zero in posted_intr_nv,
10798 * the descriptor address has been already checked
10799 * in nested_get_vmcs12_pages.
10801 if (nested_cpu_has_posted_intr(vmcs12) &&
10802 (!nested_cpu_has_vid(vmcs12) ||
10803 !nested_exit_intr_ack_set(vcpu) ||
10804 vmcs12->posted_intr_nv & 0xff00))
10807 /* tpr shadow is needed by all apicv features. */
10808 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10814 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10815 unsigned long count_field,
10816 unsigned long addr_field)
10821 if (vmcs12_read_any(vcpu, count_field, &count) ||
10822 vmcs12_read_any(vcpu, addr_field, &addr)) {
10828 maxphyaddr = cpuid_maxphyaddr(vcpu);
10829 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10830 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10831 pr_debug_ratelimited(
10832 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10833 addr_field, maxphyaddr, count, addr);
10839 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10840 struct vmcs12 *vmcs12)
10842 if (vmcs12->vm_exit_msr_load_count == 0 &&
10843 vmcs12->vm_exit_msr_store_count == 0 &&
10844 vmcs12->vm_entry_msr_load_count == 0)
10845 return 0; /* Fast path */
10846 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10847 VM_EXIT_MSR_LOAD_ADDR) ||
10848 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10849 VM_EXIT_MSR_STORE_ADDR) ||
10850 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10851 VM_ENTRY_MSR_LOAD_ADDR))
10856 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10857 struct vmcs12 *vmcs12)
10859 u64 address = vmcs12->pml_address;
10860 int maxphyaddr = cpuid_maxphyaddr(vcpu);
10862 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10863 if (!nested_cpu_has_ept(vmcs12) ||
10864 !IS_ALIGNED(address, 4096) ||
10865 address >> maxphyaddr)
10872 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10873 struct vmx_msr_entry *e)
10875 /* x2APIC MSR accesses are not allowed */
10876 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10878 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10879 e->index == MSR_IA32_UCODE_REV)
10881 if (e->reserved != 0)
10886 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10887 struct vmx_msr_entry *e)
10889 if (e->index == MSR_FS_BASE ||
10890 e->index == MSR_GS_BASE ||
10891 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10892 nested_vmx_msr_check_common(vcpu, e))
10897 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10898 struct vmx_msr_entry *e)
10900 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10901 nested_vmx_msr_check_common(vcpu, e))
10907 * Load guest's/host's msr at nested entry/exit.
10908 * return 0 for success, entry index for failure.
10910 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10913 struct vmx_msr_entry e;
10914 struct msr_data msr;
10916 msr.host_initiated = false;
10917 for (i = 0; i < count; i++) {
10918 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10920 pr_debug_ratelimited(
10921 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10922 __func__, i, gpa + i * sizeof(e));
10925 if (nested_vmx_load_msr_check(vcpu, &e)) {
10926 pr_debug_ratelimited(
10927 "%s check failed (%u, 0x%x, 0x%x)\n",
10928 __func__, i, e.index, e.reserved);
10931 msr.index = e.index;
10932 msr.data = e.value;
10933 if (kvm_set_msr(vcpu, &msr)) {
10934 pr_debug_ratelimited(
10935 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10936 __func__, i, e.index, e.value);
10945 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10948 struct vmx_msr_entry e;
10950 for (i = 0; i < count; i++) {
10951 struct msr_data msr_info;
10952 if (kvm_vcpu_read_guest(vcpu,
10953 gpa + i * sizeof(e),
10954 &e, 2 * sizeof(u32))) {
10955 pr_debug_ratelimited(
10956 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10957 __func__, i, gpa + i * sizeof(e));
10960 if (nested_vmx_store_msr_check(vcpu, &e)) {
10961 pr_debug_ratelimited(
10962 "%s check failed (%u, 0x%x, 0x%x)\n",
10963 __func__, i, e.index, e.reserved);
10966 msr_info.host_initiated = false;
10967 msr_info.index = e.index;
10968 if (kvm_get_msr(vcpu, &msr_info)) {
10969 pr_debug_ratelimited(
10970 "%s cannot read MSR (%u, 0x%x)\n",
10971 __func__, i, e.index);
10974 if (kvm_vcpu_write_guest(vcpu,
10975 gpa + i * sizeof(e) +
10976 offsetof(struct vmx_msr_entry, value),
10977 &msr_info.data, sizeof(msr_info.data))) {
10978 pr_debug_ratelimited(
10979 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10980 __func__, i, e.index, msr_info.data);
10987 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10989 unsigned long invalid_mask;
10991 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10992 return (val & invalid_mask) == 0;
10996 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10997 * emulating VM entry into a guest with EPT enabled.
10998 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10999 * is assigned to entry_failure_code on failure.
11001 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11002 u32 *entry_failure_code)
11004 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11005 if (!nested_cr3_valid(vcpu, cr3)) {
11006 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11011 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11012 * must not be dereferenced.
11014 if (is_pae_paging(vcpu) && !nested_ept) {
11015 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11016 *entry_failure_code = ENTRY_FAIL_PDPTE;
11021 vcpu->arch.cr3 = cr3;
11022 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11025 kvm_mmu_reset_context(vcpu);
11030 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
11031 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
11032 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
11033 * guest in a way that will both be appropriate to L1's requests, and our
11034 * needs. In addition to modifying the active vmcs (which is vmcs02), this
11035 * function also has additional necessary side-effects, like setting various
11036 * vcpu->arch fields.
11037 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11038 * is assigned to entry_failure_code on failure.
11040 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11041 bool from_vmentry, u32 *entry_failure_code)
11043 struct vcpu_vmx *vmx = to_vmx(vcpu);
11044 u32 exec_control, vmcs12_exec_ctrl;
11046 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11047 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11048 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11049 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11050 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11051 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11052 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11053 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11054 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11055 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11056 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11057 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11058 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11059 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11060 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11061 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11062 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11063 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11064 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11065 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11066 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11067 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11068 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11069 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11070 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11071 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11072 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11073 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11074 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11075 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11076 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11077 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11078 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11079 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11080 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11081 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11083 if (from_vmentry &&
11084 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11085 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11086 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11088 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11089 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11091 if (from_vmentry) {
11092 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11093 vmcs12->vm_entry_intr_info_field);
11094 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11095 vmcs12->vm_entry_exception_error_code);
11096 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11097 vmcs12->vm_entry_instruction_len);
11098 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11099 vmcs12->guest_interruptibility_info);
11100 vmx->loaded_vmcs->nmi_known_unmasked =
11101 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11103 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11105 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11106 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11107 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11108 vmcs12->guest_pending_dbg_exceptions);
11109 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11110 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11112 if (nested_cpu_has_xsaves(vmcs12))
11113 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11114 vmcs_write64(VMCS_LINK_POINTER, -1ull);
11116 exec_control = vmcs12->pin_based_vm_exec_control;
11118 /* Preemption timer setting is only taken from vmcs01. */
11119 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11120 exec_control |= vmcs_config.pin_based_exec_ctrl;
11121 if (vmx->hv_deadline_tsc == -1)
11122 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11124 /* Posted interrupts setting is only taken from vmcs12. */
11125 if (nested_cpu_has_posted_intr(vmcs12)) {
11126 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11127 vmx->nested.pi_pending = false;
11128 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11130 exec_control &= ~PIN_BASED_POSTED_INTR;
11133 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11135 vmx->nested.preemption_timer_expired = false;
11136 if (nested_cpu_has_preemption_timer(vmcs12))
11137 vmx_start_preemption_timer(vcpu);
11140 * Whether page-faults are trapped is determined by a combination of
11141 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11142 * If enable_ept, L0 doesn't care about page faults and we should
11143 * set all of these to L1's desires. However, if !enable_ept, L0 does
11144 * care about (at least some) page faults, and because it is not easy
11145 * (if at all possible?) to merge L0 and L1's desires, we simply ask
11146 * to exit on each and every L2 page fault. This is done by setting
11147 * MASK=MATCH=0 and (see below) EB.PF=1.
11148 * Note that below we don't need special code to set EB.PF beyond the
11149 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11150 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11151 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11153 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11154 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11155 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11156 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11158 if (cpu_has_secondary_exec_ctrls()) {
11159 exec_control = vmx->secondary_exec_control;
11161 /* Take the following fields only from vmcs12 */
11162 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11163 SECONDARY_EXEC_ENABLE_INVPCID |
11164 SECONDARY_EXEC_RDTSCP |
11165 SECONDARY_EXEC_XSAVES |
11166 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11167 SECONDARY_EXEC_APIC_REGISTER_VIRT |
11168 SECONDARY_EXEC_ENABLE_VMFUNC);
11169 if (nested_cpu_has(vmcs12,
11170 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11171 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11172 ~SECONDARY_EXEC_ENABLE_PML;
11173 exec_control |= vmcs12_exec_ctrl;
11176 /* All VMFUNCs are currently emulated through L0 vmexits. */
11177 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
11178 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11180 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
11181 vmcs_write64(EOI_EXIT_BITMAP0,
11182 vmcs12->eoi_exit_bitmap0);
11183 vmcs_write64(EOI_EXIT_BITMAP1,
11184 vmcs12->eoi_exit_bitmap1);
11185 vmcs_write64(EOI_EXIT_BITMAP2,
11186 vmcs12->eoi_exit_bitmap2);
11187 vmcs_write64(EOI_EXIT_BITMAP3,
11188 vmcs12->eoi_exit_bitmap3);
11189 vmcs_write16(GUEST_INTR_STATUS,
11190 vmcs12->guest_intr_status);
11194 * Write an illegal value to APIC_ACCESS_ADDR. Later,
11195 * nested_get_vmcs12_pages will either fix it up or
11196 * remove the VM execution control.
11198 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11199 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11201 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11206 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11207 * Some constant fields are set here by vmx_set_constant_host_state().
11208 * Other fields are different per CPU, and will be set later when
11209 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
11211 vmx_set_constant_host_state(vmx);
11214 * Set the MSR load/store lists to match L0's settings.
11216 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11217 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
11218 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
11219 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
11220 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
11223 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11224 * entry, but only if the current (host) sp changed from the value
11225 * we wrote last (vmx->host_rsp). This cache is no longer relevant
11226 * if we switch vmcs, and rather than hold a separate cache per vmcs,
11227 * here we just force the write to happen on entry.
11231 exec_control = vmx_exec_control(vmx); /* L0's desires */
11232 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11233 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11234 exec_control &= ~CPU_BASED_TPR_SHADOW;
11235 exec_control |= vmcs12->cpu_based_vm_exec_control;
11238 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11239 * nested_get_vmcs12_pages can't fix it up, the illegal value
11240 * will result in a VM entry failure.
11242 if (exec_control & CPU_BASED_TPR_SHADOW) {
11243 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11244 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11246 #ifdef CONFIG_X86_64
11247 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11248 CPU_BASED_CR8_STORE_EXITING;
11253 * Merging of IO bitmap not currently supported.
11254 * Rather, exit every time.
11256 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11257 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11259 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11261 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11262 * bitwise-or of what L1 wants to trap for L2, and what we want to
11263 * trap. Note that CR0.TS also needs updating - we do this later.
11265 update_exception_bitmap(vcpu);
11266 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11267 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11269 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11270 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11271 * bits are further modified by vmx_set_efer() below.
11273 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11275 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11276 * emulated by vmx_set_efer(), below.
11278 vm_entry_controls_init(vmx,
11279 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11280 ~VM_ENTRY_IA32E_MODE) |
11281 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11283 if (from_vmentry &&
11284 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11285 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11286 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11287 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11288 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11291 set_cr4_guest_host_mask(vmx);
11293 if (from_vmentry &&
11294 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
11295 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
11297 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11298 vmcs_write64(TSC_OFFSET,
11299 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
11301 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11302 if (kvm_has_tsc_control)
11303 decache_tsc_multiplier(vmx);
11305 if (cpu_has_vmx_msr_bitmap())
11306 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11310 * There is no direct mapping between vpid02 and vpid12, the
11311 * vpid02 is per-vCPU for L0 and reused while the value of
11312 * vpid12 is changed w/ one invvpid during nested vmentry.
11313 * The vpid12 is allocated by L1 for L2, so it will not
11314 * influence global bitmap(for vpid01 and vpid02 allocation)
11315 * even if spawn a lot of nested vCPUs.
11317 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11318 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11319 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11320 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11321 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true);
11324 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11325 vmx_flush_tlb(vcpu, true);
11332 * Conceptually we want to copy the PML address and index from
11333 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11334 * since we always flush the log on each vmexit, this happens
11335 * to be equivalent to simply resetting the fields in vmcs02.
11337 ASSERT(vmx->pml_pg);
11338 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11339 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11342 if (nested_cpu_has_ept(vmcs12)) {
11343 if (nested_ept_init_mmu_context(vcpu)) {
11344 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11347 } else if (nested_cpu_has2(vmcs12,
11348 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11349 vmx_flush_tlb(vcpu, true);
11353 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11354 * bits which we consider mandatory enabled.
11355 * The CR0_READ_SHADOW is what L2 should have expected to read given
11356 * the specifications by L1; It's not enough to take
11357 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11358 * have more bits than L1 expected.
11360 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11361 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11363 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11364 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11366 if (from_vmentry &&
11367 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11368 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11369 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11370 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11372 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11373 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11374 vmx_set_efer(vcpu, vcpu->arch.efer);
11376 /* Shadow page tables on either EPT or shadow page tables. */
11377 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11378 entry_failure_code))
11382 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11385 * L1 may access the L2's PDPTR, so save them to construct vmcs12
11388 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
11389 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
11390 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
11391 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
11394 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11395 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11399 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11401 struct vcpu_vmx *vmx = to_vmx(vcpu);
11403 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11404 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11405 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11407 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11408 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11410 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11411 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11413 if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11414 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11416 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11417 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11419 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11420 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11422 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11423 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11425 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11426 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11428 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11429 vmx->nested.nested_vmx_procbased_ctls_low,
11430 vmx->nested.nested_vmx_procbased_ctls_high) ||
11431 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11432 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11433 vmx->nested.nested_vmx_secondary_ctls_low,
11434 vmx->nested.nested_vmx_secondary_ctls_high)) ||
11435 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11436 vmx->nested.nested_vmx_pinbased_ctls_low,
11437 vmx->nested.nested_vmx_pinbased_ctls_high) ||
11438 !vmx_control_verify(vmcs12->vm_exit_controls,
11439 vmx->nested.nested_vmx_exit_ctls_low,
11440 vmx->nested.nested_vmx_exit_ctls_high) ||
11441 !vmx_control_verify(vmcs12->vm_entry_controls,
11442 vmx->nested.nested_vmx_entry_ctls_low,
11443 vmx->nested.nested_vmx_entry_ctls_high))
11444 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11446 if (nested_cpu_has_vmfunc(vmcs12)) {
11447 if (vmcs12->vm_function_control &
11448 ~vmx->nested.nested_vmx_vmfunc_controls)
11449 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11451 if (nested_cpu_has_eptp_switching(vmcs12)) {
11452 if (!nested_cpu_has_ept(vmcs12) ||
11453 !page_address_valid(vcpu, vmcs12->eptp_list_address))
11454 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11458 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11459 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11461 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11462 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11463 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11464 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11469 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11474 *exit_qual = ENTRY_FAIL_DEFAULT;
11476 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11477 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11480 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11481 vmcs12->vmcs_link_pointer != -1ull) {
11482 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11487 * If the load IA32_EFER VM-entry control is 1, the following checks
11488 * are performed on the field for the IA32_EFER MSR:
11489 * - Bits reserved in the IA32_EFER MSR must be 0.
11490 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11491 * the IA-32e mode guest VM-exit control. It must also be identical
11492 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11495 if (to_vmx(vcpu)->nested.nested_run_pending &&
11496 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11497 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11498 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11499 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11500 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11501 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11506 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11507 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11508 * the values of the LMA and LME bits in the field must each be that of
11509 * the host address-space size VM-exit control.
11511 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11512 ia32e = (vmcs12->vm_exit_controls &
11513 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11514 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11515 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11516 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11523 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11525 struct vcpu_vmx *vmx = to_vmx(vcpu);
11526 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11530 enter_guest_mode(vcpu);
11532 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11533 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11535 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11536 vmx_segment_cache_clear(vmx);
11538 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
11539 leave_guest_mode(vcpu);
11540 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11541 nested_vmx_entry_failure(vcpu, vmcs12,
11542 EXIT_REASON_INVALID_STATE, exit_qual);
11546 nested_get_vmcs12_pages(vcpu, vmcs12);
11548 msr_entry_idx = nested_vmx_load_msr(vcpu,
11549 vmcs12->vm_entry_msr_load_addr,
11550 vmcs12->vm_entry_msr_load_count);
11551 if (msr_entry_idx) {
11552 leave_guest_mode(vcpu);
11553 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11554 nested_vmx_entry_failure(vcpu, vmcs12,
11555 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
11560 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11561 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11562 * returned as far as L1 is concerned. It will only return (and set
11563 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11569 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11570 * for running an L2 nested guest.
11572 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11574 struct vmcs12 *vmcs12;
11575 struct vcpu_vmx *vmx = to_vmx(vcpu);
11576 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11580 if (!nested_vmx_check_permission(vcpu))
11583 if (!nested_vmx_check_vmcs12(vcpu))
11586 vmcs12 = get_vmcs12(vcpu);
11588 if (enable_shadow_vmcs)
11589 copy_shadow_to_vmcs12(vmx);
11592 * The nested entry process starts with enforcing various prerequisites
11593 * on vmcs12 as required by the Intel SDM, and act appropriately when
11594 * they fail: As the SDM explains, some conditions should cause the
11595 * instruction to fail, while others will cause the instruction to seem
11596 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11597 * To speed up the normal (success) code path, we should avoid checking
11598 * for misconfigurations which will anyway be caught by the processor
11599 * when using the merged vmcs02.
11601 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11602 nested_vmx_failValid(vcpu,
11603 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11607 if (vmcs12->launch_state == launch) {
11608 nested_vmx_failValid(vcpu,
11609 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11610 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11614 ret = check_vmentry_prereqs(vcpu, vmcs12);
11616 nested_vmx_failValid(vcpu, ret);
11621 * After this point, the trap flag no longer triggers a singlestep trap
11622 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11623 * This is not 100% correct; for performance reasons, we delegate most
11624 * of the checks on host state to the processor. If those fail,
11625 * the singlestep trap is missed.
11627 skip_emulated_instruction(vcpu);
11629 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11631 nested_vmx_entry_failure(vcpu, vmcs12,
11632 EXIT_REASON_INVALID_STATE, exit_qual);
11637 * We're finally done with prerequisite checking, and can start with
11638 * the nested entry.
11641 ret = enter_vmx_non_root_mode(vcpu, true);
11645 /* Hide L1D cache contents from the nested guest. */
11646 vmx->vcpu.arch.l1tf_flush_l1d = true;
11649 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11650 * by event injection, halt vcpu.
11652 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11653 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK))
11654 return kvm_vcpu_halt(vcpu);
11656 vmx->nested.nested_run_pending = 1;
11661 return kvm_skip_emulated_instruction(vcpu);
11665 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11666 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11667 * This function returns the new value we should put in vmcs12.guest_cr0.
11668 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11669 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11670 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11671 * didn't trap the bit, because if L1 did, so would L0).
11672 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11673 * been modified by L2, and L1 knows it. So just leave the old value of
11674 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11675 * isn't relevant, because if L0 traps this bit it can set it to anything.
11676 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11677 * changed these bits, and therefore they need to be updated, but L0
11678 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11679 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11681 static inline unsigned long
11682 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11685 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11686 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11687 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11688 vcpu->arch.cr0_guest_owned_bits));
11691 static inline unsigned long
11692 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11695 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11696 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11697 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11698 vcpu->arch.cr4_guest_owned_bits));
11701 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11702 struct vmcs12 *vmcs12)
11707 if (vcpu->arch.exception.injected) {
11708 nr = vcpu->arch.exception.nr;
11709 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11711 if (kvm_exception_is_soft(nr)) {
11712 vmcs12->vm_exit_instruction_len =
11713 vcpu->arch.event_exit_inst_len;
11714 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11716 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11718 if (vcpu->arch.exception.has_error_code) {
11719 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11720 vmcs12->idt_vectoring_error_code =
11721 vcpu->arch.exception.error_code;
11724 vmcs12->idt_vectoring_info_field = idt_vectoring;
11725 } else if (vcpu->arch.nmi_injected) {
11726 vmcs12->idt_vectoring_info_field =
11727 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11728 } else if (vcpu->arch.interrupt.pending) {
11729 nr = vcpu->arch.interrupt.nr;
11730 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11732 if (vcpu->arch.interrupt.soft) {
11733 idt_vectoring |= INTR_TYPE_SOFT_INTR;
11734 vmcs12->vm_entry_instruction_len =
11735 vcpu->arch.event_exit_inst_len;
11737 idt_vectoring |= INTR_TYPE_EXT_INTR;
11739 vmcs12->idt_vectoring_info_field = idt_vectoring;
11743 static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
11745 struct vcpu_vmx *vmx = to_vmx(vcpu);
11746 unsigned long exit_qual;
11747 bool block_nested_events =
11748 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11750 if (vcpu->arch.exception.pending &&
11751 nested_vmx_check_exception(vcpu, &exit_qual)) {
11752 if (block_nested_events)
11754 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11758 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11759 vmx->nested.preemption_timer_expired) {
11760 if (block_nested_events)
11762 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11766 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11767 if (block_nested_events)
11769 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11770 NMI_VECTOR | INTR_TYPE_NMI_INTR |
11771 INTR_INFO_VALID_MASK, 0);
11773 * The NMI-triggered VM exit counts as injection:
11774 * clear this one and block further NMIs.
11776 vcpu->arch.nmi_pending = 0;
11777 vmx_set_nmi_mask(vcpu, true);
11781 if (kvm_cpu_has_interrupt(vcpu) && nested_exit_on_intr(vcpu)) {
11782 if (block_nested_events)
11784 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11788 vmx_complete_nested_posted_interrupt(vcpu);
11792 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11794 ktime_t remaining =
11795 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11798 if (ktime_to_ns(remaining) <= 0)
11801 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11802 do_div(value, 1000000);
11803 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11807 * Update the guest state fields of vmcs12 to reflect changes that
11808 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11809 * VM-entry controls is also updated, since this is really a guest
11812 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11814 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11815 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11817 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11818 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11819 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11821 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11822 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11823 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11824 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11825 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11826 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11827 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11828 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11829 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11830 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11831 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11832 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11833 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11834 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11835 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11836 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11837 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11838 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11839 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11840 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11841 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11842 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11843 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11844 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11845 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11846 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11847 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11848 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11849 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11850 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11851 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11852 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11853 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11854 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11855 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11856 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11858 vmcs12->guest_interruptibility_info =
11859 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11860 vmcs12->guest_pending_dbg_exceptions =
11861 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11862 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11863 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11865 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11867 if (nested_cpu_has_preemption_timer(vmcs12)) {
11868 if (vmcs12->vm_exit_controls &
11869 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11870 vmcs12->vmx_preemption_timer_value =
11871 vmx_get_preemption_timer_value(vcpu);
11872 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11876 * In some cases (usually, nested EPT), L2 is allowed to change its
11877 * own CR3 without exiting. If it has changed it, we must keep it.
11878 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11879 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11881 * Additionally, restore L2's PDPTR to vmcs12.
11884 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11885 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11886 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11887 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11888 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11891 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11893 if (nested_cpu_has_vid(vmcs12))
11894 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11896 vmcs12->vm_entry_controls =
11897 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11898 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11900 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11901 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11902 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11905 /* TODO: These cannot have changed unless we have MSR bitmaps and
11906 * the relevant bit asks not to trap the change */
11907 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11908 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11909 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11910 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11911 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11912 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11913 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11914 if (kvm_mpx_supported())
11915 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11919 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11920 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11921 * and this function updates it to reflect the changes to the guest state while
11922 * L2 was running (and perhaps made some exits which were handled directly by L0
11923 * without going back to L1), and to reflect the exit reason.
11924 * Note that we do not have to copy here all VMCS fields, just those that
11925 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11926 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11927 * which already writes to vmcs12 directly.
11929 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11930 u32 exit_reason, u32 exit_intr_info,
11931 unsigned long exit_qualification)
11933 /* update guest state fields: */
11934 sync_vmcs12(vcpu, vmcs12);
11936 /* update exit information fields: */
11938 vmcs12->vm_exit_reason = exit_reason;
11939 vmcs12->exit_qualification = exit_qualification;
11940 vmcs12->vm_exit_intr_info = exit_intr_info;
11942 vmcs12->idt_vectoring_info_field = 0;
11943 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11944 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11946 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11947 vmcs12->launch_state = 1;
11949 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11950 * instead of reading the real value. */
11951 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11954 * Transfer the event that L0 or L1 may wanted to inject into
11955 * L2 to IDT_VECTORING_INFO_FIELD.
11957 vmcs12_save_pending_event(vcpu, vmcs12);
11962 * A part of what we need to when the nested L2 guest exits and we want to
11963 * run its L1 parent, is to reset L1's guest state to the host state specified
11965 * This function is to be called not only on normal nested exit, but also on
11966 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11967 * Failures During or After Loading Guest State").
11968 * This function should be called when the active VMCS is L1's (vmcs01).
11970 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11971 struct vmcs12 *vmcs12)
11973 struct kvm_segment seg;
11974 u32 entry_failure_code;
11976 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11977 vcpu->arch.efer = vmcs12->host_ia32_efer;
11978 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11979 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11981 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11982 vmx_set_efer(vcpu, vcpu->arch.efer);
11984 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11985 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11986 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11988 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11989 * actually changed, because vmx_set_cr0 refers to efer set above.
11991 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11992 * (KVM doesn't change it);
11994 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11995 vmx_set_cr0(vcpu, vmcs12->host_cr0);
11997 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11998 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11999 vmx_set_cr4(vcpu, vmcs12->host_cr4);
12001 nested_ept_uninit_mmu_context(vcpu);
12004 * Only PDPTE load can fail as the value of cr3 was checked on entry and
12005 * couldn't have changed.
12007 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
12008 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
12011 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
12015 * Trivially support vpid by letting L2s share their parent
12016 * L1's vpid. TODO: move to a more elaborate solution, giving
12017 * each L2 its own vpid and exposing the vpid feature to L1.
12019 vmx_flush_tlb(vcpu, true);
12021 /* Restore posted intr vector. */
12022 if (nested_cpu_has_posted_intr(vmcs12))
12023 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
12025 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
12026 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
12027 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
12028 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
12029 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
12030 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
12031 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
12033 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
12034 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
12035 vmcs_write64(GUEST_BNDCFGS, 0);
12037 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
12038 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
12039 vcpu->arch.pat = vmcs12->host_ia32_pat;
12041 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
12042 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
12043 vmcs12->host_ia32_perf_global_ctrl);
12045 /* Set L1 segment info according to Intel SDM
12046 27.5.2 Loading Host Segment and Descriptor-Table Registers */
12047 seg = (struct kvm_segment) {
12049 .limit = 0xFFFFFFFF,
12050 .selector = vmcs12->host_cs_selector,
12056 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12060 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
12061 seg = (struct kvm_segment) {
12063 .limit = 0xFFFFFFFF,
12070 seg.selector = vmcs12->host_ds_selector;
12071 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
12072 seg.selector = vmcs12->host_es_selector;
12073 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
12074 seg.selector = vmcs12->host_ss_selector;
12075 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
12076 seg.selector = vmcs12->host_fs_selector;
12077 seg.base = vmcs12->host_fs_base;
12078 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
12079 seg.selector = vmcs12->host_gs_selector;
12080 seg.base = vmcs12->host_gs_base;
12081 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
12082 seg = (struct kvm_segment) {
12083 .base = vmcs12->host_tr_base,
12085 .selector = vmcs12->host_tr_selector,
12089 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
12091 kvm_set_dr(vcpu, 7, 0x400);
12092 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
12094 if (cpu_has_vmx_msr_bitmap())
12095 vmx_update_msr_bitmap(vcpu);
12097 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12098 vmcs12->vm_exit_msr_load_count))
12099 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12102 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
12104 struct shared_msr_entry *efer_msr;
12107 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
12108 return vmcs_read64(GUEST_IA32_EFER);
12110 if (cpu_has_load_ia32_efer)
12113 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
12114 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
12115 return vmx->msr_autoload.guest.val[i].value;
12118 efer_msr = find_msr_entry(vmx, MSR_EFER);
12120 return efer_msr->data;
12125 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
12127 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12128 struct vcpu_vmx *vmx = to_vmx(vcpu);
12129 struct vmx_msr_entry g, h;
12130 struct msr_data msr;
12134 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
12136 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
12138 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
12139 * as vmcs01.GUEST_DR7 contains a userspace defined value
12140 * and vcpu->arch.dr7 is not squirreled away before the
12141 * nested VMENTER (not worth adding a variable in nested_vmx).
12143 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
12144 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
12146 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
12150 * Note that calling vmx_set_{efer,cr0,cr4} is important as they
12151 * handle a variety of side effects to KVM's software model.
12153 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
12155 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
12156 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
12158 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
12159 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
12161 nested_ept_uninit_mmu_context(vcpu);
12162 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
12163 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
12166 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
12167 * from vmcs01 (if necessary). The PDPTRs are not loaded on
12168 * VMFail, like everything else we just need to ensure our
12169 * software model is up-to-date.
12171 ept_save_pdptrs(vcpu);
12173 kvm_mmu_reset_context(vcpu);
12175 if (cpu_has_vmx_msr_bitmap())
12176 vmx_update_msr_bitmap(vcpu);
12179 * This nasty bit of open coding is a compromise between blindly
12180 * loading L1's MSRs using the exit load lists (incorrect emulation
12181 * of VMFail), leaving the nested VM's MSRs in the software model
12182 * (incorrect behavior) and snapshotting the modified MSRs (too
12183 * expensive since the lists are unbound by hardware). For each
12184 * MSR that was (prematurely) loaded from the nested VMEntry load
12185 * list, reload it from the exit load list if it exists and differs
12186 * from the guest value. The intent is to stuff host state as
12187 * silently as possible, not to fully process the exit load list.
12189 msr.host_initiated = false;
12190 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
12191 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
12192 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
12193 pr_debug_ratelimited(
12194 "%s read MSR index failed (%u, 0x%08llx)\n",
12199 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
12200 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
12201 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
12202 pr_debug_ratelimited(
12203 "%s read MSR failed (%u, 0x%08llx)\n",
12207 if (h.index != g.index)
12209 if (h.value == g.value)
12212 if (nested_vmx_load_msr_check(vcpu, &h)) {
12213 pr_debug_ratelimited(
12214 "%s check failed (%u, 0x%x, 0x%x)\n",
12215 __func__, j, h.index, h.reserved);
12219 msr.index = h.index;
12220 msr.data = h.value;
12221 if (kvm_set_msr(vcpu, &msr)) {
12222 pr_debug_ratelimited(
12223 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
12224 __func__, j, h.index, h.value);
12233 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12237 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12238 * and modify vmcs12 to make it see what it would expect to see there if
12239 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12241 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12242 u32 exit_intr_info,
12243 unsigned long exit_qualification)
12245 struct vcpu_vmx *vmx = to_vmx(vcpu);
12246 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12248 /* trying to cancel vmlaunch/vmresume is a bug */
12249 WARN_ON_ONCE(vmx->nested.nested_run_pending);
12252 * The only expected VM-instruction error is "VM entry with
12253 * invalid control field(s)." Anything else indicates a
12256 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12257 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12259 leave_guest_mode(vcpu);
12261 if (likely(!vmx->fail)) {
12262 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12263 exit_qualification);
12265 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12266 vmcs12->vm_exit_msr_store_count))
12267 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12271 * Drop events/exceptions that were queued for re-injection to L2
12272 * (picked up via vmx_complete_interrupts()), as well as exceptions
12273 * that were pending for L2. Note, this must NOT be hoisted above
12274 * prepare_vmcs12(), events/exceptions queued for re-injection need to
12275 * be captured in vmcs12 (see vmcs12_save_pending_event()).
12277 vcpu->arch.nmi_injected = false;
12278 kvm_clear_exception_queue(vcpu);
12279 kvm_clear_interrupt_queue(vcpu);
12281 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12282 vm_entry_controls_reset_shadow(vmx);
12283 vm_exit_controls_reset_shadow(vmx);
12284 vmx_segment_cache_clear(vmx);
12286 /* Update any VMCS fields that might have changed while L2 ran */
12287 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12288 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12289 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12290 if (vmx->hv_deadline_tsc == -1)
12291 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12292 PIN_BASED_VMX_PREEMPTION_TIMER);
12294 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12295 PIN_BASED_VMX_PREEMPTION_TIMER);
12296 if (kvm_has_tsc_control)
12297 decache_tsc_multiplier(vmx);
12299 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
12300 vmx->nested.change_vmcs01_virtual_apic_mode = false;
12301 vmx_set_virtual_apic_mode(vcpu);
12302 } else if (!nested_cpu_has_ept(vmcs12) &&
12303 nested_cpu_has2(vmcs12,
12304 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12305 vmx_flush_tlb(vcpu, true);
12308 /* This is needed for same reason as it was needed in prepare_vmcs02 */
12311 /* Unpin physical memory we referred to in vmcs02 */
12312 if (vmx->nested.apic_access_page) {
12313 kvm_release_page_dirty(vmx->nested.apic_access_page);
12314 vmx->nested.apic_access_page = NULL;
12316 if (vmx->nested.virtual_apic_page) {
12317 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12318 vmx->nested.virtual_apic_page = NULL;
12320 if (vmx->nested.pi_desc_page) {
12321 kunmap(vmx->nested.pi_desc_page);
12322 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12323 vmx->nested.pi_desc_page = NULL;
12324 vmx->nested.pi_desc = NULL;
12328 * We are now running in L2, mmu_notifier will force to reload the
12329 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12331 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12333 if (enable_shadow_vmcs)
12334 vmx->nested.sync_shadow_vmcs = true;
12336 /* in case we halted in L2 */
12337 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12339 if (likely(!vmx->fail)) {
12340 if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12341 nested_exit_intr_ack_set(vcpu)) {
12342 int irq = kvm_cpu_get_interrupt(vcpu);
12344 vmcs12->vm_exit_intr_info = irq |
12345 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12348 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12349 vmcs12->exit_qualification,
12350 vmcs12->idt_vectoring_info_field,
12351 vmcs12->vm_exit_intr_info,
12352 vmcs12->vm_exit_intr_error_code,
12355 load_vmcs12_host_state(vcpu, vmcs12);
12361 * After an early L2 VM-entry failure, we're now back
12362 * in L1 which thinks it just finished a VMLAUNCH or
12363 * VMRESUME instruction, so we need to set the failure
12364 * flag and the VM-instruction error field of the VMCS
12367 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12370 * Restore L1's host state to KVM's software model. We're here
12371 * because a consistency check was caught by hardware, which
12372 * means some amount of guest state has been propagated to KVM's
12373 * model and needs to be unwound to the host's state.
12375 nested_vmx_restore_host_state(vcpu);
12378 * The emulated instruction was already skipped in
12379 * nested_vmx_run, but the updated RIP was never
12380 * written back to the vmcs01.
12382 skip_emulated_instruction(vcpu);
12387 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12389 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12391 if (is_guest_mode(vcpu)) {
12392 to_vmx(vcpu)->nested.nested_run_pending = 0;
12393 nested_vmx_vmexit(vcpu, -1, 0, 0);
12395 free_nested(to_vmx(vcpu));
12399 * L1's failure to enter L2 is a subset of a normal exit, as explained in
12400 * 23.7 "VM-entry failures during or after loading guest state" (this also
12401 * lists the acceptable exit-reason and exit-qualification parameters).
12402 * It should only be called before L2 actually succeeded to run, and when
12403 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12405 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12406 struct vmcs12 *vmcs12,
12407 u32 reason, unsigned long qualification)
12409 load_vmcs12_host_state(vcpu, vmcs12);
12410 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12411 vmcs12->exit_qualification = qualification;
12412 nested_vmx_succeed(vcpu);
12413 if (enable_shadow_vmcs)
12414 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12417 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
12418 struct x86_instruction_info *info)
12420 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12421 unsigned short port;
12425 if (info->intercept == x86_intercept_in ||
12426 info->intercept == x86_intercept_ins) {
12427 port = info->src_val;
12428 size = info->dst_bytes;
12430 port = info->dst_val;
12431 size = info->src_bytes;
12435 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
12436 * VM-exits depend on the 'unconditional IO exiting' VM-execution
12439 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
12441 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
12442 intercept = nested_cpu_has(vmcs12,
12443 CPU_BASED_UNCOND_IO_EXITING);
12445 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
12447 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
12448 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
12451 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12452 struct x86_instruction_info *info,
12453 enum x86_intercept_stage stage)
12455 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12456 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12458 switch (info->intercept) {
12460 * RDPID causes #UD if disabled through secondary execution controls.
12461 * Because it is marked as EmulateOnUD, we need to intercept it here.
12463 case x86_intercept_rdtscp:
12464 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12465 ctxt->exception.vector = UD_VECTOR;
12466 ctxt->exception.error_code_valid = false;
12467 return X86EMUL_PROPAGATE_FAULT;
12471 case x86_intercept_in:
12472 case x86_intercept_ins:
12473 case x86_intercept_out:
12474 case x86_intercept_outs:
12475 return vmx_check_intercept_io(vcpu, info);
12477 case x86_intercept_lgdt:
12478 case x86_intercept_lidt:
12479 case x86_intercept_lldt:
12480 case x86_intercept_ltr:
12481 case x86_intercept_sgdt:
12482 case x86_intercept_sidt:
12483 case x86_intercept_sldt:
12484 case x86_intercept_str:
12485 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
12486 return X86EMUL_CONTINUE;
12488 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
12491 /* TODO: check more intercepts... */
12496 return X86EMUL_UNHANDLEABLE;
12499 #ifdef CONFIG_X86_64
12500 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12501 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12502 u64 divisor, u64 *result)
12504 u64 low = a << shift, high = a >> (64 - shift);
12506 /* To avoid the overflow on divq */
12507 if (high >= divisor)
12510 /* Low hold the result, high hold rem which is discarded */
12511 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12512 "rm" (divisor), "0" (low), "1" (high));
12518 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12520 struct vcpu_vmx *vmx = to_vmx(vcpu);
12521 u64 tscl = rdtsc();
12522 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12523 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12525 /* Convert to host delta tsc if tsc scaling is enabled */
12526 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12527 u64_shl_div_u64(delta_tsc,
12528 kvm_tsc_scaling_ratio_frac_bits,
12529 vcpu->arch.tsc_scaling_ratio,
12534 * If the delta tsc can't fit in the 32 bit after the multi shift,
12535 * we can't use the preemption timer.
12536 * It's possible that it fits on later vmentries, but checking
12537 * on every vmentry is costly so we just use an hrtimer.
12539 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12542 vmx->hv_deadline_tsc = tscl + delta_tsc;
12543 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12544 PIN_BASED_VMX_PREEMPTION_TIMER);
12546 return delta_tsc == 0;
12549 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12551 struct vcpu_vmx *vmx = to_vmx(vcpu);
12552 vmx->hv_deadline_tsc = -1;
12553 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12554 PIN_BASED_VMX_PREEMPTION_TIMER);
12558 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12561 shrink_ple_window(vcpu);
12564 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12565 struct kvm_memory_slot *slot)
12567 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12568 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12571 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12572 struct kvm_memory_slot *slot)
12574 kvm_mmu_slot_set_dirty(kvm, slot);
12577 static void vmx_flush_log_dirty(struct kvm *kvm)
12579 kvm_flush_pml_buffers(kvm);
12582 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa)
12584 struct vmcs12 *vmcs12;
12585 struct vcpu_vmx *vmx = to_vmx(vcpu);
12586 struct page *page = NULL;
12589 if (is_guest_mode(vcpu)) {
12590 WARN_ON_ONCE(vmx->nested.pml_full);
12593 * Check if PML is enabled for the nested guest.
12594 * Whether eptp bit 6 is set is already checked
12595 * as part of A/D emulation.
12597 vmcs12 = get_vmcs12(vcpu);
12598 if (!nested_cpu_has_pml(vmcs12))
12601 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12602 vmx->nested.pml_full = true;
12608 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12609 if (is_error_page(page))
12612 pml_address = kmap(page);
12613 pml_address[vmcs12->guest_pml_index--] = gpa;
12615 kvm_release_page_clean(page);
12621 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12622 struct kvm_memory_slot *memslot,
12623 gfn_t offset, unsigned long mask)
12625 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12628 static void __pi_post_block(struct kvm_vcpu *vcpu)
12630 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12631 struct pi_desc old, new;
12635 old.control = new.control = pi_desc->control;
12636 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12637 "Wakeup handler not enabled while the VCPU is blocked\n");
12639 dest = cpu_physical_id(vcpu->cpu);
12641 if (x2apic_enabled())
12644 new.ndst = (dest << 8) & 0xFF00;
12646 /* set 'NV' to 'notification vector' */
12647 new.nv = POSTED_INTR_VECTOR;
12648 } while (cmpxchg64(&pi_desc->control, old.control,
12649 new.control) != old.control);
12651 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12652 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12653 list_del(&vcpu->blocked_vcpu_list);
12654 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12655 vcpu->pre_pcpu = -1;
12660 * This routine does the following things for vCPU which is going
12661 * to be blocked if VT-d PI is enabled.
12662 * - Store the vCPU to the wakeup list, so when interrupts happen
12663 * we can find the right vCPU to wake up.
12664 * - Change the Posted-interrupt descriptor as below:
12665 * 'NDST' <-- vcpu->pre_pcpu
12666 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12667 * - If 'ON' is set during this process, which means at least one
12668 * interrupt is posted for this vCPU, we cannot block it, in
12669 * this case, return 1, otherwise, return 0.
12672 static int pi_pre_block(struct kvm_vcpu *vcpu)
12675 struct pi_desc old, new;
12676 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12678 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12679 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12680 !kvm_vcpu_apicv_active(vcpu))
12683 WARN_ON(irqs_disabled());
12684 local_irq_disable();
12685 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12686 vcpu->pre_pcpu = vcpu->cpu;
12687 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12688 list_add_tail(&vcpu->blocked_vcpu_list,
12689 &per_cpu(blocked_vcpu_on_cpu,
12691 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12695 old.control = new.control = pi_desc->control;
12697 WARN((pi_desc->sn == 1),
12698 "Warning: SN field of posted-interrupts "
12699 "is set before blocking\n");
12702 * Since vCPU can be preempted during this process,
12703 * vcpu->cpu could be different with pre_pcpu, we
12704 * need to set pre_pcpu as the destination of wakeup
12705 * notification event, then we can find the right vCPU
12706 * to wakeup in wakeup handler if interrupts happen
12707 * when the vCPU is in blocked state.
12709 dest = cpu_physical_id(vcpu->pre_pcpu);
12711 if (x2apic_enabled())
12714 new.ndst = (dest << 8) & 0xFF00;
12716 /* set 'NV' to 'wakeup vector' */
12717 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12718 } while (cmpxchg64(&pi_desc->control, old.control,
12719 new.control) != old.control);
12721 /* We should not block the vCPU if an interrupt is posted for it. */
12722 if (pi_test_on(pi_desc) == 1)
12723 __pi_post_block(vcpu);
12725 local_irq_enable();
12726 return (vcpu->pre_pcpu == -1);
12729 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12731 if (pi_pre_block(vcpu))
12734 if (kvm_lapic_hv_timer_in_use(vcpu))
12735 kvm_lapic_switch_to_sw_timer(vcpu);
12740 static void pi_post_block(struct kvm_vcpu *vcpu)
12742 if (vcpu->pre_pcpu == -1)
12745 WARN_ON(irqs_disabled());
12746 local_irq_disable();
12747 __pi_post_block(vcpu);
12748 local_irq_enable();
12751 static void vmx_post_block(struct kvm_vcpu *vcpu)
12753 if (kvm_x86_ops->set_hv_timer)
12754 kvm_lapic_switch_to_hv_timer(vcpu);
12756 pi_post_block(vcpu);
12760 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12763 * @host_irq: host irq of the interrupt
12764 * @guest_irq: gsi of the interrupt
12765 * @set: set or unset PI
12766 * returns 0 on success, < 0 on failure
12768 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12769 uint32_t guest_irq, bool set)
12771 struct kvm_kernel_irq_routing_entry *e;
12772 struct kvm_irq_routing_table *irq_rt;
12773 struct kvm_lapic_irq irq;
12774 struct kvm_vcpu *vcpu;
12775 struct vcpu_data vcpu_info;
12778 if (!kvm_arch_has_assigned_device(kvm) ||
12779 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12780 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12783 idx = srcu_read_lock(&kvm->irq_srcu);
12784 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12785 if (guest_irq >= irq_rt->nr_rt_entries ||
12786 hlist_empty(&irq_rt->map[guest_irq])) {
12787 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12788 guest_irq, irq_rt->nr_rt_entries);
12792 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12793 if (e->type != KVM_IRQ_ROUTING_MSI)
12796 * VT-d PI cannot support posting multicast/broadcast
12797 * interrupts to a vCPU, we still use interrupt remapping
12798 * for these kind of interrupts.
12800 * For lowest-priority interrupts, we only support
12801 * those with single CPU as the destination, e.g. user
12802 * configures the interrupts via /proc/irq or uses
12803 * irqbalance to make the interrupts single-CPU.
12805 * We will support full lowest-priority interrupt later.
12808 kvm_set_msi_irq(kvm, e, &irq);
12809 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12811 * Make sure the IRTE is in remapped mode if
12812 * we don't handle it in posted mode.
12814 ret = irq_set_vcpu_affinity(host_irq, NULL);
12817 "failed to back to remapped mode, irq: %u\n",
12825 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12826 vcpu_info.vector = irq.vector;
12828 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12829 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12832 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12834 ret = irq_set_vcpu_affinity(host_irq, NULL);
12837 printk(KERN_INFO "%s: failed to update PI IRTE\n",
12845 srcu_read_unlock(&kvm->irq_srcu, idx);
12849 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12851 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12852 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12853 FEATURE_CONTROL_LMCE;
12855 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12856 ~FEATURE_CONTROL_LMCE;
12859 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12860 .cpu_has_kvm_support = cpu_has_kvm_support,
12861 .disabled_by_bios = vmx_disabled_by_bios,
12862 .hardware_setup = hardware_setup,
12863 .hardware_unsetup = hardware_unsetup,
12864 .check_processor_compatibility = vmx_check_processor_compat,
12865 .hardware_enable = hardware_enable,
12866 .hardware_disable = hardware_disable,
12867 .cpu_has_accelerated_tpr = report_flexpriority,
12868 .has_emulated_msr = vmx_has_emulated_msr,
12870 .vm_init = vmx_vm_init,
12872 .vcpu_create = vmx_create_vcpu,
12873 .vcpu_free = vmx_free_vcpu,
12874 .vcpu_reset = vmx_vcpu_reset,
12876 .prepare_guest_switch = vmx_save_host_state,
12877 .vcpu_load = vmx_vcpu_load,
12878 .vcpu_put = vmx_vcpu_put,
12880 .update_bp_intercept = update_exception_bitmap,
12881 .get_msr_feature = vmx_get_msr_feature,
12882 .get_msr = vmx_get_msr,
12883 .set_msr = vmx_set_msr,
12884 .get_segment_base = vmx_get_segment_base,
12885 .get_segment = vmx_get_segment,
12886 .set_segment = vmx_set_segment,
12887 .get_cpl = vmx_get_cpl,
12888 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12889 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12890 .decache_cr3 = vmx_decache_cr3,
12891 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12892 .set_cr0 = vmx_set_cr0,
12893 .set_cr3 = vmx_set_cr3,
12894 .set_cr4 = vmx_set_cr4,
12895 .set_efer = vmx_set_efer,
12896 .get_idt = vmx_get_idt,
12897 .set_idt = vmx_set_idt,
12898 .get_gdt = vmx_get_gdt,
12899 .set_gdt = vmx_set_gdt,
12900 .get_dr6 = vmx_get_dr6,
12901 .set_dr6 = vmx_set_dr6,
12902 .set_dr7 = vmx_set_dr7,
12903 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12904 .cache_reg = vmx_cache_reg,
12905 .get_rflags = vmx_get_rflags,
12906 .set_rflags = vmx_set_rflags,
12908 .tlb_flush = vmx_flush_tlb,
12910 .run = vmx_vcpu_run,
12911 .handle_exit = vmx_handle_exit,
12912 .skip_emulated_instruction = skip_emulated_instruction,
12913 .set_interrupt_shadow = vmx_set_interrupt_shadow,
12914 .get_interrupt_shadow = vmx_get_interrupt_shadow,
12915 .patch_hypercall = vmx_patch_hypercall,
12916 .set_irq = vmx_inject_irq,
12917 .set_nmi = vmx_inject_nmi,
12918 .queue_exception = vmx_queue_exception,
12919 .cancel_injection = vmx_cancel_injection,
12920 .interrupt_allowed = vmx_interrupt_allowed,
12921 .nmi_allowed = vmx_nmi_allowed,
12922 .get_nmi_mask = vmx_get_nmi_mask,
12923 .set_nmi_mask = vmx_set_nmi_mask,
12924 .enable_nmi_window = enable_nmi_window,
12925 .enable_irq_window = enable_irq_window,
12926 .update_cr8_intercept = update_cr8_intercept,
12927 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
12928 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12929 .get_enable_apicv = vmx_get_enable_apicv,
12930 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12931 .load_eoi_exitmap = vmx_load_eoi_exitmap,
12932 .apicv_post_state_restore = vmx_apicv_post_state_restore,
12933 .hwapic_irr_update = vmx_hwapic_irr_update,
12934 .hwapic_isr_update = vmx_hwapic_isr_update,
12935 .sync_pir_to_irr = vmx_sync_pir_to_irr,
12936 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12937 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
12939 .set_tss_addr = vmx_set_tss_addr,
12940 .get_tdp_level = get_ept_level,
12941 .get_mt_mask = vmx_get_mt_mask,
12943 .get_exit_info = vmx_get_exit_info,
12945 .get_lpage_level = vmx_get_lpage_level,
12947 .cpuid_update = vmx_cpuid_update,
12949 .rdtscp_supported = vmx_rdtscp_supported,
12950 .invpcid_supported = vmx_invpcid_supported,
12952 .set_supported_cpuid = vmx_set_supported_cpuid,
12954 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12956 .write_tsc_offset = vmx_write_tsc_offset,
12958 .set_tdp_cr3 = vmx_set_cr3,
12960 .check_intercept = vmx_check_intercept,
12961 .handle_external_intr = vmx_handle_external_intr,
12962 .mpx_supported = vmx_mpx_supported,
12963 .xsaves_supported = vmx_xsaves_supported,
12965 .check_nested_events = vmx_check_nested_events,
12967 .sched_in = vmx_sched_in,
12969 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12970 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12971 .flush_log_dirty = vmx_flush_log_dirty,
12972 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12973 .write_log_dirty = vmx_write_pml_buffer,
12975 .pre_block = vmx_pre_block,
12976 .post_block = vmx_post_block,
12978 .pmu_ops = &intel_pmu_ops,
12980 .update_pi_irte = vmx_update_pi_irte,
12982 #ifdef CONFIG_X86_64
12983 .set_hv_timer = vmx_set_hv_timer,
12984 .cancel_hv_timer = vmx_cancel_hv_timer,
12987 .setup_mce = vmx_setup_mce,
12990 static void vmx_cleanup_l1d_flush(void)
12992 if (vmx_l1d_flush_pages) {
12993 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
12994 vmx_l1d_flush_pages = NULL;
12996 /* Restore state so sysfs ignores VMX */
12997 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
13001 static void vmx_exit(void)
13003 #ifdef CONFIG_KEXEC_CORE
13004 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
13010 vmx_cleanup_l1d_flush();
13012 module_exit(vmx_exit)
13014 static int __init vmx_init(void)
13018 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
13019 __alignof__(struct vcpu_vmx), THIS_MODULE);
13024 * Must be called after kvm_init() so enable_ept is properly set
13025 * up. Hand the parameter mitigation value in which was stored in
13026 * the pre module init parser. If no parameter was given, it will
13027 * contain 'auto' which will be turned into the default 'cond'
13030 if (boot_cpu_has(X86_BUG_L1TF)) {
13031 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
13038 vmx_setup_fb_clear_ctrl();
13040 for_each_possible_cpu(cpu) {
13041 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
13043 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
13044 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
13047 #ifdef CONFIG_KEXEC_CORE
13048 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
13049 crash_vmclear_local_loaded_vmcss);
13054 module_init(vmx_init)