arch/x86/kvm/vmx/vmx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_H
   3 #define __KVM_X86_VMX_H
   4
   5 #include <linux/kvm_host.h>
   6
   7 #include <asm/kvm.h>
   8 #include <asm/intel_pt.h>
   9
  10 #include "capabilities.h"
  11 #include "ops.h"
  12 #include "vmcs.h"
  13 #include "run_flags.h"
  14
  15 extern const u32 vmx_msr_index[];
  16 extern u64 host_efer;
  17
  18 #define MSR_TYPE_R      1
  19 #define MSR_TYPE_W      2
  20 #define MSR_TYPE_RW     3
  21
  22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
  23
  24 #define NR_AUTOLOAD_MSRS 8
  25
  26 struct vmx_msrs {
  27         unsigned int            nr;
  28         struct vmx_msr_entry    val[NR_AUTOLOAD_MSRS];
  29 };
  30
  31 struct shared_msr_entry {
  32         unsigned index;
  33         u64 data;
  34         u64 mask;
  35 };
  36
  37 enum segment_cache_field {
  38         SEG_FIELD_SEL = 0,
  39         SEG_FIELD_BASE = 1,
  40         SEG_FIELD_LIMIT = 2,
  41         SEG_FIELD_AR = 3,
  42
  43         SEG_FIELD_NR = 4
  44 };
  45
  46 /* Posted-Interrupt Descriptor */
  47 struct pi_desc {
  48         u32 pir[8];     /* Posted interrupt requested */
  49         union {
  50                 struct {
  51                                 /* bit 256 - Outstanding Notification */
  52                         u16     on      : 1,
  53                                 /* bit 257 - Suppress Notification */
  54                                 sn      : 1,
  55                                 /* bit 271:258 - Reserved */
  56                                 rsvd_1  : 14;
  57                                 /* bit 279:272 - Notification Vector */
  58                         u8      nv;
  59                                 /* bit 287:280 - Reserved */
  60                         u8      rsvd_2;
  61                                 /* bit 319:288 - Notification Destination */
  62                         u32     ndst;
  63                 };
  64                 u64 control;
  65         };
  66         u32 rsvd[6];
  67 } __aligned(64);
  68
  69 #define RTIT_ADDR_RANGE         4
  70
  71 struct pt_ctx {
  72         u64 ctl;
  73         u64 status;
  74         u64 output_base;
  75         u64 output_mask;
  76         u64 cr3_match;
  77         u64 addr_a[RTIT_ADDR_RANGE];
  78         u64 addr_b[RTIT_ADDR_RANGE];
  79 };
  80
  81 struct pt_desc {
  82         u64 ctl_bitmask;
  83         u32 addr_range;
  84         u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
  85         struct pt_ctx host;
  86         struct pt_ctx guest;
  87 };
  88
  89 /*
  90  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
  91  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
  92  */
  93 struct nested_vmx {
  94         /* Has the level1 guest done vmxon? */
  95         bool vmxon;
  96         gpa_t vmxon_ptr;
  97         bool pml_full;
  98
  99         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 100         gpa_t current_vmptr;
 101         /*
 102          * Cache of the guest's VMCS, existing outside of guest memory.
 103          * Loaded from guest memory during VMPTRLD. Flushed to guest
 104          * memory during VMCLEAR and VMPTRLD.
 105          */
 106         struct vmcs12 *cached_vmcs12;
 107         /*
 108          * Cache of the guest's shadow VMCS, existing outside of guest
 109          * memory. Loaded from guest memory during VM entry. Flushed
 110          * to guest memory during VM exit.
 111          */
 112         struct vmcs12 *cached_shadow_vmcs12;
 113
 114         /*
 115          * Indicates if the shadow vmcs or enlightened vmcs must be updated
 116          * with the data held by struct vmcs12.
 117          */
 118         bool need_vmcs12_to_shadow_sync;
 119         bool dirty_vmcs12;
 120
 121         /*
 122          * Indicates lazily loaded guest state has not yet been decached from
 123          * vmcs02.
 124          */
 125         bool need_sync_vmcs02_to_vmcs12_rare;
 126
 127         /*
 128          * vmcs02 has been initialized, i.e. state that is constant for
 129          * vmcs02 has been written to the backing VMCS.  Initialization
 130          * is delayed until L1 actually attempts to run a nested VM.
 131          */
 132         bool vmcs02_initialized;
 133
 134         bool change_vmcs01_virtual_apic_mode;
 135
 136         /*
 137          * Enlightened VMCS has been enabled. It does not mean that L1 has to
 138          * use it. However, VMX features available to L1 will be limited based
 139          * on what the enlightened VMCS supports.
 140          */
 141         bool enlightened_vmcs_enabled;
 142
 143         /* L2 must run next, and mustn't decide to exit to L1. */
 144         bool nested_run_pending;
 145
 146         struct loaded_vmcs vmcs02;
 147
 148         /*
 149          * Guest pages referred to in the vmcs02 with host-physical
 150          * pointers, so we must keep them pinned while L2 runs.
 151          */
 152         struct page *apic_access_page;
 153         struct kvm_host_map virtual_apic_map;
 154         struct kvm_host_map pi_desc_map;
 155
 156         struct kvm_host_map msr_bitmap_map;
 157
 158         struct pi_desc *pi_desc;
 159         bool pi_pending;
 160         u16 posted_intr_nv;
 161
 162         struct hrtimer preemption_timer;
 163         bool preemption_timer_expired;
 164
 165         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 166         u64 vmcs01_debugctl;
 167         u64 vmcs01_guest_bndcfgs;
 168
 169         u16 vpid02;
 170         u16 last_vpid;
 171
 172         struct nested_vmx_msrs msrs;
 173
 174         /* SMM related state */
 175         struct {
 176                 /* in VMX operation on SMM entry? */
 177                 bool vmxon;
 178                 /* in guest mode on SMM entry? */
 179                 bool guest_mode;
 180         } smm;
 181
 182         gpa_t hv_evmcs_vmptr;
 183         struct kvm_host_map hv_evmcs_map;
 184         struct hv_enlightened_vmcs *hv_evmcs;
 185 };
 186
 187 struct vcpu_vmx {
 188         struct kvm_vcpu       vcpu;
 189         u8                    fail;
 190         u8                    msr_bitmap_mode;
 191
 192         /*
 193          * If true, host state has been stored in vmx->loaded_vmcs for
 194          * the CPU registers that only need to be switched when transitioning
 195          * to/from the kernel, and the registers have been loaded with guest
 196          * values.  If false, host state is loaded in the CPU registers
 197          * and vmx->loaded_vmcs->host_state is invalid.
 198          */
 199         bool                  guest_state_loaded;
 200
 201         u32                   exit_intr_info;
 202         u32                   idt_vectoring_info;
 203         ulong                 rflags;
 204
 205         struct shared_msr_entry *guest_msrs;
 206         int                   nmsrs;
 207         int                   save_nmsrs;
 208         bool                  guest_msrs_ready;
 209 #ifdef CONFIG_X86_64
 210         u64                   msr_host_kernel_gs_base;
 211         u64                   msr_guest_kernel_gs_base;
 212 #endif
 213
 214         u64                   spec_ctrl;
 215         u32                   msr_ia32_umwait_control;
 216
 217         u32 secondary_exec_control;
 218
 219         /*
 220          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 221          * non-nested (L1) guest, it always points to vmcs01. For a nested
 222          * guest (L2), it points to a different VMCS.
 223          */
 224         struct loaded_vmcs    vmcs01;
 225         struct loaded_vmcs   *loaded_vmcs;
 226
 227         struct msr_autoload {
 228                 struct vmx_msrs guest;
 229                 struct vmx_msrs host;
 230         } msr_autoload;
 231
 232         struct {
 233                 int vm86_active;
 234                 ulong save_rflags;
 235                 struct kvm_segment segs[8];
 236         } rmode;
 237         struct {
 238                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 239                 struct kvm_save_segment {
 240                         u16 selector;
 241                         unsigned long base;
 242                         u32 limit;
 243                         u32 ar;
 244                 } seg[8];
 245         } segment_cache;
 246         int vpid;
 247         bool emulation_required;
 248
 249         u32 exit_reason;
 250
 251         /* Posted interrupt descriptor */
 252         struct pi_desc pi_desc;
 253
 254         /* Support for a guest hypervisor (nested VMX) */
 255         struct nested_vmx nested;
 256
 257         /* Dynamic PLE window. */
 258         unsigned int ple_window;
 259         bool ple_window_dirty;
 260
 261         bool req_immediate_exit;
 262
 263         /* Support for PML */
 264 #define PML_ENTITY_NUM          512
 265         struct page *pml_pg;
 266
 267         /* apic deadline value in host tsc */
 268         u64 hv_deadline_tsc;
 269
 270         u64 current_tsc_ratio;
 271
 272         u32 host_pkru;
 273
 274         unsigned long host_debugctlmsr;
 275
 276         /*
 277          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 278          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 279          * in msr_ia32_feature_control_valid_bits.
 280          */
 281         u64 msr_ia32_feature_control;
 282         u64 msr_ia32_feature_control_valid_bits;
 283         u64 ept_pointer;
 284         u64 msr_ia32_mcu_opt_ctrl;
 285         bool disable_fb_clear;
 286
 287         struct pt_desc pt_desc;
 288
 289 };
 290
 291 enum ept_pointers_status {
 292         EPT_POINTERS_CHECK = 0,
 293         EPT_POINTERS_MATCH = 1,
 294         EPT_POINTERS_MISMATCH = 2
 295 };
 296
 297 struct kvm_vmx {
 298         struct kvm kvm;
 299
 300         unsigned int tss_addr;
 301         bool ept_identity_pagetable_done;
 302         gpa_t ept_identity_map_addr;
 303
 304         enum ept_pointers_status ept_pointers_match;
 305         spinlock_t ept_pointer_lock;
 306 };
 307
 308 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
 309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
 310                         struct loaded_vmcs *buddy);
 311 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 312 int allocate_vpid(void);
 313 void free_vpid(int vpid);
 314 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
 315 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
 316 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
 317                         unsigned long fs_base, unsigned long gs_base);
 318 int vmx_get_cpl(struct kvm_vcpu *vcpu);
 319 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
 320 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 321 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
 322 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
 323 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 324 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 325 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 326 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 327 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
 328 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 329 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 330 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 331 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 332 void update_exception_bitmap(struct kvm_vcpu *vcpu);
 333 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 334 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 335 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 336 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 337 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
 338 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
 339 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
 340 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
 341 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
 342 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
 343                     unsigned int flags);
 344
 345 #define POSTED_INTR_ON  0
 346 #define POSTED_INTR_SN  1
 347
 348 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
 349 {
 350         return test_and_set_bit(POSTED_INTR_ON,
 351                         (unsigned long *)&pi_desc->control);
 352 }
 353
 354 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 355 {
 356         return test_and_clear_bit(POSTED_INTR_ON,
 357                         (unsigned long *)&pi_desc->control);
 358 }
 359
 360 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 361 {
 362         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 363 }
 364
 365 static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
 366 {
 367         return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
 368 }
 369
 370 static inline void pi_set_sn(struct pi_desc *pi_desc)
 371 {
 372         set_bit(POSTED_INTR_SN,
 373                 (unsigned long *)&pi_desc->control);
 374 }
 375
 376 static inline void pi_set_on(struct pi_desc *pi_desc)
 377 {
 378         set_bit(POSTED_INTR_ON,
 379                 (unsigned long *)&pi_desc->control);
 380 }
 381
 382 static inline void pi_clear_on(struct pi_desc *pi_desc)
 383 {
 384         clear_bit(POSTED_INTR_ON,
 385                 (unsigned long *)&pi_desc->control);
 386 }
 387
 388 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 389 {
 390         clear_bit(POSTED_INTR_SN,
 391                 (unsigned long *)&pi_desc->control);
 392 }
 393
 394 static inline int pi_test_on(struct pi_desc *pi_desc)
 395 {
 396         return test_bit(POSTED_INTR_ON,
 397                         (unsigned long *)&pi_desc->control);
 398 }
 399
 400 static inline int pi_test_sn(struct pi_desc *pi_desc)
 401 {
 402         return test_bit(POSTED_INTR_SN,
 403                         (unsigned long *)&pi_desc->control);
 404 }
 405
 406 static inline u8 vmx_get_rvi(void)
 407 {
 408         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
 409 }
 410
 411 #define BUILD_CONTROLS_SHADOW(lname, uname)                                 \
 412 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)      \
 413 {                                                                           \
 414         if (vmx->loaded_vmcs->controls_shadow.lname != val) {               \
 415                 vmcs_write32(uname, val);                                   \
 416                 vmx->loaded_vmcs->controls_shadow.lname = val;              \
 417         }                                                                   \
 418 }                                                                           \
 419 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)                \
 420 {                                                                           \
 421         return vmx->loaded_vmcs->controls_shadow.lname;                     \
 422 }                                                                           \
 423 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
 424 {                                                                           \
 425         lname##_controls_set(vmx, lname##_controls_get(vmx) | val);         \
 426 }                                                                           \
 427 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
 428 {                                                                           \
 429         lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);        \
 430 }
 431 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
 432 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
 433 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
 434 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
 435 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
 436
 437 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 438 {
 439         vmx->segment_cache.bitmask = 0;
 440 }
 441
 442 static inline u32 vmx_vmentry_ctrl(void)
 443 {
 444         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
 445         if (pt_mode == PT_MODE_SYSTEM)
 446                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
 447                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
 448         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 449         return vmentry_ctrl &
 450                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
 451 }
 452
 453 static inline u32 vmx_vmexit_ctrl(void)
 454 {
 455         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
 456         if (pt_mode == PT_MODE_SYSTEM)
 457                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
 458                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
 459         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 460         return vmexit_ctrl &
 461                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
 462 }
 463
 464 u32 vmx_exec_control(struct vcpu_vmx *vmx);
 465 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
 466
 467 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 468 {
 469         return container_of(kvm, struct kvm_vmx, kvm);
 470 }
 471
 472 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 473 {
 474         return container_of(vcpu, struct vcpu_vmx, vcpu);
 475 }
 476
 477 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 478 {
 479         return &(to_vmx(vcpu)->pi_desc);
 480 }
 481
 482 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
 483 void free_vmcs(struct vmcs *vmcs);
 484 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 485 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 486 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
 487 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
 488
 489 static inline struct vmcs *alloc_vmcs(bool shadow)
 490 {
 491         return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
 492                               GFP_KERNEL_ACCOUNT);
 493 }
 494
 495 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 496
 497 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
 498                                 bool invalidate_gpa)
 499 {
 500         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
 501                 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
 502                         return;
 503                 ept_sync_context(construct_eptp(vcpu,
 504                                                 vcpu->arch.mmu->root_hpa));
 505         } else {
 506                 vpid_sync_context(vpid);
 507         }
 508 }
 509
 510 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
 511 {
 512         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
 513 }
 514
 515 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
 516 {
 517         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
 518         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
 519 }
 520
 521 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
 522 {
 523         return secondary_exec_controls_get(vmx) &
 524                 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
 525 }
 526
 527 void dump_vmcs(void);
 528
 529 #endif /* __KVM_X86_VMX_H */