1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_NESTED_H
3 #define __KVM_X86_VMX_NESTED_H
5 #include "kvm_cache_regs.h"
10 * Status returned by nested_vmx_enter_non_root_mode():
12 enum nvmx_vmentry_status {
13 NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */
14 NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */
15 NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */
16 NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */
19 void vmx_leave_nested(struct kvm_vcpu *vcpu);
20 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps);
21 void nested_vmx_hardware_unsetup(void);
22 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *));
23 void nested_vmx_set_vmcs_shadowing_bitmap(void);
24 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu);
25 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
27 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu);
28 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
29 u32 exit_intr_info, unsigned long exit_qualification);
30 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu);
31 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
32 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata);
33 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
34 u32 vmx_instruction_info, bool wr, int len, gva_t *ret);
35 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu);
36 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu);
37 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
40 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
42 return to_vmx(vcpu)->nested.cached_vmcs12;
45 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
47 return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
51 * Note: the same condition is checked against the state provided by userspace
52 * in vmx_set_nested_state; if it is satisfied, the nested state must include
55 static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu)
57 struct vcpu_vmx *vmx = to_vmx(vcpu);
60 * In case we do two consecutive get/set_nested_state()s while L2 was
61 * running hv_evmcs may end up not being mapped (we map it from
62 * nested_vmx_run()/vmx_vcpu_run()). Check is_guest_mode() as we always
63 * have vmcs12 if it is true.
65 return is_guest_mode(vcpu) || vmx->nested.current_vmptr != -1ull ||
69 static inline u16 nested_get_vpid02(struct kvm_vcpu *vcpu)
71 struct vcpu_vmx *vmx = to_vmx(vcpu);
73 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid;
76 static inline unsigned long nested_ept_get_eptp(struct kvm_vcpu *vcpu)
78 /* return the page table to be shadowed - in our case, EPT12 */
79 return get_vmcs12(vcpu)->ept_pointer;
82 static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
84 return nested_ept_get_eptp(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
88 * Return the cr0 value that a nested guest would read. This is a combination
89 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
90 * its hypervisor (cr0_read_shadow).
92 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
94 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
95 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
97 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
99 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
100 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
103 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
105 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
109 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
110 * to modify any valid field of the VMCS, or are the VM-exit
111 * information fields read-only?
113 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
115 return to_vmx(vcpu)->nested.msrs.misc_low &
116 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
119 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
121 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
124 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
126 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
127 CPU_BASED_MONITOR_TRAP_FLAG;
130 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
132 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
133 SECONDARY_EXEC_SHADOW_VMCS;
136 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
138 return vmcs12->cpu_based_vm_exec_control & bit;
141 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
143 return (vmcs12->cpu_based_vm_exec_control &
144 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
145 (vmcs12->secondary_vm_exec_control & bit);
148 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
150 return vmcs12->pin_based_vm_exec_control &
151 PIN_BASED_VMX_PREEMPTION_TIMER;
154 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
156 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
159 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
161 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
164 static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12)
166 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
169 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
171 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
174 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
176 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
179 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
181 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
184 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
186 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
189 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
191 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
194 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
196 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
199 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
201 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
204 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
206 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
209 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
211 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
214 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
216 return nested_cpu_has_vmfunc(vmcs12) &&
217 (vmcs12->vm_function_control &
218 VMX_VMFUNC_EPTP_SWITCHING);
221 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
223 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
226 static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12)
228 return vmcs12->vm_exit_controls &
229 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
232 static inline bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
234 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
238 * In nested virtualization, check if L1 asked to exit on external interrupts.
239 * For most existing hypervisors, this will always return true.
241 static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
243 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
244 PIN_BASED_EXT_INTR_MASK;
248 * if fixed0[i] == 1: val[i] must be 1
249 * if fixed1[i] == 0: val[i] must be 0
251 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
253 return ((val & fixed1) | fixed0) == val;
256 static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
258 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
259 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
260 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
262 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
263 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
264 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
265 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
267 return fixed_bits_valid(val, fixed0, fixed1);
270 static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
272 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
273 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
275 return fixed_bits_valid(val, fixed0, fixed1);
278 static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
280 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
281 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
283 return fixed_bits_valid(val, fixed0, fixed1);
286 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
287 #define nested_guest_cr4_valid nested_cr4_valid
288 #define nested_host_cr4_valid nested_cr4_valid
290 extern struct kvm_x86_nested_ops vmx_nested_ops;
292 #endif /* __KVM_X86_VMX_NESTED_H */