2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM),
66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly;
123 static const u32 host_save_user_msrs[] = {
125 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
128 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info {
135 bool active; /* SEV enabled guest */
136 unsigned int asid; /* ASID used for this guest */
137 unsigned int handle; /* SEV firmware handle */
138 int fd; /* SEV device fd */
139 unsigned long pages_locked; /* Number of pages locked */
140 struct list_head regions_list; /* List of registered regions */
146 /* Struct members for AVIC */
149 struct page *avic_logical_id_table_page;
150 struct page *avic_physical_id_table_page;
151 struct hlist_node hnode;
153 struct kvm_sev_info sev_info;
158 struct nested_state {
164 /* These are the merged vectors */
167 /* gpa pointers to the real vectors */
171 /* A VMEXIT is required but not yet emulated */
174 /* cache for intercepts of the guest */
177 u32 intercept_exceptions;
180 /* Nested Paging related state */
184 #define MSRPM_OFFSETS 16
185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
188 * Set osvw_len to higher value when updated Revision Guides
189 * are published and we know what the new status bits are
191 static uint64_t osvw_len = 4, osvw_status;
194 struct kvm_vcpu vcpu;
196 unsigned long vmcb_pa;
197 struct svm_cpu_data *svm_data;
198 uint64_t asid_generation;
199 uint64_t sysenter_esp;
200 uint64_t sysenter_eip;
207 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
217 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
218 * translated into the appropriate L2_CFG bits on the host to
219 * perform speculative control.
227 struct nested_state nested;
230 u64 nmi_singlestep_guest_rflags;
232 unsigned int3_injected;
233 unsigned long int3_rip;
235 /* cached guest cpuid flags for faster access */
236 bool nrips_enabled : 1;
239 struct page *avic_backing_page;
240 u64 *avic_physical_id_cache;
241 bool avic_is_running;
244 * Per-vcpu list of struct amd_svm_iommu_ir:
245 * This is used mainly to store interrupt remapping information used
246 * when update the vcpu affinity. This avoids the need to scan for
247 * IRTE and try to match ga_tag in the IOMMU driver.
249 struct list_head ir_list;
250 spinlock_t ir_list_lock;
252 /* which host CPU was used for running this vcpu */
253 unsigned int last_cpu;
257 * This is a wrapper of struct amd_iommu_ir_data.
259 struct amd_svm_iommu_ir {
260 struct list_head node; /* Used by SVM for per-vcpu ir_list */
261 void *data; /* Storing pointer to struct amd_ir_data */
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
273 #define TSC_RATIO_DEFAULT 0x0100000000ULL
275 #define MSR_INVALID 0xffffffffU
277 static const struct svm_direct_access_msrs {
278 u32 index; /* Index of the MSR */
279 bool always; /* True if intercept is always on */
280 } direct_access_msrs[] = {
281 { .index = MSR_STAR, .always = true },
282 { .index = MSR_IA32_SYSENTER_CS, .always = true },
284 { .index = MSR_GS_BASE, .always = true },
285 { .index = MSR_FS_BASE, .always = true },
286 { .index = MSR_KERNEL_GS_BASE, .always = true },
287 { .index = MSR_LSTAR, .always = true },
288 { .index = MSR_CSTAR, .always = true },
289 { .index = MSR_SYSCALL_MASK, .always = true },
291 { .index = MSR_IA32_SPEC_CTRL, .always = false },
292 { .index = MSR_IA32_PRED_CMD, .always = false },
293 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
294 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
295 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
296 { .index = MSR_IA32_LASTINTTOIP, .always = false },
297 { .index = MSR_INVALID, .always = false },
300 /* enable NPT for AMD64 and X86 with PAE */
301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
302 static bool npt_enabled = true;
304 static bool npt_enabled;
308 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
309 * pause_filter_count: On processors that support Pause filtering(indicated
310 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
311 * count value. On VMRUN this value is loaded into an internal counter.
312 * Each time a pause instruction is executed, this counter is decremented
313 * until it reaches zero at which time a #VMEXIT is generated if pause
314 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
315 * Intercept Filtering for more details.
316 * This also indicate if ple logic enabled.
318 * pause_filter_thresh: In addition, some processor families support advanced
319 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
320 * the amount of time a guest is allowed to execute in a pause loop.
321 * In this mode, a 16-bit pause filter threshold field is added in the
322 * VMCB. The threshold value is a cycle count that is used to reset the
323 * pause counter. As with simple pause filtering, VMRUN loads the pause
324 * count value from VMCB into an internal counter. Then, on each pause
325 * instruction the hardware checks the elapsed number of cycles since
326 * the most recent pause instruction against the pause filter threshold.
327 * If the elapsed cycle count is greater than the pause filter threshold,
328 * then the internal pause count is reloaded from the VMCB and execution
329 * continues. If the elapsed cycle count is less than the pause filter
330 * threshold, then the internal pause count is decremented. If the count
331 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
332 * triggered. If advanced pause filtering is supported and pause filter
333 * threshold field is set to zero, the filter will operate in the simpler,
337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
338 module_param(pause_filter_thresh, ushort, 0444);
340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
341 module_param(pause_filter_count, ushort, 0444);
343 /* Default doubles per-vcpu window every exit. */
344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
345 module_param(pause_filter_count_grow, ushort, 0444);
347 /* Default resets per-vcpu window every exit to pause_filter_count. */
348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
349 module_param(pause_filter_count_shrink, ushort, 0444);
351 /* Default is to compute the maximum so we can never overflow. */
352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
353 module_param(pause_filter_count_max, ushort, 0444);
355 /* allow nested paging (virtualized MMU) for all guests */
356 static int npt = true;
357 module_param(npt, int, S_IRUGO);
359 /* allow nested virtualization in KVM/SVM */
360 static int nested = true;
361 module_param(nested, int, S_IRUGO);
363 /* enable / disable AVIC */
365 #ifdef CONFIG_X86_LOCAL_APIC
366 module_param(avic, int, S_IRUGO);
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls = true;
371 module_param(vls, int, 0444);
373 /* enable/disable Virtual GIF */
374 static int vgif = true;
375 module_param(vgif, int, 0444);
377 /* enable/disable SEV support */
378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
379 module_param(sev, int, 0444);
381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
385 static void svm_complete_interrupts(struct vcpu_svm *svm);
387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
388 static int nested_svm_intercept(struct vcpu_svm *svm);
389 static int nested_svm_vmexit(struct vcpu_svm *svm);
390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
391 bool has_error_code, u32 error_code);
394 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
395 pause filter count */
396 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
397 VMCB_ASID, /* ASID */
398 VMCB_INTR, /* int_ctl, int_vector */
399 VMCB_NPT, /* npt_en, nCR3, gPAT */
400 VMCB_CR, /* CR0, CR3, CR4, EFER */
401 VMCB_DR, /* DR6, DR7 */
402 VMCB_DT, /* GDT, IDT */
403 VMCB_SEG, /* CS, DS, SS, ES, CPL */
404 VMCB_CR2, /* CR2 only */
405 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
406 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
407 * AVIC PHYSICAL_TABLE pointer,
408 * AVIC LOGICAL_TABLE pointer
413 /* TPR and CR2 are always written before VMRUN */
414 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
416 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
418 static unsigned int max_sev_asid;
419 static unsigned int min_sev_asid;
420 static unsigned long *sev_asid_bitmap;
421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
424 struct list_head list;
425 unsigned long npages;
432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
434 return container_of(kvm, struct kvm_svm, kvm);
437 static inline bool svm_sev_enabled(void)
439 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
442 static inline bool sev_guest(struct kvm *kvm)
444 #ifdef CONFIG_KVM_AMD_SEV
445 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
453 static inline int sev_get_asid(struct kvm *kvm)
455 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
460 static inline void mark_all_dirty(struct vmcb *vmcb)
462 vmcb->control.clean = 0;
465 static inline void mark_all_clean(struct vmcb *vmcb)
467 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
468 & ~VMCB_ALWAYS_DIRTY_MASK;
471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
473 vmcb->control.clean &= ~(1 << bit);
476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
478 return container_of(vcpu, struct vcpu_svm, vcpu);
481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
483 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
484 mark_dirty(svm->vmcb, VMCB_AVIC);
487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
489 struct vcpu_svm *svm = to_svm(vcpu);
490 u64 *entry = svm->avic_physical_id_cache;
495 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
498 static void recalc_intercepts(struct vcpu_svm *svm)
500 struct vmcb_control_area *c, *h;
501 struct nested_state *g;
503 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
505 if (!is_guest_mode(&svm->vcpu))
508 c = &svm->vmcb->control;
509 h = &svm->nested.hsave->control;
512 c->intercept_cr = h->intercept_cr | g->intercept_cr;
513 c->intercept_dr = h->intercept_dr | g->intercept_dr;
514 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
515 c->intercept = h->intercept | g->intercept;
517 c->intercept |= (1ULL << INTERCEPT_VMLOAD);
518 c->intercept |= (1ULL << INTERCEPT_VMSAVE);
521 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
523 if (is_guest_mode(&svm->vcpu))
524 return svm->nested.hsave;
529 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
531 struct vmcb *vmcb = get_host_vmcb(svm);
533 vmcb->control.intercept_cr |= (1U << bit);
535 recalc_intercepts(svm);
538 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
540 struct vmcb *vmcb = get_host_vmcb(svm);
542 vmcb->control.intercept_cr &= ~(1U << bit);
544 recalc_intercepts(svm);
547 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
549 struct vmcb *vmcb = get_host_vmcb(svm);
551 return vmcb->control.intercept_cr & (1U << bit);
554 static inline void set_dr_intercepts(struct vcpu_svm *svm)
556 struct vmcb *vmcb = get_host_vmcb(svm);
558 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
559 | (1 << INTERCEPT_DR1_READ)
560 | (1 << INTERCEPT_DR2_READ)
561 | (1 << INTERCEPT_DR3_READ)
562 | (1 << INTERCEPT_DR4_READ)
563 | (1 << INTERCEPT_DR5_READ)
564 | (1 << INTERCEPT_DR6_READ)
565 | (1 << INTERCEPT_DR7_READ)
566 | (1 << INTERCEPT_DR0_WRITE)
567 | (1 << INTERCEPT_DR1_WRITE)
568 | (1 << INTERCEPT_DR2_WRITE)
569 | (1 << INTERCEPT_DR3_WRITE)
570 | (1 << INTERCEPT_DR4_WRITE)
571 | (1 << INTERCEPT_DR5_WRITE)
572 | (1 << INTERCEPT_DR6_WRITE)
573 | (1 << INTERCEPT_DR7_WRITE);
575 recalc_intercepts(svm);
578 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
580 struct vmcb *vmcb = get_host_vmcb(svm);
582 vmcb->control.intercept_dr = 0;
584 recalc_intercepts(svm);
587 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
589 struct vmcb *vmcb = get_host_vmcb(svm);
591 vmcb->control.intercept_exceptions |= (1U << bit);
593 recalc_intercepts(svm);
596 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
598 struct vmcb *vmcb = get_host_vmcb(svm);
600 vmcb->control.intercept_exceptions &= ~(1U << bit);
602 recalc_intercepts(svm);
605 static inline void set_intercept(struct vcpu_svm *svm, int bit)
607 struct vmcb *vmcb = get_host_vmcb(svm);
609 vmcb->control.intercept |= (1ULL << bit);
611 recalc_intercepts(svm);
614 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
616 struct vmcb *vmcb = get_host_vmcb(svm);
618 vmcb->control.intercept &= ~(1ULL << bit);
620 recalc_intercepts(svm);
623 static inline bool vgif_enabled(struct vcpu_svm *svm)
625 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
628 static inline void enable_gif(struct vcpu_svm *svm)
630 if (vgif_enabled(svm))
631 svm->vmcb->control.int_ctl |= V_GIF_MASK;
633 svm->vcpu.arch.hflags |= HF_GIF_MASK;
636 static inline void disable_gif(struct vcpu_svm *svm)
638 if (vgif_enabled(svm))
639 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
641 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
644 static inline bool gif_set(struct vcpu_svm *svm)
646 if (vgif_enabled(svm))
647 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
649 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
652 static unsigned long iopm_base;
654 struct kvm_ldttss_desc {
657 unsigned base1:8, type:5, dpl:2, p:1;
658 unsigned limit1:4, zero0:3, g:1, base2:8;
661 } __attribute__((packed));
663 struct svm_cpu_data {
670 struct kvm_ldttss_desc *tss_desc;
672 struct page *save_area;
673 struct vmcb *current_vmcb;
675 /* index = sev_asid, value = vmcb pointer */
676 struct vmcb **sev_vmcbs;
679 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
681 struct svm_init_data {
686 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
688 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
689 #define MSRS_RANGE_SIZE 2048
690 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
692 static u32 svm_msrpm_offset(u32 msr)
697 for (i = 0; i < NUM_MSR_MAPS; i++) {
698 if (msr < msrpm_ranges[i] ||
699 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
702 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
703 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
705 /* Now we have the u8 offset - but need the u32 offset */
709 /* MSR not in any range */
713 #define MAX_INST_SIZE 15
715 static inline void clgi(void)
717 asm volatile (__ex(SVM_CLGI));
720 static inline void stgi(void)
722 asm volatile (__ex(SVM_STGI));
725 static inline void invlpga(unsigned long addr, u32 asid)
727 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
730 static int get_npt_level(struct kvm_vcpu *vcpu)
733 return PT64_ROOT_4LEVEL;
735 return PT32E_ROOT_LEVEL;
739 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
741 vcpu->arch.efer = efer;
744 /* Shadow paging assumes NX to be available. */
747 if (!(efer & EFER_LMA))
751 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
752 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
755 static int is_external_interrupt(u32 info)
757 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
758 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
761 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
763 struct vcpu_svm *svm = to_svm(vcpu);
766 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
767 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
771 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
773 struct vcpu_svm *svm = to_svm(vcpu);
776 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
778 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
782 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
784 struct vcpu_svm *svm = to_svm(vcpu);
786 if (svm->vmcb->control.next_rip != 0) {
787 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
788 svm->next_rip = svm->vmcb->control.next_rip;
791 if (!svm->next_rip) {
792 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
794 printk(KERN_DEBUG "%s: NOP\n", __func__);
797 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
798 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
799 __func__, kvm_rip_read(vcpu), svm->next_rip);
801 kvm_rip_write(vcpu, svm->next_rip);
802 svm_set_interrupt_shadow(vcpu, 0);
805 static void svm_queue_exception(struct kvm_vcpu *vcpu)
807 struct vcpu_svm *svm = to_svm(vcpu);
808 unsigned nr = vcpu->arch.exception.nr;
809 bool has_error_code = vcpu->arch.exception.has_error_code;
810 bool reinject = vcpu->arch.exception.injected;
811 u32 error_code = vcpu->arch.exception.error_code;
814 * If we are within a nested VM we'd better #VMEXIT and let the guest
815 * handle the exception
818 nested_svm_check_exception(svm, nr, has_error_code, error_code))
821 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
822 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
825 * For guest debugging where we have to reinject #BP if some
826 * INT3 is guest-owned:
827 * Emulate nRIP by moving RIP forward. Will fail if injection
828 * raises a fault that is not intercepted. Still better than
829 * failing in all cases.
831 skip_emulated_instruction(&svm->vcpu);
832 rip = kvm_rip_read(&svm->vcpu);
833 svm->int3_rip = rip + svm->vmcb->save.cs.base;
834 svm->int3_injected = rip - old_rip;
837 svm->vmcb->control.event_inj = nr
839 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
840 | SVM_EVTINJ_TYPE_EXEPT;
841 svm->vmcb->control.event_inj_err = error_code;
844 static void svm_init_erratum_383(void)
850 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
853 /* Use _safe variants to not break nested virtualization */
854 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
860 low = lower_32_bits(val);
861 high = upper_32_bits(val);
863 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
865 erratum_383_found = true;
868 static void svm_init_osvw(struct kvm_vcpu *vcpu)
871 * Guests should see errata 400 and 415 as fixed (assuming that
872 * HLT and IO instructions are intercepted).
874 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
875 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
878 * By increasing VCPU's osvw.length to 3 we are telling the guest that
879 * all osvw.status bits inside that length, including bit 0 (which is
880 * reserved for erratum 298), are valid. However, if host processor's
881 * osvw_len is 0 then osvw_status[0] carries no information. We need to
882 * be conservative here and therefore we tell the guest that erratum 298
883 * is present (because we really don't know).
885 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
886 vcpu->arch.osvw.status |= 1;
889 static int has_svm(void)
893 if (!cpu_has_svm(&msg)) {
894 printk(KERN_INFO "has_svm: %s\n", msg);
899 pr_info("KVM is unsupported when running as an SEV guest\n");
906 static void svm_hardware_disable(void)
908 /* Make sure we clean up behind us */
909 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
910 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
914 amd_pmu_disable_virt();
917 static int svm_hardware_enable(void)
920 struct svm_cpu_data *sd;
922 struct desc_struct *gdt;
923 int me = raw_smp_processor_id();
925 rdmsrl(MSR_EFER, efer);
926 if (efer & EFER_SVME)
930 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
933 sd = per_cpu(svm_data, me);
935 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
939 sd->asid_generation = 1;
940 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
941 sd->next_asid = sd->max_asid + 1;
942 sd->min_asid = max_sev_asid + 1;
944 gdt = get_current_gdt_rw();
945 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
947 wrmsrl(MSR_EFER, efer | EFER_SVME);
949 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
951 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
952 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
953 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
960 * Note that it is possible to have a system with mixed processor
961 * revisions and therefore different OSVW bits. If bits are not the same
962 * on different processors then choose the worst case (i.e. if erratum
963 * is present on one processor and not on another then assume that the
964 * erratum is present everywhere).
966 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
967 uint64_t len, status = 0;
970 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
972 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
976 osvw_status = osvw_len = 0;
980 osvw_status |= status;
981 osvw_status &= (1ULL << osvw_len) - 1;
984 osvw_status = osvw_len = 0;
986 svm_init_erratum_383();
988 amd_pmu_enable_virt();
993 static void svm_cpu_uninit(int cpu)
995 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
1000 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
1001 kfree(sd->sev_vmcbs);
1002 __free_page(sd->save_area);
1006 static int svm_cpu_init(int cpu)
1008 struct svm_cpu_data *sd;
1010 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1014 sd->save_area = alloc_page(GFP_KERNEL);
1018 if (svm_sev_enabled()) {
1019 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1023 goto free_save_area;
1026 per_cpu(svm_data, cpu) = sd;
1031 __free_page(sd->save_area);
1038 static bool valid_msr_intercept(u32 index)
1042 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1043 if (direct_access_msrs[i].index == index)
1049 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1056 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1057 to_svm(vcpu)->msrpm;
1059 offset = svm_msrpm_offset(msr);
1060 bit_write = 2 * (msr & 0x0f) + 1;
1061 tmp = msrpm[offset];
1063 BUG_ON(offset == MSR_INVALID);
1065 return !!test_bit(bit_write, &tmp);
1068 static void set_msr_interception(u32 *msrpm, unsigned msr,
1069 int read, int write)
1071 u8 bit_read, bit_write;
1076 * If this warning triggers extend the direct_access_msrs list at the
1077 * beginning of the file
1079 WARN_ON(!valid_msr_intercept(msr));
1081 offset = svm_msrpm_offset(msr);
1082 bit_read = 2 * (msr & 0x0f);
1083 bit_write = 2 * (msr & 0x0f) + 1;
1084 tmp = msrpm[offset];
1086 BUG_ON(offset == MSR_INVALID);
1088 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1089 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1091 msrpm[offset] = tmp;
1094 static void svm_vcpu_init_msrpm(u32 *msrpm)
1098 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1100 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1101 if (!direct_access_msrs[i].always)
1104 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1108 static void add_msr_offset(u32 offset)
1112 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1114 /* Offset already in list? */
1115 if (msrpm_offsets[i] == offset)
1118 /* Slot used by another offset? */
1119 if (msrpm_offsets[i] != MSR_INVALID)
1122 /* Add offset to list */
1123 msrpm_offsets[i] = offset;
1129 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1130 * increase MSRPM_OFFSETS in this case.
1135 static void init_msrpm_offsets(void)
1139 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1141 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1144 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1145 BUG_ON(offset == MSR_INVALID);
1147 add_msr_offset(offset);
1151 static void svm_enable_lbrv(struct vcpu_svm *svm)
1153 u32 *msrpm = svm->msrpm;
1155 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1156 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1157 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1158 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1159 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1162 static void svm_disable_lbrv(struct vcpu_svm *svm)
1164 u32 *msrpm = svm->msrpm;
1166 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1167 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1168 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1169 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1170 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1173 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1175 svm->nmi_singlestep = false;
1177 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1178 /* Clear our flags if they were not set by the guest */
1179 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1180 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1181 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1182 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1187 * This hash table is used to map VM_ID to a struct kvm_svm,
1188 * when handling AMD IOMMU GALOG notification to schedule in
1189 * a particular vCPU.
1191 #define SVM_VM_DATA_HASH_BITS 8
1192 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1193 static u32 next_vm_id = 0;
1194 static bool next_vm_id_wrapped = 0;
1195 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1198 * This function is called from IOMMU driver to notify
1199 * SVM to schedule in a particular vCPU of a particular VM.
1201 static int avic_ga_log_notifier(u32 ga_tag)
1203 unsigned long flags;
1204 struct kvm_svm *kvm_svm;
1205 struct kvm_vcpu *vcpu = NULL;
1206 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1207 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1209 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1211 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1212 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1213 if (kvm_svm->avic_vm_id != vm_id)
1215 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1218 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1221 * At this point, the IOMMU should have already set the pending
1222 * bit in the vAPIC backing page. So, we just need to schedule
1226 kvm_vcpu_wake_up(vcpu);
1231 static __init int sev_hardware_setup(void)
1233 struct sev_user_data_status *status;
1236 /* Maximum number of encrypted guests supported simultaneously */
1237 max_sev_asid = cpuid_ecx(0x8000001F);
1242 /* Minimum ASID value that should be used for SEV guest */
1243 min_sev_asid = cpuid_edx(0x8000001F);
1245 /* Initialize SEV ASID bitmap */
1246 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1247 if (!sev_asid_bitmap)
1250 status = kmalloc(sizeof(*status), GFP_KERNEL);
1255 * Check SEV platform status.
1257 * PLATFORM_STATUS can be called in any state, if we failed to query
1258 * the PLATFORM status then either PSP firmware does not support SEV
1259 * feature or SEV firmware is dead.
1261 rc = sev_platform_status(status, NULL);
1265 pr_info("SEV supported\n");
1272 static void grow_ple_window(struct kvm_vcpu *vcpu)
1274 struct vcpu_svm *svm = to_svm(vcpu);
1275 struct vmcb_control_area *control = &svm->vmcb->control;
1276 int old = control->pause_filter_count;
1278 control->pause_filter_count = __grow_ple_window(old,
1280 pause_filter_count_grow,
1281 pause_filter_count_max);
1283 if (control->pause_filter_count != old)
1284 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1286 trace_kvm_ple_window_grow(vcpu->vcpu_id,
1287 control->pause_filter_count, old);
1290 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1292 struct vcpu_svm *svm = to_svm(vcpu);
1293 struct vmcb_control_area *control = &svm->vmcb->control;
1294 int old = control->pause_filter_count;
1296 control->pause_filter_count =
1297 __shrink_ple_window(old,
1299 pause_filter_count_shrink,
1300 pause_filter_count);
1301 if (control->pause_filter_count != old)
1302 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1304 trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1305 control->pause_filter_count, old);
1309 * The default MMIO mask is a single bit (excluding the present bit),
1310 * which could conflict with the memory encryption bit. Check for
1311 * memory encryption support and override the default MMIO mask if
1312 * memory encryption is enabled.
1314 static __init void svm_adjust_mmio_mask(void)
1316 unsigned int enc_bit, mask_bit;
1319 /* If there is no memory encryption support, use existing mask */
1320 if (cpuid_eax(0x80000000) < 0x8000001f)
1323 /* If memory encryption is not enabled, use existing mask */
1324 rdmsrl(MSR_K8_SYSCFG, msr);
1325 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
1328 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
1329 mask_bit = boot_cpu_data.x86_phys_bits;
1331 /* Increment the mask bit if it is the same as the encryption bit */
1332 if (enc_bit == mask_bit)
1336 * If the mask bit location is below 52, then some bits above the
1337 * physical addressing limit will always be reserved, so use the
1338 * rsvd_bits() function to generate the mask. This mask, along with
1339 * the present bit, will be used to generate a page fault with
1342 * If the mask bit location is 52 (or above), then clear the mask.
1344 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
1346 kvm_mmu_set_mmio_spte_mask(mask, mask);
1349 static __init int svm_hardware_setup(void)
1352 struct page *iopm_pages;
1356 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1361 iopm_va = page_address(iopm_pages);
1362 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1363 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1365 init_msrpm_offsets();
1367 if (boot_cpu_has(X86_FEATURE_NX))
1368 kvm_enable_efer_bits(EFER_NX);
1370 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1371 kvm_enable_efer_bits(EFER_FFXSR);
1373 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1374 kvm_has_tsc_control = true;
1375 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1376 kvm_tsc_scaling_ratio_frac_bits = 32;
1379 /* Check for pause filtering support */
1380 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1381 pause_filter_count = 0;
1382 pause_filter_thresh = 0;
1383 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1384 pause_filter_thresh = 0;
1388 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1389 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1393 if (boot_cpu_has(X86_FEATURE_SEV) &&
1394 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1395 r = sev_hardware_setup();
1403 svm_adjust_mmio_mask();
1405 for_each_possible_cpu(cpu) {
1406 r = svm_cpu_init(cpu);
1411 if (!boot_cpu_has(X86_FEATURE_NPT))
1412 npt_enabled = false;
1414 if (npt_enabled && !npt) {
1415 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1416 npt_enabled = false;
1420 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1427 !boot_cpu_has(X86_FEATURE_AVIC) ||
1428 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1431 pr_info("AVIC enabled\n");
1433 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1439 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1440 !IS_ENABLED(CONFIG_X86_64)) {
1443 pr_info("Virtual VMLOAD VMSAVE supported\n");
1447 vgif = false; /* Disabled for CVE-2021-3653 */
1452 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1457 static __exit void svm_hardware_unsetup(void)
1461 if (svm_sev_enabled())
1462 bitmap_free(sev_asid_bitmap);
1464 for_each_possible_cpu(cpu)
1465 svm_cpu_uninit(cpu);
1467 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1471 static void init_seg(struct vmcb_seg *seg)
1474 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1475 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1476 seg->limit = 0xffff;
1480 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1483 seg->attrib = SVM_SELECTOR_P_MASK | type;
1484 seg->limit = 0xffff;
1488 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1490 struct vcpu_svm *svm = to_svm(vcpu);
1492 if (is_guest_mode(vcpu))
1493 return svm->nested.hsave->control.tsc_offset;
1495 return vcpu->arch.tsc_offset;
1498 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1500 struct vcpu_svm *svm = to_svm(vcpu);
1501 u64 g_tsc_offset = 0;
1503 if (is_guest_mode(vcpu)) {
1504 /* Write L1's TSC offset. */
1505 g_tsc_offset = svm->vmcb->control.tsc_offset -
1506 svm->nested.hsave->control.tsc_offset;
1507 svm->nested.hsave->control.tsc_offset = offset;
1509 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1510 svm->vmcb->control.tsc_offset,
1513 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1515 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1516 return svm->vmcb->control.tsc_offset;
1519 static void avic_init_vmcb(struct vcpu_svm *svm)
1521 struct vmcb *vmcb = svm->vmcb;
1522 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1523 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1524 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1525 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1527 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1528 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1529 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1530 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1531 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1534 static void init_vmcb(struct vcpu_svm *svm)
1536 struct vmcb_control_area *control = &svm->vmcb->control;
1537 struct vmcb_save_area *save = &svm->vmcb->save;
1539 svm->vcpu.arch.hflags = 0;
1541 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1542 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1543 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1544 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1545 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1546 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1547 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1548 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1550 set_dr_intercepts(svm);
1552 set_exception_intercept(svm, PF_VECTOR);
1553 set_exception_intercept(svm, UD_VECTOR);
1554 set_exception_intercept(svm, MC_VECTOR);
1555 set_exception_intercept(svm, AC_VECTOR);
1556 set_exception_intercept(svm, DB_VECTOR);
1558 * Guest access to VMware backdoor ports could legitimately
1559 * trigger #GP because of TSS I/O permission bitmap.
1560 * We intercept those #GP and allow access to them anyway
1563 if (enable_vmware_backdoor)
1564 set_exception_intercept(svm, GP_VECTOR);
1566 set_intercept(svm, INTERCEPT_INTR);
1567 set_intercept(svm, INTERCEPT_NMI);
1568 set_intercept(svm, INTERCEPT_SMI);
1569 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1570 set_intercept(svm, INTERCEPT_RDPMC);
1571 set_intercept(svm, INTERCEPT_CPUID);
1572 set_intercept(svm, INTERCEPT_INVD);
1573 set_intercept(svm, INTERCEPT_INVLPG);
1574 set_intercept(svm, INTERCEPT_INVLPGA);
1575 set_intercept(svm, INTERCEPT_IOIO_PROT);
1576 set_intercept(svm, INTERCEPT_MSR_PROT);
1577 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1578 set_intercept(svm, INTERCEPT_SHUTDOWN);
1579 set_intercept(svm, INTERCEPT_VMRUN);
1580 set_intercept(svm, INTERCEPT_VMMCALL);
1581 set_intercept(svm, INTERCEPT_VMLOAD);
1582 set_intercept(svm, INTERCEPT_VMSAVE);
1583 set_intercept(svm, INTERCEPT_STGI);
1584 set_intercept(svm, INTERCEPT_CLGI);
1585 set_intercept(svm, INTERCEPT_SKINIT);
1586 set_intercept(svm, INTERCEPT_WBINVD);
1587 set_intercept(svm, INTERCEPT_XSETBV);
1588 set_intercept(svm, INTERCEPT_RSM);
1590 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1591 set_intercept(svm, INTERCEPT_MONITOR);
1592 set_intercept(svm, INTERCEPT_MWAIT);
1595 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1596 set_intercept(svm, INTERCEPT_HLT);
1598 control->iopm_base_pa = __sme_set(iopm_base);
1599 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1600 control->int_ctl = V_INTR_MASKING_MASK;
1602 init_seg(&save->es);
1603 init_seg(&save->ss);
1604 init_seg(&save->ds);
1605 init_seg(&save->fs);
1606 init_seg(&save->gs);
1608 save->cs.selector = 0xf000;
1609 save->cs.base = 0xffff0000;
1610 /* Executable/Readable Code Segment */
1611 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1612 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1613 save->cs.limit = 0xffff;
1615 save->gdtr.limit = 0xffff;
1616 save->idtr.limit = 0xffff;
1618 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1619 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1621 svm_set_efer(&svm->vcpu, 0);
1622 save->dr6 = 0xffff0ff0;
1623 kvm_set_rflags(&svm->vcpu, 2);
1624 save->rip = 0x0000fff0;
1625 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1628 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1629 * It also updates the guest-visible cr0 value.
1631 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1632 kvm_mmu_reset_context(&svm->vcpu);
1634 save->cr4 = X86_CR4_PAE;
1638 /* Setup VMCB for Nested Paging */
1639 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1640 clr_intercept(svm, INTERCEPT_INVLPG);
1641 clr_exception_intercept(svm, PF_VECTOR);
1642 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1643 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1644 save->g_pat = svm->vcpu.arch.pat;
1648 svm->asid_generation = 0;
1650 svm->nested.vmcb = 0;
1651 svm->vcpu.arch.hflags = 0;
1653 if (pause_filter_count) {
1654 control->pause_filter_count = pause_filter_count;
1655 if (pause_filter_thresh)
1656 control->pause_filter_thresh = pause_filter_thresh;
1657 set_intercept(svm, INTERCEPT_PAUSE);
1659 clr_intercept(svm, INTERCEPT_PAUSE);
1662 if (kvm_vcpu_apicv_active(&svm->vcpu))
1663 avic_init_vmcb(svm);
1666 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1667 * in VMCB and clear intercepts to avoid #VMEXIT.
1670 clr_intercept(svm, INTERCEPT_VMLOAD);
1671 clr_intercept(svm, INTERCEPT_VMSAVE);
1672 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1676 clr_intercept(svm, INTERCEPT_STGI);
1677 clr_intercept(svm, INTERCEPT_CLGI);
1678 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1681 if (sev_guest(svm->vcpu.kvm)) {
1682 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1683 clr_exception_intercept(svm, UD_VECTOR);
1686 mark_all_dirty(svm->vmcb);
1692 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1695 u64 *avic_physical_id_table;
1696 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1698 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1701 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1703 return &avic_physical_id_table[index];
1708 * AVIC hardware walks the nested page table to check permissions,
1709 * but does not use the SPA address specified in the leaf page
1710 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1711 * field of the VMCB. Therefore, we set up the
1712 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1714 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1716 struct kvm *kvm = vcpu->kvm;
1719 mutex_lock(&kvm->slots_lock);
1720 if (kvm->arch.apic_access_page_done)
1723 ret = __x86_set_memory_region(kvm,
1724 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1725 APIC_DEFAULT_PHYS_BASE,
1730 kvm->arch.apic_access_page_done = true;
1732 mutex_unlock(&kvm->slots_lock);
1736 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1739 u64 *entry, new_entry;
1740 int id = vcpu->vcpu_id;
1741 struct vcpu_svm *svm = to_svm(vcpu);
1743 ret = avic_init_access_page(vcpu);
1747 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1750 if (!svm->vcpu.arch.apic->regs)
1753 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1755 /* Setting AVIC backing page address in the phy APIC ID table */
1756 entry = avic_get_physical_id_entry(vcpu, id);
1760 new_entry = READ_ONCE(*entry);
1761 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1762 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1763 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1764 WRITE_ONCE(*entry, new_entry);
1766 svm->avic_physical_id_cache = entry;
1771 static void __sev_asid_free(int asid)
1773 struct svm_cpu_data *sd;
1777 clear_bit(pos, sev_asid_bitmap);
1779 for_each_possible_cpu(cpu) {
1780 sd = per_cpu(svm_data, cpu);
1781 sd->sev_vmcbs[asid] = NULL;
1785 static void sev_asid_free(struct kvm *kvm)
1787 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1789 __sev_asid_free(sev->asid);
1792 static void sev_decommission(unsigned int handle)
1794 struct sev_data_decommission *decommission;
1799 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1803 decommission->handle = handle;
1804 sev_guest_decommission(decommission, NULL);
1806 kfree(decommission);
1809 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1811 struct sev_data_deactivate *data;
1816 data = kzalloc(sizeof(*data), GFP_KERNEL);
1820 /* deactivate handle */
1821 data->handle = handle;
1822 sev_guest_deactivate(data, NULL);
1824 wbinvd_on_all_cpus();
1825 sev_guest_df_flush(NULL);
1828 sev_decommission(handle);
1831 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1832 unsigned long ulen, unsigned long *n,
1835 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1836 unsigned long npages, npinned, size;
1837 unsigned long locked, lock_limit;
1838 struct page **pages;
1839 unsigned long first, last;
1841 lockdep_assert_held(&kvm->lock);
1843 if (ulen == 0 || uaddr + ulen < uaddr)
1846 /* Calculate number of pages. */
1847 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1848 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1849 npages = (last - first + 1);
1851 locked = sev->pages_locked + npages;
1852 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1853 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1854 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1858 /* Avoid using vmalloc for smaller buffers. */
1859 size = npages * sizeof(struct page *);
1860 if (size > PAGE_SIZE)
1861 pages = vmalloc(size);
1863 pages = kmalloc(size, GFP_KERNEL);
1868 /* Pin the user virtual address. */
1869 npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1870 if (npinned != npages) {
1871 pr_err("SEV: Failure locking %lu pages.\n", npages);
1876 sev->pages_locked = locked;
1882 release_pages(pages, npinned);
1888 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1889 unsigned long npages)
1891 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1893 release_pages(pages, npages);
1895 sev->pages_locked -= npages;
1898 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1900 uint8_t *page_virtual;
1903 if (npages == 0 || pages == NULL)
1906 for (i = 0; i < npages; i++) {
1907 page_virtual = kmap_atomic(pages[i]);
1908 clflush_cache_range(page_virtual, PAGE_SIZE);
1909 kunmap_atomic(page_virtual);
1913 static void __unregister_enc_region_locked(struct kvm *kvm,
1914 struct enc_region *region)
1917 * The guest may change the memory encryption attribute from C=0 -> C=1
1918 * or vice versa for this memory range. Lets make sure caches are
1919 * flushed to ensure that guest data gets written into memory with
1922 sev_clflush_pages(region->pages, region->npages);
1924 sev_unpin_memory(kvm, region->pages, region->npages);
1925 list_del(®ion->list);
1929 static struct kvm *svm_vm_alloc(void)
1931 struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1936 return &kvm_svm->kvm;
1939 static void svm_vm_free(struct kvm *kvm)
1941 vfree(to_kvm_svm(kvm));
1944 static void sev_vm_destroy(struct kvm *kvm)
1946 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1947 struct list_head *head = &sev->regions_list;
1948 struct list_head *pos, *q;
1950 if (!sev_guest(kvm))
1953 mutex_lock(&kvm->lock);
1956 * if userspace was terminated before unregistering the memory regions
1957 * then lets unpin all the registered memory.
1959 if (!list_empty(head)) {
1960 list_for_each_safe(pos, q, head) {
1961 __unregister_enc_region_locked(kvm,
1962 list_entry(pos, struct enc_region, list));
1967 mutex_unlock(&kvm->lock);
1969 sev_unbind_asid(kvm, sev->handle);
1973 static void avic_vm_destroy(struct kvm *kvm)
1975 unsigned long flags;
1976 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1981 if (kvm_svm->avic_logical_id_table_page)
1982 __free_page(kvm_svm->avic_logical_id_table_page);
1983 if (kvm_svm->avic_physical_id_table_page)
1984 __free_page(kvm_svm->avic_physical_id_table_page);
1986 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1987 hash_del(&kvm_svm->hnode);
1988 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1991 static void svm_vm_destroy(struct kvm *kvm)
1993 avic_vm_destroy(kvm);
1994 sev_vm_destroy(kvm);
1997 static int avic_vm_init(struct kvm *kvm)
1999 unsigned long flags;
2001 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
2003 struct page *p_page;
2004 struct page *l_page;
2010 /* Allocating physical APIC ID table (4KB) */
2011 p_page = alloc_page(GFP_KERNEL);
2015 kvm_svm->avic_physical_id_table_page = p_page;
2016 clear_page(page_address(p_page));
2018 /* Allocating logical APIC ID table (4KB) */
2019 l_page = alloc_page(GFP_KERNEL);
2023 kvm_svm->avic_logical_id_table_page = l_page;
2024 clear_page(page_address(l_page));
2026 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2028 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
2029 if (vm_id == 0) { /* id is 1-based, zero is not okay */
2030 next_vm_id_wrapped = 1;
2033 /* Is it still in use? Only possible if wrapped at least once */
2034 if (next_vm_id_wrapped) {
2035 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
2036 if (k2->avic_vm_id == vm_id)
2040 kvm_svm->avic_vm_id = vm_id;
2041 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
2042 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2047 avic_vm_destroy(kvm);
2052 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2055 unsigned long flags;
2056 struct amd_svm_iommu_ir *ir;
2057 struct vcpu_svm *svm = to_svm(vcpu);
2059 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2063 * Here, we go through the per-vcpu ir_list to update all existing
2064 * interrupt remapping table entry targeting this vcpu.
2066 spin_lock_irqsave(&svm->ir_list_lock, flags);
2068 if (list_empty(&svm->ir_list))
2071 list_for_each_entry(ir, &svm->ir_list, node) {
2072 ret = amd_iommu_update_ga(cpu, r, ir->data);
2077 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2081 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2084 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2085 int h_physical_id = kvm_cpu_get_apicid(cpu);
2086 struct vcpu_svm *svm = to_svm(vcpu);
2088 if (!kvm_vcpu_apicv_active(vcpu))
2092 * Since the host physical APIC id is 8 bits,
2093 * we can support host APIC ID upto 255.
2095 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2098 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2099 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2101 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2102 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2104 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2105 if (svm->avic_is_running)
2106 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2108 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2109 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2110 svm->avic_is_running);
2113 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2116 struct vcpu_svm *svm = to_svm(vcpu);
2118 if (!kvm_vcpu_apicv_active(vcpu))
2121 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2122 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2123 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2125 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2126 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2130 * This function is called during VCPU halt/unhalt.
2132 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2134 struct vcpu_svm *svm = to_svm(vcpu);
2136 svm->avic_is_running = is_run;
2138 avic_vcpu_load(vcpu, vcpu->cpu);
2140 avic_vcpu_put(vcpu);
2143 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2145 struct vcpu_svm *svm = to_svm(vcpu);
2149 vcpu->arch.microcode_version = 0x01000065;
2151 svm->virt_spec_ctrl = 0;
2154 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2155 MSR_IA32_APICBASE_ENABLE;
2156 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2157 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2161 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2162 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2164 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2165 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2168 static int avic_init_vcpu(struct vcpu_svm *svm)
2172 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2175 ret = avic_init_backing_page(&svm->vcpu);
2179 INIT_LIST_HEAD(&svm->ir_list);
2180 spin_lock_init(&svm->ir_list_lock);
2185 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2187 struct vcpu_svm *svm;
2189 struct page *msrpm_pages;
2190 struct page *hsave_page;
2191 struct page *nested_msrpm_pages;
2194 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2200 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2205 page = alloc_page(GFP_KERNEL);
2209 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2213 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2214 if (!nested_msrpm_pages)
2217 hsave_page = alloc_page(GFP_KERNEL);
2221 err = avic_init_vcpu(svm);
2225 /* We initialize this flag to true to make sure that the is_running
2226 * bit would be set the first time the vcpu is loaded.
2228 svm->avic_is_running = true;
2230 svm->nested.hsave = page_address(hsave_page);
2232 svm->msrpm = page_address(msrpm_pages);
2233 svm_vcpu_init_msrpm(svm->msrpm);
2235 svm->nested.msrpm = page_address(nested_msrpm_pages);
2236 svm_vcpu_init_msrpm(svm->nested.msrpm);
2238 svm->vmcb = page_address(page);
2239 clear_page(svm->vmcb);
2240 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2241 svm->asid_generation = 0;
2244 svm_init_osvw(&svm->vcpu);
2249 __free_page(hsave_page);
2251 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2253 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2257 kvm_vcpu_uninit(&svm->vcpu);
2259 kmem_cache_free(kvm_vcpu_cache, svm);
2261 return ERR_PTR(err);
2264 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2268 for_each_online_cpu(i)
2269 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2272 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2274 struct vcpu_svm *svm = to_svm(vcpu);
2277 * The vmcb page can be recycled, causing a false negative in
2278 * svm_vcpu_load(). So, ensure that no logical CPU has this
2279 * vmcb page recorded as its current vmcb.
2281 svm_clear_current_vmcb(svm->vmcb);
2283 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2284 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2285 __free_page(virt_to_page(svm->nested.hsave));
2286 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2287 kvm_vcpu_uninit(vcpu);
2288 kmem_cache_free(kvm_vcpu_cache, svm);
2291 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2293 struct vcpu_svm *svm = to_svm(vcpu);
2294 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2297 if (unlikely(cpu != vcpu->cpu)) {
2298 svm->asid_generation = 0;
2299 mark_all_dirty(svm->vmcb);
2302 #ifdef CONFIG_X86_64
2303 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2305 savesegment(fs, svm->host.fs);
2306 savesegment(gs, svm->host.gs);
2307 svm->host.ldt = kvm_read_ldt();
2309 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2310 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2312 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2313 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2314 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2315 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2316 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2319 /* This assumes that the kernel never uses MSR_TSC_AUX */
2320 if (static_cpu_has(X86_FEATURE_RDTSCP))
2321 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2323 if (sd->current_vmcb != svm->vmcb) {
2324 sd->current_vmcb = svm->vmcb;
2325 indirect_branch_prediction_barrier();
2327 avic_vcpu_load(vcpu, cpu);
2330 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2332 struct vcpu_svm *svm = to_svm(vcpu);
2335 avic_vcpu_put(vcpu);
2337 ++vcpu->stat.host_state_reload;
2338 kvm_load_ldt(svm->host.ldt);
2339 #ifdef CONFIG_X86_64
2340 loadsegment(fs, svm->host.fs);
2341 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2342 load_gs_index(svm->host.gs);
2344 #ifdef CONFIG_X86_32_LAZY_GS
2345 loadsegment(gs, svm->host.gs);
2348 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2349 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2352 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2354 avic_set_running(vcpu, false);
2357 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2359 avic_set_running(vcpu, true);
2362 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2364 struct vcpu_svm *svm = to_svm(vcpu);
2365 unsigned long rflags = svm->vmcb->save.rflags;
2367 if (svm->nmi_singlestep) {
2368 /* Hide our flags if they were not set by the guest */
2369 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2370 rflags &= ~X86_EFLAGS_TF;
2371 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2372 rflags &= ~X86_EFLAGS_RF;
2377 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2379 if (to_svm(vcpu)->nmi_singlestep)
2380 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2383 * Any change of EFLAGS.VM is accompanied by a reload of SS
2384 * (caused by either a task switch or an inter-privilege IRET),
2385 * so we do not need to update the CPL here.
2387 to_svm(vcpu)->vmcb->save.rflags = rflags;
2390 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2393 case VCPU_EXREG_PDPTR:
2394 BUG_ON(!npt_enabled);
2395 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2402 static void svm_set_vintr(struct vcpu_svm *svm)
2404 set_intercept(svm, INTERCEPT_VINTR);
2407 static void svm_clear_vintr(struct vcpu_svm *svm)
2409 clr_intercept(svm, INTERCEPT_VINTR);
2412 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2414 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2417 case VCPU_SREG_CS: return &save->cs;
2418 case VCPU_SREG_DS: return &save->ds;
2419 case VCPU_SREG_ES: return &save->es;
2420 case VCPU_SREG_FS: return &save->fs;
2421 case VCPU_SREG_GS: return &save->gs;
2422 case VCPU_SREG_SS: return &save->ss;
2423 case VCPU_SREG_TR: return &save->tr;
2424 case VCPU_SREG_LDTR: return &save->ldtr;
2430 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2432 struct vmcb_seg *s = svm_seg(vcpu, seg);
2437 static void svm_get_segment(struct kvm_vcpu *vcpu,
2438 struct kvm_segment *var, int seg)
2440 struct vmcb_seg *s = svm_seg(vcpu, seg);
2442 var->base = s->base;
2443 var->limit = s->limit;
2444 var->selector = s->selector;
2445 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2446 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2447 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2448 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2449 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2450 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2451 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2454 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2455 * However, the SVM spec states that the G bit is not observed by the
2456 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2457 * So let's synthesize a legal G bit for all segments, this helps
2458 * running KVM nested. It also helps cross-vendor migration, because
2459 * Intel's vmentry has a check on the 'G' bit.
2461 var->g = s->limit > 0xfffff;
2464 * AMD's VMCB does not have an explicit unusable field, so emulate it
2465 * for cross vendor migration purposes by "not present"
2467 var->unusable = !var->present;
2472 * Work around a bug where the busy flag in the tr selector
2482 * The accessed bit must always be set in the segment
2483 * descriptor cache, although it can be cleared in the
2484 * descriptor, the cached bit always remains at 1. Since
2485 * Intel has a check on this, set it here to support
2486 * cross-vendor migration.
2493 * On AMD CPUs sometimes the DB bit in the segment
2494 * descriptor is left as 1, although the whole segment has
2495 * been made unusable. Clear it here to pass an Intel VMX
2496 * entry check when cross vendor migrating.
2500 /* This is symmetric with svm_set_segment() */
2501 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2506 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2508 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2513 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2515 struct vcpu_svm *svm = to_svm(vcpu);
2517 dt->size = svm->vmcb->save.idtr.limit;
2518 dt->address = svm->vmcb->save.idtr.base;
2521 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2523 struct vcpu_svm *svm = to_svm(vcpu);
2525 svm->vmcb->save.idtr.limit = dt->size;
2526 svm->vmcb->save.idtr.base = dt->address ;
2527 mark_dirty(svm->vmcb, VMCB_DT);
2530 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2532 struct vcpu_svm *svm = to_svm(vcpu);
2534 dt->size = svm->vmcb->save.gdtr.limit;
2535 dt->address = svm->vmcb->save.gdtr.base;
2538 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2540 struct vcpu_svm *svm = to_svm(vcpu);
2542 svm->vmcb->save.gdtr.limit = dt->size;
2543 svm->vmcb->save.gdtr.base = dt->address ;
2544 mark_dirty(svm->vmcb, VMCB_DT);
2547 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2551 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2555 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2559 static void update_cr0_intercept(struct vcpu_svm *svm)
2561 ulong gcr0 = svm->vcpu.arch.cr0;
2562 u64 *hcr0 = &svm->vmcb->save.cr0;
2564 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2565 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2567 mark_dirty(svm->vmcb, VMCB_CR);
2569 if (gcr0 == *hcr0) {
2570 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2571 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2573 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2574 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2578 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2580 struct vcpu_svm *svm = to_svm(vcpu);
2582 #ifdef CONFIG_X86_64
2583 if (vcpu->arch.efer & EFER_LME) {
2584 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2585 vcpu->arch.efer |= EFER_LMA;
2586 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2589 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2590 vcpu->arch.efer &= ~EFER_LMA;
2591 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2595 vcpu->arch.cr0 = cr0;
2598 cr0 |= X86_CR0_PG | X86_CR0_WP;
2601 * re-enable caching here because the QEMU bios
2602 * does not do it - this results in some delay at
2605 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2606 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2607 svm->vmcb->save.cr0 = cr0;
2608 mark_dirty(svm->vmcb, VMCB_CR);
2609 update_cr0_intercept(svm);
2612 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2614 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2615 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2617 if (cr4 & X86_CR4_VMXE)
2620 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2621 svm_flush_tlb(vcpu, true);
2623 vcpu->arch.cr4 = cr4;
2626 cr4 |= host_cr4_mce;
2627 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2628 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2632 static void svm_set_segment(struct kvm_vcpu *vcpu,
2633 struct kvm_segment *var, int seg)
2635 struct vcpu_svm *svm = to_svm(vcpu);
2636 struct vmcb_seg *s = svm_seg(vcpu, seg);
2638 s->base = var->base;
2639 s->limit = var->limit;
2640 s->selector = var->selector;
2641 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2642 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2643 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2644 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2645 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2646 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2647 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2648 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2651 * This is always accurate, except if SYSRET returned to a segment
2652 * with SS.DPL != 3. Intel does not have this quirk, and always
2653 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2654 * would entail passing the CPL to userspace and back.
2656 if (seg == VCPU_SREG_SS)
2657 /* This is symmetric with svm_get_segment() */
2658 svm->vmcb->save.cpl = (var->dpl & 3);
2660 mark_dirty(svm->vmcb, VMCB_SEG);
2663 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2665 struct vcpu_svm *svm = to_svm(vcpu);
2667 clr_exception_intercept(svm, BP_VECTOR);
2669 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2670 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2671 set_exception_intercept(svm, BP_VECTOR);
2673 vcpu->guest_debug = 0;
2676 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2678 if (sd->next_asid > sd->max_asid) {
2679 ++sd->asid_generation;
2680 sd->next_asid = sd->min_asid;
2681 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2684 svm->asid_generation = sd->asid_generation;
2685 svm->vmcb->control.asid = sd->next_asid++;
2687 mark_dirty(svm->vmcb, VMCB_ASID);
2690 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2692 return to_svm(vcpu)->vmcb->save.dr6;
2695 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2697 struct vcpu_svm *svm = to_svm(vcpu);
2699 svm->vmcb->save.dr6 = value;
2700 mark_dirty(svm->vmcb, VMCB_DR);
2703 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2705 struct vcpu_svm *svm = to_svm(vcpu);
2707 get_debugreg(vcpu->arch.db[0], 0);
2708 get_debugreg(vcpu->arch.db[1], 1);
2709 get_debugreg(vcpu->arch.db[2], 2);
2710 get_debugreg(vcpu->arch.db[3], 3);
2711 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2712 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2714 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2715 set_dr_intercepts(svm);
2718 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2720 struct vcpu_svm *svm = to_svm(vcpu);
2722 svm->vmcb->save.dr7 = value;
2723 mark_dirty(svm->vmcb, VMCB_DR);
2726 static int pf_interception(struct vcpu_svm *svm)
2728 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2729 u64 error_code = svm->vmcb->control.exit_info_1;
2731 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2732 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2733 svm->vmcb->control.insn_bytes : NULL,
2734 svm->vmcb->control.insn_len);
2737 static int npf_interception(struct vcpu_svm *svm)
2739 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2740 u64 error_code = svm->vmcb->control.exit_info_1;
2742 trace_kvm_page_fault(fault_address, error_code);
2743 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2744 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2745 svm->vmcb->control.insn_bytes : NULL,
2746 svm->vmcb->control.insn_len);
2749 static int db_interception(struct vcpu_svm *svm)
2751 struct kvm_run *kvm_run = svm->vcpu.run;
2752 struct kvm_vcpu *vcpu = &svm->vcpu;
2754 if (!(svm->vcpu.guest_debug &
2755 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2756 !svm->nmi_singlestep) {
2757 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2761 if (svm->nmi_singlestep) {
2762 disable_nmi_singlestep(svm);
2763 /* Make sure we check for pending NMIs upon entry */
2764 kvm_make_request(KVM_REQ_EVENT, vcpu);
2767 if (svm->vcpu.guest_debug &
2768 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2769 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2770 kvm_run->debug.arch.pc =
2771 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2772 kvm_run->debug.arch.exception = DB_VECTOR;
2779 static int bp_interception(struct vcpu_svm *svm)
2781 struct kvm_run *kvm_run = svm->vcpu.run;
2783 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2784 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2785 kvm_run->debug.arch.exception = BP_VECTOR;
2789 static int ud_interception(struct vcpu_svm *svm)
2791 return handle_ud(&svm->vcpu);
2794 static int ac_interception(struct vcpu_svm *svm)
2796 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2800 static int gp_interception(struct vcpu_svm *svm)
2802 struct kvm_vcpu *vcpu = &svm->vcpu;
2803 u32 error_code = svm->vmcb->control.exit_info_1;
2806 WARN_ON_ONCE(!enable_vmware_backdoor);
2808 er = kvm_emulate_instruction(vcpu,
2809 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2810 if (er == EMULATE_USER_EXIT)
2812 else if (er != EMULATE_DONE)
2813 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2817 static bool is_erratum_383(void)
2822 if (!erratum_383_found)
2825 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2829 /* Bit 62 may or may not be set for this mce */
2830 value &= ~(1ULL << 62);
2832 if (value != 0xb600000000010015ULL)
2835 /* Clear MCi_STATUS registers */
2836 for (i = 0; i < 6; ++i)
2837 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2839 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2843 value &= ~(1ULL << 2);
2844 low = lower_32_bits(value);
2845 high = upper_32_bits(value);
2847 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2850 /* Flush tlb to evict multi-match entries */
2856 static void svm_handle_mce(struct vcpu_svm *svm)
2858 if (is_erratum_383()) {
2860 * Erratum 383 triggered. Guest state is corrupt so kill the
2863 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2865 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2871 * On an #MC intercept the MCE handler is not called automatically in
2872 * the host. So do it by hand here.
2876 /* not sure if we ever come back to this point */
2881 static int mc_interception(struct vcpu_svm *svm)
2886 static int shutdown_interception(struct vcpu_svm *svm)
2888 struct kvm_run *kvm_run = svm->vcpu.run;
2891 * VMCB is undefined after a SHUTDOWN intercept
2892 * so reinitialize it.
2894 clear_page(svm->vmcb);
2897 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2901 static int io_interception(struct vcpu_svm *svm)
2903 struct kvm_vcpu *vcpu = &svm->vcpu;
2904 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2905 int size, in, string;
2908 ++svm->vcpu.stat.io_exits;
2909 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2910 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2912 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2914 port = io_info >> 16;
2915 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2916 svm->next_rip = svm->vmcb->control.exit_info_2;
2918 return kvm_fast_pio(&svm->vcpu, size, port, in);
2921 static int nmi_interception(struct vcpu_svm *svm)
2926 static int intr_interception(struct vcpu_svm *svm)
2928 ++svm->vcpu.stat.irq_exits;
2932 static int nop_on_interception(struct vcpu_svm *svm)
2937 static int halt_interception(struct vcpu_svm *svm)
2939 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2940 return kvm_emulate_halt(&svm->vcpu);
2943 static int vmmcall_interception(struct vcpu_svm *svm)
2945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2946 return kvm_emulate_hypercall(&svm->vcpu);
2949 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2951 struct vcpu_svm *svm = to_svm(vcpu);
2953 return svm->nested.nested_cr3;
2956 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2958 struct vcpu_svm *svm = to_svm(vcpu);
2959 u64 cr3 = svm->nested.nested_cr3;
2963 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2964 offset_in_page(cr3) + index * 8, 8);
2970 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2973 struct vcpu_svm *svm = to_svm(vcpu);
2975 svm->vmcb->control.nested_cr3 = __sme_set(root);
2976 mark_dirty(svm->vmcb, VMCB_NPT);
2979 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2980 struct x86_exception *fault)
2982 struct vcpu_svm *svm = to_svm(vcpu);
2984 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2986 * TODO: track the cause of the nested page fault, and
2987 * correctly fill in the high bits of exit_info_1.
2989 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2990 svm->vmcb->control.exit_code_hi = 0;
2991 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2992 svm->vmcb->control.exit_info_2 = fault->address;
2995 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2996 svm->vmcb->control.exit_info_1 |= fault->error_code;
2999 * The present bit is always zero for page structure faults on real
3002 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
3003 svm->vmcb->control.exit_info_1 &= ~1;
3005 nested_svm_vmexit(svm);
3008 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
3010 WARN_ON(mmu_is_nested(vcpu));
3011 kvm_init_shadow_mmu(vcpu);
3012 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
3013 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
3014 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
3015 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
3016 vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
3017 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
3018 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
3021 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
3023 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
3026 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3028 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3029 !is_paging(&svm->vcpu)) {
3030 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3034 if (svm->vmcb->save.cpl) {
3035 kvm_inject_gp(&svm->vcpu, 0);
3042 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3043 bool has_error_code, u32 error_code)
3047 if (!is_guest_mode(&svm->vcpu))
3050 vmexit = nested_svm_intercept(svm);
3051 if (vmexit != NESTED_EXIT_DONE)
3054 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3055 svm->vmcb->control.exit_code_hi = 0;
3056 svm->vmcb->control.exit_info_1 = error_code;
3059 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
3060 * The fix is to add the ancillary datum (CR2 or DR6) to structs
3061 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
3062 * written only when inject_pending_event runs (DR6 would written here
3063 * too). This should be conditional on a new capability---if the
3064 * capability is disabled, kvm_multiple_exception would write the
3065 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
3067 if (svm->vcpu.arch.exception.nested_apf)
3068 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3070 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3072 svm->nested.exit_required = true;
3076 /* This function returns true if it is save to enable the irq window */
3077 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3079 if (!is_guest_mode(&svm->vcpu))
3082 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3085 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3089 * if vmexit was already requested (by intercepted exception
3090 * for instance) do not overwrite it with "external interrupt"
3093 if (svm->nested.exit_required)
3096 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3097 svm->vmcb->control.exit_info_1 = 0;
3098 svm->vmcb->control.exit_info_2 = 0;
3100 if (svm->nested.intercept & 1ULL) {
3102 * The #vmexit can't be emulated here directly because this
3103 * code path runs with irqs and preemption disabled. A
3104 * #vmexit emulation might sleep. Only signal request for
3107 svm->nested.exit_required = true;
3108 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3115 /* This function returns true if it is save to enable the nmi window */
3116 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3118 if (!is_guest_mode(&svm->vcpu))
3121 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3124 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3125 svm->nested.exit_required = true;
3130 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3136 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3137 if (is_error_page(page))
3145 kvm_inject_gp(&svm->vcpu, 0);
3150 static void nested_svm_unmap(struct page *page)
3153 kvm_release_page_dirty(page);
3156 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3158 unsigned port, size, iopm_len;
3163 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3164 return NESTED_EXIT_HOST;
3166 port = svm->vmcb->control.exit_info_1 >> 16;
3167 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3168 SVM_IOIO_SIZE_SHIFT;
3169 gpa = svm->nested.vmcb_iopm + (port / 8);
3170 start_bit = port % 8;
3171 iopm_len = (start_bit + size > 8) ? 2 : 1;
3172 mask = (0xf >> (4 - size)) << start_bit;
3175 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3176 return NESTED_EXIT_DONE;
3178 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3181 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3183 u32 offset, msr, value;
3186 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3187 return NESTED_EXIT_HOST;
3189 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3190 offset = svm_msrpm_offset(msr);
3191 write = svm->vmcb->control.exit_info_1 & 1;
3192 mask = 1 << ((2 * (msr & 0xf)) + write);
3194 if (offset == MSR_INVALID)
3195 return NESTED_EXIT_DONE;
3197 /* Offset is in 32 bit units but need in 8 bit units */
3200 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3201 return NESTED_EXIT_DONE;
3203 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3206 /* DB exceptions for our internal use must not cause vmexit */
3207 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3211 /* if we're not singlestepping, it's not ours */
3212 if (!svm->nmi_singlestep)
3213 return NESTED_EXIT_DONE;
3215 /* if it's not a singlestep exception, it's not ours */
3216 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3217 return NESTED_EXIT_DONE;
3218 if (!(dr6 & DR6_BS))
3219 return NESTED_EXIT_DONE;
3221 /* if the guest is singlestepping, it should get the vmexit */
3222 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3223 disable_nmi_singlestep(svm);
3224 return NESTED_EXIT_DONE;
3227 /* it's ours, the nested hypervisor must not see this one */
3228 return NESTED_EXIT_HOST;
3231 static int nested_svm_exit_special(struct vcpu_svm *svm)
3233 u32 exit_code = svm->vmcb->control.exit_code;
3235 switch (exit_code) {
3238 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3239 return NESTED_EXIT_HOST;
3241 /* For now we are always handling NPFs when using them */
3243 return NESTED_EXIT_HOST;
3245 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3246 /* Trap async PF even if not shadowing */
3247 if (!npt_enabled || svm->vcpu.arch.apf.host_apf_reason)
3248 return NESTED_EXIT_HOST;
3254 return NESTED_EXIT_CONTINUE;
3258 * If this function returns true, this #vmexit was already handled
3260 static int nested_svm_intercept(struct vcpu_svm *svm)
3262 u32 exit_code = svm->vmcb->control.exit_code;
3263 int vmexit = NESTED_EXIT_HOST;
3265 switch (exit_code) {
3267 vmexit = nested_svm_exit_handled_msr(svm);
3270 vmexit = nested_svm_intercept_ioio(svm);
3272 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3273 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3274 if (svm->nested.intercept_cr & bit)
3275 vmexit = NESTED_EXIT_DONE;
3278 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3279 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3280 if (svm->nested.intercept_dr & bit)
3281 vmexit = NESTED_EXIT_DONE;
3284 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3285 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3286 if (svm->nested.intercept_exceptions & excp_bits) {
3287 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3288 vmexit = nested_svm_intercept_db(svm);
3290 vmexit = NESTED_EXIT_DONE;
3292 /* async page fault always cause vmexit */
3293 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3294 svm->vcpu.arch.exception.nested_apf != 0)
3295 vmexit = NESTED_EXIT_DONE;
3298 case SVM_EXIT_ERR: {
3299 vmexit = NESTED_EXIT_DONE;
3303 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3304 if (svm->nested.intercept & exit_bits)
3305 vmexit = NESTED_EXIT_DONE;
3312 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3316 vmexit = nested_svm_intercept(svm);
3318 if (vmexit == NESTED_EXIT_DONE)
3319 nested_svm_vmexit(svm);
3324 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3326 struct vmcb_control_area *dst = &dst_vmcb->control;
3327 struct vmcb_control_area *from = &from_vmcb->control;
3329 dst->intercept_cr = from->intercept_cr;
3330 dst->intercept_dr = from->intercept_dr;
3331 dst->intercept_exceptions = from->intercept_exceptions;
3332 dst->intercept = from->intercept;
3333 dst->iopm_base_pa = from->iopm_base_pa;
3334 dst->msrpm_base_pa = from->msrpm_base_pa;
3335 dst->tsc_offset = from->tsc_offset;
3336 /* asid not copied, it is handled manually for svm->vmcb. */
3337 dst->tlb_ctl = from->tlb_ctl;
3338 dst->int_ctl = from->int_ctl;
3339 dst->int_vector = from->int_vector;
3340 dst->int_state = from->int_state;
3341 dst->exit_code = from->exit_code;
3342 dst->exit_code_hi = from->exit_code_hi;
3343 dst->exit_info_1 = from->exit_info_1;
3344 dst->exit_info_2 = from->exit_info_2;
3345 dst->exit_int_info = from->exit_int_info;
3346 dst->exit_int_info_err = from->exit_int_info_err;
3347 dst->nested_ctl = from->nested_ctl;
3348 dst->event_inj = from->event_inj;
3349 dst->event_inj_err = from->event_inj_err;
3350 dst->nested_cr3 = from->nested_cr3;
3351 dst->virt_ext = from->virt_ext;
3354 static int nested_svm_vmexit(struct vcpu_svm *svm)
3356 struct vmcb *nested_vmcb;
3357 struct vmcb *hsave = svm->nested.hsave;
3358 struct vmcb *vmcb = svm->vmcb;
3361 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3362 vmcb->control.exit_info_1,
3363 vmcb->control.exit_info_2,
3364 vmcb->control.exit_int_info,
3365 vmcb->control.exit_int_info_err,
3368 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3372 /* Exit Guest-Mode */
3373 leave_guest_mode(&svm->vcpu);
3374 svm->nested.vmcb = 0;
3376 /* Give the current vmcb to the guest */
3379 nested_vmcb->save.es = vmcb->save.es;
3380 nested_vmcb->save.cs = vmcb->save.cs;
3381 nested_vmcb->save.ss = vmcb->save.ss;
3382 nested_vmcb->save.ds = vmcb->save.ds;
3383 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3384 nested_vmcb->save.idtr = vmcb->save.idtr;
3385 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3386 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3387 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3388 nested_vmcb->save.cr2 = vmcb->save.cr2;
3389 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3390 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3391 nested_vmcb->save.rip = vmcb->save.rip;
3392 nested_vmcb->save.rsp = vmcb->save.rsp;
3393 nested_vmcb->save.rax = vmcb->save.rax;
3394 nested_vmcb->save.dr7 = vmcb->save.dr7;
3395 nested_vmcb->save.dr6 = vmcb->save.dr6;
3396 nested_vmcb->save.cpl = vmcb->save.cpl;
3398 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3399 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3400 nested_vmcb->control.int_state = vmcb->control.int_state;
3401 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3402 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3403 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3404 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3405 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3406 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3408 if (svm->nrips_enabled)
3409 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3412 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3413 * to make sure that we do not lose injected events. So check event_inj
3414 * here and copy it to exit_int_info if it is valid.
3415 * Exit_int_info and event_inj can't be both valid because the case
3416 * below only happens on a VMRUN instruction intercept which has
3417 * no valid exit_int_info set.
3419 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3420 struct vmcb_control_area *nc = &nested_vmcb->control;
3422 nc->exit_int_info = vmcb->control.event_inj;
3423 nc->exit_int_info_err = vmcb->control.event_inj_err;
3426 nested_vmcb->control.tlb_ctl = 0;
3427 nested_vmcb->control.event_inj = 0;
3428 nested_vmcb->control.event_inj_err = 0;
3430 /* We always set V_INTR_MASKING and remember the old value in hflags */
3431 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3432 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3434 /* Restore the original control entries */
3435 copy_vmcb_control_area(vmcb, hsave);
3437 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3438 kvm_clear_exception_queue(&svm->vcpu);
3439 kvm_clear_interrupt_queue(&svm->vcpu);
3441 svm->nested.nested_cr3 = 0;
3443 /* Restore selected save entries */
3444 svm->vmcb->save.es = hsave->save.es;
3445 svm->vmcb->save.cs = hsave->save.cs;
3446 svm->vmcb->save.ss = hsave->save.ss;
3447 svm->vmcb->save.ds = hsave->save.ds;
3448 svm->vmcb->save.gdtr = hsave->save.gdtr;
3449 svm->vmcb->save.idtr = hsave->save.idtr;
3450 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3451 svm_set_efer(&svm->vcpu, hsave->save.efer);
3452 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3453 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3455 svm->vmcb->save.cr3 = hsave->save.cr3;
3456 svm->vcpu.arch.cr3 = hsave->save.cr3;
3458 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3460 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3461 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3462 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3463 svm->vmcb->save.dr7 = 0;
3464 svm->vmcb->save.cpl = 0;
3465 svm->vmcb->control.exit_int_info = 0;
3467 mark_all_dirty(svm->vmcb);
3469 nested_svm_unmap(page);
3471 nested_svm_uninit_mmu_context(&svm->vcpu);
3472 kvm_mmu_reset_context(&svm->vcpu);
3473 kvm_mmu_load(&svm->vcpu);
3476 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3477 * doesn't end up in L1.
3479 svm->vcpu.arch.nmi_injected = false;
3480 kvm_clear_exception_queue(&svm->vcpu);
3481 kvm_clear_interrupt_queue(&svm->vcpu);
3486 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3489 * This function merges the msr permission bitmaps of kvm and the
3490 * nested vmcb. It is optimized in that it only merges the parts where
3491 * the kvm msr permission bitmap may contain zero bits
3495 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3498 for (i = 0; i < MSRPM_OFFSETS; i++) {
3502 if (msrpm_offsets[i] == 0xffffffff)
3505 p = msrpm_offsets[i];
3506 offset = svm->nested.vmcb_msrpm + (p * 4);
3508 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3511 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3514 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3519 static bool nested_vmcb_checks(struct vmcb *vmcb)
3521 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3524 if (vmcb->control.asid == 0)
3527 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3534 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3535 struct vmcb *nested_vmcb, struct page *page)
3537 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3538 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3540 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3542 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3543 kvm_mmu_unload(&svm->vcpu);
3544 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3545 nested_svm_init_mmu_context(&svm->vcpu);
3548 /* Load the nested guest state */
3549 svm->vmcb->save.es = nested_vmcb->save.es;
3550 svm->vmcb->save.cs = nested_vmcb->save.cs;
3551 svm->vmcb->save.ss = nested_vmcb->save.ss;
3552 svm->vmcb->save.ds = nested_vmcb->save.ds;
3553 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3554 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3555 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3556 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3557 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3558 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3560 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3561 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3563 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3565 /* Guest paging mode is active - reset mmu */
3566 kvm_mmu_reset_context(&svm->vcpu);
3568 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3569 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3570 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3571 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3573 /* In case we don't even reach vcpu_run, the fields are not updated */
3574 svm->vmcb->save.rax = nested_vmcb->save.rax;
3575 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3576 svm->vmcb->save.rip = nested_vmcb->save.rip;
3577 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3578 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3579 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3581 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3582 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3584 /* cache intercepts */
3585 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3586 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3587 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3588 svm->nested.intercept = nested_vmcb->control.intercept;
3590 svm_flush_tlb(&svm->vcpu, true);
3592 svm->vmcb->control.int_ctl &=
3593 V_INTR_MASKING_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK;
3595 svm->vmcb->control.int_ctl |= nested_vmcb->control.int_ctl &
3596 (V_TPR_MASK | V_IRQ_INJECTION_BITS_MASK);
3598 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3599 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3601 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3603 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3604 /* We only want the cr8 intercept bits of the guest */
3605 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3606 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3609 /* We don't want to see VMMCALLs from a nested guest */
3610 clr_intercept(svm, INTERCEPT_VMMCALL);
3612 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3613 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3615 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3616 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3617 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3618 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3619 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3621 nested_svm_unmap(page);
3623 /* Enter Guest-Mode */
3624 enter_guest_mode(&svm->vcpu);
3627 * Merge guest and host intercepts - must be called with vcpu in
3628 * guest-mode to take affect here
3630 recalc_intercepts(svm);
3632 svm->nested.vmcb = vmcb_gpa;
3636 mark_all_dirty(svm->vmcb);
3639 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3641 struct vmcb *nested_vmcb;
3642 struct vmcb *hsave = svm->nested.hsave;
3643 struct vmcb *vmcb = svm->vmcb;
3647 vmcb_gpa = svm->vmcb->save.rax;
3649 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3653 if (!nested_vmcb_checks(nested_vmcb)) {
3654 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3655 nested_vmcb->control.exit_code_hi = 0;
3656 nested_vmcb->control.exit_info_1 = 0;
3657 nested_vmcb->control.exit_info_2 = 0;
3659 nested_svm_unmap(page);
3664 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3665 nested_vmcb->save.rip,
3666 nested_vmcb->control.int_ctl,
3667 nested_vmcb->control.event_inj,
3668 nested_vmcb->control.nested_ctl);
3670 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3671 nested_vmcb->control.intercept_cr >> 16,
3672 nested_vmcb->control.intercept_exceptions,
3673 nested_vmcb->control.intercept);
3675 /* Clear internal status */
3676 kvm_clear_exception_queue(&svm->vcpu);
3677 kvm_clear_interrupt_queue(&svm->vcpu);
3680 * Save the old vmcb, so we don't need to pick what we save, but can
3681 * restore everything when a VMEXIT occurs
3683 hsave->save.es = vmcb->save.es;
3684 hsave->save.cs = vmcb->save.cs;
3685 hsave->save.ss = vmcb->save.ss;
3686 hsave->save.ds = vmcb->save.ds;
3687 hsave->save.gdtr = vmcb->save.gdtr;
3688 hsave->save.idtr = vmcb->save.idtr;
3689 hsave->save.efer = svm->vcpu.arch.efer;
3690 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3691 hsave->save.cr4 = svm->vcpu.arch.cr4;
3692 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3693 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3694 hsave->save.rsp = vmcb->save.rsp;
3695 hsave->save.rax = vmcb->save.rax;
3697 hsave->save.cr3 = vmcb->save.cr3;
3699 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3701 copy_vmcb_control_area(hsave, vmcb);
3703 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3708 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3710 to_vmcb->save.fs = from_vmcb->save.fs;
3711 to_vmcb->save.gs = from_vmcb->save.gs;
3712 to_vmcb->save.tr = from_vmcb->save.tr;
3713 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3714 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3715 to_vmcb->save.star = from_vmcb->save.star;
3716 to_vmcb->save.lstar = from_vmcb->save.lstar;
3717 to_vmcb->save.cstar = from_vmcb->save.cstar;
3718 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3719 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3720 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3721 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3724 static int vmload_interception(struct vcpu_svm *svm)
3726 struct vmcb *nested_vmcb;
3730 if (nested_svm_check_permissions(svm))
3733 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3737 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3738 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3740 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3741 nested_svm_unmap(page);
3746 static int vmsave_interception(struct vcpu_svm *svm)
3748 struct vmcb *nested_vmcb;
3752 if (nested_svm_check_permissions(svm))
3755 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3759 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3760 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3762 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3763 nested_svm_unmap(page);
3768 static int vmrun_interception(struct vcpu_svm *svm)
3770 if (nested_svm_check_permissions(svm))
3773 /* Save rip after vmrun instruction */
3774 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3776 if (!nested_svm_vmrun(svm))
3779 if (!nested_svm_vmrun_msrpm(svm))
3786 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3787 svm->vmcb->control.exit_code_hi = 0;
3788 svm->vmcb->control.exit_info_1 = 0;
3789 svm->vmcb->control.exit_info_2 = 0;
3791 nested_svm_vmexit(svm);
3796 static int stgi_interception(struct vcpu_svm *svm)
3800 if (nested_svm_check_permissions(svm))
3804 * If VGIF is enabled, the STGI intercept is only added to
3805 * detect the opening of the SMI/NMI window; remove it now.
3807 if (vgif_enabled(svm))
3808 clr_intercept(svm, INTERCEPT_STGI);
3810 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3811 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3812 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3819 static int clgi_interception(struct vcpu_svm *svm)
3823 if (nested_svm_check_permissions(svm))
3826 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3827 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3831 /* After a CLGI no interrupts should come */
3832 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3833 svm_clear_vintr(svm);
3834 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3835 mark_dirty(svm->vmcb, VMCB_INTR);
3841 static int invlpga_interception(struct vcpu_svm *svm)
3843 struct kvm_vcpu *vcpu = &svm->vcpu;
3845 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3846 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3848 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3849 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3851 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3852 return kvm_skip_emulated_instruction(&svm->vcpu);
3855 static int skinit_interception(struct vcpu_svm *svm)
3857 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3859 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3863 static int wbinvd_interception(struct vcpu_svm *svm)
3865 return kvm_emulate_wbinvd(&svm->vcpu);
3868 static int xsetbv_interception(struct vcpu_svm *svm)
3870 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3871 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3873 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3874 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3875 return kvm_skip_emulated_instruction(&svm->vcpu);
3881 static int task_switch_interception(struct vcpu_svm *svm)
3885 int int_type = svm->vmcb->control.exit_int_info &
3886 SVM_EXITINTINFO_TYPE_MASK;
3887 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3889 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3891 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3892 bool has_error_code = false;
3895 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3897 if (svm->vmcb->control.exit_info_2 &
3898 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3899 reason = TASK_SWITCH_IRET;
3900 else if (svm->vmcb->control.exit_info_2 &
3901 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3902 reason = TASK_SWITCH_JMP;
3904 reason = TASK_SWITCH_GATE;
3906 reason = TASK_SWITCH_CALL;
3908 if (reason == TASK_SWITCH_GATE) {
3910 case SVM_EXITINTINFO_TYPE_NMI:
3911 svm->vcpu.arch.nmi_injected = false;
3913 case SVM_EXITINTINFO_TYPE_EXEPT:
3914 if (svm->vmcb->control.exit_info_2 &
3915 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3916 has_error_code = true;
3918 (u32)svm->vmcb->control.exit_info_2;
3920 kvm_clear_exception_queue(&svm->vcpu);
3922 case SVM_EXITINTINFO_TYPE_INTR:
3923 kvm_clear_interrupt_queue(&svm->vcpu);
3930 if (reason != TASK_SWITCH_GATE ||
3931 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3932 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3933 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3934 skip_emulated_instruction(&svm->vcpu);
3936 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3939 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3940 has_error_code, error_code) == EMULATE_FAIL) {
3941 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3942 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3943 svm->vcpu.run->internal.ndata = 0;
3949 static int cpuid_interception(struct vcpu_svm *svm)
3951 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3952 return kvm_emulate_cpuid(&svm->vcpu);
3955 static int iret_interception(struct vcpu_svm *svm)
3957 ++svm->vcpu.stat.nmi_window_exits;
3958 clr_intercept(svm, INTERCEPT_IRET);
3959 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3960 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3961 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3965 static int invd_interception(struct vcpu_svm *svm)
3967 /* Treat an INVD instruction as a NOP and just skip it. */
3968 return kvm_skip_emulated_instruction(&svm->vcpu);
3971 static int invlpg_interception(struct vcpu_svm *svm)
3973 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3974 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3976 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3977 return kvm_skip_emulated_instruction(&svm->vcpu);
3980 static int emulate_on_interception(struct vcpu_svm *svm)
3982 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3985 static int rsm_interception(struct vcpu_svm *svm)
3987 return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3988 rsm_ins_bytes, 2) == EMULATE_DONE;
3991 static int rdpmc_interception(struct vcpu_svm *svm)
3995 if (!static_cpu_has(X86_FEATURE_NRIPS))
3996 return emulate_on_interception(svm);
3998 err = kvm_rdpmc(&svm->vcpu);
3999 return kvm_complete_insn_gp(&svm->vcpu, err);
4002 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
4005 unsigned long cr0 = svm->vcpu.arch.cr0;
4009 intercept = svm->nested.intercept;
4011 if (!is_guest_mode(&svm->vcpu) ||
4012 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
4015 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
4016 val &= ~SVM_CR0_SELECTIVE_MASK;
4019 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4020 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
4026 #define CR_VALID (1ULL << 63)
4028 static int cr_interception(struct vcpu_svm *svm)
4034 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
4035 return emulate_on_interception(svm);
4037 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
4038 return emulate_on_interception(svm);
4040 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4041 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4042 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4044 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4047 if (cr >= 16) { /* mov to cr */
4049 val = kvm_register_readl(&svm->vcpu, reg);
4052 if (!check_selective_cr0_intercepted(svm, val))
4053 err = kvm_set_cr0(&svm->vcpu, val);
4059 err = kvm_set_cr3(&svm->vcpu, val);
4062 err = kvm_set_cr4(&svm->vcpu, val);
4065 err = kvm_set_cr8(&svm->vcpu, val);
4068 WARN(1, "unhandled write to CR%d", cr);
4069 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4072 } else { /* mov from cr */
4075 val = kvm_read_cr0(&svm->vcpu);
4078 val = svm->vcpu.arch.cr2;
4081 val = kvm_read_cr3(&svm->vcpu);
4084 val = kvm_read_cr4(&svm->vcpu);
4087 val = kvm_get_cr8(&svm->vcpu);
4090 WARN(1, "unhandled read from CR%d", cr);
4091 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4094 kvm_register_writel(&svm->vcpu, reg, val);
4096 return kvm_complete_insn_gp(&svm->vcpu, err);
4099 static int dr_interception(struct vcpu_svm *svm)
4104 if (svm->vcpu.guest_debug == 0) {
4106 * No more DR vmexits; force a reload of the debug registers
4107 * and reenter on this instruction. The next vmexit will
4108 * retrieve the full state of the debug registers.
4110 clr_dr_intercepts(svm);
4111 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4115 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4116 return emulate_on_interception(svm);
4118 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4119 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4121 if (dr >= 16) { /* mov to DRn */
4122 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4124 val = kvm_register_readl(&svm->vcpu, reg);
4125 kvm_set_dr(&svm->vcpu, dr - 16, val);
4127 if (!kvm_require_dr(&svm->vcpu, dr))
4129 kvm_get_dr(&svm->vcpu, dr, &val);
4130 kvm_register_writel(&svm->vcpu, reg, val);
4133 return kvm_skip_emulated_instruction(&svm->vcpu);
4136 static int cr8_write_interception(struct vcpu_svm *svm)
4138 struct kvm_run *kvm_run = svm->vcpu.run;
4141 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4142 /* instruction emulation calls kvm_set_cr8() */
4143 r = cr_interception(svm);
4144 if (lapic_in_kernel(&svm->vcpu))
4146 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4148 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4152 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4156 switch (msr->index) {
4157 case MSR_F10H_DECFG:
4158 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4159 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4168 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4170 struct vcpu_svm *svm = to_svm(vcpu);
4172 switch (msr_info->index) {
4174 msr_info->data = svm->vmcb->save.star;
4176 #ifdef CONFIG_X86_64
4178 msr_info->data = svm->vmcb->save.lstar;
4181 msr_info->data = svm->vmcb->save.cstar;
4183 case MSR_KERNEL_GS_BASE:
4184 msr_info->data = svm->vmcb->save.kernel_gs_base;
4186 case MSR_SYSCALL_MASK:
4187 msr_info->data = svm->vmcb->save.sfmask;
4190 case MSR_IA32_SYSENTER_CS:
4191 msr_info->data = svm->vmcb->save.sysenter_cs;
4193 case MSR_IA32_SYSENTER_EIP:
4194 msr_info->data = svm->sysenter_eip;
4196 case MSR_IA32_SYSENTER_ESP:
4197 msr_info->data = svm->sysenter_esp;
4200 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4202 msr_info->data = svm->tsc_aux;
4205 * Nobody will change the following 5 values in the VMCB so we can
4206 * safely return them on rdmsr. They will always be 0 until LBRV is
4209 case MSR_IA32_DEBUGCTLMSR:
4210 msr_info->data = svm->vmcb->save.dbgctl;
4212 case MSR_IA32_LASTBRANCHFROMIP:
4213 msr_info->data = svm->vmcb->save.br_from;
4215 case MSR_IA32_LASTBRANCHTOIP:
4216 msr_info->data = svm->vmcb->save.br_to;
4218 case MSR_IA32_LASTINTFROMIP:
4219 msr_info->data = svm->vmcb->save.last_excp_from;
4221 case MSR_IA32_LASTINTTOIP:
4222 msr_info->data = svm->vmcb->save.last_excp_to;
4224 case MSR_VM_HSAVE_PA:
4225 msr_info->data = svm->nested.hsave_msr;
4228 msr_info->data = svm->nested.vm_cr_msr;
4230 case MSR_IA32_SPEC_CTRL:
4231 if (!msr_info->host_initiated &&
4232 !guest_has_spec_ctrl_msr(vcpu))
4235 msr_info->data = svm->spec_ctrl;
4237 case MSR_AMD64_VIRT_SPEC_CTRL:
4238 if (!msr_info->host_initiated &&
4239 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4242 msr_info->data = svm->virt_spec_ctrl;
4244 case MSR_F15H_IC_CFG: {
4248 family = guest_cpuid_family(vcpu);
4249 model = guest_cpuid_model(vcpu);
4251 if (family < 0 || model < 0)
4252 return kvm_get_msr_common(vcpu, msr_info);
4256 if (family == 0x15 &&
4257 (model >= 0x2 && model < 0x20))
4258 msr_info->data = 0x1E;
4261 case MSR_F10H_DECFG:
4262 msr_info->data = svm->msr_decfg;
4265 return kvm_get_msr_common(vcpu, msr_info);
4270 static int rdmsr_interception(struct vcpu_svm *svm)
4272 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4273 struct msr_data msr_info;
4275 msr_info.index = ecx;
4276 msr_info.host_initiated = false;
4277 if (svm_get_msr(&svm->vcpu, &msr_info)) {
4278 trace_kvm_msr_read_ex(ecx);
4279 kvm_inject_gp(&svm->vcpu, 0);
4282 trace_kvm_msr_read(ecx, msr_info.data);
4284 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4285 msr_info.data & 0xffffffff);
4286 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4287 msr_info.data >> 32);
4288 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4289 return kvm_skip_emulated_instruction(&svm->vcpu);
4293 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4295 struct vcpu_svm *svm = to_svm(vcpu);
4296 int svm_dis, chg_mask;
4298 if (data & ~SVM_VM_CR_VALID_MASK)
4301 chg_mask = SVM_VM_CR_VALID_MASK;
4303 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4304 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4306 svm->nested.vm_cr_msr &= ~chg_mask;
4307 svm->nested.vm_cr_msr |= (data & chg_mask);
4309 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4311 /* check for svm_disable while efer.svme is set */
4312 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4318 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4320 struct vcpu_svm *svm = to_svm(vcpu);
4322 u32 ecx = msr->index;
4323 u64 data = msr->data;
4325 case MSR_IA32_CR_PAT:
4326 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4328 vcpu->arch.pat = data;
4329 svm->vmcb->save.g_pat = data;
4330 mark_dirty(svm->vmcb, VMCB_NPT);
4332 case MSR_IA32_SPEC_CTRL:
4333 if (!msr->host_initiated &&
4334 !guest_has_spec_ctrl_msr(vcpu))
4337 /* The STIBP bit doesn't fault even if it's not advertised */
4338 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4341 svm->spec_ctrl = data;
4348 * When it's written (to non-zero) for the first time, pass
4352 * The handling of the MSR bitmap for L2 guests is done in
4353 * nested_svm_vmrun_msrpm.
4354 * We update the L1 MSR bit as well since it will end up
4355 * touching the MSR anyway now.
4357 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4359 case MSR_IA32_PRED_CMD:
4360 if (!msr->host_initiated &&
4361 !guest_has_pred_cmd_msr(vcpu))
4364 if (data & ~PRED_CMD_IBPB)
4369 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4370 if (is_guest_mode(vcpu))
4372 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4374 case MSR_AMD64_VIRT_SPEC_CTRL:
4375 if (!msr->host_initiated &&
4376 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4379 if (data & ~SPEC_CTRL_SSBD)
4382 svm->virt_spec_ctrl = data;
4385 svm->vmcb->save.star = data;
4387 #ifdef CONFIG_X86_64
4389 svm->vmcb->save.lstar = data;
4392 svm->vmcb->save.cstar = data;
4394 case MSR_KERNEL_GS_BASE:
4395 svm->vmcb->save.kernel_gs_base = data;
4397 case MSR_SYSCALL_MASK:
4398 svm->vmcb->save.sfmask = data;
4401 case MSR_IA32_SYSENTER_CS:
4402 svm->vmcb->save.sysenter_cs = data;
4404 case MSR_IA32_SYSENTER_EIP:
4405 svm->sysenter_eip = data;
4406 svm->vmcb->save.sysenter_eip = data;
4408 case MSR_IA32_SYSENTER_ESP:
4409 svm->sysenter_esp = data;
4410 svm->vmcb->save.sysenter_esp = data;
4413 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4417 * This is rare, so we update the MSR here instead of using
4418 * direct_access_msrs. Doing that would require a rdmsr in
4421 svm->tsc_aux = data;
4422 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4424 case MSR_IA32_DEBUGCTLMSR:
4425 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4426 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4430 if (data & DEBUGCTL_RESERVED_BITS)
4433 svm->vmcb->save.dbgctl = data;
4434 mark_dirty(svm->vmcb, VMCB_LBR);
4435 if (data & (1ULL<<0))
4436 svm_enable_lbrv(svm);
4438 svm_disable_lbrv(svm);
4440 case MSR_VM_HSAVE_PA:
4441 svm->nested.hsave_msr = data;
4444 return svm_set_vm_cr(vcpu, data);
4446 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4448 case MSR_F10H_DECFG: {
4449 struct kvm_msr_entry msr_entry;
4451 msr_entry.index = msr->index;
4452 if (svm_get_msr_feature(&msr_entry))
4455 /* Check the supported bits */
4456 if (data & ~msr_entry.data)
4459 /* Don't allow the guest to change a bit, #GP */
4460 if (!msr->host_initiated && (data ^ msr_entry.data))
4463 svm->msr_decfg = data;
4466 case MSR_IA32_APICBASE:
4467 if (kvm_vcpu_apicv_active(vcpu))
4468 avic_update_vapic_bar(to_svm(vcpu), data);
4469 /* Follow through */
4471 return kvm_set_msr_common(vcpu, msr);
4476 static int wrmsr_interception(struct vcpu_svm *svm)
4478 struct msr_data msr;
4479 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4480 u64 data = kvm_read_edx_eax(&svm->vcpu);
4484 msr.host_initiated = false;
4486 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4487 if (kvm_set_msr(&svm->vcpu, &msr)) {
4488 trace_kvm_msr_write_ex(ecx, data);
4489 kvm_inject_gp(&svm->vcpu, 0);
4492 trace_kvm_msr_write(ecx, data);
4493 return kvm_skip_emulated_instruction(&svm->vcpu);
4497 static int msr_interception(struct vcpu_svm *svm)
4499 if (svm->vmcb->control.exit_info_1)
4500 return wrmsr_interception(svm);
4502 return rdmsr_interception(svm);
4505 static int interrupt_window_interception(struct vcpu_svm *svm)
4507 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4508 svm_clear_vintr(svm);
4509 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4510 mark_dirty(svm->vmcb, VMCB_INTR);
4511 ++svm->vcpu.stat.irq_window_exits;
4515 static int pause_interception(struct vcpu_svm *svm)
4517 struct kvm_vcpu *vcpu = &svm->vcpu;
4518 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4520 if (pause_filter_thresh)
4521 grow_ple_window(vcpu);
4523 kvm_vcpu_on_spin(vcpu, in_kernel);
4527 static int nop_interception(struct vcpu_svm *svm)
4529 return kvm_skip_emulated_instruction(&(svm->vcpu));
4532 static int monitor_interception(struct vcpu_svm *svm)
4534 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4535 return nop_interception(svm);
4538 static int mwait_interception(struct vcpu_svm *svm)
4540 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4541 return nop_interception(svm);
4544 enum avic_ipi_failure_cause {
4545 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4546 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4547 AVIC_IPI_FAILURE_INVALID_TARGET,
4548 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4551 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4553 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4554 u32 icrl = svm->vmcb->control.exit_info_1;
4555 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4556 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4557 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4559 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4562 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4564 * AVIC hardware handles the generation of
4565 * IPIs when the specified Message Type is Fixed
4566 * (also known as fixed delivery mode) and
4567 * the Trigger Mode is edge-triggered. The hardware
4568 * also supports self and broadcast delivery modes
4569 * specified via the Destination Shorthand(DSH)
4570 * field of the ICRL. Logical and physical APIC ID
4571 * formats are supported. All other IPI types cause
4572 * a #VMEXIT, which needs to emulated.
4574 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4575 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4577 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4579 struct kvm_vcpu *vcpu;
4580 struct kvm *kvm = svm->vcpu.kvm;
4581 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4584 * At this point, we expect that the AVIC HW has already
4585 * set the appropriate IRR bits on the valid target
4586 * vcpus. So, we just need to kick the appropriate vcpu.
4588 kvm_for_each_vcpu(i, vcpu, kvm) {
4589 bool m = kvm_apic_match_dest(vcpu, apic,
4590 icrl & KVM_APIC_SHORT_MASK,
4591 GET_APIC_DEST_FIELD(icrh),
4592 icrl & KVM_APIC_DEST_MASK);
4594 if (m && !avic_vcpu_is_running(vcpu))
4595 kvm_vcpu_wake_up(vcpu);
4599 case AVIC_IPI_FAILURE_INVALID_TARGET:
4601 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4602 WARN_ONCE(1, "Invalid backing page\n");
4605 pr_err("Unknown IPI interception\n");
4611 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4613 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4615 u32 *logical_apic_id_table;
4616 int dlid = GET_APIC_LOGICAL_ID(ldr);
4621 if (flat) { /* flat */
4622 index = ffs(dlid) - 1;
4625 } else { /* cluster */
4626 int cluster = (dlid & 0xf0) >> 4;
4627 int apic = ffs(dlid & 0x0f) - 1;
4629 if ((apic < 0) || (apic > 7) ||
4632 index = (cluster << 2) + apic;
4635 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4637 return &logical_apic_id_table[index];
4640 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4644 u32 *entry, new_entry;
4646 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4647 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4651 new_entry = READ_ONCE(*entry);
4652 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4653 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4655 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4657 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4658 WRITE_ONCE(*entry, new_entry);
4663 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4666 struct vcpu_svm *svm = to_svm(vcpu);
4667 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4672 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4673 if (ret && svm->ldr_reg) {
4674 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4682 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4685 struct vcpu_svm *svm = to_svm(vcpu);
4686 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4687 u32 id = (apic_id_reg >> 24) & 0xff;
4689 if (vcpu->vcpu_id == id)
4692 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4693 new = avic_get_physical_id_entry(vcpu, id);
4697 /* We need to move physical_id_entry to new offset */
4700 to_svm(vcpu)->avic_physical_id_cache = new;
4703 * Also update the guest physical APIC ID in the logical
4704 * APIC ID table entry if already setup the LDR.
4707 avic_handle_ldr_update(vcpu);
4712 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4714 struct vcpu_svm *svm = to_svm(vcpu);
4715 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4716 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4717 u32 mod = (dfr >> 28) & 0xf;
4720 * We assume that all local APICs are using the same type.
4721 * If this changes, we need to flush the AVIC logical
4724 if (kvm_svm->ldr_mode == mod)
4727 clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4728 kvm_svm->ldr_mode = mod;
4731 avic_handle_ldr_update(vcpu);
4735 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4737 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4738 u32 offset = svm->vmcb->control.exit_info_1 &
4739 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4743 if (avic_handle_apic_id_update(&svm->vcpu))
4747 if (avic_handle_ldr_update(&svm->vcpu))
4751 avic_handle_dfr_update(&svm->vcpu);
4757 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4762 static bool is_avic_unaccelerated_access_trap(u32 offset)
4791 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4794 u32 offset = svm->vmcb->control.exit_info_1 &
4795 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4796 u32 vector = svm->vmcb->control.exit_info_2 &
4797 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4798 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4799 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4800 bool trap = is_avic_unaccelerated_access_trap(offset);
4802 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4803 trap, write, vector);
4806 WARN_ONCE(!write, "svm: Handling trap read.\n");
4807 ret = avic_unaccel_trap_write(svm);
4809 /* Handling Fault */
4810 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4816 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4817 [SVM_EXIT_READ_CR0] = cr_interception,
4818 [SVM_EXIT_READ_CR3] = cr_interception,
4819 [SVM_EXIT_READ_CR4] = cr_interception,
4820 [SVM_EXIT_READ_CR8] = cr_interception,
4821 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4822 [SVM_EXIT_WRITE_CR0] = cr_interception,
4823 [SVM_EXIT_WRITE_CR3] = cr_interception,
4824 [SVM_EXIT_WRITE_CR4] = cr_interception,
4825 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4826 [SVM_EXIT_READ_DR0] = dr_interception,
4827 [SVM_EXIT_READ_DR1] = dr_interception,
4828 [SVM_EXIT_READ_DR2] = dr_interception,
4829 [SVM_EXIT_READ_DR3] = dr_interception,
4830 [SVM_EXIT_READ_DR4] = dr_interception,
4831 [SVM_EXIT_READ_DR5] = dr_interception,
4832 [SVM_EXIT_READ_DR6] = dr_interception,
4833 [SVM_EXIT_READ_DR7] = dr_interception,
4834 [SVM_EXIT_WRITE_DR0] = dr_interception,
4835 [SVM_EXIT_WRITE_DR1] = dr_interception,
4836 [SVM_EXIT_WRITE_DR2] = dr_interception,
4837 [SVM_EXIT_WRITE_DR3] = dr_interception,
4838 [SVM_EXIT_WRITE_DR4] = dr_interception,
4839 [SVM_EXIT_WRITE_DR5] = dr_interception,
4840 [SVM_EXIT_WRITE_DR6] = dr_interception,
4841 [SVM_EXIT_WRITE_DR7] = dr_interception,
4842 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4843 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4844 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4845 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4846 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4847 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4848 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4849 [SVM_EXIT_INTR] = intr_interception,
4850 [SVM_EXIT_NMI] = nmi_interception,
4851 [SVM_EXIT_SMI] = nop_on_interception,
4852 [SVM_EXIT_INIT] = nop_on_interception,
4853 [SVM_EXIT_VINTR] = interrupt_window_interception,
4854 [SVM_EXIT_RDPMC] = rdpmc_interception,
4855 [SVM_EXIT_CPUID] = cpuid_interception,
4856 [SVM_EXIT_IRET] = iret_interception,
4857 [SVM_EXIT_INVD] = invd_interception,
4858 [SVM_EXIT_PAUSE] = pause_interception,
4859 [SVM_EXIT_HLT] = halt_interception,
4860 [SVM_EXIT_INVLPG] = invlpg_interception,
4861 [SVM_EXIT_INVLPGA] = invlpga_interception,
4862 [SVM_EXIT_IOIO] = io_interception,
4863 [SVM_EXIT_MSR] = msr_interception,
4864 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4865 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4866 [SVM_EXIT_VMRUN] = vmrun_interception,
4867 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4868 [SVM_EXIT_VMLOAD] = vmload_interception,
4869 [SVM_EXIT_VMSAVE] = vmsave_interception,
4870 [SVM_EXIT_STGI] = stgi_interception,
4871 [SVM_EXIT_CLGI] = clgi_interception,
4872 [SVM_EXIT_SKINIT] = skinit_interception,
4873 [SVM_EXIT_WBINVD] = wbinvd_interception,
4874 [SVM_EXIT_MONITOR] = monitor_interception,
4875 [SVM_EXIT_MWAIT] = mwait_interception,
4876 [SVM_EXIT_XSETBV] = xsetbv_interception,
4877 [SVM_EXIT_NPF] = npf_interception,
4878 [SVM_EXIT_RSM] = rsm_interception,
4879 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4880 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4883 static void dump_vmcb(struct kvm_vcpu *vcpu)
4885 struct vcpu_svm *svm = to_svm(vcpu);
4886 struct vmcb_control_area *control = &svm->vmcb->control;
4887 struct vmcb_save_area *save = &svm->vmcb->save;
4889 pr_err("VMCB Control Area:\n");
4890 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4891 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4892 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4893 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4894 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4895 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4896 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4897 pr_err("%-20s%d\n", "pause filter threshold:",
4898 control->pause_filter_thresh);
4899 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4900 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4901 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4902 pr_err("%-20s%d\n", "asid:", control->asid);
4903 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4904 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4905 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4906 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4907 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4908 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4909 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4910 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4911 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4912 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4913 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4914 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4915 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4916 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4917 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4918 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4919 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4920 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4921 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4922 pr_err("VMCB State Save Area:\n");
4923 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4925 save->es.selector, save->es.attrib,
4926 save->es.limit, save->es.base);
4927 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4929 save->cs.selector, save->cs.attrib,
4930 save->cs.limit, save->cs.base);
4931 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4933 save->ss.selector, save->ss.attrib,
4934 save->ss.limit, save->ss.base);
4935 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4937 save->ds.selector, save->ds.attrib,
4938 save->ds.limit, save->ds.base);
4939 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4941 save->fs.selector, save->fs.attrib,
4942 save->fs.limit, save->fs.base);
4943 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4945 save->gs.selector, save->gs.attrib,
4946 save->gs.limit, save->gs.base);
4947 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4949 save->gdtr.selector, save->gdtr.attrib,
4950 save->gdtr.limit, save->gdtr.base);
4951 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4953 save->ldtr.selector, save->ldtr.attrib,
4954 save->ldtr.limit, save->ldtr.base);
4955 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4957 save->idtr.selector, save->idtr.attrib,
4958 save->idtr.limit, save->idtr.base);
4959 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4961 save->tr.selector, save->tr.attrib,
4962 save->tr.limit, save->tr.base);
4963 pr_err("cpl: %d efer: %016llx\n",
4964 save->cpl, save->efer);
4965 pr_err("%-15s %016llx %-13s %016llx\n",
4966 "cr0:", save->cr0, "cr2:", save->cr2);
4967 pr_err("%-15s %016llx %-13s %016llx\n",
4968 "cr3:", save->cr3, "cr4:", save->cr4);
4969 pr_err("%-15s %016llx %-13s %016llx\n",
4970 "dr6:", save->dr6, "dr7:", save->dr7);
4971 pr_err("%-15s %016llx %-13s %016llx\n",
4972 "rip:", save->rip, "rflags:", save->rflags);
4973 pr_err("%-15s %016llx %-13s %016llx\n",
4974 "rsp:", save->rsp, "rax:", save->rax);
4975 pr_err("%-15s %016llx %-13s %016llx\n",
4976 "star:", save->star, "lstar:", save->lstar);
4977 pr_err("%-15s %016llx %-13s %016llx\n",
4978 "cstar:", save->cstar, "sfmask:", save->sfmask);
4979 pr_err("%-15s %016llx %-13s %016llx\n",
4980 "kernel_gs_base:", save->kernel_gs_base,
4981 "sysenter_cs:", save->sysenter_cs);
4982 pr_err("%-15s %016llx %-13s %016llx\n",
4983 "sysenter_esp:", save->sysenter_esp,
4984 "sysenter_eip:", save->sysenter_eip);
4985 pr_err("%-15s %016llx %-13s %016llx\n",
4986 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4987 pr_err("%-15s %016llx %-13s %016llx\n",
4988 "br_from:", save->br_from, "br_to:", save->br_to);
4989 pr_err("%-15s %016llx %-13s %016llx\n",
4990 "excp_from:", save->last_excp_from,
4991 "excp_to:", save->last_excp_to);
4994 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4996 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4998 *info1 = control->exit_info_1;
4999 *info2 = control->exit_info_2;
5002 static int handle_exit(struct kvm_vcpu *vcpu)
5004 struct vcpu_svm *svm = to_svm(vcpu);
5005 struct kvm_run *kvm_run = vcpu->run;
5006 u32 exit_code = svm->vmcb->control.exit_code;
5008 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
5010 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
5011 vcpu->arch.cr0 = svm->vmcb->save.cr0;
5013 vcpu->arch.cr3 = svm->vmcb->save.cr3;
5015 if (unlikely(svm->nested.exit_required)) {
5016 nested_svm_vmexit(svm);
5017 svm->nested.exit_required = false;
5022 if (is_guest_mode(vcpu)) {
5025 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
5026 svm->vmcb->control.exit_info_1,
5027 svm->vmcb->control.exit_info_2,
5028 svm->vmcb->control.exit_int_info,
5029 svm->vmcb->control.exit_int_info_err,
5032 vmexit = nested_svm_exit_special(svm);
5034 if (vmexit == NESTED_EXIT_CONTINUE)
5035 vmexit = nested_svm_exit_handled(svm);
5037 if (vmexit == NESTED_EXIT_DONE)
5041 svm_complete_interrupts(svm);
5043 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
5044 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5045 kvm_run->fail_entry.hardware_entry_failure_reason
5046 = svm->vmcb->control.exit_code;
5047 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
5052 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5053 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5054 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5055 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5056 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5058 __func__, svm->vmcb->control.exit_int_info,
5061 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5062 || !svm_exit_handlers[exit_code]) {
5063 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
5064 kvm_queue_exception(vcpu, UD_VECTOR);
5068 return svm_exit_handlers[exit_code](svm);
5071 static void reload_tss(struct kvm_vcpu *vcpu)
5073 int cpu = raw_smp_processor_id();
5075 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5076 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5080 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5082 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5083 int asid = sev_get_asid(svm->vcpu.kvm);
5085 /* Assign the asid allocated with this SEV guest */
5086 svm->vmcb->control.asid = asid;
5091 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5092 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5094 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5095 svm->last_cpu == cpu)
5098 svm->last_cpu = cpu;
5099 sd->sev_vmcbs[asid] = svm->vmcb;
5100 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5101 mark_dirty(svm->vmcb, VMCB_ASID);
5104 static void pre_svm_run(struct vcpu_svm *svm)
5106 int cpu = raw_smp_processor_id();
5108 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5110 if (sev_guest(svm->vcpu.kvm))
5111 return pre_sev_run(svm, cpu);
5113 /* FIXME: handle wraparound of asid_generation */
5114 if (svm->asid_generation != sd->asid_generation)
5118 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5120 struct vcpu_svm *svm = to_svm(vcpu);
5122 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5123 vcpu->arch.hflags |= HF_NMI_MASK;
5124 set_intercept(svm, INTERCEPT_IRET);
5125 ++vcpu->stat.nmi_injections;
5128 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5130 struct vmcb_control_area *control;
5132 /* The following fields are ignored when AVIC is enabled */
5133 control = &svm->vmcb->control;
5134 control->int_vector = irq;
5135 control->int_ctl &= ~V_INTR_PRIO_MASK;
5136 control->int_ctl |= V_IRQ_MASK |
5137 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5138 mark_dirty(svm->vmcb, VMCB_INTR);
5141 static void svm_set_irq(struct kvm_vcpu *vcpu)
5143 struct vcpu_svm *svm = to_svm(vcpu);
5145 BUG_ON(!(gif_set(svm)));
5147 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5148 ++vcpu->stat.irq_injections;
5150 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5151 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5154 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5156 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5159 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5161 struct vcpu_svm *svm = to_svm(vcpu);
5163 if (svm_nested_virtualize_tpr(vcpu) ||
5164 kvm_vcpu_apicv_active(vcpu))
5167 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5173 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5176 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5181 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5183 return avic && irqchip_split(vcpu->kvm);
5186 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5190 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5194 /* Note: Currently only used by Hyper-V. */
5195 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5197 struct vcpu_svm *svm = to_svm(vcpu);
5198 struct vmcb *vmcb = svm->vmcb;
5200 if (!kvm_vcpu_apicv_active(&svm->vcpu))
5203 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5204 mark_dirty(vmcb, VMCB_INTR);
5207 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5212 static int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5214 if (!vcpu->arch.apicv_active)
5217 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5218 smp_mb__after_atomic();
5220 if (avic_vcpu_is_running(vcpu))
5221 wrmsrl(SVM_AVIC_DOORBELL,
5222 kvm_cpu_get_apicid(vcpu->cpu));
5224 kvm_vcpu_wake_up(vcpu);
5229 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5234 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5236 unsigned long flags;
5237 struct amd_svm_iommu_ir *cur;
5239 spin_lock_irqsave(&svm->ir_list_lock, flags);
5240 list_for_each_entry(cur, &svm->ir_list, node) {
5241 if (cur->data != pi->ir_data)
5243 list_del(&cur->node);
5247 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5250 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5253 unsigned long flags;
5254 struct amd_svm_iommu_ir *ir;
5257 * In some cases, the existing irte is updaed and re-set,
5258 * so we need to check here if it's already been * added
5261 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5262 struct kvm *kvm = svm->vcpu.kvm;
5263 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5264 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5265 struct vcpu_svm *prev_svm;
5272 prev_svm = to_svm(prev_vcpu);
5273 svm_ir_list_del(prev_svm, pi);
5277 * Allocating new amd_iommu_pi_data, which will get
5278 * add to the per-vcpu ir_list.
5280 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5285 ir->data = pi->ir_data;
5287 spin_lock_irqsave(&svm->ir_list_lock, flags);
5288 list_add(&ir->node, &svm->ir_list);
5289 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5296 * The HW cannot support posting multicast/broadcast
5297 * interrupts to a vCPU. So, we still use legacy interrupt
5298 * remapping for these kind of interrupts.
5300 * For lowest-priority interrupts, we only support
5301 * those with single CPU as the destination, e.g. user
5302 * configures the interrupts via /proc/irq or uses
5303 * irqbalance to make the interrupts single-CPU.
5306 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5307 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5309 struct kvm_lapic_irq irq;
5310 struct kvm_vcpu *vcpu = NULL;
5312 kvm_set_msi_irq(kvm, e, &irq);
5314 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5315 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5316 __func__, irq.vector);
5320 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5322 *svm = to_svm(vcpu);
5323 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5324 vcpu_info->vector = irq.vector;
5330 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5333 * @host_irq: host irq of the interrupt
5334 * @guest_irq: gsi of the interrupt
5335 * @set: set or unset PI
5336 * returns 0 on success, < 0 on failure
5338 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5339 uint32_t guest_irq, bool set)
5341 struct kvm_kernel_irq_routing_entry *e;
5342 struct kvm_irq_routing_table *irq_rt;
5343 int idx, ret = -EINVAL;
5345 if (!kvm_arch_has_assigned_device(kvm) ||
5346 !irq_remapping_cap(IRQ_POSTING_CAP))
5349 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5350 __func__, host_irq, guest_irq, set);
5352 idx = srcu_read_lock(&kvm->irq_srcu);
5353 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5354 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5356 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5357 struct vcpu_data vcpu_info;
5358 struct vcpu_svm *svm = NULL;
5360 if (e->type != KVM_IRQ_ROUTING_MSI)
5364 * Here, we setup with legacy mode in the following cases:
5365 * 1. When cannot target interrupt to a specific vcpu.
5366 * 2. Unsetting posted interrupt.
5367 * 3. APIC virtialization is disabled for the vcpu.
5369 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5370 kvm_vcpu_apicv_active(&svm->vcpu)) {
5371 struct amd_iommu_pi_data pi;
5373 /* Try to enable guest_mode in IRTE */
5374 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5376 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5378 pi.is_guest_mode = true;
5379 pi.vcpu_data = &vcpu_info;
5380 ret = irq_set_vcpu_affinity(host_irq, &pi);
5383 * Here, we successfully setting up vcpu affinity in
5384 * IOMMU guest mode. Now, we need to store the posted
5385 * interrupt information in a per-vcpu ir_list so that
5386 * we can reference to them directly when we update vcpu
5387 * scheduling information in IOMMU irte.
5389 if (!ret && pi.is_guest_mode)
5390 svm_ir_list_add(svm, &pi);
5392 /* Use legacy mode in IRTE */
5393 struct amd_iommu_pi_data pi;
5396 * Here, pi is used to:
5397 * - Tell IOMMU to use legacy mode for this interrupt.
5398 * - Retrieve ga_tag of prior interrupt remapping data.
5401 pi.is_guest_mode = false;
5402 ret = irq_set_vcpu_affinity(host_irq, &pi);
5405 * Check if the posted interrupt was previously
5406 * setup with the guest_mode by checking if the ga_tag
5407 * was cached. If so, we need to clean up the per-vcpu
5410 if (!ret && pi.prev_ga_tag) {
5411 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5412 struct kvm_vcpu *vcpu;
5414 vcpu = kvm_get_vcpu_by_id(kvm, id);
5416 svm_ir_list_del(to_svm(vcpu), &pi);
5421 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5422 e->gsi, vcpu_info.vector,
5423 vcpu_info.pi_desc_addr, set);
5427 pr_err("%s: failed to update PI IRTE\n", __func__);
5434 srcu_read_unlock(&kvm->irq_srcu, idx);
5438 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5440 struct vcpu_svm *svm = to_svm(vcpu);
5441 struct vmcb *vmcb = svm->vmcb;
5443 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5444 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5445 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5450 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5452 struct vcpu_svm *svm = to_svm(vcpu);
5454 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5457 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5459 struct vcpu_svm *svm = to_svm(vcpu);
5462 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5463 set_intercept(svm, INTERCEPT_IRET);
5465 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5466 clr_intercept(svm, INTERCEPT_IRET);
5470 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5472 struct vcpu_svm *svm = to_svm(vcpu);
5473 struct vmcb *vmcb = svm->vmcb;
5476 if (!gif_set(svm) ||
5477 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5480 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5482 if (is_guest_mode(vcpu))
5483 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5488 static void enable_irq_window(struct kvm_vcpu *vcpu)
5490 struct vcpu_svm *svm = to_svm(vcpu);
5492 if (kvm_vcpu_apicv_active(vcpu))
5496 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5497 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5498 * get that intercept, this function will be called again though and
5499 * we'll get the vintr intercept. However, if the vGIF feature is
5500 * enabled, the STGI interception will not occur. Enable the irq
5501 * window under the assumption that the hardware will set the GIF.
5503 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5505 svm_inject_irq(svm, 0x0);
5509 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5511 struct vcpu_svm *svm = to_svm(vcpu);
5513 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5515 return; /* IRET will cause a vm exit */
5517 if (!gif_set(svm)) {
5518 if (vgif_enabled(svm))
5519 set_intercept(svm, INTERCEPT_STGI);
5520 return; /* STGI will cause a vm exit */
5523 if (svm->nested.exit_required)
5524 return; /* we're not going to run the guest yet */
5527 * Something prevents NMI from been injected. Single step over possible
5528 * problem (IRET or exception injection or interrupt shadow)
5530 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5531 svm->nmi_singlestep = true;
5532 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5535 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5540 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5545 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5547 struct vcpu_svm *svm = to_svm(vcpu);
5549 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5550 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5552 svm->asid_generation--;
5555 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5557 struct vcpu_svm *svm = to_svm(vcpu);
5559 invlpga(gva, svm->vmcb->control.asid);
5562 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5566 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5568 struct vcpu_svm *svm = to_svm(vcpu);
5570 if (svm_nested_virtualize_tpr(vcpu))
5573 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5574 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5575 kvm_set_cr8(vcpu, cr8);
5579 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5581 struct vcpu_svm *svm = to_svm(vcpu);
5584 if (svm_nested_virtualize_tpr(vcpu) ||
5585 kvm_vcpu_apicv_active(vcpu))
5588 cr8 = kvm_get_cr8(vcpu);
5589 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5590 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5593 static void svm_complete_interrupts(struct vcpu_svm *svm)
5597 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5598 unsigned int3_injected = svm->int3_injected;
5600 svm->int3_injected = 0;
5603 * If we've made progress since setting HF_IRET_MASK, we've
5604 * executed an IRET and can allow NMI injection.
5606 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5607 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5608 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5609 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5612 svm->vcpu.arch.nmi_injected = false;
5613 kvm_clear_exception_queue(&svm->vcpu);
5614 kvm_clear_interrupt_queue(&svm->vcpu);
5616 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5619 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5621 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5622 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5625 case SVM_EXITINTINFO_TYPE_NMI:
5626 svm->vcpu.arch.nmi_injected = true;
5628 case SVM_EXITINTINFO_TYPE_EXEPT:
5630 * In case of software exceptions, do not reinject the vector,
5631 * but re-execute the instruction instead. Rewind RIP first
5632 * if we emulated INT3 before.
5634 if (kvm_exception_is_soft(vector)) {
5635 if (vector == BP_VECTOR && int3_injected &&
5636 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5637 kvm_rip_write(&svm->vcpu,
5638 kvm_rip_read(&svm->vcpu) -
5642 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5643 u32 err = svm->vmcb->control.exit_int_info_err;
5644 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5647 kvm_requeue_exception(&svm->vcpu, vector);
5649 case SVM_EXITINTINFO_TYPE_INTR:
5650 kvm_queue_interrupt(&svm->vcpu, vector, false);
5657 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5659 struct vcpu_svm *svm = to_svm(vcpu);
5660 struct vmcb_control_area *control = &svm->vmcb->control;
5662 control->exit_int_info = control->event_inj;
5663 control->exit_int_info_err = control->event_inj_err;
5664 control->event_inj = 0;
5665 svm_complete_interrupts(svm);
5668 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5670 struct vcpu_svm *svm = to_svm(vcpu);
5672 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5673 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5674 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5677 * A vmexit emulation is required before the vcpu can be executed
5680 if (unlikely(svm->nested.exit_required))
5684 * Disable singlestep if we're injecting an interrupt/exception.
5685 * We don't want our modified rflags to be pushed on the stack where
5686 * we might not be able to easily reset them if we disabled NMI
5689 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5691 * Event injection happens before external interrupts cause a
5692 * vmexit and interrupts are disabled here, so smp_send_reschedule
5693 * is enough to force an immediate vmexit.
5695 disable_nmi_singlestep(svm);
5696 smp_send_reschedule(vcpu->cpu);
5701 sync_lapic_to_cr8(vcpu);
5703 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5706 kvm_load_guest_xcr0(vcpu);
5709 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5710 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5711 * is no need to worry about the conditional branch over the wrmsr
5712 * being speculatively taken.
5714 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5719 "push %%" _ASM_BP "; \n\t"
5720 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5721 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5722 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5723 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5724 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5725 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5726 #ifdef CONFIG_X86_64
5727 "mov %c[r8](%[svm]), %%r8 \n\t"
5728 "mov %c[r9](%[svm]), %%r9 \n\t"
5729 "mov %c[r10](%[svm]), %%r10 \n\t"
5730 "mov %c[r11](%[svm]), %%r11 \n\t"
5731 "mov %c[r12](%[svm]), %%r12 \n\t"
5732 "mov %c[r13](%[svm]), %%r13 \n\t"
5733 "mov %c[r14](%[svm]), %%r14 \n\t"
5734 "mov %c[r15](%[svm]), %%r15 \n\t"
5737 /* Enter guest mode */
5738 "push %%" _ASM_AX " \n\t"
5739 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5740 __ex(SVM_VMLOAD) "\n\t"
5741 __ex(SVM_VMRUN) "\n\t"
5742 __ex(SVM_VMSAVE) "\n\t"
5743 "pop %%" _ASM_AX " \n\t"
5745 /* Save guest registers, load host registers */
5746 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5747 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5748 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5749 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5750 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5751 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5752 #ifdef CONFIG_X86_64
5753 "mov %%r8, %c[r8](%[svm]) \n\t"
5754 "mov %%r9, %c[r9](%[svm]) \n\t"
5755 "mov %%r10, %c[r10](%[svm]) \n\t"
5756 "mov %%r11, %c[r11](%[svm]) \n\t"
5757 "mov %%r12, %c[r12](%[svm]) \n\t"
5758 "mov %%r13, %c[r13](%[svm]) \n\t"
5759 "mov %%r14, %c[r14](%[svm]) \n\t"
5760 "mov %%r15, %c[r15](%[svm]) \n\t"
5763 * Clear host registers marked as clobbered to prevent
5766 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5767 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5768 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5769 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5770 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5771 #ifdef CONFIG_X86_64
5772 "xor %%r8, %%r8 \n\t"
5773 "xor %%r9, %%r9 \n\t"
5774 "xor %%r10, %%r10 \n\t"
5775 "xor %%r11, %%r11 \n\t"
5776 "xor %%r12, %%r12 \n\t"
5777 "xor %%r13, %%r13 \n\t"
5778 "xor %%r14, %%r14 \n\t"
5779 "xor %%r15, %%r15 \n\t"
5784 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5785 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5786 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5787 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5788 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5789 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5790 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5791 #ifdef CONFIG_X86_64
5792 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5793 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5794 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5795 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5796 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5797 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5798 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5799 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5802 #ifdef CONFIG_X86_64
5803 , "rbx", "rcx", "rdx", "rsi", "rdi"
5804 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5806 , "ebx", "ecx", "edx", "esi", "edi"
5810 /* Eliminate branch target predictions from guest mode */
5813 #ifdef CONFIG_X86_64
5814 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5816 loadsegment(fs, svm->host.fs);
5817 #ifndef CONFIG_X86_32_LAZY_GS
5818 loadsegment(gs, svm->host.gs);
5823 * We do not use IBRS in the kernel. If this vCPU has used the
5824 * SPEC_CTRL MSR it may have left it on; save the value and
5825 * turn it off. This is much more efficient than blindly adding
5826 * it to the atomic save/restore list. Especially as the former
5827 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5829 * For non-nested case:
5830 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5834 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5837 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5838 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5842 local_irq_disable();
5844 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5846 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5847 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5848 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5849 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5851 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5852 kvm_before_interrupt(&svm->vcpu);
5854 kvm_put_guest_xcr0(vcpu);
5857 /* Any pending NMI will happen here */
5859 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5860 kvm_after_interrupt(&svm->vcpu);
5862 sync_cr8_to_lapic(vcpu);
5866 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5868 /* if exit due to PF check for async PF */
5869 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5870 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5873 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5874 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5878 * We need to handle MC intercepts here before the vcpu has a chance to
5879 * change the physical cpu
5881 if (unlikely(svm->vmcb->control.exit_code ==
5882 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5883 svm_handle_mce(svm);
5885 mark_all_clean(svm->vmcb);
5887 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5889 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5891 struct vcpu_svm *svm = to_svm(vcpu);
5893 svm->vmcb->save.cr3 = __sme_set(root);
5894 mark_dirty(svm->vmcb, VMCB_CR);
5897 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5899 struct vcpu_svm *svm = to_svm(vcpu);
5901 svm->vmcb->control.nested_cr3 = __sme_set(root);
5902 mark_dirty(svm->vmcb, VMCB_NPT);
5904 /* Also sync guest cr3 here in case we live migrate */
5905 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5906 mark_dirty(svm->vmcb, VMCB_CR);
5909 static int is_disabled(void)
5913 rdmsrl(MSR_VM_CR, vm_cr);
5914 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5921 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5924 * Patch in the VMMCALL instruction:
5926 hypercall[0] = 0x0f;
5927 hypercall[1] = 0x01;
5928 hypercall[2] = 0xd9;
5931 static void svm_check_processor_compat(void *rtn)
5936 static bool svm_cpu_has_accelerated_tpr(void)
5941 static bool svm_has_emulated_msr(int index)
5944 case MSR_IA32_MCG_EXT_CTL:
5953 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5958 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5960 struct vcpu_svm *svm = to_svm(vcpu);
5962 /* Update nrips enabled cache */
5963 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5965 if (!kvm_vcpu_apicv_active(vcpu))
5968 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5971 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5976 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5980 entry->ecx |= (1 << 2); /* Set SVM bit */
5983 entry->eax = 1; /* SVM revision 1 */
5984 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5985 ASID emulation to nested SVM */
5986 entry->ecx = 0; /* Reserved */
5987 entry->edx = 0; /* Per default do not support any
5988 additional features */
5990 /* Support next_rip if host supports it */
5991 if (boot_cpu_has(X86_FEATURE_NRIPS))
5992 entry->edx |= SVM_FEATURE_NRIP;
5994 /* Support NPT for the guest if enabled */
5996 entry->edx |= SVM_FEATURE_NPT;
6000 /* Support memory encryption cpuid if host supports it */
6001 if (boot_cpu_has(X86_FEATURE_SEV))
6002 cpuid(0x8000001f, &entry->eax, &entry->ebx,
6003 &entry->ecx, &entry->edx);
6008 static int svm_get_lpage_level(void)
6010 return PT_PDPE_LEVEL;
6013 static bool svm_rdtscp_supported(void)
6015 return boot_cpu_has(X86_FEATURE_RDTSCP);
6018 static bool svm_invpcid_supported(void)
6023 static bool svm_mpx_supported(void)
6028 static bool svm_xsaves_supported(void)
6033 static bool svm_umip_emulated(void)
6038 static bool svm_has_wbinvd_exit(void)
6043 #define PRE_EX(exit) { .exit_code = (exit), \
6044 .stage = X86_ICPT_PRE_EXCEPT, }
6045 #define POST_EX(exit) { .exit_code = (exit), \
6046 .stage = X86_ICPT_POST_EXCEPT, }
6047 #define POST_MEM(exit) { .exit_code = (exit), \
6048 .stage = X86_ICPT_POST_MEMACCESS, }
6050 static const struct __x86_intercept {
6052 enum x86_intercept_stage stage;
6053 } x86_intercept_map[] = {
6054 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6055 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6056 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6057 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6058 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6059 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6060 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6061 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6062 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6063 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6064 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6065 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6066 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6067 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6068 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6069 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6070 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6071 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6072 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6073 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6074 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6075 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6076 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6077 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6078 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6079 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6080 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6081 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6082 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6083 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6084 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6085 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6086 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6087 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6088 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6089 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6090 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6091 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6092 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6093 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6094 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6095 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6096 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6097 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6098 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6099 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6106 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6107 struct x86_instruction_info *info,
6108 enum x86_intercept_stage stage)
6110 struct vcpu_svm *svm = to_svm(vcpu);
6111 int vmexit, ret = X86EMUL_CONTINUE;
6112 struct __x86_intercept icpt_info;
6113 struct vmcb *vmcb = svm->vmcb;
6115 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6118 icpt_info = x86_intercept_map[info->intercept];
6120 if (stage != icpt_info.stage)
6123 switch (icpt_info.exit_code) {
6124 case SVM_EXIT_READ_CR0:
6125 if (info->intercept == x86_intercept_cr_read)
6126 icpt_info.exit_code += info->modrm_reg;
6128 case SVM_EXIT_WRITE_CR0: {
6129 unsigned long cr0, val;
6132 if (info->intercept == x86_intercept_cr_write)
6133 icpt_info.exit_code += info->modrm_reg;
6135 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6136 info->intercept == x86_intercept_clts)
6139 intercept = svm->nested.intercept;
6141 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6144 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6145 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6147 if (info->intercept == x86_intercept_lmsw) {
6150 /* lmsw can't clear PE - catch this here */
6151 if (cr0 & X86_CR0_PE)
6156 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6160 case SVM_EXIT_READ_DR0:
6161 case SVM_EXIT_WRITE_DR0:
6162 icpt_info.exit_code += info->modrm_reg;
6165 if (info->intercept == x86_intercept_wrmsr)
6166 vmcb->control.exit_info_1 = 1;
6168 vmcb->control.exit_info_1 = 0;
6170 case SVM_EXIT_PAUSE:
6172 * We get this for NOP only, but pause
6173 * is rep not, check this here
6175 if (info->rep_prefix != REPE_PREFIX)
6178 case SVM_EXIT_IOIO: {
6182 if (info->intercept == x86_intercept_in ||
6183 info->intercept == x86_intercept_ins) {
6184 exit_info = ((info->src_val & 0xffff) << 16) |
6186 bytes = info->dst_bytes;
6188 exit_info = (info->dst_val & 0xffff) << 16;
6189 bytes = info->src_bytes;
6192 if (info->intercept == x86_intercept_outs ||
6193 info->intercept == x86_intercept_ins)
6194 exit_info |= SVM_IOIO_STR_MASK;
6196 if (info->rep_prefix)
6197 exit_info |= SVM_IOIO_REP_MASK;
6199 bytes = min(bytes, 4u);
6201 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6203 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6205 vmcb->control.exit_info_1 = exit_info;
6206 vmcb->control.exit_info_2 = info->next_rip;
6214 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6215 if (static_cpu_has(X86_FEATURE_NRIPS))
6216 vmcb->control.next_rip = info->next_rip;
6217 vmcb->control.exit_code = icpt_info.exit_code;
6218 vmexit = nested_svm_exit_handled(svm);
6220 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6227 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6231 * We must have an instruction with interrupts enabled, so
6232 * the timer interrupt isn't delayed by the interrupt shadow.
6235 local_irq_disable();
6238 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6240 if (pause_filter_thresh)
6241 shrink_ple_window(vcpu);
6244 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6246 if (avic_handle_apic_id_update(vcpu) != 0)
6248 if (avic_handle_dfr_update(vcpu) != 0)
6250 avic_handle_ldr_update(vcpu);
6253 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6255 /* [63:9] are reserved. */
6256 vcpu->arch.mcg_cap &= 0x1ff;
6259 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6261 struct vcpu_svm *svm = to_svm(vcpu);
6263 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6267 if (is_guest_mode(&svm->vcpu) &&
6268 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6269 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6270 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6271 svm->nested.exit_required = true;
6278 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6280 struct vcpu_svm *svm = to_svm(vcpu);
6283 if (is_guest_mode(vcpu)) {
6284 /* FED8h - SVM Guest */
6285 put_smstate(u64, smstate, 0x7ed8, 1);
6286 /* FEE0h - SVM Guest VMCB Physical Address */
6287 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6289 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6290 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6291 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6293 ret = nested_svm_vmexit(svm);
6300 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6302 struct vcpu_svm *svm = to_svm(vcpu);
6303 struct vmcb *nested_vmcb;
6311 ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6312 sizeof(svm_state_save));
6316 if (svm_state_save.guest) {
6317 vcpu->arch.hflags &= ~HF_SMM_MASK;
6318 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6320 enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6323 vcpu->arch.hflags |= HF_SMM_MASK;
6328 static int enable_smi_window(struct kvm_vcpu *vcpu)
6330 struct vcpu_svm *svm = to_svm(vcpu);
6332 if (!gif_set(svm)) {
6333 if (vgif_enabled(svm))
6334 set_intercept(svm, INTERCEPT_STGI);
6335 /* STGI will cause a vm exit */
6341 static int sev_asid_new(void)
6346 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6348 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6349 if (pos >= max_sev_asid)
6352 set_bit(pos, sev_asid_bitmap);
6356 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6358 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6362 if (unlikely(sev->active))
6365 asid = sev_asid_new();
6369 ret = sev_platform_init(&argp->error);
6375 INIT_LIST_HEAD(&sev->regions_list);
6380 __sev_asid_free(asid);
6384 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6386 struct sev_data_activate *data;
6387 int asid = sev_get_asid(kvm);
6390 wbinvd_on_all_cpus();
6392 ret = sev_guest_df_flush(error);
6396 data = kzalloc(sizeof(*data), GFP_KERNEL);
6400 /* activate ASID on the given handle */
6401 data->handle = handle;
6403 ret = sev_guest_activate(data, error);
6409 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6418 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6424 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6426 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6428 return __sev_issue_cmd(sev->fd, id, data, error);
6431 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6433 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6434 struct sev_data_launch_start *start;
6435 struct kvm_sev_launch_start params;
6436 void *dh_blob, *session_blob;
6437 int *error = &argp->error;
6440 if (!sev_guest(kvm))
6443 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6446 start = kzalloc(sizeof(*start), GFP_KERNEL);
6451 if (params.dh_uaddr) {
6452 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6453 if (IS_ERR(dh_blob)) {
6454 ret = PTR_ERR(dh_blob);
6458 start->dh_cert_address = __sme_set(__pa(dh_blob));
6459 start->dh_cert_len = params.dh_len;
6462 session_blob = NULL;
6463 if (params.session_uaddr) {
6464 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6465 if (IS_ERR(session_blob)) {
6466 ret = PTR_ERR(session_blob);
6470 start->session_address = __sme_set(__pa(session_blob));
6471 start->session_len = params.session_len;
6474 start->handle = params.handle;
6475 start->policy = params.policy;
6477 /* create memory encryption context */
6478 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6480 goto e_free_session;
6482 /* Bind ASID to this guest */
6483 ret = sev_bind_asid(kvm, start->handle, error);
6485 sev_decommission(start->handle);
6486 goto e_free_session;
6489 /* return handle to userspace */
6490 params.handle = start->handle;
6491 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6492 sev_unbind_asid(kvm, start->handle);
6494 goto e_free_session;
6497 sev->handle = start->handle;
6498 sev->fd = argp->sev_fd;
6501 kfree(session_blob);
6509 static unsigned long get_num_contig_pages(unsigned long idx,
6510 struct page **inpages, unsigned long npages)
6512 unsigned long paddr, next_paddr;
6513 unsigned long i = idx + 1, pages = 1;
6515 /* find the number of contiguous pages starting from idx */
6516 paddr = __sme_page_pa(inpages[idx]);
6517 while (i < npages) {
6518 next_paddr = __sme_page_pa(inpages[i++]);
6519 if ((paddr + PAGE_SIZE) == next_paddr) {
6530 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6532 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6533 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6534 struct kvm_sev_launch_update_data params;
6535 struct sev_data_launch_update_data *data;
6536 struct page **inpages;
6539 if (!sev_guest(kvm))
6542 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6545 data = kzalloc(sizeof(*data), GFP_KERNEL);
6549 vaddr = params.uaddr;
6551 vaddr_end = vaddr + size;
6553 /* Lock the user memory. */
6554 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6561 * The LAUNCH_UPDATE command will perform in-place encryption of the
6562 * memory content (i.e it will write the same memory region with C=1).
6563 * It's possible that the cache may contain the data with C=0, i.e.,
6564 * unencrypted so invalidate it first.
6566 sev_clflush_pages(inpages, npages);
6568 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6572 * If the user buffer is not page-aligned, calculate the offset
6575 offset = vaddr & (PAGE_SIZE - 1);
6577 /* Calculate the number of pages that can be encrypted in one go. */
6578 pages = get_num_contig_pages(i, inpages, npages);
6580 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6582 data->handle = sev->handle;
6584 data->address = __sme_page_pa(inpages[i]) + offset;
6585 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6590 next_vaddr = vaddr + len;
6594 /* content of memory is updated, mark pages dirty */
6595 for (i = 0; i < npages; i++) {
6596 set_page_dirty_lock(inpages[i]);
6597 mark_page_accessed(inpages[i]);
6599 /* unlock the user pages */
6600 sev_unpin_memory(kvm, inpages, npages);
6606 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6608 void __user *measure = (void __user *)(uintptr_t)argp->data;
6609 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6610 struct sev_data_launch_measure *data;
6611 struct kvm_sev_launch_measure params;
6612 void __user *p = NULL;
6616 if (!sev_guest(kvm))
6619 if (copy_from_user(¶ms, measure, sizeof(params)))
6622 data = kzalloc(sizeof(*data), GFP_KERNEL);
6626 /* User wants to query the blob length */
6630 p = (void __user *)(uintptr_t)params.uaddr;
6632 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6638 blob = kmalloc(params.len, GFP_KERNEL);
6642 data->address = __psp_pa(blob);
6643 data->len = params.len;
6647 data->handle = sev->handle;
6648 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6651 * If we query the session length, FW responded with expected data.
6660 if (copy_to_user(p, blob, params.len))
6665 params.len = data->len;
6666 if (copy_to_user(measure, ¶ms, sizeof(params)))
6675 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6677 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6678 struct sev_data_launch_finish *data;
6681 if (!sev_guest(kvm))
6684 data = kzalloc(sizeof(*data), GFP_KERNEL);
6688 data->handle = sev->handle;
6689 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6695 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6697 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6698 struct kvm_sev_guest_status params;
6699 struct sev_data_guest_status *data;
6702 if (!sev_guest(kvm))
6705 data = kzalloc(sizeof(*data), GFP_KERNEL);
6709 data->handle = sev->handle;
6710 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6714 params.policy = data->policy;
6715 params.state = data->state;
6716 params.handle = data->handle;
6718 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6725 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6726 unsigned long dst, int size,
6727 int *error, bool enc)
6729 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6730 struct sev_data_dbg *data;
6733 data = kzalloc(sizeof(*data), GFP_KERNEL);
6737 data->handle = sev->handle;
6738 data->dst_addr = dst;
6739 data->src_addr = src;
6742 ret = sev_issue_cmd(kvm,
6743 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6749 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6750 unsigned long dst_paddr, int sz, int *err)
6755 * Its safe to read more than we are asked, caller should ensure that
6756 * destination has enough space.
6758 src_paddr = round_down(src_paddr, 16);
6759 offset = src_paddr & 15;
6760 sz = round_up(sz + offset, 16);
6762 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6765 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6766 unsigned long __user dst_uaddr,
6767 unsigned long dst_paddr,
6770 struct page *tpage = NULL;
6773 /* if inputs are not 16-byte then use intermediate buffer */
6774 if (!IS_ALIGNED(dst_paddr, 16) ||
6775 !IS_ALIGNED(paddr, 16) ||
6776 !IS_ALIGNED(size, 16)) {
6777 tpage = (void *)alloc_page(GFP_KERNEL);
6781 dst_paddr = __sme_page_pa(tpage);
6784 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6789 offset = paddr & 15;
6790 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6791 page_address(tpage) + offset, size))
6802 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6803 unsigned long __user vaddr,
6804 unsigned long dst_paddr,
6805 unsigned long __user dst_vaddr,
6806 int size, int *error)
6808 struct page *src_tpage = NULL;
6809 struct page *dst_tpage = NULL;
6810 int ret, len = size;
6812 /* If source buffer is not aligned then use an intermediate buffer */
6813 if (!IS_ALIGNED(vaddr, 16)) {
6814 src_tpage = alloc_page(GFP_KERNEL);
6818 if (copy_from_user(page_address(src_tpage),
6819 (void __user *)(uintptr_t)vaddr, size)) {
6820 __free_page(src_tpage);
6824 paddr = __sme_page_pa(src_tpage);
6828 * If destination buffer or length is not aligned then do read-modify-write:
6829 * - decrypt destination in an intermediate buffer
6830 * - copy the source buffer in an intermediate buffer
6831 * - use the intermediate buffer as source buffer
6833 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6836 dst_tpage = alloc_page(GFP_KERNEL);
6842 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6843 __sme_page_pa(dst_tpage), size, error);
6848 * If source is kernel buffer then use memcpy() otherwise
6851 dst_offset = dst_paddr & 15;
6854 memcpy(page_address(dst_tpage) + dst_offset,
6855 page_address(src_tpage), size);
6857 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6858 (void __user *)(uintptr_t)vaddr, size)) {
6864 paddr = __sme_page_pa(dst_tpage);
6865 dst_paddr = round_down(dst_paddr, 16);
6866 len = round_up(size, 16);
6869 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6873 __free_page(src_tpage);
6875 __free_page(dst_tpage);
6879 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6881 unsigned long vaddr, vaddr_end, next_vaddr;
6882 unsigned long dst_vaddr;
6883 struct page **src_p, **dst_p;
6884 struct kvm_sev_dbg debug;
6889 if (!sev_guest(kvm))
6892 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6895 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6897 if (!debug.dst_uaddr)
6900 vaddr = debug.src_uaddr;
6902 vaddr_end = vaddr + size;
6903 dst_vaddr = debug.dst_uaddr;
6905 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6906 int len, s_off, d_off;
6908 /* lock userspace source and destination page */
6909 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6913 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6915 sev_unpin_memory(kvm, src_p, n);
6920 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6921 * memory content (i.e it will write the same memory region with C=1).
6922 * It's possible that the cache may contain the data with C=0, i.e.,
6923 * unencrypted so invalidate it first.
6925 sev_clflush_pages(src_p, 1);
6926 sev_clflush_pages(dst_p, 1);
6929 * Since user buffer may not be page aligned, calculate the
6930 * offset within the page.
6932 s_off = vaddr & ~PAGE_MASK;
6933 d_off = dst_vaddr & ~PAGE_MASK;
6934 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6937 ret = __sev_dbg_decrypt_user(kvm,
6938 __sme_page_pa(src_p[0]) + s_off,
6940 __sme_page_pa(dst_p[0]) + d_off,
6943 ret = __sev_dbg_encrypt_user(kvm,
6944 __sme_page_pa(src_p[0]) + s_off,
6946 __sme_page_pa(dst_p[0]) + d_off,
6950 sev_unpin_memory(kvm, src_p, n);
6951 sev_unpin_memory(kvm, dst_p, n);
6956 next_vaddr = vaddr + len;
6957 dst_vaddr = dst_vaddr + len;
6964 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6966 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6967 struct sev_data_launch_secret *data;
6968 struct kvm_sev_launch_secret params;
6969 struct page **pages;
6974 if (!sev_guest(kvm))
6977 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6980 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6985 * The secret must be copied into contiguous memory region, lets verify
6986 * that userspace memory pages are contiguous before we issue command.
6988 if (get_num_contig_pages(0, pages, n) != n) {
6990 goto e_unpin_memory;
6994 data = kzalloc(sizeof(*data), GFP_KERNEL);
6996 goto e_unpin_memory;
6998 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6999 data->guest_address = __sme_page_pa(pages[0]) + offset;
7000 data->guest_len = params.guest_len;
7002 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
7004 ret = PTR_ERR(blob);
7008 data->trans_address = __psp_pa(blob);
7009 data->trans_len = params.trans_len;
7011 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
7016 data->hdr_address = __psp_pa(hdr);
7017 data->hdr_len = params.hdr_len;
7019 data->handle = sev->handle;
7020 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
7029 sev_unpin_memory(kvm, pages, n);
7033 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
7035 struct kvm_sev_cmd sev_cmd;
7038 if (!svm_sev_enabled())
7041 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
7044 mutex_lock(&kvm->lock);
7046 switch (sev_cmd.id) {
7048 r = sev_guest_init(kvm, &sev_cmd);
7050 case KVM_SEV_LAUNCH_START:
7051 r = sev_launch_start(kvm, &sev_cmd);
7053 case KVM_SEV_LAUNCH_UPDATE_DATA:
7054 r = sev_launch_update_data(kvm, &sev_cmd);
7056 case KVM_SEV_LAUNCH_MEASURE:
7057 r = sev_launch_measure(kvm, &sev_cmd);
7059 case KVM_SEV_LAUNCH_FINISH:
7060 r = sev_launch_finish(kvm, &sev_cmd);
7062 case KVM_SEV_GUEST_STATUS:
7063 r = sev_guest_status(kvm, &sev_cmd);
7065 case KVM_SEV_DBG_DECRYPT:
7066 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7068 case KVM_SEV_DBG_ENCRYPT:
7069 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7071 case KVM_SEV_LAUNCH_SECRET:
7072 r = sev_launch_secret(kvm, &sev_cmd);
7079 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7083 mutex_unlock(&kvm->lock);
7087 static int svm_register_enc_region(struct kvm *kvm,
7088 struct kvm_enc_region *range)
7090 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7091 struct enc_region *region;
7094 if (!sev_guest(kvm))
7097 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7100 region = kzalloc(sizeof(*region), GFP_KERNEL);
7104 mutex_lock(&kvm->lock);
7105 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7106 if (!region->pages) {
7108 mutex_unlock(&kvm->lock);
7112 region->uaddr = range->addr;
7113 region->size = range->size;
7115 list_add_tail(®ion->list, &sev->regions_list);
7116 mutex_unlock(&kvm->lock);
7119 * The guest may change the memory encryption attribute from C=0 -> C=1
7120 * or vice versa for this memory range. Lets make sure caches are
7121 * flushed to ensure that guest data gets written into memory with
7124 sev_clflush_pages(region->pages, region->npages);
7133 static struct enc_region *
7134 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7136 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7137 struct list_head *head = &sev->regions_list;
7138 struct enc_region *i;
7140 list_for_each_entry(i, head, list) {
7141 if (i->uaddr == range->addr &&
7142 i->size == range->size)
7150 static int svm_unregister_enc_region(struct kvm *kvm,
7151 struct kvm_enc_region *range)
7153 struct enc_region *region;
7156 mutex_lock(&kvm->lock);
7158 if (!sev_guest(kvm)) {
7163 region = find_enc_region(kvm, range);
7169 __unregister_enc_region_locked(kvm, region);
7171 mutex_unlock(&kvm->lock);
7175 mutex_unlock(&kvm->lock);
7179 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7180 .cpu_has_kvm_support = has_svm,
7181 .disabled_by_bios = is_disabled,
7182 .hardware_setup = svm_hardware_setup,
7183 .hardware_unsetup = svm_hardware_unsetup,
7184 .check_processor_compatibility = svm_check_processor_compat,
7185 .hardware_enable = svm_hardware_enable,
7186 .hardware_disable = svm_hardware_disable,
7187 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7188 .has_emulated_msr = svm_has_emulated_msr,
7190 .vcpu_create = svm_create_vcpu,
7191 .vcpu_free = svm_free_vcpu,
7192 .vcpu_reset = svm_vcpu_reset,
7194 .vm_alloc = svm_vm_alloc,
7195 .vm_free = svm_vm_free,
7196 .vm_init = avic_vm_init,
7197 .vm_destroy = svm_vm_destroy,
7199 .prepare_guest_switch = svm_prepare_guest_switch,
7200 .vcpu_load = svm_vcpu_load,
7201 .vcpu_put = svm_vcpu_put,
7202 .vcpu_blocking = svm_vcpu_blocking,
7203 .vcpu_unblocking = svm_vcpu_unblocking,
7205 .update_bp_intercept = update_bp_intercept,
7206 .get_msr_feature = svm_get_msr_feature,
7207 .get_msr = svm_get_msr,
7208 .set_msr = svm_set_msr,
7209 .get_segment_base = svm_get_segment_base,
7210 .get_segment = svm_get_segment,
7211 .set_segment = svm_set_segment,
7212 .get_cpl = svm_get_cpl,
7213 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7214 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7215 .decache_cr3 = svm_decache_cr3,
7216 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7217 .set_cr0 = svm_set_cr0,
7218 .set_cr3 = svm_set_cr3,
7219 .set_cr4 = svm_set_cr4,
7220 .set_efer = svm_set_efer,
7221 .get_idt = svm_get_idt,
7222 .set_idt = svm_set_idt,
7223 .get_gdt = svm_get_gdt,
7224 .set_gdt = svm_set_gdt,
7225 .get_dr6 = svm_get_dr6,
7226 .set_dr6 = svm_set_dr6,
7227 .set_dr7 = svm_set_dr7,
7228 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7229 .cache_reg = svm_cache_reg,
7230 .get_rflags = svm_get_rflags,
7231 .set_rflags = svm_set_rflags,
7233 .tlb_flush = svm_flush_tlb,
7234 .tlb_flush_gva = svm_flush_tlb_gva,
7236 .run = svm_vcpu_run,
7237 .handle_exit = handle_exit,
7238 .skip_emulated_instruction = skip_emulated_instruction,
7239 .set_interrupt_shadow = svm_set_interrupt_shadow,
7240 .get_interrupt_shadow = svm_get_interrupt_shadow,
7241 .patch_hypercall = svm_patch_hypercall,
7242 .set_irq = svm_set_irq,
7243 .set_nmi = svm_inject_nmi,
7244 .queue_exception = svm_queue_exception,
7245 .cancel_injection = svm_cancel_injection,
7246 .interrupt_allowed = svm_interrupt_allowed,
7247 .nmi_allowed = svm_nmi_allowed,
7248 .get_nmi_mask = svm_get_nmi_mask,
7249 .set_nmi_mask = svm_set_nmi_mask,
7250 .enable_nmi_window = enable_nmi_window,
7251 .enable_irq_window = enable_irq_window,
7252 .update_cr8_intercept = update_cr8_intercept,
7253 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7254 .get_enable_apicv = svm_get_enable_apicv,
7255 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7256 .load_eoi_exitmap = svm_load_eoi_exitmap,
7257 .hwapic_irr_update = svm_hwapic_irr_update,
7258 .hwapic_isr_update = svm_hwapic_isr_update,
7259 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7260 .apicv_post_state_restore = avic_post_state_restore,
7262 .set_tss_addr = svm_set_tss_addr,
7263 .set_identity_map_addr = svm_set_identity_map_addr,
7264 .get_tdp_level = get_npt_level,
7265 .get_mt_mask = svm_get_mt_mask,
7267 .get_exit_info = svm_get_exit_info,
7269 .get_lpage_level = svm_get_lpage_level,
7271 .cpuid_update = svm_cpuid_update,
7273 .rdtscp_supported = svm_rdtscp_supported,
7274 .invpcid_supported = svm_invpcid_supported,
7275 .mpx_supported = svm_mpx_supported,
7276 .xsaves_supported = svm_xsaves_supported,
7277 .umip_emulated = svm_umip_emulated,
7279 .set_supported_cpuid = svm_set_supported_cpuid,
7281 .has_wbinvd_exit = svm_has_wbinvd_exit,
7283 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7284 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7286 .set_tdp_cr3 = set_tdp_cr3,
7288 .check_intercept = svm_check_intercept,
7289 .handle_external_intr = svm_handle_external_intr,
7291 .request_immediate_exit = __kvm_request_immediate_exit,
7293 .sched_in = svm_sched_in,
7295 .pmu_ops = &amd_pmu_ops,
7296 .deliver_posted_interrupt = svm_deliver_avic_intr,
7297 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7298 .update_pi_irte = svm_update_pi_irte,
7299 .setup_mce = svm_setup_mce,
7301 .smi_allowed = svm_smi_allowed,
7302 .pre_enter_smm = svm_pre_enter_smm,
7303 .pre_leave_smm = svm_pre_leave_smm,
7304 .enable_smi_window = enable_smi_window,
7306 .mem_enc_op = svm_mem_enc_op,
7307 .mem_enc_reg_region = svm_register_enc_region,
7308 .mem_enc_unreg_region = svm_unregister_enc_region,
7311 static int __init svm_init(void)
7313 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7314 __alignof__(struct vcpu_svm), THIS_MODULE);
7317 static void __exit svm_exit(void)
7322 module_init(svm_init)
7323 module_exit(svm_exit)