1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
28 #include <linux/cc_platform.h>
31 #include <asm/perf_event.h>
32 #include <asm/tlbflush.h>
34 #include <asm/debugreg.h>
35 #include <asm/kvm_para.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/spec-ctrl.h>
38 #include <asm/cpu_device_id.h>
39 #include <asm/traps.h>
40 #include <asm/fpu/api.h>
42 #include <asm/virtext.h>
48 #include "kvm_onhyperv.h"
49 #include "svm_onhyperv.h"
51 MODULE_AUTHOR("Qumranet");
52 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id svm_cpu_id[] = {
56 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
59 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62 #define SEG_TYPE_LDT 2
63 #define SEG_TYPE_BUSY_TSS16 3
65 static bool erratum_383_found __read_mostly;
67 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
70 * Set osvw_len to higher value when updated Revision Guides
71 * are published and we know what the new status bits are
73 static uint64_t osvw_len = 4, osvw_status;
75 static DEFINE_PER_CPU(u64, current_tsc_ratio);
77 static const struct svm_direct_access_msrs {
78 u32 index; /* Index of the MSR */
79 bool always; /* True if intercept is initially cleared */
80 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
81 { .index = MSR_STAR, .always = true },
82 { .index = MSR_IA32_SYSENTER_CS, .always = true },
83 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
84 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
86 { .index = MSR_GS_BASE, .always = true },
87 { .index = MSR_FS_BASE, .always = true },
88 { .index = MSR_KERNEL_GS_BASE, .always = true },
89 { .index = MSR_LSTAR, .always = true },
90 { .index = MSR_CSTAR, .always = true },
91 { .index = MSR_SYSCALL_MASK, .always = true },
93 { .index = MSR_IA32_SPEC_CTRL, .always = false },
94 { .index = MSR_IA32_PRED_CMD, .always = false },
95 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
96 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
97 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
98 { .index = MSR_IA32_LASTINTTOIP, .always = false },
99 { .index = MSR_EFER, .always = false },
100 { .index = MSR_IA32_CR_PAT, .always = false },
101 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
102 { .index = MSR_TSC_AUX, .always = false },
103 { .index = MSR_INVALID, .always = false },
107 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
108 * pause_filter_count: On processors that support Pause filtering(indicated
109 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
110 * count value. On VMRUN this value is loaded into an internal counter.
111 * Each time a pause instruction is executed, this counter is decremented
112 * until it reaches zero at which time a #VMEXIT is generated if pause
113 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
114 * Intercept Filtering for more details.
115 * This also indicate if ple logic enabled.
117 * pause_filter_thresh: In addition, some processor families support advanced
118 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
119 * the amount of time a guest is allowed to execute in a pause loop.
120 * In this mode, a 16-bit pause filter threshold field is added in the
121 * VMCB. The threshold value is a cycle count that is used to reset the
122 * pause counter. As with simple pause filtering, VMRUN loads the pause
123 * count value from VMCB into an internal counter. Then, on each pause
124 * instruction the hardware checks the elapsed number of cycles since
125 * the most recent pause instruction against the pause filter threshold.
126 * If the elapsed cycle count is greater than the pause filter threshold,
127 * then the internal pause count is reloaded from the VMCB and execution
128 * continues. If the elapsed cycle count is less than the pause filter
129 * threshold, then the internal pause count is decremented. If the count
130 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
131 * triggered. If advanced pause filtering is supported and pause filter
132 * threshold field is set to zero, the filter will operate in the simpler,
136 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
137 module_param(pause_filter_thresh, ushort, 0444);
139 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
140 module_param(pause_filter_count, ushort, 0444);
142 /* Default doubles per-vcpu window every exit. */
143 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
144 module_param(pause_filter_count_grow, ushort, 0444);
146 /* Default resets per-vcpu window every exit to pause_filter_count. */
147 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
148 module_param(pause_filter_count_shrink, ushort, 0444);
150 /* Default is to compute the maximum so we can never overflow. */
151 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
152 module_param(pause_filter_count_max, ushort, 0444);
155 * Use nested page tables by default. Note, NPT may get forced off by
156 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
158 bool npt_enabled = true;
159 module_param_named(npt, npt_enabled, bool, 0444);
161 /* allow nested virtualization in KVM/SVM */
162 static int nested = true;
163 module_param(nested, int, S_IRUGO);
165 /* enable/disable Next RIP Save */
166 static int nrips = true;
167 module_param(nrips, int, 0444);
169 /* enable/disable Virtual VMLOAD VMSAVE */
170 static int vls = true;
171 module_param(vls, int, 0444);
173 /* enable/disable Virtual GIF */
175 module_param(vgif, int, 0444);
177 /* enable/disable LBR virtualization */
178 static int lbrv = true;
179 module_param(lbrv, int, 0444);
181 static int tsc_scaling = true;
182 module_param(tsc_scaling, int, 0444);
185 * enable / disable AVIC. Because the defaults differ for APICv
186 * support between VMX and SVM we cannot use module_param_named.
189 module_param(avic, bool, 0444);
191 static bool force_avic;
192 module_param_unsafe(force_avic, bool, 0444);
194 bool __read_mostly dump_invalid_vmcb;
195 module_param(dump_invalid_vmcb, bool, 0644);
198 bool intercept_smi = true;
199 module_param(intercept_smi, bool, 0444);
202 static bool svm_gp_erratum_intercept = true;
204 static u8 rsm_ins_bytes[] = "\x0f\xaa";
206 static unsigned long iopm_base;
208 struct kvm_ldttss_desc {
211 unsigned base1:8, type:5, dpl:2, p:1;
212 unsigned limit1:4, zero0:3, g:1, base2:8;
215 } __attribute__((packed));
217 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
220 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
221 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
223 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
224 * defer the restoration of TSC_AUX until the CPU returns to userspace.
226 static int tsc_aux_uret_slot __read_mostly = -1;
228 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
230 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
231 #define MSRS_RANGE_SIZE 2048
232 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
234 u32 svm_msrpm_offset(u32 msr)
239 for (i = 0; i < NUM_MSR_MAPS; i++) {
240 if (msr < msrpm_ranges[i] ||
241 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
244 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
245 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
247 /* Now we have the u8 offset - but need the u32 offset */
251 /* MSR not in any range */
255 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu);
257 static int get_npt_level(void)
260 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
262 return PT32E_ROOT_LEVEL;
266 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
268 struct vcpu_svm *svm = to_svm(vcpu);
269 u64 old_efer = vcpu->arch.efer;
270 vcpu->arch.efer = efer;
273 /* Shadow paging assumes NX to be available. */
276 if (!(efer & EFER_LMA))
280 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
281 if (!(efer & EFER_SVME)) {
282 svm_leave_nested(vcpu);
283 svm_set_gif(svm, true);
284 /* #GP intercept is still needed for vmware backdoor */
285 if (!enable_vmware_backdoor)
286 clr_exception_intercept(svm, GP_VECTOR);
289 * Free the nested guest state, unless we are in SMM.
290 * In this case we will return to the nested guest
291 * as soon as we leave SMM.
294 svm_free_nested(svm);
297 int ret = svm_allocate_nested(svm);
300 vcpu->arch.efer = old_efer;
305 * Never intercept #GP for SEV guests, KVM can't
306 * decrypt guest memory to workaround the erratum.
308 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm))
309 set_exception_intercept(svm, GP_VECTOR);
313 svm->vmcb->save.efer = efer | EFER_SVME;
314 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
318 static int is_external_interrupt(u32 info)
320 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
321 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
324 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
326 struct vcpu_svm *svm = to_svm(vcpu);
329 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
330 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
334 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
336 struct vcpu_svm *svm = to_svm(vcpu);
339 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
341 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
345 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
347 struct vcpu_svm *svm = to_svm(vcpu);
350 * SEV-ES does not expose the next RIP. The RIP update is controlled by
351 * the type of exit and the #VC handler in the guest.
353 if (sev_es_guest(vcpu->kvm))
356 if (nrips && svm->vmcb->control.next_rip != 0) {
357 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
358 svm->next_rip = svm->vmcb->control.next_rip;
361 if (!svm->next_rip) {
362 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
365 kvm_rip_write(vcpu, svm->next_rip);
369 svm_set_interrupt_shadow(vcpu, 0);
374 static void svm_queue_exception(struct kvm_vcpu *vcpu)
376 struct vcpu_svm *svm = to_svm(vcpu);
377 unsigned nr = vcpu->arch.exception.nr;
378 bool has_error_code = vcpu->arch.exception.has_error_code;
379 u32 error_code = vcpu->arch.exception.error_code;
381 kvm_deliver_exception_payload(vcpu);
383 if (nr == BP_VECTOR && !nrips) {
384 unsigned long rip, old_rip = kvm_rip_read(vcpu);
387 * For guest debugging where we have to reinject #BP if some
388 * INT3 is guest-owned:
389 * Emulate nRIP by moving RIP forward. Will fail if injection
390 * raises a fault that is not intercepted. Still better than
391 * failing in all cases.
393 (void)svm_skip_emulated_instruction(vcpu);
394 rip = kvm_rip_read(vcpu);
395 svm->int3_rip = rip + svm->vmcb->save.cs.base;
396 svm->int3_injected = rip - old_rip;
399 svm->vmcb->control.event_inj = nr
401 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
402 | SVM_EVTINJ_TYPE_EXEPT;
403 svm->vmcb->control.event_inj_err = error_code;
406 static void svm_init_erratum_383(void)
412 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
415 /* Use _safe variants to not break nested virtualization */
416 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
422 low = lower_32_bits(val);
423 high = upper_32_bits(val);
425 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
427 erratum_383_found = true;
430 static void svm_init_osvw(struct kvm_vcpu *vcpu)
433 * Guests should see errata 400 and 415 as fixed (assuming that
434 * HLT and IO instructions are intercepted).
436 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
437 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
440 * By increasing VCPU's osvw.length to 3 we are telling the guest that
441 * all osvw.status bits inside that length, including bit 0 (which is
442 * reserved for erratum 298), are valid. However, if host processor's
443 * osvw_len is 0 then osvw_status[0] carries no information. We need to
444 * be conservative here and therefore we tell the guest that erratum 298
445 * is present (because we really don't know).
447 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
448 vcpu->arch.osvw.status |= 1;
451 static int has_svm(void)
455 if (!cpu_has_svm(&msg)) {
456 printk(KERN_INFO "has_svm: %s\n", msg);
460 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
461 pr_info("KVM is unsupported when running as an SEV guest\n");
468 void __svm_write_tsc_multiplier(u64 multiplier)
472 if (multiplier == __this_cpu_read(current_tsc_ratio))
475 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
476 __this_cpu_write(current_tsc_ratio, multiplier);
481 static void svm_hardware_disable(void)
483 /* Make sure we clean up behind us */
485 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
489 amd_pmu_disable_virt();
492 static int svm_hardware_enable(void)
495 struct svm_cpu_data *sd;
497 struct desc_struct *gdt;
498 int me = raw_smp_processor_id();
500 rdmsrl(MSR_EFER, efer);
501 if (efer & EFER_SVME)
505 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
508 sd = per_cpu(svm_data, me);
510 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
514 sd->asid_generation = 1;
515 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
516 sd->next_asid = sd->max_asid + 1;
517 sd->min_asid = max_sev_asid + 1;
519 gdt = get_current_gdt_rw();
520 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
522 wrmsrl(MSR_EFER, efer | EFER_SVME);
524 wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
526 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
528 * Set the default value, even if we don't use TSC scaling
529 * to avoid having stale value in the msr
531 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
538 * Note that it is possible to have a system with mixed processor
539 * revisions and therefore different OSVW bits. If bits are not the same
540 * on different processors then choose the worst case (i.e. if erratum
541 * is present on one processor and not on another then assume that the
542 * erratum is present everywhere).
544 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
545 uint64_t len, status = 0;
548 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
550 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
554 osvw_status = osvw_len = 0;
558 osvw_status |= status;
559 osvw_status &= (1ULL << osvw_len) - 1;
562 osvw_status = osvw_len = 0;
564 svm_init_erratum_383();
566 amd_pmu_enable_virt();
571 static void svm_cpu_uninit(int cpu)
573 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
578 per_cpu(svm_data, cpu) = NULL;
579 kfree(sd->sev_vmcbs);
580 __free_page(sd->save_area);
584 static int svm_cpu_init(int cpu)
586 struct svm_cpu_data *sd;
589 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
593 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
597 ret = sev_cpu_init(sd);
601 per_cpu(svm_data, cpu) = sd;
606 __free_page(sd->save_area);
613 static int direct_access_msr_slot(u32 msr)
617 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
618 if (direct_access_msrs[i].index == msr)
624 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
627 struct vcpu_svm *svm = to_svm(vcpu);
628 int slot = direct_access_msr_slot(msr);
633 /* Set the shadow bitmaps to the desired intercept states */
635 set_bit(slot, svm->shadow_msr_intercept.read);
637 clear_bit(slot, svm->shadow_msr_intercept.read);
640 set_bit(slot, svm->shadow_msr_intercept.write);
642 clear_bit(slot, svm->shadow_msr_intercept.write);
645 static bool valid_msr_intercept(u32 index)
647 return direct_access_msr_slot(index) != -ENOENT;
650 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
657 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
660 offset = svm_msrpm_offset(msr);
661 bit_write = 2 * (msr & 0x0f) + 1;
664 BUG_ON(offset == MSR_INVALID);
666 return !!test_bit(bit_write, &tmp);
669 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
670 u32 msr, int read, int write)
672 struct vcpu_svm *svm = to_svm(vcpu);
673 u8 bit_read, bit_write;
678 * If this warning triggers extend the direct_access_msrs list at the
679 * beginning of the file
681 WARN_ON(!valid_msr_intercept(msr));
683 /* Enforce non allowed MSRs to trap */
684 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
687 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
690 offset = svm_msrpm_offset(msr);
691 bit_read = 2 * (msr & 0x0f);
692 bit_write = 2 * (msr & 0x0f) + 1;
695 BUG_ON(offset == MSR_INVALID);
697 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
698 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
702 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
703 svm->nested.force_msr_bitmap_recalc = true;
706 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
709 set_shadow_msr_intercept(vcpu, msr, read, write);
710 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
713 u32 *svm_vcpu_alloc_msrpm(void)
715 unsigned int order = get_order(MSRPM_SIZE);
716 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
722 msrpm = page_address(pages);
723 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
728 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
732 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
733 if (!direct_access_msrs[i].always)
735 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
740 void svm_vcpu_free_msrpm(u32 *msrpm)
742 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
745 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
747 struct vcpu_svm *svm = to_svm(vcpu);
751 * Set intercept permissions for all direct access MSRs again. They
752 * will automatically get filtered through the MSR filter, so we are
753 * back in sync after this.
755 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
756 u32 msr = direct_access_msrs[i].index;
757 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
758 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
760 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
764 static void add_msr_offset(u32 offset)
768 for (i = 0; i < MSRPM_OFFSETS; ++i) {
770 /* Offset already in list? */
771 if (msrpm_offsets[i] == offset)
774 /* Slot used by another offset? */
775 if (msrpm_offsets[i] != MSR_INVALID)
778 /* Add offset to list */
779 msrpm_offsets[i] = offset;
785 * If this BUG triggers the msrpm_offsets table has an overflow. Just
786 * increase MSRPM_OFFSETS in this case.
791 static void init_msrpm_offsets(void)
795 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
797 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
800 offset = svm_msrpm_offset(direct_access_msrs[i].index);
801 BUG_ON(offset == MSR_INVALID);
803 add_msr_offset(offset);
807 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb)
809 to_vmcb->save.dbgctl = from_vmcb->save.dbgctl;
810 to_vmcb->save.br_from = from_vmcb->save.br_from;
811 to_vmcb->save.br_to = from_vmcb->save.br_to;
812 to_vmcb->save.last_excp_from = from_vmcb->save.last_excp_from;
813 to_vmcb->save.last_excp_to = from_vmcb->save.last_excp_to;
815 vmcb_mark_dirty(to_vmcb, VMCB_LBR);
818 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
820 struct vcpu_svm *svm = to_svm(vcpu);
822 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
823 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
824 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
825 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
826 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
828 /* Move the LBR msrs to the vmcb02 so that the guest can see them. */
829 if (is_guest_mode(vcpu))
830 svm_copy_lbrs(svm->vmcb, svm->vmcb01.ptr);
833 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
835 struct vcpu_svm *svm = to_svm(vcpu);
837 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
838 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
839 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
840 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
841 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
844 * Move the LBR msrs back to the vmcb01 to avoid copying them
845 * on nested guest entries.
847 if (is_guest_mode(vcpu))
848 svm_copy_lbrs(svm->vmcb01.ptr, svm->vmcb);
851 static int svm_get_lbr_msr(struct vcpu_svm *svm, u32 index)
854 * If the LBR virtualization is disabled, the LBR msrs are always
855 * kept in the vmcb01 to avoid copying them on nested guest entries.
857 * If nested, and the LBR virtualization is enabled/disabled, the msrs
858 * are moved between the vmcb01 and vmcb02 as needed.
861 (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK) ?
862 svm->vmcb : svm->vmcb01.ptr;
865 case MSR_IA32_DEBUGCTLMSR:
866 return vmcb->save.dbgctl;
867 case MSR_IA32_LASTBRANCHFROMIP:
868 return vmcb->save.br_from;
869 case MSR_IA32_LASTBRANCHTOIP:
870 return vmcb->save.br_to;
871 case MSR_IA32_LASTINTFROMIP:
872 return vmcb->save.last_excp_from;
873 case MSR_IA32_LASTINTTOIP:
874 return vmcb->save.last_excp_to;
876 KVM_BUG(false, svm->vcpu.kvm,
877 "%s: Unknown MSR 0x%x", __func__, index);
882 void svm_update_lbrv(struct kvm_vcpu *vcpu)
884 struct vcpu_svm *svm = to_svm(vcpu);
886 bool enable_lbrv = svm_get_lbr_msr(svm, MSR_IA32_DEBUGCTLMSR) &
889 bool current_enable_lbrv = !!(svm->vmcb->control.virt_ext &
890 LBR_CTL_ENABLE_MASK);
892 if (unlikely(is_guest_mode(vcpu) && svm->lbrv_enabled))
893 if (unlikely(svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK))
896 if (enable_lbrv == current_enable_lbrv)
900 svm_enable_lbrv(vcpu);
902 svm_disable_lbrv(vcpu);
905 void disable_nmi_singlestep(struct vcpu_svm *svm)
907 svm->nmi_singlestep = false;
909 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
910 /* Clear our flags if they were not set by the guest */
911 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
912 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
913 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
914 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
918 static void grow_ple_window(struct kvm_vcpu *vcpu)
920 struct vcpu_svm *svm = to_svm(vcpu);
921 struct vmcb_control_area *control = &svm->vmcb->control;
922 int old = control->pause_filter_count;
924 if (kvm_pause_in_guest(vcpu->kvm))
927 control->pause_filter_count = __grow_ple_window(old,
929 pause_filter_count_grow,
930 pause_filter_count_max);
932 if (control->pause_filter_count != old) {
933 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
934 trace_kvm_ple_window_update(vcpu->vcpu_id,
935 control->pause_filter_count, old);
939 static void shrink_ple_window(struct kvm_vcpu *vcpu)
941 struct vcpu_svm *svm = to_svm(vcpu);
942 struct vmcb_control_area *control = &svm->vmcb->control;
943 int old = control->pause_filter_count;
945 if (kvm_pause_in_guest(vcpu->kvm))
948 control->pause_filter_count =
949 __shrink_ple_window(old,
951 pause_filter_count_shrink,
953 if (control->pause_filter_count != old) {
954 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
955 trace_kvm_ple_window_update(vcpu->vcpu_id,
956 control->pause_filter_count, old);
960 static void svm_hardware_unsetup(void)
964 sev_hardware_unsetup();
966 for_each_possible_cpu(cpu)
969 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
970 get_order(IOPM_SIZE));
974 static void init_seg(struct vmcb_seg *seg)
977 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
978 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
983 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
986 seg->attrib = SVM_SELECTOR_P_MASK | type;
991 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
993 struct vcpu_svm *svm = to_svm(vcpu);
995 return svm->nested.ctl.tsc_offset;
998 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1000 struct vcpu_svm *svm = to_svm(vcpu);
1002 return svm->tsc_ratio_msr;
1005 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1007 struct vcpu_svm *svm = to_svm(vcpu);
1009 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1010 svm->vmcb->control.tsc_offset = offset;
1011 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1014 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1016 __svm_write_tsc_multiplier(multiplier);
1020 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1021 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1022 struct vcpu_svm *svm)
1025 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1026 * roots, or if INVPCID is disabled in the guest to inject #UD.
1028 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1030 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1031 svm_set_intercept(svm, INTERCEPT_INVPCID);
1033 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1036 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1037 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1038 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1040 svm_set_intercept(svm, INTERCEPT_RDTSCP);
1044 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
1046 struct vcpu_svm *svm = to_svm(vcpu);
1048 if (guest_cpuid_is_intel(vcpu)) {
1050 * We must intercept SYSENTER_EIP and SYSENTER_ESP
1051 * accesses because the processor only stores 32 bits.
1052 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
1054 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1055 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1056 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1058 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
1059 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
1061 svm->v_vmload_vmsave_enabled = false;
1064 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1065 * in VMCB and clear intercepts to avoid #VMEXIT.
1068 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1069 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1070 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1072 /* No need to intercept these MSRs */
1073 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
1074 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
1078 static void init_vmcb(struct kvm_vcpu *vcpu)
1080 struct vcpu_svm *svm = to_svm(vcpu);
1081 struct vmcb *vmcb = svm->vmcb01.ptr;
1082 struct vmcb_control_area *control = &vmcb->control;
1083 struct vmcb_save_area *save = &vmcb->save;
1085 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1086 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1087 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1088 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1089 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1090 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1091 if (!kvm_vcpu_apicv_active(vcpu))
1092 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1094 set_dr_intercepts(svm);
1096 set_exception_intercept(svm, PF_VECTOR);
1097 set_exception_intercept(svm, UD_VECTOR);
1098 set_exception_intercept(svm, MC_VECTOR);
1099 set_exception_intercept(svm, AC_VECTOR);
1100 set_exception_intercept(svm, DB_VECTOR);
1102 * Guest access to VMware backdoor ports could legitimately
1103 * trigger #GP because of TSS I/O permission bitmap.
1104 * We intercept those #GP and allow access to them anyway
1105 * as VMware does. Don't intercept #GP for SEV guests as KVM can't
1106 * decrypt guest memory to decode the faulting instruction.
1108 if (enable_vmware_backdoor && !sev_guest(vcpu->kvm))
1109 set_exception_intercept(svm, GP_VECTOR);
1111 svm_set_intercept(svm, INTERCEPT_INTR);
1112 svm_set_intercept(svm, INTERCEPT_NMI);
1115 svm_set_intercept(svm, INTERCEPT_SMI);
1117 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1118 svm_set_intercept(svm, INTERCEPT_RDPMC);
1119 svm_set_intercept(svm, INTERCEPT_CPUID);
1120 svm_set_intercept(svm, INTERCEPT_INVD);
1121 svm_set_intercept(svm, INTERCEPT_INVLPG);
1122 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1123 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1124 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1125 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1126 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1127 svm_set_intercept(svm, INTERCEPT_VMRUN);
1128 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1129 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1130 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1131 svm_set_intercept(svm, INTERCEPT_STGI);
1132 svm_set_intercept(svm, INTERCEPT_CLGI);
1133 svm_set_intercept(svm, INTERCEPT_SKINIT);
1134 svm_set_intercept(svm, INTERCEPT_WBINVD);
1135 svm_set_intercept(svm, INTERCEPT_XSETBV);
1136 svm_set_intercept(svm, INTERCEPT_RDPRU);
1137 svm_set_intercept(svm, INTERCEPT_RSM);
1139 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1140 svm_set_intercept(svm, INTERCEPT_MONITOR);
1141 svm_set_intercept(svm, INTERCEPT_MWAIT);
1144 if (!kvm_hlt_in_guest(vcpu->kvm))
1145 svm_set_intercept(svm, INTERCEPT_HLT);
1147 control->iopm_base_pa = __sme_set(iopm_base);
1148 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1149 control->int_ctl = V_INTR_MASKING_MASK;
1151 init_seg(&save->es);
1152 init_seg(&save->ss);
1153 init_seg(&save->ds);
1154 init_seg(&save->fs);
1155 init_seg(&save->gs);
1157 save->cs.selector = 0xf000;
1158 save->cs.base = 0xffff0000;
1159 /* Executable/Readable Code Segment */
1160 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1161 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1162 save->cs.limit = 0xffff;
1164 save->gdtr.base = 0;
1165 save->gdtr.limit = 0xffff;
1166 save->idtr.base = 0;
1167 save->idtr.limit = 0xffff;
1169 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1170 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1173 /* Setup VMCB for Nested Paging */
1174 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1175 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1176 clr_exception_intercept(svm, PF_VECTOR);
1177 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1178 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1179 save->g_pat = vcpu->arch.pat;
1182 svm->current_vmcb->asid_generation = 0;
1185 svm->nested.vmcb12_gpa = INVALID_GPA;
1186 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1188 if (!kvm_pause_in_guest(vcpu->kvm)) {
1189 control->pause_filter_count = pause_filter_count;
1190 if (pause_filter_thresh)
1191 control->pause_filter_thresh = pause_filter_thresh;
1192 svm_set_intercept(svm, INTERCEPT_PAUSE);
1194 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1197 svm_recalc_instruction_intercepts(vcpu, svm);
1200 * If the host supports V_SPEC_CTRL then disable the interception
1201 * of MSR_IA32_SPEC_CTRL.
1203 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1204 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1206 if (kvm_vcpu_apicv_active(vcpu))
1207 avic_init_vmcb(svm, vmcb);
1210 svm_clr_intercept(svm, INTERCEPT_STGI);
1211 svm_clr_intercept(svm, INTERCEPT_CLGI);
1212 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1215 if (sev_guest(vcpu->kvm))
1218 svm_hv_init_vmcb(vmcb);
1219 init_vmcb_after_set_cpuid(vcpu);
1221 vmcb_mark_all_dirty(vmcb);
1226 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
1228 struct vcpu_svm *svm = to_svm(vcpu);
1230 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1232 svm_init_osvw(vcpu);
1233 vcpu->arch.microcode_version = 0x01000065;
1234 svm->tsc_ratio_msr = kvm_default_tsc_scaling_ratio;
1236 if (sev_es_guest(vcpu->kvm))
1237 sev_es_vcpu_reset(svm);
1240 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1242 struct vcpu_svm *svm = to_svm(vcpu);
1245 svm->virt_spec_ctrl = 0;
1250 __svm_vcpu_reset(vcpu);
1253 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1255 svm->current_vmcb = target_vmcb;
1256 svm->vmcb = target_vmcb->ptr;
1259 static int svm_vcpu_create(struct kvm_vcpu *vcpu)
1261 struct vcpu_svm *svm;
1262 struct page *vmcb01_page;
1263 struct page *vmsa_page = NULL;
1266 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1270 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1274 if (sev_es_guest(vcpu->kvm)) {
1276 * SEV-ES guests require a separate VMSA page used to contain
1277 * the encrypted register state of the guest.
1279 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1281 goto error_free_vmcb_page;
1284 * SEV-ES guests maintain an encrypted version of their FPU
1285 * state which is restored and saved on VMRUN and VMEXIT.
1286 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't
1287 * do xsave/xrstor on it.
1289 fpstate_set_confidential(&vcpu->arch.guest_fpu);
1292 err = avic_init_vcpu(svm);
1294 goto error_free_vmsa_page;
1296 svm->msrpm = svm_vcpu_alloc_msrpm();
1299 goto error_free_vmsa_page;
1302 svm->vmcb01.ptr = page_address(vmcb01_page);
1303 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1304 svm_switch_vmcb(svm, &svm->vmcb01);
1307 svm->sev_es.vmsa = page_address(vmsa_page);
1309 svm->guest_state_loaded = false;
1313 error_free_vmsa_page:
1315 __free_page(vmsa_page);
1316 error_free_vmcb_page:
1317 __free_page(vmcb01_page);
1322 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1326 for_each_online_cpu(i)
1327 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1330 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
1332 struct vcpu_svm *svm = to_svm(vcpu);
1335 * The vmcb page can be recycled, causing a false negative in
1336 * svm_vcpu_load(). So, ensure that no logical CPU has this
1337 * vmcb page recorded as its current vmcb.
1339 svm_clear_current_vmcb(svm->vmcb);
1341 svm_free_nested(svm);
1343 sev_free_vcpu(vcpu);
1345 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1346 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1349 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1351 struct vcpu_svm *svm = to_svm(vcpu);
1352 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1354 if (sev_es_guest(vcpu->kvm))
1355 sev_es_unmap_ghcb(svm);
1357 if (svm->guest_state_loaded)
1361 * Save additional host state that will be restored on VMEXIT (sev-es)
1362 * or subsequent vmload of host save area.
1364 vmsave(__sme_page_pa(sd->save_area));
1365 if (sev_es_guest(vcpu->kvm)) {
1366 struct sev_es_save_area *hostsa;
1367 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
1369 sev_es_prepare_switch_to_guest(hostsa);
1373 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
1375 if (likely(tsc_aux_uret_slot >= 0))
1376 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1378 svm->guest_state_loaded = true;
1381 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1383 to_svm(vcpu)->guest_state_loaded = false;
1386 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1388 struct vcpu_svm *svm = to_svm(vcpu);
1389 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1391 if (sd->current_vmcb != svm->vmcb) {
1392 sd->current_vmcb = svm->vmcb;
1393 indirect_branch_prediction_barrier();
1395 if (kvm_vcpu_apicv_active(vcpu))
1396 avic_vcpu_load(vcpu, cpu);
1399 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1401 if (kvm_vcpu_apicv_active(vcpu))
1402 avic_vcpu_put(vcpu);
1404 svm_prepare_host_switch(vcpu);
1406 ++vcpu->stat.host_state_reload;
1409 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1411 struct vcpu_svm *svm = to_svm(vcpu);
1412 unsigned long rflags = svm->vmcb->save.rflags;
1414 if (svm->nmi_singlestep) {
1415 /* Hide our flags if they were not set by the guest */
1416 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1417 rflags &= ~X86_EFLAGS_TF;
1418 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1419 rflags &= ~X86_EFLAGS_RF;
1424 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1426 if (to_svm(vcpu)->nmi_singlestep)
1427 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1430 * Any change of EFLAGS.VM is accompanied by a reload of SS
1431 * (caused by either a task switch or an inter-privilege IRET),
1432 * so we do not need to update the CPL here.
1434 to_svm(vcpu)->vmcb->save.rflags = rflags;
1437 static bool svm_get_if_flag(struct kvm_vcpu *vcpu)
1439 struct vmcb *vmcb = to_svm(vcpu)->vmcb;
1441 return sev_es_guest(vcpu->kvm)
1442 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK
1443 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF;
1446 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1448 kvm_register_mark_available(vcpu, reg);
1451 case VCPU_EXREG_PDPTR:
1453 * When !npt_enabled, mmu->pdptrs[] is already available since
1454 * it is always updated per SDM when moving to CRs.
1457 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
1460 KVM_BUG_ON(1, vcpu->kvm);
1464 static void svm_set_vintr(struct vcpu_svm *svm)
1466 struct vmcb_control_area *control;
1469 * The following fields are ignored when AVIC is enabled
1471 WARN_ON(kvm_vcpu_apicv_activated(&svm->vcpu));
1473 svm_set_intercept(svm, INTERCEPT_VINTR);
1476 * This is just a dummy VINTR to actually cause a vmexit to happen.
1477 * Actual injection of virtual interrupts happens through EVENTINJ.
1479 control = &svm->vmcb->control;
1480 control->int_vector = 0x0;
1481 control->int_ctl &= ~V_INTR_PRIO_MASK;
1482 control->int_ctl |= V_IRQ_MASK |
1483 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1484 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1487 static void svm_clear_vintr(struct vcpu_svm *svm)
1489 svm_clr_intercept(svm, INTERCEPT_VINTR);
1491 /* Drop int_ctl fields related to VINTR injection. */
1492 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1493 if (is_guest_mode(&svm->vcpu)) {
1494 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1496 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1497 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1499 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1500 V_IRQ_INJECTION_BITS_MASK;
1502 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1505 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1508 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1510 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1511 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1514 case VCPU_SREG_CS: return &save->cs;
1515 case VCPU_SREG_DS: return &save->ds;
1516 case VCPU_SREG_ES: return &save->es;
1517 case VCPU_SREG_FS: return &save01->fs;
1518 case VCPU_SREG_GS: return &save01->gs;
1519 case VCPU_SREG_SS: return &save->ss;
1520 case VCPU_SREG_TR: return &save01->tr;
1521 case VCPU_SREG_LDTR: return &save01->ldtr;
1527 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1529 struct vmcb_seg *s = svm_seg(vcpu, seg);
1534 static void svm_get_segment(struct kvm_vcpu *vcpu,
1535 struct kvm_segment *var, int seg)
1537 struct vmcb_seg *s = svm_seg(vcpu, seg);
1539 var->base = s->base;
1540 var->limit = s->limit;
1541 var->selector = s->selector;
1542 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1543 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1544 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1545 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1546 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1547 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1548 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1551 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1552 * However, the SVM spec states that the G bit is not observed by the
1553 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1554 * So let's synthesize a legal G bit for all segments, this helps
1555 * running KVM nested. It also helps cross-vendor migration, because
1556 * Intel's vmentry has a check on the 'G' bit.
1558 var->g = s->limit > 0xfffff;
1561 * AMD's VMCB does not have an explicit unusable field, so emulate it
1562 * for cross vendor migration purposes by "not present"
1564 var->unusable = !var->present;
1569 * Work around a bug where the busy flag in the tr selector
1579 * The accessed bit must always be set in the segment
1580 * descriptor cache, although it can be cleared in the
1581 * descriptor, the cached bit always remains at 1. Since
1582 * Intel has a check on this, set it here to support
1583 * cross-vendor migration.
1590 * On AMD CPUs sometimes the DB bit in the segment
1591 * descriptor is left as 1, although the whole segment has
1592 * been made unusable. Clear it here to pass an Intel VMX
1593 * entry check when cross vendor migrating.
1597 /* This is symmetric with svm_set_segment() */
1598 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1603 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1605 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1610 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1612 struct kvm_segment cs;
1614 svm_get_segment(vcpu, &cs, VCPU_SREG_CS);
1619 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1621 struct vcpu_svm *svm = to_svm(vcpu);
1623 dt->size = svm->vmcb->save.idtr.limit;
1624 dt->address = svm->vmcb->save.idtr.base;
1627 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1629 struct vcpu_svm *svm = to_svm(vcpu);
1631 svm->vmcb->save.idtr.limit = dt->size;
1632 svm->vmcb->save.idtr.base = dt->address ;
1633 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1636 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1638 struct vcpu_svm *svm = to_svm(vcpu);
1640 dt->size = svm->vmcb->save.gdtr.limit;
1641 dt->address = svm->vmcb->save.gdtr.base;
1644 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1646 struct vcpu_svm *svm = to_svm(vcpu);
1648 svm->vmcb->save.gdtr.limit = dt->size;
1649 svm->vmcb->save.gdtr.base = dt->address ;
1650 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1653 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1655 struct vcpu_svm *svm = to_svm(vcpu);
1658 * For guests that don't set guest_state_protected, the cr3 update is
1659 * handled via kvm_mmu_load() while entering the guest. For guests
1660 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to
1661 * VMCB save area now, since the save area will become the initial
1662 * contents of the VMSA, and future VMCB save area updates won't be
1665 if (sev_es_guest(vcpu->kvm)) {
1666 svm->vmcb->save.cr3 = cr3;
1667 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1671 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1673 struct vcpu_svm *svm = to_svm(vcpu);
1675 bool old_paging = is_paging(vcpu);
1677 #ifdef CONFIG_X86_64
1678 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1679 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1680 vcpu->arch.efer |= EFER_LMA;
1681 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1684 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1685 vcpu->arch.efer &= ~EFER_LMA;
1686 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1690 vcpu->arch.cr0 = cr0;
1693 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1694 if (old_paging != is_paging(vcpu))
1695 svm_set_cr4(vcpu, kvm_read_cr4(vcpu));
1699 * re-enable caching here because the QEMU bios
1700 * does not do it - this results in some delay at
1703 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1704 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1706 svm->vmcb->save.cr0 = hcr0;
1707 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1710 * SEV-ES guests must always keep the CR intercepts cleared. CR
1711 * tracking is done using the CR write traps.
1713 if (sev_es_guest(vcpu->kvm))
1717 /* Selective CR0 write remains on. */
1718 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1719 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1721 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1722 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1726 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1731 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1733 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1734 unsigned long old_cr4 = vcpu->arch.cr4;
1736 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1737 svm_flush_tlb_current(vcpu);
1739 vcpu->arch.cr4 = cr4;
1743 if (!is_paging(vcpu))
1744 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
1746 cr4 |= host_cr4_mce;
1747 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1748 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1750 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1751 kvm_update_cpuid_runtime(vcpu);
1754 static void svm_set_segment(struct kvm_vcpu *vcpu,
1755 struct kvm_segment *var, int seg)
1757 struct vcpu_svm *svm = to_svm(vcpu);
1758 struct vmcb_seg *s = svm_seg(vcpu, seg);
1760 s->base = var->base;
1761 s->limit = var->limit;
1762 s->selector = var->selector;
1763 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1764 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1765 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1766 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1767 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1768 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1769 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1770 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1773 * This is always accurate, except if SYSRET returned to a segment
1774 * with SS.DPL != 3. Intel does not have this quirk, and always
1775 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1776 * would entail passing the CPL to userspace and back.
1778 if (seg == VCPU_SREG_SS)
1779 /* This is symmetric with svm_get_segment() */
1780 svm->vmcb->save.cpl = (var->dpl & 3);
1782 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1785 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1787 struct vcpu_svm *svm = to_svm(vcpu);
1789 clr_exception_intercept(svm, BP_VECTOR);
1791 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1792 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1793 set_exception_intercept(svm, BP_VECTOR);
1797 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1799 if (sd->next_asid > sd->max_asid) {
1800 ++sd->asid_generation;
1801 sd->next_asid = sd->min_asid;
1802 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1803 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1806 svm->current_vmcb->asid_generation = sd->asid_generation;
1807 svm->asid = sd->next_asid++;
1810 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1812 struct vmcb *vmcb = svm->vmcb;
1814 if (svm->vcpu.arch.guest_state_protected)
1817 if (unlikely(value != vmcb->save.dr6)) {
1818 vmcb->save.dr6 = value;
1819 vmcb_mark_dirty(vmcb, VMCB_DR);
1823 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1825 struct vcpu_svm *svm = to_svm(vcpu);
1827 if (vcpu->arch.guest_state_protected)
1830 get_debugreg(vcpu->arch.db[0], 0);
1831 get_debugreg(vcpu->arch.db[1], 1);
1832 get_debugreg(vcpu->arch.db[2], 2);
1833 get_debugreg(vcpu->arch.db[3], 3);
1835 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1836 * because db_interception might need it. We can do it before vmentry.
1838 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1839 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1840 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1841 set_dr_intercepts(svm);
1844 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1846 struct vcpu_svm *svm = to_svm(vcpu);
1848 if (vcpu->arch.guest_state_protected)
1851 svm->vmcb->save.dr7 = value;
1852 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1855 static int pf_interception(struct kvm_vcpu *vcpu)
1857 struct vcpu_svm *svm = to_svm(vcpu);
1859 u64 fault_address = svm->vmcb->control.exit_info_2;
1860 u64 error_code = svm->vmcb->control.exit_info_1;
1862 return kvm_handle_page_fault(vcpu, error_code, fault_address,
1863 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1864 svm->vmcb->control.insn_bytes : NULL,
1865 svm->vmcb->control.insn_len);
1868 static int npf_interception(struct kvm_vcpu *vcpu)
1870 struct vcpu_svm *svm = to_svm(vcpu);
1872 u64 fault_address = svm->vmcb->control.exit_info_2;
1873 u64 error_code = svm->vmcb->control.exit_info_1;
1875 trace_kvm_page_fault(fault_address, error_code);
1876 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1877 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1878 svm->vmcb->control.insn_bytes : NULL,
1879 svm->vmcb->control.insn_len);
1882 static int db_interception(struct kvm_vcpu *vcpu)
1884 struct kvm_run *kvm_run = vcpu->run;
1885 struct vcpu_svm *svm = to_svm(vcpu);
1887 if (!(vcpu->guest_debug &
1888 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1889 !svm->nmi_singlestep) {
1890 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1891 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1895 if (svm->nmi_singlestep) {
1896 disable_nmi_singlestep(svm);
1897 /* Make sure we check for pending NMIs upon entry */
1898 kvm_make_request(KVM_REQ_EVENT, vcpu);
1901 if (vcpu->guest_debug &
1902 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1903 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1904 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1905 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1906 kvm_run->debug.arch.pc =
1907 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1908 kvm_run->debug.arch.exception = DB_VECTOR;
1915 static int bp_interception(struct kvm_vcpu *vcpu)
1917 struct vcpu_svm *svm = to_svm(vcpu);
1918 struct kvm_run *kvm_run = vcpu->run;
1920 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1921 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1922 kvm_run->debug.arch.exception = BP_VECTOR;
1926 static int ud_interception(struct kvm_vcpu *vcpu)
1928 return handle_ud(vcpu);
1931 static int ac_interception(struct kvm_vcpu *vcpu)
1933 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1937 static bool is_erratum_383(void)
1942 if (!erratum_383_found)
1945 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1949 /* Bit 62 may or may not be set for this mce */
1950 value &= ~(1ULL << 62);
1952 if (value != 0xb600000000010015ULL)
1955 /* Clear MCi_STATUS registers */
1956 for (i = 0; i < 6; ++i)
1957 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1959 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1963 value &= ~(1ULL << 2);
1964 low = lower_32_bits(value);
1965 high = upper_32_bits(value);
1967 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1970 /* Flush tlb to evict multi-match entries */
1976 static void svm_handle_mce(struct kvm_vcpu *vcpu)
1978 if (is_erratum_383()) {
1980 * Erratum 383 triggered. Guest state is corrupt so kill the
1983 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1985 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1991 * On an #MC intercept the MCE handler is not called automatically in
1992 * the host. So do it by hand here.
1994 kvm_machine_check();
1997 static int mc_interception(struct kvm_vcpu *vcpu)
2002 static int shutdown_interception(struct kvm_vcpu *vcpu)
2004 struct kvm_run *kvm_run = vcpu->run;
2005 struct vcpu_svm *svm = to_svm(vcpu);
2008 * The VM save area has already been encrypted so it
2009 * cannot be reinitialized - just terminate.
2011 if (sev_es_guest(vcpu->kvm))
2015 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
2016 * the VMCB in a known good state. Unfortuately, KVM doesn't have
2017 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2018 * userspace. At a platform view, INIT is acceptable behavior as
2019 * there exist bare metal platforms that automatically INIT the CPU
2020 * in response to shutdown.
2022 clear_page(svm->vmcb);
2023 kvm_vcpu_reset(vcpu, true);
2025 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2029 static int io_interception(struct kvm_vcpu *vcpu)
2031 struct vcpu_svm *svm = to_svm(vcpu);
2032 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2033 int size, in, string;
2036 ++vcpu->stat.io_exits;
2037 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2038 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2039 port = io_info >> 16;
2040 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2043 if (sev_es_guest(vcpu->kvm))
2044 return sev_es_string_io(svm, size, port, in);
2046 return kvm_emulate_instruction(vcpu, 0);
2049 svm->next_rip = svm->vmcb->control.exit_info_2;
2051 return kvm_fast_pio(vcpu, size, port, in);
2054 static int nmi_interception(struct kvm_vcpu *vcpu)
2059 static int smi_interception(struct kvm_vcpu *vcpu)
2064 static int intr_interception(struct kvm_vcpu *vcpu)
2066 ++vcpu->stat.irq_exits;
2070 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2072 struct vcpu_svm *svm = to_svm(vcpu);
2073 struct vmcb *vmcb12;
2074 struct kvm_host_map map;
2077 if (nested_svm_check_permissions(vcpu))
2080 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2083 kvm_inject_gp(vcpu, 0);
2089 ret = kvm_skip_emulated_instruction(vcpu);
2092 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2093 svm->sysenter_eip_hi = 0;
2094 svm->sysenter_esp_hi = 0;
2096 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2099 kvm_vcpu_unmap(vcpu, &map, true);
2104 static int vmload_interception(struct kvm_vcpu *vcpu)
2106 return vmload_vmsave_interception(vcpu, true);
2109 static int vmsave_interception(struct kvm_vcpu *vcpu)
2111 return vmload_vmsave_interception(vcpu, false);
2114 static int vmrun_interception(struct kvm_vcpu *vcpu)
2116 if (nested_svm_check_permissions(vcpu))
2119 return nested_svm_vmrun(vcpu);
2129 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2130 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2132 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2134 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2135 return NONE_SVM_INSTR;
2137 switch (ctxt->modrm) {
2138 case 0xd8: /* VMRUN */
2139 return SVM_INSTR_VMRUN;
2140 case 0xda: /* VMLOAD */
2141 return SVM_INSTR_VMLOAD;
2142 case 0xdb: /* VMSAVE */
2143 return SVM_INSTR_VMSAVE;
2148 return NONE_SVM_INSTR;
2151 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2153 const int guest_mode_exit_codes[] = {
2154 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2155 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2156 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2158 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2159 [SVM_INSTR_VMRUN] = vmrun_interception,
2160 [SVM_INSTR_VMLOAD] = vmload_interception,
2161 [SVM_INSTR_VMSAVE] = vmsave_interception,
2163 struct vcpu_svm *svm = to_svm(vcpu);
2166 if (is_guest_mode(vcpu)) {
2167 /* Returns '1' or -errno on failure, '0' on success. */
2168 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2173 return svm_instr_handlers[opcode](vcpu);
2177 * #GP handling code. Note that #GP can be triggered under the following two
2179 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2180 * some AMD CPUs when EAX of these instructions are in the reserved memory
2181 * regions (e.g. SMM memory on host).
2182 * 2) VMware backdoor
2184 static int gp_interception(struct kvm_vcpu *vcpu)
2186 struct vcpu_svm *svm = to_svm(vcpu);
2187 u32 error_code = svm->vmcb->control.exit_info_1;
2190 /* Both #GP cases have zero error_code */
2194 /* Decode the instruction for usage later */
2195 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2198 opcode = svm_instr_opcode(vcpu);
2200 if (opcode == NONE_SVM_INSTR) {
2201 if (!enable_vmware_backdoor)
2205 * VMware backdoor emulation on #GP interception only handles
2206 * IN{S}, OUT{S}, and RDPMC.
2208 if (!is_guest_mode(vcpu))
2209 return kvm_emulate_instruction(vcpu,
2210 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2212 /* All SVM instructions expect page aligned RAX */
2213 if (svm->vmcb->save.rax & ~PAGE_MASK)
2216 return emulate_svm_instr(vcpu, opcode);
2220 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2224 void svm_set_gif(struct vcpu_svm *svm, bool value)
2228 * If VGIF is enabled, the STGI intercept is only added to
2229 * detect the opening of the SMI/NMI window; remove it now.
2230 * Likewise, clear the VINTR intercept, we will set it
2231 * again while processing KVM_REQ_EVENT if needed.
2234 svm_clr_intercept(svm, INTERCEPT_STGI);
2235 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2236 svm_clear_vintr(svm);
2239 if (svm->vcpu.arch.smi_pending ||
2240 svm->vcpu.arch.nmi_pending ||
2241 kvm_cpu_has_injectable_intr(&svm->vcpu))
2242 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2247 * After a CLGI no interrupts should come. But if vGIF is
2248 * in use, we still rely on the VINTR intercept (rather than
2249 * STGI) to detect an open interrupt window.
2252 svm_clear_vintr(svm);
2256 static int stgi_interception(struct kvm_vcpu *vcpu)
2260 if (nested_svm_check_permissions(vcpu))
2263 ret = kvm_skip_emulated_instruction(vcpu);
2264 svm_set_gif(to_svm(vcpu), true);
2268 static int clgi_interception(struct kvm_vcpu *vcpu)
2272 if (nested_svm_check_permissions(vcpu))
2275 ret = kvm_skip_emulated_instruction(vcpu);
2276 svm_set_gif(to_svm(vcpu), false);
2280 static int invlpga_interception(struct kvm_vcpu *vcpu)
2282 gva_t gva = kvm_rax_read(vcpu);
2283 u32 asid = kvm_rcx_read(vcpu);
2285 /* FIXME: Handle an address size prefix. */
2286 if (!is_long_mode(vcpu))
2289 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2291 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2292 kvm_mmu_invlpg(vcpu, gva);
2294 return kvm_skip_emulated_instruction(vcpu);
2297 static int skinit_interception(struct kvm_vcpu *vcpu)
2299 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2301 kvm_queue_exception(vcpu, UD_VECTOR);
2305 static int task_switch_interception(struct kvm_vcpu *vcpu)
2307 struct vcpu_svm *svm = to_svm(vcpu);
2310 int int_type = svm->vmcb->control.exit_int_info &
2311 SVM_EXITINTINFO_TYPE_MASK;
2312 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2314 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2316 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2317 bool has_error_code = false;
2320 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2322 if (svm->vmcb->control.exit_info_2 &
2323 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2324 reason = TASK_SWITCH_IRET;
2325 else if (svm->vmcb->control.exit_info_2 &
2326 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2327 reason = TASK_SWITCH_JMP;
2329 reason = TASK_SWITCH_GATE;
2331 reason = TASK_SWITCH_CALL;
2333 if (reason == TASK_SWITCH_GATE) {
2335 case SVM_EXITINTINFO_TYPE_NMI:
2336 vcpu->arch.nmi_injected = false;
2338 case SVM_EXITINTINFO_TYPE_EXEPT:
2339 if (svm->vmcb->control.exit_info_2 &
2340 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2341 has_error_code = true;
2343 (u32)svm->vmcb->control.exit_info_2;
2345 kvm_clear_exception_queue(vcpu);
2347 case SVM_EXITINTINFO_TYPE_INTR:
2348 kvm_clear_interrupt_queue(vcpu);
2355 if (reason != TASK_SWITCH_GATE ||
2356 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2357 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2358 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2359 if (!svm_skip_emulated_instruction(vcpu))
2363 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2366 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2367 has_error_code, error_code);
2370 static int iret_interception(struct kvm_vcpu *vcpu)
2372 struct vcpu_svm *svm = to_svm(vcpu);
2374 ++vcpu->stat.nmi_window_exits;
2375 vcpu->arch.hflags |= HF_IRET_MASK;
2376 if (!sev_es_guest(vcpu->kvm)) {
2377 svm_clr_intercept(svm, INTERCEPT_IRET);
2378 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2380 kvm_make_request(KVM_REQ_EVENT, vcpu);
2384 static int invlpg_interception(struct kvm_vcpu *vcpu)
2386 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2387 return kvm_emulate_instruction(vcpu, 0);
2389 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2390 return kvm_skip_emulated_instruction(vcpu);
2393 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2395 return kvm_emulate_instruction(vcpu, 0);
2398 static int rsm_interception(struct kvm_vcpu *vcpu)
2400 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2403 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2406 struct vcpu_svm *svm = to_svm(vcpu);
2407 unsigned long cr0 = vcpu->arch.cr0;
2410 if (!is_guest_mode(vcpu) ||
2411 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2414 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2415 val &= ~SVM_CR0_SELECTIVE_MASK;
2418 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2419 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2425 #define CR_VALID (1ULL << 63)
2427 static int cr_interception(struct kvm_vcpu *vcpu)
2429 struct vcpu_svm *svm = to_svm(vcpu);
2434 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2435 return emulate_on_interception(vcpu);
2437 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2438 return emulate_on_interception(vcpu);
2440 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2441 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2442 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2444 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2447 if (cr >= 16) { /* mov to cr */
2449 val = kvm_register_read(vcpu, reg);
2450 trace_kvm_cr_write(cr, val);
2453 if (!check_selective_cr0_intercepted(vcpu, val))
2454 err = kvm_set_cr0(vcpu, val);
2460 err = kvm_set_cr3(vcpu, val);
2463 err = kvm_set_cr4(vcpu, val);
2466 err = kvm_set_cr8(vcpu, val);
2469 WARN(1, "unhandled write to CR%d", cr);
2470 kvm_queue_exception(vcpu, UD_VECTOR);
2473 } else { /* mov from cr */
2476 val = kvm_read_cr0(vcpu);
2479 val = vcpu->arch.cr2;
2482 val = kvm_read_cr3(vcpu);
2485 val = kvm_read_cr4(vcpu);
2488 val = kvm_get_cr8(vcpu);
2491 WARN(1, "unhandled read from CR%d", cr);
2492 kvm_queue_exception(vcpu, UD_VECTOR);
2495 kvm_register_write(vcpu, reg, val);
2496 trace_kvm_cr_read(cr, val);
2498 return kvm_complete_insn_gp(vcpu, err);
2501 static int cr_trap(struct kvm_vcpu *vcpu)
2503 struct vcpu_svm *svm = to_svm(vcpu);
2504 unsigned long old_value, new_value;
2508 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2510 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2513 old_value = kvm_read_cr0(vcpu);
2514 svm_set_cr0(vcpu, new_value);
2516 kvm_post_set_cr0(vcpu, old_value, new_value);
2519 old_value = kvm_read_cr4(vcpu);
2520 svm_set_cr4(vcpu, new_value);
2522 kvm_post_set_cr4(vcpu, old_value, new_value);
2525 ret = kvm_set_cr8(vcpu, new_value);
2528 WARN(1, "unhandled CR%d write trap", cr);
2529 kvm_queue_exception(vcpu, UD_VECTOR);
2533 return kvm_complete_insn_gp(vcpu, ret);
2536 static int dr_interception(struct kvm_vcpu *vcpu)
2538 struct vcpu_svm *svm = to_svm(vcpu);
2543 if (vcpu->guest_debug == 0) {
2545 * No more DR vmexits; force a reload of the debug registers
2546 * and reenter on this instruction. The next vmexit will
2547 * retrieve the full state of the debug registers.
2549 clr_dr_intercepts(svm);
2550 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2554 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2555 return emulate_on_interception(vcpu);
2557 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2558 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2559 if (dr >= 16) { /* mov to DRn */
2561 val = kvm_register_read(vcpu, reg);
2562 err = kvm_set_dr(vcpu, dr, val);
2564 kvm_get_dr(vcpu, dr, &val);
2565 kvm_register_write(vcpu, reg, val);
2568 return kvm_complete_insn_gp(vcpu, err);
2571 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2575 u8 cr8_prev = kvm_get_cr8(vcpu);
2576 /* instruction emulation calls kvm_set_cr8() */
2577 r = cr_interception(vcpu);
2578 if (lapic_in_kernel(vcpu))
2580 if (cr8_prev <= kvm_get_cr8(vcpu))
2582 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2586 static int efer_trap(struct kvm_vcpu *vcpu)
2588 struct msr_data msr_info;
2592 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2593 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2594 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2595 * the guest doesn't have X86_FEATURE_SVM.
2597 msr_info.host_initiated = false;
2598 msr_info.index = MSR_EFER;
2599 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2600 ret = kvm_set_msr_common(vcpu, &msr_info);
2602 return kvm_complete_insn_gp(vcpu, ret);
2605 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2609 switch (msr->index) {
2610 case MSR_F10H_DECFG:
2611 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2612 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2614 case MSR_IA32_PERF_CAPABILITIES:
2617 return KVM_MSR_RET_INVALID;
2623 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2625 struct vcpu_svm *svm = to_svm(vcpu);
2627 switch (msr_info->index) {
2628 case MSR_AMD64_TSC_RATIO:
2629 if (!msr_info->host_initiated && !svm->tsc_scaling_enabled)
2631 msr_info->data = svm->tsc_ratio_msr;
2634 msr_info->data = svm->vmcb01.ptr->save.star;
2636 #ifdef CONFIG_X86_64
2638 msr_info->data = svm->vmcb01.ptr->save.lstar;
2641 msr_info->data = svm->vmcb01.ptr->save.cstar;
2643 case MSR_KERNEL_GS_BASE:
2644 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2646 case MSR_SYSCALL_MASK:
2647 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2650 case MSR_IA32_SYSENTER_CS:
2651 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2653 case MSR_IA32_SYSENTER_EIP:
2654 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2655 if (guest_cpuid_is_intel(vcpu))
2656 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2658 case MSR_IA32_SYSENTER_ESP:
2659 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2660 if (guest_cpuid_is_intel(vcpu))
2661 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2664 msr_info->data = svm->tsc_aux;
2666 case MSR_IA32_DEBUGCTLMSR:
2667 case MSR_IA32_LASTBRANCHFROMIP:
2668 case MSR_IA32_LASTBRANCHTOIP:
2669 case MSR_IA32_LASTINTFROMIP:
2670 case MSR_IA32_LASTINTTOIP:
2671 msr_info->data = svm_get_lbr_msr(svm, msr_info->index);
2673 case MSR_VM_HSAVE_PA:
2674 msr_info->data = svm->nested.hsave_msr;
2677 msr_info->data = svm->nested.vm_cr_msr;
2679 case MSR_IA32_SPEC_CTRL:
2680 if (!msr_info->host_initiated &&
2681 !guest_has_spec_ctrl_msr(vcpu))
2684 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2685 msr_info->data = svm->vmcb->save.spec_ctrl;
2687 msr_info->data = svm->spec_ctrl;
2689 case MSR_AMD64_VIRT_SPEC_CTRL:
2690 if (!msr_info->host_initiated &&
2691 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2694 msr_info->data = svm->virt_spec_ctrl;
2696 case MSR_F15H_IC_CFG: {
2700 family = guest_cpuid_family(vcpu);
2701 model = guest_cpuid_model(vcpu);
2703 if (family < 0 || model < 0)
2704 return kvm_get_msr_common(vcpu, msr_info);
2708 if (family == 0x15 &&
2709 (model >= 0x2 && model < 0x20))
2710 msr_info->data = 0x1E;
2713 case MSR_F10H_DECFG:
2714 msr_info->data = svm->msr_decfg;
2717 return kvm_get_msr_common(vcpu, msr_info);
2722 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2724 struct vcpu_svm *svm = to_svm(vcpu);
2725 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb))
2726 return kvm_complete_insn_gp(vcpu, err);
2728 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1);
2729 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
2731 SVM_EVTINJ_TYPE_EXEPT |
2736 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2738 struct vcpu_svm *svm = to_svm(vcpu);
2739 int svm_dis, chg_mask;
2741 if (data & ~SVM_VM_CR_VALID_MASK)
2744 chg_mask = SVM_VM_CR_VALID_MASK;
2746 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2747 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2749 svm->nested.vm_cr_msr &= ~chg_mask;
2750 svm->nested.vm_cr_msr |= (data & chg_mask);
2752 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2754 /* check for svm_disable while efer.svme is set */
2755 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2761 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2763 struct vcpu_svm *svm = to_svm(vcpu);
2766 u32 ecx = msr->index;
2767 u64 data = msr->data;
2769 case MSR_AMD64_TSC_RATIO:
2771 if (!svm->tsc_scaling_enabled) {
2773 if (!msr->host_initiated)
2776 * In case TSC scaling is not enabled, always
2777 * leave this MSR at the default value.
2779 * Due to bug in qemu 6.2.0, it would try to set
2780 * this msr to 0 if tsc scaling is not enabled.
2781 * Ignore this value as well.
2783 if (data != 0 && data != svm->tsc_ratio_msr)
2788 if (data & SVM_TSC_RATIO_RSVD)
2791 svm->tsc_ratio_msr = data;
2793 if (svm->tsc_scaling_enabled && is_guest_mode(vcpu))
2794 nested_svm_update_tsc_ratio_msr(vcpu);
2797 case MSR_IA32_CR_PAT:
2798 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2800 vcpu->arch.pat = data;
2801 svm->vmcb01.ptr->save.g_pat = data;
2802 if (is_guest_mode(vcpu))
2803 nested_vmcb02_compute_g_pat(svm);
2804 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2806 case MSR_IA32_SPEC_CTRL:
2807 if (!msr->host_initiated &&
2808 !guest_has_spec_ctrl_msr(vcpu))
2811 if (kvm_spec_ctrl_test_value(data))
2814 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2815 svm->vmcb->save.spec_ctrl = data;
2817 svm->spec_ctrl = data;
2823 * When it's written (to non-zero) for the first time, pass
2827 * The handling of the MSR bitmap for L2 guests is done in
2828 * nested_svm_vmrun_msrpm.
2829 * We update the L1 MSR bit as well since it will end up
2830 * touching the MSR anyway now.
2832 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2834 case MSR_IA32_PRED_CMD:
2835 if (!msr->host_initiated &&
2836 !guest_has_pred_cmd_msr(vcpu))
2839 if (data & ~PRED_CMD_IBPB)
2841 if (!boot_cpu_has(X86_FEATURE_IBPB))
2846 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2847 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2849 case MSR_AMD64_VIRT_SPEC_CTRL:
2850 if (!msr->host_initiated &&
2851 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2854 if (data & ~SPEC_CTRL_SSBD)
2857 svm->virt_spec_ctrl = data;
2860 svm->vmcb01.ptr->save.star = data;
2862 #ifdef CONFIG_X86_64
2864 svm->vmcb01.ptr->save.lstar = data;
2867 svm->vmcb01.ptr->save.cstar = data;
2869 case MSR_KERNEL_GS_BASE:
2870 svm->vmcb01.ptr->save.kernel_gs_base = data;
2872 case MSR_SYSCALL_MASK:
2873 svm->vmcb01.ptr->save.sfmask = data;
2876 case MSR_IA32_SYSENTER_CS:
2877 svm->vmcb01.ptr->save.sysenter_cs = data;
2879 case MSR_IA32_SYSENTER_EIP:
2880 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2882 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2883 * when we spoof an Intel vendor ID (for cross vendor migration).
2884 * In this case we use this intercept to track the high
2885 * 32 bit part of these msrs to support Intel's
2886 * implementation of SYSENTER/SYSEXIT.
2888 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2890 case MSR_IA32_SYSENTER_ESP:
2891 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2892 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2896 * TSC_AUX is usually changed only during boot and never read
2897 * directly. Intercept TSC_AUX instead of exposing it to the
2898 * guest via direct_access_msrs, and switch it via user return.
2901 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2906 svm->tsc_aux = data;
2908 case MSR_IA32_DEBUGCTLMSR:
2910 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2914 if (data & DEBUGCTL_RESERVED_BITS)
2917 if (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK)
2918 svm->vmcb->save.dbgctl = data;
2920 svm->vmcb01.ptr->save.dbgctl = data;
2922 svm_update_lbrv(vcpu);
2925 case MSR_VM_HSAVE_PA:
2927 * Old kernels did not validate the value written to
2928 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
2929 * value to allow live migrating buggy or malicious guests
2930 * originating from those kernels.
2932 if (!msr->host_initiated && !page_address_valid(vcpu, data))
2935 svm->nested.hsave_msr = data & PAGE_MASK;
2938 return svm_set_vm_cr(vcpu, data);
2940 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2942 case MSR_F10H_DECFG: {
2943 struct kvm_msr_entry msr_entry;
2945 msr_entry.index = msr->index;
2946 if (svm_get_msr_feature(&msr_entry))
2949 /* Check the supported bits */
2950 if (data & ~msr_entry.data)
2953 /* Don't allow the guest to change a bit, #GP */
2954 if (!msr->host_initiated && (data ^ msr_entry.data))
2957 svm->msr_decfg = data;
2961 return kvm_set_msr_common(vcpu, msr);
2966 static int msr_interception(struct kvm_vcpu *vcpu)
2968 if (to_svm(vcpu)->vmcb->control.exit_info_1)
2969 return kvm_emulate_wrmsr(vcpu);
2971 return kvm_emulate_rdmsr(vcpu);
2974 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2976 kvm_make_request(KVM_REQ_EVENT, vcpu);
2977 svm_clear_vintr(to_svm(vcpu));
2980 * If not running nested, for AVIC, the only reason to end up here is ExtINTs.
2981 * In this case AVIC was temporarily disabled for
2982 * requesting the IRQ window and we have to re-enable it.
2984 * If running nested, still remove the VM wide AVIC inhibit to
2985 * support case in which the interrupt window was requested when the
2986 * vCPU was not running nested.
2988 * All vCPUs which run still run nested, will remain to have their
2989 * AVIC still inhibited due to per-cpu AVIC inhibition.
2991 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
2993 ++vcpu->stat.irq_window_exits;
2997 static int pause_interception(struct kvm_vcpu *vcpu)
3001 * CPL is not made available for an SEV-ES guest, therefore
3002 * vcpu->arch.preempted_in_kernel can never be true. Just
3003 * set in_kernel to false as well.
3005 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3007 grow_ple_window(vcpu);
3009 kvm_vcpu_on_spin(vcpu, in_kernel);
3010 return kvm_skip_emulated_instruction(vcpu);
3013 static int invpcid_interception(struct kvm_vcpu *vcpu)
3015 struct vcpu_svm *svm = to_svm(vcpu);
3019 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3020 kvm_queue_exception(vcpu, UD_VECTOR);
3025 * For an INVPCID intercept:
3026 * EXITINFO1 provides the linear address of the memory operand.
3027 * EXITINFO2 provides the contents of the register operand.
3029 type = svm->vmcb->control.exit_info_2;
3030 gva = svm->vmcb->control.exit_info_1;
3032 return kvm_handle_invpcid(vcpu, type, gva);
3035 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3036 [SVM_EXIT_READ_CR0] = cr_interception,
3037 [SVM_EXIT_READ_CR3] = cr_interception,
3038 [SVM_EXIT_READ_CR4] = cr_interception,
3039 [SVM_EXIT_READ_CR8] = cr_interception,
3040 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3041 [SVM_EXIT_WRITE_CR0] = cr_interception,
3042 [SVM_EXIT_WRITE_CR3] = cr_interception,
3043 [SVM_EXIT_WRITE_CR4] = cr_interception,
3044 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3045 [SVM_EXIT_READ_DR0] = dr_interception,
3046 [SVM_EXIT_READ_DR1] = dr_interception,
3047 [SVM_EXIT_READ_DR2] = dr_interception,
3048 [SVM_EXIT_READ_DR3] = dr_interception,
3049 [SVM_EXIT_READ_DR4] = dr_interception,
3050 [SVM_EXIT_READ_DR5] = dr_interception,
3051 [SVM_EXIT_READ_DR6] = dr_interception,
3052 [SVM_EXIT_READ_DR7] = dr_interception,
3053 [SVM_EXIT_WRITE_DR0] = dr_interception,
3054 [SVM_EXIT_WRITE_DR1] = dr_interception,
3055 [SVM_EXIT_WRITE_DR2] = dr_interception,
3056 [SVM_EXIT_WRITE_DR3] = dr_interception,
3057 [SVM_EXIT_WRITE_DR4] = dr_interception,
3058 [SVM_EXIT_WRITE_DR5] = dr_interception,
3059 [SVM_EXIT_WRITE_DR6] = dr_interception,
3060 [SVM_EXIT_WRITE_DR7] = dr_interception,
3061 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3062 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3063 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3064 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3065 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3066 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3067 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3068 [SVM_EXIT_INTR] = intr_interception,
3069 [SVM_EXIT_NMI] = nmi_interception,
3070 [SVM_EXIT_SMI] = smi_interception,
3071 [SVM_EXIT_VINTR] = interrupt_window_interception,
3072 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
3073 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
3074 [SVM_EXIT_IRET] = iret_interception,
3075 [SVM_EXIT_INVD] = kvm_emulate_invd,
3076 [SVM_EXIT_PAUSE] = pause_interception,
3077 [SVM_EXIT_HLT] = kvm_emulate_halt,
3078 [SVM_EXIT_INVLPG] = invlpg_interception,
3079 [SVM_EXIT_INVLPGA] = invlpga_interception,
3080 [SVM_EXIT_IOIO] = io_interception,
3081 [SVM_EXIT_MSR] = msr_interception,
3082 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3083 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3084 [SVM_EXIT_VMRUN] = vmrun_interception,
3085 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3086 [SVM_EXIT_VMLOAD] = vmload_interception,
3087 [SVM_EXIT_VMSAVE] = vmsave_interception,
3088 [SVM_EXIT_STGI] = stgi_interception,
3089 [SVM_EXIT_CLGI] = clgi_interception,
3090 [SVM_EXIT_SKINIT] = skinit_interception,
3091 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3092 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3093 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3094 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3095 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3096 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3097 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3098 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3099 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3100 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3101 [SVM_EXIT_INVPCID] = invpcid_interception,
3102 [SVM_EXIT_NPF] = npf_interception,
3103 [SVM_EXIT_RSM] = rsm_interception,
3104 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3105 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3106 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3109 static void dump_vmcb(struct kvm_vcpu *vcpu)
3111 struct vcpu_svm *svm = to_svm(vcpu);
3112 struct vmcb_control_area *control = &svm->vmcb->control;
3113 struct vmcb_save_area *save = &svm->vmcb->save;
3114 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3116 if (!dump_invalid_vmcb) {
3117 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3121 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3122 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3123 pr_err("VMCB Control Area:\n");
3124 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3125 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3126 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3127 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3128 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3129 pr_err("%-20s%08x %08x\n", "intercepts:",
3130 control->intercepts[INTERCEPT_WORD3],
3131 control->intercepts[INTERCEPT_WORD4]);
3132 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3133 pr_err("%-20s%d\n", "pause filter threshold:",
3134 control->pause_filter_thresh);
3135 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3136 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3137 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3138 pr_err("%-20s%d\n", "asid:", control->asid);
3139 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3140 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3141 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3142 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3143 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3144 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3145 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3146 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3147 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3148 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3149 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3150 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3151 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3152 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3153 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3154 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3155 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3156 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3157 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3158 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3159 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3160 pr_err("VMCB State Save Area:\n");
3161 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3163 save->es.selector, save->es.attrib,
3164 save->es.limit, save->es.base);
3165 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3167 save->cs.selector, save->cs.attrib,
3168 save->cs.limit, save->cs.base);
3169 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3171 save->ss.selector, save->ss.attrib,
3172 save->ss.limit, save->ss.base);
3173 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3175 save->ds.selector, save->ds.attrib,
3176 save->ds.limit, save->ds.base);
3177 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3179 save01->fs.selector, save01->fs.attrib,
3180 save01->fs.limit, save01->fs.base);
3181 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3183 save01->gs.selector, save01->gs.attrib,
3184 save01->gs.limit, save01->gs.base);
3185 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3187 save->gdtr.selector, save->gdtr.attrib,
3188 save->gdtr.limit, save->gdtr.base);
3189 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3191 save01->ldtr.selector, save01->ldtr.attrib,
3192 save01->ldtr.limit, save01->ldtr.base);
3193 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3195 save->idtr.selector, save->idtr.attrib,
3196 save->idtr.limit, save->idtr.base);
3197 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3199 save01->tr.selector, save01->tr.attrib,
3200 save01->tr.limit, save01->tr.base);
3201 pr_err("vmpl: %d cpl: %d efer: %016llx\n",
3202 save->vmpl, save->cpl, save->efer);
3203 pr_err("%-15s %016llx %-13s %016llx\n",
3204 "cr0:", save->cr0, "cr2:", save->cr2);
3205 pr_err("%-15s %016llx %-13s %016llx\n",
3206 "cr3:", save->cr3, "cr4:", save->cr4);
3207 pr_err("%-15s %016llx %-13s %016llx\n",
3208 "dr6:", save->dr6, "dr7:", save->dr7);
3209 pr_err("%-15s %016llx %-13s %016llx\n",
3210 "rip:", save->rip, "rflags:", save->rflags);
3211 pr_err("%-15s %016llx %-13s %016llx\n",
3212 "rsp:", save->rsp, "rax:", save->rax);
3213 pr_err("%-15s %016llx %-13s %016llx\n",
3214 "star:", save01->star, "lstar:", save01->lstar);
3215 pr_err("%-15s %016llx %-13s %016llx\n",
3216 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3217 pr_err("%-15s %016llx %-13s %016llx\n",
3218 "kernel_gs_base:", save01->kernel_gs_base,
3219 "sysenter_cs:", save01->sysenter_cs);
3220 pr_err("%-15s %016llx %-13s %016llx\n",
3221 "sysenter_esp:", save01->sysenter_esp,
3222 "sysenter_eip:", save01->sysenter_eip);
3223 pr_err("%-15s %016llx %-13s %016llx\n",
3224 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3225 pr_err("%-15s %016llx %-13s %016llx\n",
3226 "br_from:", save->br_from, "br_to:", save->br_to);
3227 pr_err("%-15s %016llx %-13s %016llx\n",
3228 "excp_from:", save->last_excp_from,
3229 "excp_to:", save->last_excp_to);
3232 static bool svm_check_exit_valid(u64 exit_code)
3234 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3235 svm_exit_handlers[exit_code]);
3238 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3240 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3242 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3243 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3244 vcpu->run->internal.ndata = 2;
3245 vcpu->run->internal.data[0] = exit_code;
3246 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3250 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3252 if (!svm_check_exit_valid(exit_code))
3253 return svm_handle_invalid_exit(vcpu, exit_code);
3255 #ifdef CONFIG_RETPOLINE
3256 if (exit_code == SVM_EXIT_MSR)
3257 return msr_interception(vcpu);
3258 else if (exit_code == SVM_EXIT_VINTR)
3259 return interrupt_window_interception(vcpu);
3260 else if (exit_code == SVM_EXIT_INTR)
3261 return intr_interception(vcpu);
3262 else if (exit_code == SVM_EXIT_HLT)
3263 return kvm_emulate_halt(vcpu);
3264 else if (exit_code == SVM_EXIT_NPF)
3265 return npf_interception(vcpu);
3267 return svm_exit_handlers[exit_code](vcpu);
3270 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
3271 u64 *info1, u64 *info2,
3272 u32 *intr_info, u32 *error_code)
3274 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3276 *reason = control->exit_code;
3277 *info1 = control->exit_info_1;
3278 *info2 = control->exit_info_2;
3279 *intr_info = control->exit_int_info;
3280 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3281 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3282 *error_code = control->exit_int_info_err;
3287 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3289 struct vcpu_svm *svm = to_svm(vcpu);
3290 struct kvm_run *kvm_run = vcpu->run;
3291 u32 exit_code = svm->vmcb->control.exit_code;
3293 trace_kvm_exit(vcpu, KVM_ISA_SVM);
3295 /* SEV-ES guests must use the CR write traps to track CR registers. */
3296 if (!sev_es_guest(vcpu->kvm)) {
3297 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3298 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3300 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3303 if (is_guest_mode(vcpu)) {
3306 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM);
3308 vmexit = nested_svm_exit_special(svm);
3310 if (vmexit == NESTED_EXIT_CONTINUE)
3311 vmexit = nested_svm_exit_handled(svm);
3313 if (vmexit == NESTED_EXIT_DONE)
3317 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3318 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3319 kvm_run->fail_entry.hardware_entry_failure_reason
3320 = svm->vmcb->control.exit_code;
3321 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3326 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3327 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3328 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3329 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3330 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3332 __func__, svm->vmcb->control.exit_int_info,
3335 if (exit_fastpath != EXIT_FASTPATH_NONE)
3338 return svm_invoke_exit_handler(vcpu, exit_code);
3341 static void reload_tss(struct kvm_vcpu *vcpu)
3343 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3345 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3349 static void pre_svm_run(struct kvm_vcpu *vcpu)
3351 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3352 struct vcpu_svm *svm = to_svm(vcpu);
3355 * If the previous vmrun of the vmcb occurred on a different physical
3356 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3357 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3359 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3360 svm->current_vmcb->asid_generation = 0;
3361 vmcb_mark_all_dirty(svm->vmcb);
3362 svm->current_vmcb->cpu = vcpu->cpu;
3365 if (sev_guest(vcpu->kvm))
3366 return pre_sev_run(svm, vcpu->cpu);
3368 /* FIXME: handle wraparound of asid_generation */
3369 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3373 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3375 struct vcpu_svm *svm = to_svm(vcpu);
3377 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3378 vcpu->arch.hflags |= HF_NMI_MASK;
3379 if (!sev_es_guest(vcpu->kvm))
3380 svm_set_intercept(svm, INTERCEPT_IRET);
3381 ++vcpu->stat.nmi_injections;
3384 static void svm_inject_irq(struct kvm_vcpu *vcpu)
3386 struct vcpu_svm *svm = to_svm(vcpu);
3388 BUG_ON(!(gif_set(svm)));
3390 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3391 ++vcpu->stat.irq_injections;
3393 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3394 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3397 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
3398 int trig_mode, int vector)
3401 * vcpu->arch.apicv_active must be read after vcpu->mode.
3402 * Pairs with smp_store_release in vcpu_enter_guest.
3404 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
3406 if (!READ_ONCE(vcpu->arch.apicv_active)) {
3407 /* Process the interrupt via inject_pending_event */
3408 kvm_make_request(KVM_REQ_EVENT, vcpu);
3409 kvm_vcpu_kick(vcpu);
3413 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector);
3414 if (in_guest_mode) {
3416 * Signal the doorbell to tell hardware to inject the IRQ. If
3417 * the vCPU exits the guest before the doorbell chimes, hardware
3418 * will automatically process AVIC interrupts at the next VMRUN.
3420 avic_ring_doorbell(vcpu);
3423 * Wake the vCPU if it was blocking. KVM will then detect the
3424 * pending IRQ when checking if the vCPU has a wake event.
3426 kvm_vcpu_wake_up(vcpu);
3430 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3431 int trig_mode, int vector)
3433 kvm_lapic_set_irr(vector, apic);
3436 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in
3437 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before
3438 * the read of guest_mode. This guarantees that either VMRUN will see
3439 * and process the new vIRR entry, or that svm_complete_interrupt_delivery
3440 * will signal the doorbell if the CPU has already entered the guest.
3442 smp_mb__after_atomic();
3443 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);
3446 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3448 struct vcpu_svm *svm = to_svm(vcpu);
3451 * SEV-ES guests must always keep the CR intercepts cleared. CR
3452 * tracking is done using the CR write traps.
3454 if (sev_es_guest(vcpu->kvm))
3457 if (nested_svm_virtualize_tpr(vcpu))
3460 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3466 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3469 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3471 struct vcpu_svm *svm = to_svm(vcpu);
3472 struct vmcb *vmcb = svm->vmcb;
3478 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3481 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3482 (vcpu->arch.hflags & HF_NMI_MASK);
3487 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3489 struct vcpu_svm *svm = to_svm(vcpu);
3490 if (svm->nested.nested_run_pending)
3493 if (svm_nmi_blocked(vcpu))
3496 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3497 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3502 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3504 return !!(vcpu->arch.hflags & HF_NMI_MASK);
3507 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3509 struct vcpu_svm *svm = to_svm(vcpu);
3512 vcpu->arch.hflags |= HF_NMI_MASK;
3513 if (!sev_es_guest(vcpu->kvm))
3514 svm_set_intercept(svm, INTERCEPT_IRET);
3516 vcpu->arch.hflags &= ~HF_NMI_MASK;
3517 if (!sev_es_guest(vcpu->kvm))
3518 svm_clr_intercept(svm, INTERCEPT_IRET);
3522 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3524 struct vcpu_svm *svm = to_svm(vcpu);
3525 struct vmcb *vmcb = svm->vmcb;
3530 if (is_guest_mode(vcpu)) {
3531 /* As long as interrupts are being delivered... */
3532 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3533 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3534 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3537 /* ... vmexits aren't blocked by the interrupt shadow */
3538 if (nested_exit_on_intr(svm))
3541 if (!svm_get_if_flag(vcpu))
3545 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3548 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3550 struct vcpu_svm *svm = to_svm(vcpu);
3552 if (svm->nested.nested_run_pending)
3555 if (svm_interrupt_blocked(vcpu))
3559 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3560 * e.g. if the IRQ arrived asynchronously after checking nested events.
3562 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3568 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3570 struct vcpu_svm *svm = to_svm(vcpu);
3573 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3574 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3575 * get that intercept, this function will be called again though and
3576 * we'll get the vintr intercept. However, if the vGIF feature is
3577 * enabled, the STGI interception will not occur. Enable the irq
3578 * window under the assumption that the hardware will set the GIF.
3580 if (vgif || gif_set(svm)) {
3582 * IRQ window is not needed when AVIC is enabled,
3583 * unless we have pending ExtINT since it cannot be injected
3584 * via AVIC. In such case, KVM needs to temporarily disable AVIC,
3585 * and fallback to injecting IRQ via V_IRQ.
3587 * If running nested, AVIC is already locally inhibited
3588 * on this vCPU, therefore there is no need to request
3589 * the VM wide AVIC inhibition.
3591 if (!is_guest_mode(vcpu))
3592 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3598 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3600 struct vcpu_svm *svm = to_svm(vcpu);
3602 if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3603 return; /* IRET will cause a vm exit */
3605 if (!gif_set(svm)) {
3607 svm_set_intercept(svm, INTERCEPT_STGI);
3608 return; /* STGI will cause a vm exit */
3612 * Something prevents NMI from been injected. Single step over possible
3613 * problem (IRET or exception injection or interrupt shadow)
3615 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3616 svm->nmi_singlestep = true;
3617 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3620 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu)
3622 struct vcpu_svm *svm = to_svm(vcpu);
3625 * Flush only the current ASID even if the TLB flush was invoked via
3626 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3627 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3628 * unconditionally does a TLB flush on both nested VM-Enter and nested
3629 * VM-Exit (via kvm_mmu_reset_context()).
3631 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3632 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3634 svm->current_vmcb->asid_generation--;
3637 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3639 struct vcpu_svm *svm = to_svm(vcpu);
3641 invlpga(gva, svm->vmcb->control.asid);
3644 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3646 struct vcpu_svm *svm = to_svm(vcpu);
3648 if (nested_svm_virtualize_tpr(vcpu))
3651 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3652 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3653 kvm_set_cr8(vcpu, cr8);
3657 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3659 struct vcpu_svm *svm = to_svm(vcpu);
3662 if (nested_svm_virtualize_tpr(vcpu) ||
3663 kvm_vcpu_apicv_active(vcpu))
3666 cr8 = kvm_get_cr8(vcpu);
3667 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3668 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3671 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3673 struct vcpu_svm *svm = to_svm(vcpu);
3676 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3677 unsigned int3_injected = svm->int3_injected;
3679 svm->int3_injected = 0;
3682 * If we've made progress since setting HF_IRET_MASK, we've
3683 * executed an IRET and can allow NMI injection.
3685 if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3686 (sev_es_guest(vcpu->kvm) ||
3687 kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3688 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3689 kvm_make_request(KVM_REQ_EVENT, vcpu);
3692 vcpu->arch.nmi_injected = false;
3693 kvm_clear_exception_queue(vcpu);
3694 kvm_clear_interrupt_queue(vcpu);
3696 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3699 kvm_make_request(KVM_REQ_EVENT, vcpu);
3701 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3702 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3705 case SVM_EXITINTINFO_TYPE_NMI:
3706 vcpu->arch.nmi_injected = true;
3708 case SVM_EXITINTINFO_TYPE_EXEPT:
3710 * Never re-inject a #VC exception.
3712 if (vector == X86_TRAP_VC)
3716 * In case of software exceptions, do not reinject the vector,
3717 * but re-execute the instruction instead. Rewind RIP first
3718 * if we emulated INT3 before.
3720 if (kvm_exception_is_soft(vector)) {
3721 if (vector == BP_VECTOR && int3_injected &&
3722 kvm_is_linear_rip(vcpu, svm->int3_rip))
3724 kvm_rip_read(vcpu) - int3_injected);
3727 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3728 u32 err = svm->vmcb->control.exit_int_info_err;
3729 kvm_requeue_exception_e(vcpu, vector, err);
3732 kvm_requeue_exception(vcpu, vector);
3734 case SVM_EXITINTINFO_TYPE_INTR:
3735 kvm_queue_interrupt(vcpu, vector, false);
3742 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3744 struct vcpu_svm *svm = to_svm(vcpu);
3745 struct vmcb_control_area *control = &svm->vmcb->control;
3747 control->exit_int_info = control->event_inj;
3748 control->exit_int_info_err = control->event_inj_err;
3749 control->event_inj = 0;
3750 svm_complete_interrupts(vcpu);
3753 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu)
3758 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3760 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3761 to_svm(vcpu)->vmcb->control.exit_info_1)
3762 return handle_fastpath_set_msr_irqoff(vcpu);
3764 return EXIT_FASTPATH_NONE;
3767 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3769 struct vcpu_svm *svm = to_svm(vcpu);
3770 unsigned long vmcb_pa = svm->current_vmcb->pa;
3772 guest_state_enter_irqoff();
3774 if (sev_es_guest(vcpu->kvm)) {
3775 __svm_sev_es_vcpu_run(vmcb_pa);
3777 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3780 * Use a single vmcb (vmcb01 because it's always valid) for
3781 * context switching guest state via VMLOAD/VMSAVE, that way
3782 * the state doesn't need to be copied between vmcb01 and
3783 * vmcb02 when switching vmcbs for nested virtualization.
3785 vmload(svm->vmcb01.pa);
3786 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3787 vmsave(svm->vmcb01.pa);
3789 vmload(__sme_page_pa(sd->save_area));
3792 guest_state_exit_irqoff();
3795 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3797 struct vcpu_svm *svm = to_svm(vcpu);
3799 trace_kvm_entry(vcpu);
3801 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3802 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3803 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3806 * Disable singlestep if we're injecting an interrupt/exception.
3807 * We don't want our modified rflags to be pushed on the stack where
3808 * we might not be able to easily reset them if we disabled NMI
3811 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3813 * Event injection happens before external interrupts cause a
3814 * vmexit and interrupts are disabled here, so smp_send_reschedule
3815 * is enough to force an immediate vmexit.
3817 disable_nmi_singlestep(svm);
3818 smp_send_reschedule(vcpu->cpu);
3823 sync_lapic_to_cr8(vcpu);
3825 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3826 svm->vmcb->control.asid = svm->asid;
3827 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3829 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3831 svm_hv_update_vp_id(svm->vmcb, vcpu);
3834 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3837 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3838 svm_set_dr6(svm, vcpu->arch.dr6);
3840 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3843 kvm_load_guest_xsave_state(vcpu);
3845 kvm_wait_lapic_expire(vcpu);
3848 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3849 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3850 * is no need to worry about the conditional branch over the wrmsr
3851 * being speculatively taken.
3853 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3854 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3856 svm_vcpu_enter_exit(vcpu);
3859 * We do not use IBRS in the kernel. If this vCPU has used the
3860 * SPEC_CTRL MSR it may have left it on; save the value and
3861 * turn it off. This is much more efficient than blindly adding
3862 * it to the atomic save/restore list. Especially as the former
3863 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3865 * For non-nested case:
3866 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3870 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3873 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3874 unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3875 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3877 if (!sev_es_guest(vcpu->kvm))
3880 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3881 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3883 if (!sev_es_guest(vcpu->kvm)) {
3884 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3885 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3886 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3887 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3889 vcpu->arch.regs_dirty = 0;
3891 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3892 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI);
3894 kvm_load_host_xsave_state(vcpu);
3897 /* Any pending NMI will happen here */
3899 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3900 kvm_after_interrupt(vcpu);
3902 sync_cr8_to_lapic(vcpu);
3905 if (is_guest_mode(vcpu)) {
3906 nested_sync_control_from_vmcb02(svm);
3908 /* Track VMRUNs that have made past consistency checking */
3909 if (svm->nested.nested_run_pending &&
3910 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
3911 ++vcpu->stat.nested_run;
3913 svm->nested.nested_run_pending = 0;
3916 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3917 vmcb_mark_all_clean(svm->vmcb);
3919 /* if exit due to PF check for async PF */
3920 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3921 vcpu->arch.apf.host_apf_flags =
3922 kvm_read_and_reset_apf_flags();
3924 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET;
3927 * We need to handle MC intercepts here before the vcpu has a chance to
3928 * change the physical cpu
3930 if (unlikely(svm->vmcb->control.exit_code ==
3931 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3932 svm_handle_mce(vcpu);
3934 svm_complete_interrupts(vcpu);
3936 if (is_guest_mode(vcpu))
3937 return EXIT_FASTPATH_NONE;
3939 return svm_exit_handlers_fastpath(vcpu);
3942 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3945 struct vcpu_svm *svm = to_svm(vcpu);
3949 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3950 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3952 hv_track_root_tdp(vcpu, root_hpa);
3954 cr3 = vcpu->arch.cr3;
3955 } else if (vcpu->arch.mmu->root_role.level >= PT64_ROOT_4LEVEL) {
3956 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3958 /* PCID in the guest should be impossible with a 32-bit MMU. */
3959 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3963 svm->vmcb->save.cr3 = cr3;
3964 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3967 static int is_disabled(void)
3971 rdmsrl(MSR_VM_CR, vm_cr);
3972 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3979 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3982 * Patch in the VMMCALL instruction:
3984 hypercall[0] = 0x0f;
3985 hypercall[1] = 0x01;
3986 hypercall[2] = 0xd9;
3989 static int __init svm_check_processor_compat(void)
3995 * The kvm parameter can be NULL (module initialization, or invocation before
3996 * VM creation). Be sure to check the kvm parameter before using it.
3998 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4001 case MSR_IA32_MCG_EXT_CTL:
4002 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4004 case MSR_IA32_SMBASE:
4005 /* SEV-ES guests do not support SMM, so report false */
4006 if (kvm && sev_es_guest(kvm))
4016 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4021 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4023 struct vcpu_svm *svm = to_svm(vcpu);
4024 struct kvm_cpuid_entry2 *best;
4025 struct kvm *kvm = vcpu->kvm;
4027 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4028 boot_cpu_has(X86_FEATURE_XSAVE) &&
4029 boot_cpu_has(X86_FEATURE_XSAVES);
4031 /* Update nrips enabled cache */
4032 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4033 guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4035 svm->tsc_scaling_enabled = tsc_scaling && guest_cpuid_has(vcpu, X86_FEATURE_TSCRATEMSR);
4036 svm->lbrv_enabled = lbrv && guest_cpuid_has(vcpu, X86_FEATURE_LBRV);
4038 svm->v_vmload_vmsave_enabled = vls && guest_cpuid_has(vcpu, X86_FEATURE_V_VMSAVE_VMLOAD);
4040 svm->pause_filter_enabled = kvm_cpu_cap_has(X86_FEATURE_PAUSEFILTER) &&
4041 guest_cpuid_has(vcpu, X86_FEATURE_PAUSEFILTER);
4043 svm->pause_threshold_enabled = kvm_cpu_cap_has(X86_FEATURE_PFTHRESHOLD) &&
4044 guest_cpuid_has(vcpu, X86_FEATURE_PFTHRESHOLD);
4046 svm->vgif_enabled = vgif && guest_cpuid_has(vcpu, X86_FEATURE_VGIF);
4048 svm_recalc_instruction_intercepts(vcpu, svm);
4050 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4051 if (sev_guest(vcpu->kvm)) {
4052 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4054 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4057 if (kvm_vcpu_apicv_active(vcpu)) {
4059 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4060 * is exposed to the guest, disable AVIC.
4062 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4063 kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_X2APIC);
4065 init_vmcb_after_set_cpuid(vcpu);
4068 static bool svm_has_wbinvd_exit(void)
4073 #define PRE_EX(exit) { .exit_code = (exit), \
4074 .stage = X86_ICPT_PRE_EXCEPT, }
4075 #define POST_EX(exit) { .exit_code = (exit), \
4076 .stage = X86_ICPT_POST_EXCEPT, }
4077 #define POST_MEM(exit) { .exit_code = (exit), \
4078 .stage = X86_ICPT_POST_MEMACCESS, }
4080 static const struct __x86_intercept {
4082 enum x86_intercept_stage stage;
4083 } x86_intercept_map[] = {
4084 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4085 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4086 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4087 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4088 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4089 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4090 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4091 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4092 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4093 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4094 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4095 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4096 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4097 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4098 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4099 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4100 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4101 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4102 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4103 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4104 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4105 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4106 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4107 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4108 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4109 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4110 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4111 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4112 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4113 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4114 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4115 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4116 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4117 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4118 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4119 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4120 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4121 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4122 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4123 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4124 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4125 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4126 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4127 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4128 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4129 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4130 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4137 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4138 struct x86_instruction_info *info,
4139 enum x86_intercept_stage stage,
4140 struct x86_exception *exception)
4142 struct vcpu_svm *svm = to_svm(vcpu);
4143 int vmexit, ret = X86EMUL_CONTINUE;
4144 struct __x86_intercept icpt_info;
4145 struct vmcb *vmcb = svm->vmcb;
4147 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4150 icpt_info = x86_intercept_map[info->intercept];
4152 if (stage != icpt_info.stage)
4155 switch (icpt_info.exit_code) {
4156 case SVM_EXIT_READ_CR0:
4157 if (info->intercept == x86_intercept_cr_read)
4158 icpt_info.exit_code += info->modrm_reg;
4160 case SVM_EXIT_WRITE_CR0: {
4161 unsigned long cr0, val;
4163 if (info->intercept == x86_intercept_cr_write)
4164 icpt_info.exit_code += info->modrm_reg;
4166 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4167 info->intercept == x86_intercept_clts)
4170 if (!(vmcb12_is_intercept(&svm->nested.ctl,
4171 INTERCEPT_SELECTIVE_CR0)))
4174 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4175 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4177 if (info->intercept == x86_intercept_lmsw) {
4180 /* lmsw can't clear PE - catch this here */
4181 if (cr0 & X86_CR0_PE)
4186 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4190 case SVM_EXIT_READ_DR0:
4191 case SVM_EXIT_WRITE_DR0:
4192 icpt_info.exit_code += info->modrm_reg;
4195 if (info->intercept == x86_intercept_wrmsr)
4196 vmcb->control.exit_info_1 = 1;
4198 vmcb->control.exit_info_1 = 0;
4200 case SVM_EXIT_PAUSE:
4202 * We get this for NOP only, but pause
4203 * is rep not, check this here
4205 if (info->rep_prefix != REPE_PREFIX)
4208 case SVM_EXIT_IOIO: {
4212 if (info->intercept == x86_intercept_in ||
4213 info->intercept == x86_intercept_ins) {
4214 exit_info = ((info->src_val & 0xffff) << 16) |
4216 bytes = info->dst_bytes;
4218 exit_info = (info->dst_val & 0xffff) << 16;
4219 bytes = info->src_bytes;
4222 if (info->intercept == x86_intercept_outs ||
4223 info->intercept == x86_intercept_ins)
4224 exit_info |= SVM_IOIO_STR_MASK;
4226 if (info->rep_prefix)
4227 exit_info |= SVM_IOIO_REP_MASK;
4229 bytes = min(bytes, 4u);
4231 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4233 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4235 vmcb->control.exit_info_1 = exit_info;
4236 vmcb->control.exit_info_2 = info->next_rip;
4244 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4245 if (static_cpu_has(X86_FEATURE_NRIPS))
4246 vmcb->control.next_rip = info->next_rip;
4247 vmcb->control.exit_code = icpt_info.exit_code;
4248 vmexit = nested_svm_exit_handled(svm);
4250 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4257 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4259 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR)
4260 vcpu->arch.at_instruction_boundary = true;
4263 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4265 if (!kvm_pause_in_guest(vcpu->kvm))
4266 shrink_ple_window(vcpu);
4269 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4271 /* [63:9] are reserved. */
4272 vcpu->arch.mcg_cap &= 0x1ff;
4275 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4277 struct vcpu_svm *svm = to_svm(vcpu);
4279 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4283 return is_smm(vcpu);
4286 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4288 struct vcpu_svm *svm = to_svm(vcpu);
4289 if (svm->nested.nested_run_pending)
4292 if (svm_smi_blocked(vcpu))
4295 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4296 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4302 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4304 struct vcpu_svm *svm = to_svm(vcpu);
4305 struct kvm_host_map map_save;
4308 if (!is_guest_mode(vcpu))
4311 /* FED8h - SVM Guest */
4312 put_smstate(u64, smstate, 0x7ed8, 1);
4313 /* FEE0h - SVM Guest VMCB Physical Address */
4314 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4316 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4317 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4318 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4320 ret = nested_svm_simple_vmexit(svm, SVM_EXIT_SW);
4325 * KVM uses VMCB01 to store L1 host state while L2 runs but
4326 * VMCB01 is going to be used during SMM and thus the state will
4327 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4328 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4329 * format of the area is identical to guest save area offsetted
4330 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4331 * within 'struct vmcb'). Note: HSAVE area may also be used by
4332 * L1 hypervisor to save additional host context (e.g. KVM does
4333 * that, see svm_prepare_switch_to_guest()) which must be
4336 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4337 &map_save) == -EINVAL)
4340 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4342 svm_copy_vmrun_state(map_save.hva + 0x400,
4343 &svm->vmcb01.ptr->save);
4345 kvm_vcpu_unmap(vcpu, &map_save, true);
4349 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4351 struct vcpu_svm *svm = to_svm(vcpu);
4352 struct kvm_host_map map, map_save;
4353 u64 saved_efer, vmcb12_gpa;
4354 struct vmcb *vmcb12;
4357 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4360 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4361 if (!GET_SMSTATE(u64, smstate, 0x7ed8))
4364 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4367 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4368 if (!(saved_efer & EFER_SVME))
4371 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4372 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4376 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save) == -EINVAL)
4379 if (svm_allocate_nested(svm))
4383 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4384 * used during SMM (see svm_enter_smm())
4387 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4390 * Enter the nested guest now
4393 vmcb_mark_all_dirty(svm->vmcb01.ptr);
4396 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control);
4397 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save);
4398 ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12, false);
4403 svm->nested.nested_run_pending = 1;
4406 kvm_vcpu_unmap(vcpu, &map_save, true);
4408 kvm_vcpu_unmap(vcpu, &map, true);
4412 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4414 struct vcpu_svm *svm = to_svm(vcpu);
4416 if (!gif_set(svm)) {
4418 svm_set_intercept(svm, INTERCEPT_STGI);
4419 /* STGI will cause a vm exit */
4421 /* We must be in SMM; RSM will cause a vmexit anyway. */
4425 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
4426 void *insn, int insn_len)
4428 bool smep, smap, is_user;
4432 /* Emulation is always possible when KVM has access to all guest state. */
4433 if (!sev_guest(vcpu->kvm))
4436 /* #UD and #GP should never be intercepted for SEV guests. */
4437 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD |
4438 EMULTYPE_TRAP_UD_FORCED |
4439 EMULTYPE_VMWARE_GP));
4442 * Emulation is impossible for SEV-ES guests as KVM doesn't have access
4443 * to guest register state.
4445 if (sev_es_guest(vcpu->kvm))
4449 * Emulation is possible if the instruction is already decoded, e.g.
4450 * when completing I/O after returning from userspace.
4452 if (emul_type & EMULTYPE_NO_DECODE)
4456 * Emulation is possible for SEV guests if and only if a prefilled
4457 * buffer containing the bytes of the intercepted instruction is
4458 * available. SEV guest memory is encrypted with a guest specific key
4459 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and
4462 * Inject #UD if KVM reached this point without an instruction buffer.
4463 * In practice, this path should never be hit by a well-behaved guest,
4464 * e.g. KVM doesn't intercept #UD or #GP for SEV guests, but this path
4465 * is still theoretically reachable, e.g. via unaccelerated fault-like
4466 * AVIC access, and needs to be handled by KVM to avoid putting the
4467 * guest into an infinite loop. Injecting #UD is somewhat arbitrary,
4468 * but its the least awful option given lack of insight into the guest.
4470 if (unlikely(!insn)) {
4471 kvm_queue_exception(vcpu, UD_VECTOR);
4476 * Emulate for SEV guests if the insn buffer is not empty. The buffer
4477 * will be empty if the DecodeAssist microcode cannot fetch bytes for
4478 * the faulting instruction because the code fetch itself faulted, e.g.
4479 * the guest attempted to fetch from emulated MMIO or a guest page
4480 * table used to translate CS:RIP resides in emulated MMIO.
4482 if (likely(insn_len))
4486 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4489 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is
4490 * possible that CPU microcode implementing DecodeAssist will fail to
4491 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly
4492 * be '0'. This happens because microcode reads CS:RIP using a _data_
4493 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode
4494 * gives up and does not fill the instruction bytes buffer.
4496 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU
4497 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler
4498 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the
4499 * GuestIntrBytes field of the VMCB.
4501 * This does _not_ mean that the erratum has been encountered, as the
4502 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate
4503 * #PF, e.g. if the guest attempt to execute from emulated MMIO and
4504 * encountered a reserved/not-present #PF.
4506 * To hit the erratum, the following conditions must be true:
4507 * 1. CR4.SMAP=1 (obviously).
4508 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot
4509 * have been hit as the guest would have encountered a SMEP
4510 * violation #PF, not a #NPF.
4511 * 3. The #NPF is not due to a code fetch, in which case failure to
4512 * retrieve the instruction bytes is legitimate (see abvoe).
4514 * In addition, don't apply the erratum workaround if the #NPF occurred
4515 * while translating guest page tables (see below).
4517 error_code = to_svm(vcpu)->vmcb->control.exit_info_1;
4518 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK))
4521 cr4 = kvm_read_cr4(vcpu);
4522 smep = cr4 & X86_CR4_SMEP;
4523 smap = cr4 & X86_CR4_SMAP;
4524 is_user = svm_get_cpl(vcpu) == 3;
4525 if (smap && (!smep || is_user)) {
4526 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4529 * If the fault occurred in userspace, arbitrarily inject #GP
4530 * to avoid killing the guest and to hopefully avoid confusing
4531 * the guest kernel too much, e.g. injecting #PF would not be
4532 * coherent with respect to the guest's page tables. Request
4533 * triple fault if the fault occurred in the kernel as there's
4534 * no fault that KVM can inject without confusing the guest.
4535 * In practice, the triple fault is moot as no sane SEV kernel
4536 * will execute from user memory while also running with SMAP=1.
4539 kvm_inject_gp(vcpu, 0);
4541 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4546 * If the erratum was not hit, simply resume the guest and let it fault
4547 * again. While awful, e.g. the vCPU may get stuck in an infinite loop
4548 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to
4549 * userspace will kill the guest, and letting the emulator read garbage
4550 * will yield random behavior and potentially corrupt the guest.
4552 * Simply resuming the guest is technically not a violation of the SEV
4553 * architecture. AMD's APM states that all code fetches and page table
4554 * accesses for SEV guest are encrypted, regardless of the C-Bit. The
4555 * APM also states that encrypted accesses to MMIO are "ignored", but
4556 * doesn't explicitly define "ignored", i.e. doing nothing and letting
4557 * the guest spin is technically "ignoring" the access.
4562 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4564 struct vcpu_svm *svm = to_svm(vcpu);
4567 * TODO: Last condition latch INIT signals on vCPU when
4568 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4569 * To properly emulate the INIT intercept,
4570 * svm_check_nested_events() should call nested_svm_vmexit()
4571 * if an INIT signal is pending.
4573 return !gif_set(svm) ||
4574 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4577 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4579 if (!sev_es_guest(vcpu->kvm))
4580 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4582 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4585 static void svm_vm_destroy(struct kvm *kvm)
4587 avic_vm_destroy(kvm);
4588 sev_vm_destroy(kvm);
4591 static int svm_vm_init(struct kvm *kvm)
4593 if (!pause_filter_count || !pause_filter_thresh)
4594 kvm->arch.pause_in_guest = true;
4597 int ret = avic_vm_init(kvm);
4605 static struct kvm_x86_ops svm_x86_ops __initdata = {
4608 .hardware_unsetup = svm_hardware_unsetup,
4609 .hardware_enable = svm_hardware_enable,
4610 .hardware_disable = svm_hardware_disable,
4611 .has_emulated_msr = svm_has_emulated_msr,
4613 .vcpu_create = svm_vcpu_create,
4614 .vcpu_free = svm_vcpu_free,
4615 .vcpu_reset = svm_vcpu_reset,
4617 .vm_size = sizeof(struct kvm_svm),
4618 .vm_init = svm_vm_init,
4619 .vm_destroy = svm_vm_destroy,
4621 .prepare_switch_to_guest = svm_prepare_switch_to_guest,
4622 .vcpu_load = svm_vcpu_load,
4623 .vcpu_put = svm_vcpu_put,
4624 .vcpu_blocking = avic_vcpu_blocking,
4625 .vcpu_unblocking = avic_vcpu_unblocking,
4627 .update_exception_bitmap = svm_update_exception_bitmap,
4628 .get_msr_feature = svm_get_msr_feature,
4629 .get_msr = svm_get_msr,
4630 .set_msr = svm_set_msr,
4631 .get_segment_base = svm_get_segment_base,
4632 .get_segment = svm_get_segment,
4633 .set_segment = svm_set_segment,
4634 .get_cpl = svm_get_cpl,
4635 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
4636 .set_cr0 = svm_set_cr0,
4637 .post_set_cr3 = sev_post_set_cr3,
4638 .is_valid_cr4 = svm_is_valid_cr4,
4639 .set_cr4 = svm_set_cr4,
4640 .set_efer = svm_set_efer,
4641 .get_idt = svm_get_idt,
4642 .set_idt = svm_set_idt,
4643 .get_gdt = svm_get_gdt,
4644 .set_gdt = svm_set_gdt,
4645 .set_dr7 = svm_set_dr7,
4646 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4647 .cache_reg = svm_cache_reg,
4648 .get_rflags = svm_get_rflags,
4649 .set_rflags = svm_set_rflags,
4650 .get_if_flag = svm_get_if_flag,
4652 .flush_tlb_all = svm_flush_tlb_current,
4653 .flush_tlb_current = svm_flush_tlb_current,
4654 .flush_tlb_gva = svm_flush_tlb_gva,
4655 .flush_tlb_guest = svm_flush_tlb_current,
4657 .vcpu_pre_run = svm_vcpu_pre_run,
4658 .vcpu_run = svm_vcpu_run,
4659 .handle_exit = svm_handle_exit,
4660 .skip_emulated_instruction = svm_skip_emulated_instruction,
4661 .update_emulated_instruction = NULL,
4662 .set_interrupt_shadow = svm_set_interrupt_shadow,
4663 .get_interrupt_shadow = svm_get_interrupt_shadow,
4664 .patch_hypercall = svm_patch_hypercall,
4665 .inject_irq = svm_inject_irq,
4666 .inject_nmi = svm_inject_nmi,
4667 .queue_exception = svm_queue_exception,
4668 .cancel_injection = svm_cancel_injection,
4669 .interrupt_allowed = svm_interrupt_allowed,
4670 .nmi_allowed = svm_nmi_allowed,
4671 .get_nmi_mask = svm_get_nmi_mask,
4672 .set_nmi_mask = svm_set_nmi_mask,
4673 .enable_nmi_window = svm_enable_nmi_window,
4674 .enable_irq_window = svm_enable_irq_window,
4675 .update_cr8_intercept = svm_update_cr8_intercept,
4676 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl,
4677 .check_apicv_inhibit_reasons = avic_check_apicv_inhibit_reasons,
4678 .apicv_post_state_restore = avic_apicv_post_state_restore,
4680 .get_mt_mask = svm_get_mt_mask,
4681 .get_exit_info = svm_get_exit_info,
4683 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4685 .has_wbinvd_exit = svm_has_wbinvd_exit,
4687 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4688 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4689 .write_tsc_offset = svm_write_tsc_offset,
4690 .write_tsc_multiplier = svm_write_tsc_multiplier,
4692 .load_mmu_pgd = svm_load_mmu_pgd,
4694 .check_intercept = svm_check_intercept,
4695 .handle_exit_irqoff = svm_handle_exit_irqoff,
4697 .request_immediate_exit = __kvm_request_immediate_exit,
4699 .sched_in = svm_sched_in,
4701 .nested_ops = &svm_nested_ops,
4703 .deliver_interrupt = svm_deliver_interrupt,
4704 .pi_update_irte = avic_pi_update_irte,
4705 .setup_mce = svm_setup_mce,
4707 .smi_allowed = svm_smi_allowed,
4708 .enter_smm = svm_enter_smm,
4709 .leave_smm = svm_leave_smm,
4710 .enable_smi_window = svm_enable_smi_window,
4712 .mem_enc_ioctl = sev_mem_enc_ioctl,
4713 .mem_enc_register_region = sev_mem_enc_register_region,
4714 .mem_enc_unregister_region = sev_mem_enc_unregister_region,
4715 .guest_memory_reclaimed = sev_guest_memory_reclaimed,
4717 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from,
4718 .vm_move_enc_context_from = sev_vm_move_enc_context_from,
4720 .can_emulate_instruction = svm_can_emulate_instruction,
4722 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4724 .msr_filter_changed = svm_msr_filter_changed,
4725 .complete_emulated_msr = svm_complete_emulated_msr,
4727 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4728 .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons,
4732 * The default MMIO mask is a single bit (excluding the present bit),
4733 * which could conflict with the memory encryption bit. Check for
4734 * memory encryption support and override the default MMIO mask if
4735 * memory encryption is enabled.
4737 static __init void svm_adjust_mmio_mask(void)
4739 unsigned int enc_bit, mask_bit;
4742 /* If there is no memory encryption support, use existing mask */
4743 if (cpuid_eax(0x80000000) < 0x8000001f)
4746 /* If memory encryption is not enabled, use existing mask */
4747 rdmsrl(MSR_AMD64_SYSCFG, msr);
4748 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
4751 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
4752 mask_bit = boot_cpu_data.x86_phys_bits;
4754 /* Increment the mask bit if it is the same as the encryption bit */
4755 if (enc_bit == mask_bit)
4759 * If the mask bit location is below 52, then some bits above the
4760 * physical addressing limit will always be reserved, so use the
4761 * rsvd_bits() function to generate the mask. This mask, along with
4762 * the present bit, will be used to generate a page fault with
4765 * If the mask bit location is 52 (or above), then clear the mask.
4767 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
4769 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
4772 static __init void svm_set_cpu_caps(void)
4778 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
4780 kvm_cpu_cap_set(X86_FEATURE_SVM);
4781 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN);
4784 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
4787 kvm_cpu_cap_set(X86_FEATURE_NPT);
4790 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR);
4793 kvm_cpu_cap_set(X86_FEATURE_V_VMSAVE_VMLOAD);
4795 kvm_cpu_cap_set(X86_FEATURE_LBRV);
4797 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER))
4798 kvm_cpu_cap_set(X86_FEATURE_PAUSEFILTER);
4800 if (boot_cpu_has(X86_FEATURE_PFTHRESHOLD))
4801 kvm_cpu_cap_set(X86_FEATURE_PFTHRESHOLD);
4804 kvm_cpu_cap_set(X86_FEATURE_VGIF);
4806 /* Nested VM can receive #VMEXIT instead of triggering #GP */
4807 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
4810 /* CPUID 0x80000008 */
4811 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
4812 boot_cpu_has(X86_FEATURE_AMD_SSBD))
4813 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
4815 /* AMD PMU PERFCTR_CORE CPUID */
4816 if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
4817 kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE);
4819 /* CPUID 0x8000001F (SME/SEV features) */
4823 static __init int svm_hardware_setup(void)
4826 struct page *iopm_pages;
4829 unsigned int order = get_order(IOPM_SIZE);
4832 * NX is required for shadow paging and for NPT if the NX huge pages
4833 * mitigation is enabled.
4835 if (!boot_cpu_has(X86_FEATURE_NX)) {
4836 pr_err_ratelimited("NX (Execute Disable) not supported\n");
4839 kvm_enable_efer_bits(EFER_NX);
4841 iopm_pages = alloc_pages(GFP_KERNEL, order);
4846 iopm_va = page_address(iopm_pages);
4847 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
4848 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
4850 init_msrpm_offsets();
4852 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
4854 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
4855 kvm_enable_efer_bits(EFER_FFXSR);
4858 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
4859 tsc_scaling = false;
4861 pr_info("TSC scaling supported\n");
4862 kvm_has_tsc_control = true;
4865 kvm_max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
4866 kvm_tsc_scaling_ratio_frac_bits = 32;
4868 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
4870 /* Check for pause filtering support */
4871 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
4872 pause_filter_count = 0;
4873 pause_filter_thresh = 0;
4874 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
4875 pause_filter_thresh = 0;
4879 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
4880 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
4884 * KVM's MMU doesn't support using 2-level paging for itself, and thus
4885 * NPT isn't supported if the host is using 2-level paging since host
4886 * CR4 is unchanged on VMRUN.
4888 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
4889 npt_enabled = false;
4891 if (!boot_cpu_has(X86_FEATURE_NPT))
4892 npt_enabled = false;
4894 /* Force VM NPT level equal to the host's paging level */
4895 kvm_configure_mmu(npt_enabled, get_npt_level(),
4896 get_npt_level(), PG_LEVEL_1G);
4897 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
4899 /* Setup shadow_me_value and shadow_me_mask */
4900 kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);
4902 /* Note, SEV setup consumes npt_enabled. */
4903 sev_hardware_setup();
4905 svm_hv_hardware_setup();
4907 svm_adjust_mmio_mask();
4909 for_each_possible_cpu(cpu) {
4910 r = svm_cpu_init(cpu);
4916 if (!boot_cpu_has(X86_FEATURE_NRIPS))
4920 enable_apicv = avic = avic && npt_enabled && (boot_cpu_has(X86_FEATURE_AVIC) || force_avic);
4923 if (!boot_cpu_has(X86_FEATURE_AVIC)) {
4924 pr_warn("AVIC is not supported in CPUID but force enabled");
4925 pr_warn("Your system might crash and burn");
4927 pr_info("AVIC enabled\n");
4929 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
4931 svm_x86_ops.vcpu_blocking = NULL;
4932 svm_x86_ops.vcpu_unblocking = NULL;
4933 svm_x86_ops.vcpu_get_apicv_inhibit_reasons = NULL;
4938 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
4939 !IS_ENABLED(CONFIG_X86_64)) {
4942 pr_info("Virtual VMLOAD VMSAVE supported\n");
4946 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
4947 svm_gp_erratum_intercept = false;
4950 if (!boot_cpu_has(X86_FEATURE_VGIF))
4953 pr_info("Virtual GIF supported\n");
4957 if (!boot_cpu_has(X86_FEATURE_LBRV))
4960 pr_info("LBR virtualization supported\n");
4964 pr_info("PMU virtualization is disabled\n");
4969 * It seems that on AMD processors PTE's accessed bit is
4970 * being set by the CPU hardware before the NPF vmexit.
4971 * This is not expected behaviour and our tests fail because
4973 * A workaround here is to disable support for
4974 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
4975 * In this case userspace can know if there is support using
4976 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
4978 * If future AMD CPU models change the behaviour described above,
4979 * this variable can be changed accordingly
4981 allow_smaller_maxphyaddr = !npt_enabled;
4986 svm_hardware_unsetup();
4991 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4992 .cpu_has_kvm_support = has_svm,
4993 .disabled_by_bios = is_disabled,
4994 .hardware_setup = svm_hardware_setup,
4995 .check_processor_compatibility = svm_check_processor_compat,
4997 .runtime_ops = &svm_x86_ops,
4998 .pmu_ops = &amd_pmu_ops,
5001 static int __init svm_init(void)
5003 __unused_size_checks();
5005 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
5006 __alignof__(struct vcpu_svm), THIS_MODULE);
5009 static void __exit svm_exit(void)
5014 module_init(svm_init)
5015 module_exit(svm_exit)