1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine -- Performance Monitoring Unit support
5 * Copyright 2015 Red Hat, Inc. and/or its affiliates.
8 * Avi Kivity <avi@redhat.com>
9 * Gleb Natapov <gleb@redhat.com>
10 * Wei Huang <wei@redhat.com>
13 #include <linux/types.h>
14 #include <linux/kvm_host.h>
15 #include <linux/perf_event.h>
16 #include <asm/perf_event.h>
22 /* This is enough to filter the vast majority of currently defined events. */
23 #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
26 * - Each perf counter is defined as "struct kvm_pmc";
27 * - There are two types of perf counters: general purpose (gp) and fixed.
28 * gp counters are stored in gp_counters[] and fixed counters are stored
29 * in fixed_counters[] respectively. Both of them are part of "struct
31 * - pmu.c understands the difference between gp counters and fixed counters.
32 * However AMD doesn't support fixed-counters;
33 * - There are three types of index to access perf counters (PMC):
34 * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
35 * has MSR_K7_PERFCTRn.
36 * 2. MSR Index (named idx): This normally is used by RDPMC instruction.
37 * For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
38 * C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
39 * that it also supports fixed counters. idx can be used to as index to
40 * gp and fixed counters.
41 * 3. Global PMC Index (named pmc): pmc is an index specific to PMU
42 * code. Each pmc, stored in kvm_pmc.idx field, is unique across
43 * all perf counters (both gp and fixed). The mapping relationship
44 * between pmc and perf counters is as the following:
45 * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
46 * [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
47 * * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
50 static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
52 struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
53 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
55 kvm_pmu_deliver_pmi(vcpu);
58 static void kvm_perf_overflow(struct perf_event *perf_event,
59 struct perf_sample_data *data,
62 struct kvm_pmc *pmc = perf_event->overflow_handler_context;
63 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
65 if (!test_and_set_bit(pmc->idx, pmu->reprogram_pmi)) {
66 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
67 kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
71 static void kvm_perf_overflow_intr(struct perf_event *perf_event,
72 struct perf_sample_data *data,
75 struct kvm_pmc *pmc = perf_event->overflow_handler_context;
76 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
78 if (!test_and_set_bit(pmc->idx, pmu->reprogram_pmi)) {
79 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
80 kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
83 * Inject PMI. If vcpu was in a guest mode during NMI PMI
84 * can be ejected on a guest mode re-entry. Otherwise we can't
85 * be sure that vcpu wasn't executing hlt instruction at the
86 * time of vmexit and is not going to re-enter guest mode until
87 * woken up. So we should wake it, but this is impossible from
88 * NMI context. Do it from irq work instead.
90 if (!kvm_is_in_guest())
91 irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
93 kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
97 static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
98 u64 config, bool exclude_user,
99 bool exclude_kernel, bool intr)
101 struct perf_event *event;
102 struct perf_event_attr attr = {
104 .size = sizeof(attr),
106 .exclude_idle = true,
108 .exclude_user = exclude_user,
109 .exclude_kernel = exclude_kernel,
113 attr.sample_period = get_sample_period(pmc, pmc->counter);
115 if ((attr.config & HSW_IN_TX_CHECKPOINTED) &&
116 guest_cpuid_is_intel(pmc->vcpu)) {
118 * HSW_IN_TX_CHECKPOINTED is not supported with nonzero
119 * period. Just clear the sample period so at least
120 * allocating the counter doesn't fail.
122 attr.sample_period = 0;
125 event = perf_event_create_kernel_counter(&attr, -1, current,
126 intr ? kvm_perf_overflow_intr :
127 kvm_perf_overflow, pmc);
129 pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n",
130 PTR_ERR(event), pmc->idx);
134 pmc->perf_event = event;
135 pmc_to_pmu(pmc)->event_count++;
136 clear_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
137 pmc->is_paused = false;
140 static void pmc_pause_counter(struct kvm_pmc *pmc)
142 u64 counter = pmc->counter;
144 if (!pmc->perf_event || pmc->is_paused)
147 /* update counter, reset event value to avoid redundant accumulation */
148 counter += perf_event_pause(pmc->perf_event, true);
149 pmc->counter = counter & pmc_bitmask(pmc);
150 pmc->is_paused = true;
153 static bool pmc_resume_counter(struct kvm_pmc *pmc)
155 if (!pmc->perf_event)
158 /* recalibrate sample period and check if it's accepted by perf core */
159 if (perf_event_period(pmc->perf_event,
160 get_sample_period(pmc, pmc->counter)))
163 /* reuse perf_event to serve as pmc_reprogram_counter() does*/
164 perf_event_enable(pmc->perf_event);
165 pmc->is_paused = false;
167 clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi);
171 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
174 u32 type = PERF_TYPE_RAW;
175 struct kvm *kvm = pmc->vcpu->kvm;
176 struct kvm_pmu_event_filter *filter;
178 struct kvm_pmu *pmu = vcpu_to_pmu(pmc->vcpu);
179 bool allow_event = true;
181 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
182 printk_once("kvm pmu: pin control bit is ignored\n");
184 pmc->eventsel = eventsel;
186 pmc_pause_counter(pmc);
188 if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
191 filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
193 for (i = 0; i < filter->nevents; i++)
194 if (filter->events[i] ==
195 (eventsel & AMD64_RAW_EVENT_MASK_NB))
197 if (filter->action == KVM_PMU_EVENT_ALLOW &&
198 i == filter->nevents)
200 if (filter->action == KVM_PMU_EVENT_DENY &&
207 if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
208 ARCH_PERFMON_EVENTSEL_INV |
209 ARCH_PERFMON_EVENTSEL_CMASK |
211 HSW_IN_TX_CHECKPOINTED))) {
212 config = kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc);
213 if (config != PERF_COUNT_HW_MAX)
214 type = PERF_TYPE_HARDWARE;
217 if (type == PERF_TYPE_RAW)
218 config = eventsel & pmu->raw_event_mask;
220 if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
223 pmc_release_perf_event(pmc);
225 pmc->current_config = eventsel;
226 pmc_reprogram_counter(pmc, type, config,
227 !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
228 !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
229 eventsel & ARCH_PERFMON_EVENTSEL_INT);
231 EXPORT_SYMBOL_GPL(reprogram_gp_counter);
233 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
235 unsigned en_field = ctrl & 0x3;
236 bool pmi = ctrl & 0x8;
237 struct kvm_pmu_event_filter *filter;
238 struct kvm *kvm = pmc->vcpu->kvm;
240 pmc_pause_counter(pmc);
242 if (!en_field || !pmc_is_enabled(pmc))
245 filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
247 if (filter->action == KVM_PMU_EVENT_DENY &&
248 test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
250 if (filter->action == KVM_PMU_EVENT_ALLOW &&
251 !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
255 if (pmc->current_config == (u64)ctrl && pmc_resume_counter(pmc))
258 pmc_release_perf_event(pmc);
260 pmc->current_config = (u64)ctrl;
261 pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
262 kvm_x86_ops.pmu_ops->find_fixed_event(idx),
263 !(en_field & 0x2), /* exclude user */
264 !(en_field & 0x1), /* exclude kernel */
267 EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
269 void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
271 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx);
277 reprogram_gp_counter(pmc, pmc->eventsel);
279 int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
280 u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
282 reprogram_fixed_counter(pmc, ctrl, idx);
285 EXPORT_SYMBOL_GPL(reprogram_counter);
287 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
289 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
292 for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) {
293 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, bit);
295 if (unlikely(!pmc || !pmc->perf_event)) {
296 clear_bit(bit, pmu->reprogram_pmi);
300 reprogram_counter(pmu, bit);
304 * Unused perf_events are only released if the corresponding MSRs
305 * weren't accessed during the last vCPU time slice. kvm_arch_sched_in
306 * triggers KVM_REQ_PMU if cleanup is needed.
308 if (unlikely(pmu->need_cleanup))
309 kvm_pmu_cleanup(vcpu);
312 /* check if idx is a valid index to access PMU */
313 int kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
315 return kvm_x86_ops.pmu_ops->is_valid_rdpmc_ecx(vcpu, idx);
318 bool is_vmware_backdoor_pmc(u32 pmc_idx)
321 case VMWARE_BACKDOOR_PMC_HOST_TSC:
322 case VMWARE_BACKDOOR_PMC_REAL_TIME:
323 case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
329 static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
334 case VMWARE_BACKDOOR_PMC_HOST_TSC:
337 case VMWARE_BACKDOOR_PMC_REAL_TIME:
338 ctr_val = ktime_get_boottime_ns();
340 case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
341 ctr_val = ktime_get_boottime_ns() +
342 vcpu->kvm->arch.kvmclock_offset;
352 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
354 bool fast_mode = idx & (1u << 31);
355 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
357 u64 mask = fast_mode ? ~0u : ~0ull;
362 if (is_vmware_backdoor_pmc(idx))
363 return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
365 pmc = kvm_x86_ops.pmu_ops->rdpmc_ecx_to_pmc(vcpu, idx, &mask);
369 if (!(kvm_read_cr4(vcpu) & X86_CR4_PCE) &&
370 (static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
371 (kvm_read_cr0(vcpu) & X86_CR0_PE))
374 *data = pmc_read_counter(pmc) & mask;
378 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
380 if (lapic_in_kernel(vcpu)) {
381 if (kvm_x86_ops.pmu_ops->deliver_pmi)
382 kvm_x86_ops.pmu_ops->deliver_pmi(vcpu);
383 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
387 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
389 return kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr) ||
390 kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, msr);
393 static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
395 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
396 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr);
399 __set_bit(pmc->idx, pmu->pmc_in_use);
402 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
404 return kvm_x86_ops.pmu_ops->get_msr(vcpu, msr_info);
407 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
409 kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
410 return kvm_x86_ops.pmu_ops->set_msr(vcpu, msr_info);
413 /* refresh PMU settings. This function generally is called when underlying
414 * settings are changed (such as changes of PMU CPUID by guest VMs), which
415 * should rarely happen.
417 void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
419 kvm_x86_ops.pmu_ops->refresh(vcpu);
422 void kvm_pmu_reset(struct kvm_vcpu *vcpu)
424 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
426 irq_work_sync(&pmu->irq_work);
427 kvm_x86_ops.pmu_ops->reset(vcpu);
430 void kvm_pmu_init(struct kvm_vcpu *vcpu)
432 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
434 memset(pmu, 0, sizeof(*pmu));
435 kvm_x86_ops.pmu_ops->init(vcpu);
436 init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
437 pmu->event_count = 0;
438 pmu->need_cleanup = false;
439 kvm_pmu_refresh(vcpu);
442 static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
444 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
446 if (pmc_is_fixed(pmc))
447 return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
448 pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
450 return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
453 /* Release perf_events for vPMCs that have been unused for a full time slice. */
454 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
456 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
457 struct kvm_pmc *pmc = NULL;
458 DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);
461 pmu->need_cleanup = false;
463 bitmap_andnot(bitmask, pmu->all_valid_pmc_idx,
464 pmu->pmc_in_use, X86_PMC_IDX_MAX);
466 for_each_set_bit(i, bitmask, X86_PMC_IDX_MAX) {
467 pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, i);
469 if (pmc && pmc->perf_event && !pmc_speculative_in_use(pmc))
470 pmc_stop_counter(pmc);
473 if (kvm_x86_ops.pmu_ops->cleanup)
474 kvm_x86_ops.pmu_ops->cleanup(vcpu);
476 bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
479 void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
484 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp)
486 struct kvm_pmu_event_filter tmp, *filter;
490 if (copy_from_user(&tmp, argp, sizeof(tmp)))
493 if (tmp.action != KVM_PMU_EVENT_ALLOW &&
494 tmp.action != KVM_PMU_EVENT_DENY)
500 if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS)
503 size = struct_size(filter, events, tmp.nevents);
504 filter = kmalloc(size, GFP_KERNEL_ACCOUNT);
509 if (copy_from_user(filter, argp, size))
512 /* Ensure nevents can't be changed between the user copies. */
515 mutex_lock(&kvm->lock);
516 filter = rcu_replace_pointer(kvm->arch.pmu_event_filter, filter,
517 mutex_is_locked(&kvm->lock));
518 mutex_unlock(&kvm->lock);
520 synchronize_srcu_expedited(&kvm->srcu);