2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
30 extern u64 __pure __using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
84 #error Invalid PTTYPE value
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
91 * The guest_walker structure emulates the behavior of the hardware page
97 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
98 pt_element_t ptes[PT_MAX_FULL_LEVELS];
99 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
100 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
101 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
102 bool pte_writable[PT_MAX_FULL_LEVELS];
106 struct x86_exception fault;
109 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
111 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
114 static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
118 /* dirty bit is not supported, so no need to track it */
119 if (!PT_GUEST_DIRTY_MASK)
122 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
124 mask = (unsigned)~ACC_WRITE_MASK;
125 /* Allow write access to dirty gptes */
126 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
131 static inline int FNAME(is_present_gpte)(unsigned long pte)
133 #if PTTYPE != PTTYPE_EPT
134 return pte & PT_PRESENT_MASK;
140 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
141 pt_element_t __user *ptep_user, unsigned index,
142 pt_element_t orig_pte, pt_element_t new_pte)
149 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
150 /* Check if the user is doing something meaningless. */
151 if (unlikely(npages != 1))
154 table = kmap_atomic(page);
155 ret = CMPXCHG(&table[index], orig_pte, new_pte);
156 kunmap_atomic(table);
158 kvm_release_page_dirty(page);
160 return (ret != orig_pte);
163 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
164 struct kvm_mmu_page *sp, u64 *spte,
167 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
170 if (!FNAME(is_present_gpte)(gpte))
173 /* if accessed bit is not supported prefetch non accessed gpte */
174 if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
180 drop_spte(vcpu->kvm, spte);
185 * For PTTYPE_EPT, a page table can be executable but not readable
186 * on supported processors. Therefore, set_spte does not automatically
187 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
188 * to signify readability since it isn't used in the EPT case
190 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
193 #if PTTYPE == PTTYPE_EPT
194 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
195 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
196 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
198 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
199 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
200 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
201 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
202 access ^= (gpte >> PT64_NX_SHIFT);
208 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
210 struct guest_walker *walker,
213 unsigned level, index;
214 pt_element_t pte, orig_pte;
215 pt_element_t __user *ptep_user;
219 /* dirty/accessed bits are not supported, so no need to update them */
220 if (!PT_GUEST_DIRTY_MASK)
223 for (level = walker->max_level; level >= walker->level; --level) {
224 pte = orig_pte = walker->ptes[level - 1];
225 table_gfn = walker->table_gfn[level - 1];
226 ptep_user = walker->ptep_user[level - 1];
227 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
228 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
229 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
230 pte |= PT_GUEST_ACCESSED_MASK;
232 if (level == walker->level && write_fault &&
233 !(pte & PT_GUEST_DIRTY_MASK)) {
234 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
235 pte |= PT_GUEST_DIRTY_MASK;
241 * If the slot is read-only, simply do not process the accessed
242 * and dirty bits. This is the correct thing to do if the slot
243 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
244 * are only supported if the accessed and dirty bits are already
245 * set in the ROM (so that MMIO writes are never needed).
247 * Note that NPT does not allow this at all and faults, since
248 * it always wants nested page table entries for the guest
249 * page tables to be writable. And EPT works but will simply
250 * overwrite the read-only memory to set the accessed and dirty
253 if (unlikely(!walker->pte_writable[level - 1]))
256 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
260 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
261 walker->ptes[level - 1] = pte;
266 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
270 pte_t pte = {.pte = gpte};
272 pkeys = pte_flags_pkey(pte_flags(pte));
278 * Fetch a guest pte for a guest virtual address
280 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
281 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
282 gva_t addr, u32 access)
286 pt_element_t __user *uninitialized_var(ptep_user);
288 unsigned index, pt_access, pte_access, accessed_dirty, pte_pkey;
291 const int write_fault = access & PFERR_WRITE_MASK;
292 const int user_fault = access & PFERR_USER_MASK;
293 const int fetch_fault = access & PFERR_FETCH_MASK;
298 trace_kvm_mmu_pagetable_walk(addr, access);
300 walker->level = mmu->root_level;
301 pte = mmu->get_cr3(vcpu);
304 if (walker->level == PT32E_ROOT_LEVEL) {
305 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
306 trace_kvm_mmu_paging_element(pte, walker->level);
307 if (!FNAME(is_present_gpte)(pte))
312 walker->max_level = walker->level;
313 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
315 accessed_dirty = PT_GUEST_ACCESSED_MASK;
316 pt_access = pte_access = ACC_ALL;
321 unsigned long host_addr;
323 pt_access &= pte_access;
326 index = PT_INDEX(addr, walker->level);
327 table_gfn = gpte_to_gfn(pte);
328 offset = index * sizeof(pt_element_t);
329 pte_gpa = gfn_to_gpa(table_gfn) + offset;
331 BUG_ON(walker->level < 1);
332 walker->table_gfn[walker->level - 1] = table_gfn;
333 walker->pte_gpa[walker->level - 1] = pte_gpa;
335 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
336 PFERR_USER_MASK|PFERR_WRITE_MASK,
340 * FIXME: This can happen if emulation (for of an INS/OUTS
341 * instruction) triggers a nested page fault. The exit
342 * qualification / exit info field will incorrectly have
343 * "guest page access" as the nested page fault's cause,
344 * instead of "guest page structure access". To fix this,
345 * the x86_exception struct should be augmented with enough
346 * information to fix the exit_qualification or exit_info_1
349 if (unlikely(real_gfn == UNMAPPED_GVA))
352 real_gfn = gpa_to_gfn(real_gfn);
354 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
355 &walker->pte_writable[walker->level - 1]);
356 if (unlikely(kvm_is_error_hva(host_addr)))
359 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
360 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
362 walker->ptep_user[walker->level - 1] = ptep_user;
364 trace_kvm_mmu_paging_element(pte, walker->level);
366 if (unlikely(!FNAME(is_present_gpte)(pte)))
369 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
370 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
374 accessed_dirty &= pte;
375 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
377 walker->ptes[walker->level - 1] = pte;
378 } while (!is_last_gpte(mmu, walker->level, pte));
380 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
381 errcode = permission_fault(vcpu, mmu, pte_access, pte_pkey, access);
382 if (unlikely(errcode))
385 gfn = gpte_to_gfn_lvl(pte, walker->level);
386 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
388 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
389 gfn += pse36_gfn_delta(pte);
391 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
392 if (real_gpa == UNMAPPED_GVA)
395 walker->gfn = real_gpa >> PAGE_SHIFT;
398 FNAME(protect_clean_gpte)(&pte_access, pte);
401 * On a write fault, fold the dirty bit into accessed_dirty.
402 * For modes without A/D bits support accessed_dirty will be
405 accessed_dirty &= pte >>
406 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
408 if (unlikely(!accessed_dirty)) {
409 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
410 if (unlikely(ret < 0))
416 walker->pt_access = pt_access;
417 walker->pte_access = pte_access;
418 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
419 __func__, (u64)pte, pte_access, pt_access);
423 errcode |= write_fault | user_fault;
424 if (fetch_fault && (mmu->nx ||
425 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
426 errcode |= PFERR_FETCH_MASK;
428 walker->fault.vector = PF_VECTOR;
429 walker->fault.error_code_valid = true;
430 walker->fault.error_code = errcode;
432 #if PTTYPE == PTTYPE_EPT
434 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
435 * misconfiguration requires to be injected. The detection is
436 * done by is_rsvd_bits_set() above.
438 * We set up the value of exit_qualification to inject:
439 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
440 * [5:3] - Calculated by the page walk of the guest EPT page tables
441 * [7:8] - Derived from [7:8] of real exit_qualification
443 * The other bits are set to 0.
445 if (!(errcode & PFERR_RSVD_MASK)) {
446 vcpu->arch.exit_qualification &= 0x187;
447 vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
450 walker->fault.address = addr;
451 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
453 trace_kvm_mmu_walker_error(walker->fault.error_code);
457 static int FNAME(walk_addr)(struct guest_walker *walker,
458 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
460 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
464 #if PTTYPE != PTTYPE_EPT
465 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
466 struct kvm_vcpu *vcpu, gva_t addr,
469 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
475 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
476 u64 *spte, pt_element_t gpte, bool no_dirty_log)
482 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
485 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
487 gfn = gpte_to_gfn(gpte);
488 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
489 FNAME(protect_clean_gpte)(&pte_access, gpte);
490 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
491 no_dirty_log && (pte_access & ACC_WRITE_MASK));
492 if (is_error_pfn(pfn))
496 * we call mmu_set_spte() with host_writable = true because
497 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
499 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
502 kvm_release_pfn_clean(pfn);
506 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
507 u64 *spte, const void *pte)
509 pt_element_t gpte = *(const pt_element_t *)pte;
511 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
514 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
515 struct guest_walker *gw, int level)
517 pt_element_t curr_pte;
518 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
522 if (level == PT_PAGE_TABLE_LEVEL) {
523 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
524 base_gpa = pte_gpa & ~mask;
525 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
527 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
528 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
529 curr_pte = gw->prefetch_ptes[index];
531 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
532 &curr_pte, sizeof(curr_pte));
534 return r || curr_pte != gw->ptes[level - 1];
537 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
540 struct kvm_mmu_page *sp;
541 pt_element_t *gptep = gw->prefetch_ptes;
545 sp = page_header(__pa(sptep));
547 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
551 return __direct_pte_prefetch(vcpu, sp, sptep);
553 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
556 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
560 if (is_shadow_present_pte(*spte))
563 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
569 * Fetch a shadow pte for a specific level in the paging hierarchy.
570 * If the guest tries to write a write-protected page, we need to
571 * emulate this operation, return 1 to indicate this case.
573 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
574 struct guest_walker *gw,
575 int write_fault, int hlevel,
576 kvm_pfn_t pfn, bool map_writable, bool prefault,
577 bool lpage_disallowed)
579 struct kvm_mmu_page *sp = NULL;
580 struct kvm_shadow_walk_iterator it;
581 unsigned direct_access, access = gw->pt_access;
585 direct_access = gw->pte_access;
587 top_level = vcpu->arch.mmu.root_level;
588 if (top_level == PT32E_ROOT_LEVEL)
589 top_level = PT32_ROOT_LEVEL;
591 * Verify that the top-level gpte is still there. Since the page
592 * is a root page, it is either write protected (and cannot be
593 * changed from now on) or it is invalid (in which case, we don't
594 * really care if it changes underneath us after this point).
596 if (FNAME(gpte_changed)(vcpu, gw, top_level))
597 goto out_gpte_changed;
599 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
600 goto out_gpte_changed;
602 for (shadow_walk_init(&it, vcpu, addr);
603 shadow_walk_okay(&it) && it.level > gw->level;
604 shadow_walk_next(&it)) {
607 clear_sp_write_flooding_count(it.sptep);
608 drop_large_spte(vcpu, it.sptep);
611 if (!is_shadow_present_pte(*it.sptep)) {
612 table_gfn = gw->table_gfn[it.level - 2];
613 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
618 * Verify that the gpte in the page we've just write
619 * protected is still there.
621 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
622 goto out_gpte_changed;
625 link_shadow_page(vcpu, it.sptep, sp);
629 * FNAME(page_fault) might have clobbered the bottom bits of
630 * gw->gfn, restore them from the virtual address.
632 gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT);
635 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
637 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
638 clear_sp_write_flooding_count(it.sptep);
641 * We cannot overwrite existing page tables with an NX
642 * large page, as the leaf could be executable.
644 disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel);
646 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
647 if (it.level == hlevel)
650 validate_direct_spte(vcpu, it.sptep, direct_access);
652 drop_large_spte(vcpu, it.sptep);
654 if (!is_shadow_present_pte(*it.sptep)) {
655 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
656 it.level - 1, true, direct_access);
657 link_shadow_page(vcpu, it.sptep, sp);
658 if (lpage_disallowed)
659 account_huge_nx_page(vcpu->kvm, sp);
663 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
664 it.level, base_gfn, pfn, prefault, map_writable);
665 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
666 ++vcpu->stat.pf_fixed;
674 * To see whether the mapped gfn can write its page table in the current
677 * It is the helper function of FNAME(page_fault). When guest uses large page
678 * size to map the writable gfn which is used as current page table, we should
679 * force kvm to use small page size to map it because new shadow page will be
680 * created when kvm establishes shadow page table that stop kvm using large
681 * page size. Do it early can avoid unnecessary #PF and emulation.
683 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
684 * currently used as its page table.
686 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
687 * since the PDPT is always shadowed, that means, we can not use large page
688 * size to map the gfn which is used as PDPT.
691 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
692 struct guest_walker *walker, int user_fault,
693 bool *write_fault_to_shadow_pgtable)
696 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
697 bool self_changed = false;
699 if (!(walker->pte_access & ACC_WRITE_MASK ||
700 (!is_write_protection(vcpu) && !user_fault)))
703 for (level = walker->level; level <= walker->max_level; level++) {
704 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
706 self_changed |= !(gfn & mask);
707 *write_fault_to_shadow_pgtable |= !gfn;
714 * Page fault handler. There are several causes for a page fault:
715 * - there is no shadow pte for the guest pte
716 * - write access through a shadow pte marked read only so that we can set
718 * - write access to a shadow pte marked read only so we can update the page
719 * dirty bitmap, when userspace requests it
720 * - mmio access; in this case we will never install a present shadow pte
721 * - normal guest page fault due to the guest pte marked not present, not
722 * writable, or not executable
724 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
725 * a negative value on error.
727 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
730 int write_fault = error_code & PFERR_WRITE_MASK;
731 int user_fault = error_code & PFERR_USER_MASK;
732 struct guest_walker walker;
735 int level = PT_PAGE_TABLE_LEVEL;
736 unsigned long mmu_seq;
737 bool map_writable, is_self_change_mapping;
738 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
739 is_nx_huge_page_enabled();
740 bool force_pt_level = lpage_disallowed;
742 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
744 r = mmu_topup_memory_caches(vcpu);
749 * If PFEC.RSVD is set, this is a shadow page fault.
750 * The bit needs to be cleared before walking guest page tables.
752 error_code &= ~PFERR_RSVD_MASK;
755 * Look up the guest pte for the faulting address.
757 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
760 * The page is not mapped by the guest. Let the guest handle it.
763 pgprintk("%s: guest page fault\n", __func__);
765 inject_page_fault(vcpu, &walker.fault);
770 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
771 shadow_page_table_clear_flood(vcpu, addr);
772 return RET_PF_EMULATE;
775 vcpu->arch.write_fault_to_shadow_pgtable = false;
777 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
778 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
780 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
781 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
782 if (likely(!force_pt_level)) {
783 level = min(walker.level, level);
784 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
787 force_pt_level = true;
789 mmu_seq = vcpu->kvm->mmu_notifier_seq;
792 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
796 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
797 walker.gfn, pfn, walker.pte_access, &r))
801 * Do not change pte_access if the pfn is a mmio page, otherwise
802 * we will cache the incorrect access into mmio spte.
804 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
805 !is_write_protection(vcpu) && !user_fault &&
806 !is_noslot_pfn(pfn)) {
807 walker.pte_access |= ACC_WRITE_MASK;
808 walker.pte_access &= ~ACC_USER_MASK;
811 * If we converted a user page to a kernel page,
812 * so that the kernel can write to it when cr0.wp=0,
813 * then we should prevent the kernel from executing it
814 * if SMEP is enabled.
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
817 walker.pte_access &= ~ACC_EXEC_MASK;
821 spin_lock(&vcpu->kvm->mmu_lock);
822 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
825 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
826 make_mmu_pages_available(vcpu);
828 transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level);
829 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
830 level, pfn, map_writable, prefault, lpage_disallowed);
831 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
834 spin_unlock(&vcpu->kvm->mmu_lock);
835 kvm_release_pfn_clean(pfn);
839 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
843 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
846 offset = sp->role.quadrant << PT64_LEVEL_BITS;
848 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
851 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
853 struct kvm_shadow_walk_iterator iterator;
854 struct kvm_mmu_page *sp;
858 vcpu_clear_mmio_info(vcpu, gva);
861 * No need to check return value here, rmap_can_add() can
862 * help us to skip pte prefetch later.
864 mmu_topup_memory_caches(vcpu);
866 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
871 spin_lock(&vcpu->kvm->mmu_lock);
872 for_each_shadow_entry(vcpu, gva, iterator) {
873 level = iterator.level;
874 sptep = iterator.sptep;
876 sp = page_header(__pa(sptep));
877 if (is_last_spte(*sptep, level)) {
884 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
885 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
887 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
888 kvm_flush_remote_tlbs(vcpu->kvm);
890 if (!rmap_can_add(vcpu))
893 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
894 sizeof(pt_element_t)))
897 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
900 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
903 spin_unlock(&vcpu->kvm->mmu_lock);
906 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
907 struct x86_exception *exception)
909 struct guest_walker walker;
910 gpa_t gpa = UNMAPPED_GVA;
913 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
916 gpa = gfn_to_gpa(walker.gfn);
917 gpa |= vaddr & ~PAGE_MASK;
918 } else if (exception)
919 *exception = walker.fault;
924 #if PTTYPE != PTTYPE_EPT
925 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
927 struct x86_exception *exception)
929 struct guest_walker walker;
930 gpa_t gpa = UNMAPPED_GVA;
933 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
936 gpa = gfn_to_gpa(walker.gfn);
937 gpa |= vaddr & ~PAGE_MASK;
938 } else if (exception)
939 *exception = walker.fault;
946 * Using the cached information from sp->gfns is safe because:
947 * - The spte has a reference to the struct page, so the pfn for a given gfn
948 * can't change unless all sptes pointing to it are nuked first.
951 * We should flush all tlbs if spte is dropped even though guest is
952 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
953 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
954 * used by guest then tlbs are not flushed, so guest is allowed to access the
956 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
958 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
960 int i, nr_present = 0;
964 /* direct kvm_mmu_page can not be unsync. */
965 BUG_ON(sp->role.direct);
967 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
969 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
978 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
980 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
981 sizeof(pt_element_t)))
984 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
986 * Update spte before increasing tlbs_dirty to make
987 * sure no tlb flush is lost after spte is zapped; see
988 * the comments in kvm_flush_remote_tlbs().
991 vcpu->kvm->tlbs_dirty++;
995 gfn = gpte_to_gfn(gpte);
996 pte_access = sp->role.access;
997 pte_access &= FNAME(gpte_access)(vcpu, gpte);
998 FNAME(protect_clean_gpte)(&pte_access, gpte);
1000 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1004 if (gfn != sp->gfns[i]) {
1005 drop_spte(vcpu->kvm, &sp->spt[i]);
1007 * The same as above where we are doing
1008 * prefetch_invalid_gpte().
1011 vcpu->kvm->tlbs_dirty++;
1017 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1019 set_spte(vcpu, &sp->spt[i], pte_access,
1020 PT_PAGE_TABLE_LEVEL, gfn,
1021 spte_to_pfn(sp->spt[i]), true, false,
1031 #undef PT_BASE_ADDR_MASK
1033 #undef PT_LVL_ADDR_MASK
1034 #undef PT_LVL_OFFSET_MASK
1035 #undef PT_LEVEL_BITS
1036 #undef PT_MAX_FULL_LEVELS
1038 #undef gpte_to_gfn_lvl
1040 #undef PT_GUEST_ACCESSED_MASK
1041 #undef PT_GUEST_DIRTY_MASK
1042 #undef PT_GUEST_DIRTY_SHIFT
1043 #undef PT_GUEST_ACCESSED_SHIFT