2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
30 extern u64 __pure __using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
84 #error Invalid PTTYPE value
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
91 * The guest_walker structure emulates the behavior of the hardware page
97 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
98 pt_element_t ptes[PT_MAX_FULL_LEVELS];
99 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
100 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
101 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
102 bool pte_writable[PT_MAX_FULL_LEVELS];
103 unsigned int pt_access[PT_MAX_FULL_LEVELS];
104 unsigned int pte_access;
106 struct x86_exception fault;
109 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
111 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
114 static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
118 /* dirty bit is not supported, so no need to track it */
119 if (!PT_GUEST_DIRTY_MASK)
122 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
124 mask = (unsigned)~ACC_WRITE_MASK;
125 /* Allow write access to dirty gptes */
126 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
131 static inline int FNAME(is_present_gpte)(unsigned long pte)
133 #if PTTYPE != PTTYPE_EPT
134 return pte & PT_PRESENT_MASK;
140 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
141 pt_element_t __user *ptep_user, unsigned index,
142 pt_element_t orig_pte, pt_element_t new_pte)
149 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
150 /* Check if the user is doing something meaningless. */
151 if (unlikely(npages != 1))
154 table = kmap_atomic(page);
155 ret = CMPXCHG(&table[index], orig_pte, new_pte);
156 kunmap_atomic(table);
158 kvm_release_page_dirty(page);
160 return (ret != orig_pte);
163 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
164 struct kvm_mmu_page *sp, u64 *spte,
167 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
170 if (!FNAME(is_present_gpte)(gpte))
173 /* if accessed bit is not supported prefetch non accessed gpte */
174 if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
180 drop_spte(vcpu->kvm, spte);
185 * For PTTYPE_EPT, a page table can be executable but not readable
186 * on supported processors. Therefore, set_spte does not automatically
187 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
188 * to signify readability since it isn't used in the EPT case
190 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
193 #if PTTYPE == PTTYPE_EPT
194 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
195 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
196 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
198 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
199 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
200 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
201 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
202 access ^= (gpte >> PT64_NX_SHIFT);
208 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
210 struct guest_walker *walker,
213 unsigned level, index;
214 pt_element_t pte, orig_pte;
215 pt_element_t __user *ptep_user;
219 /* dirty/accessed bits are not supported, so no need to update them */
220 if (!PT_GUEST_DIRTY_MASK)
223 for (level = walker->max_level; level >= walker->level; --level) {
224 pte = orig_pte = walker->ptes[level - 1];
225 table_gfn = walker->table_gfn[level - 1];
226 ptep_user = walker->ptep_user[level - 1];
227 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
228 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
229 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
230 pte |= PT_GUEST_ACCESSED_MASK;
232 if (level == walker->level && write_fault &&
233 !(pte & PT_GUEST_DIRTY_MASK)) {
234 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
235 pte |= PT_GUEST_DIRTY_MASK;
241 * If the slot is read-only, simply do not process the accessed
242 * and dirty bits. This is the correct thing to do if the slot
243 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
244 * are only supported if the accessed and dirty bits are already
245 * set in the ROM (so that MMIO writes are never needed).
247 * Note that NPT does not allow this at all and faults, since
248 * it always wants nested page table entries for the guest
249 * page tables to be writable. And EPT works but will simply
250 * overwrite the read-only memory to set the accessed and dirty
253 if (unlikely(!walker->pte_writable[level - 1]))
256 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
260 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
261 walker->ptes[level - 1] = pte;
266 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
270 pte_t pte = {.pte = gpte};
272 pkeys = pte_flags_pkey(pte_flags(pte));
278 * Fetch a guest pte for a guest virtual address
280 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
281 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
282 gva_t addr, u32 access)
286 pt_element_t __user *uninitialized_var(ptep_user);
288 u64 pt_access, pte_access;
289 unsigned index, accessed_dirty, pte_pkey;
292 u64 walk_nx_mask = 0;
293 const int write_fault = access & PFERR_WRITE_MASK;
294 const int user_fault = access & PFERR_USER_MASK;
295 const int fetch_fault = access & PFERR_FETCH_MASK;
300 trace_kvm_mmu_pagetable_walk(addr, access);
302 walker->level = mmu->root_level;
303 pte = mmu->get_cr3(vcpu);
306 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
307 if (walker->level == PT32E_ROOT_LEVEL) {
308 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
309 trace_kvm_mmu_paging_element(pte, walker->level);
310 if (!FNAME(is_present_gpte)(pte))
315 walker->max_level = walker->level;
316 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
323 unsigned long host_addr;
325 pt_access = pte_access;
328 index = PT_INDEX(addr, walker->level);
329 table_gfn = gpte_to_gfn(pte);
330 offset = index * sizeof(pt_element_t);
331 pte_gpa = gfn_to_gpa(table_gfn) + offset;
333 BUG_ON(walker->level < 1);
334 walker->table_gfn[walker->level - 1] = table_gfn;
335 walker->pte_gpa[walker->level - 1] = pte_gpa;
337 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
338 PFERR_USER_MASK|PFERR_WRITE_MASK,
342 * FIXME: This can happen if emulation (for of an INS/OUTS
343 * instruction) triggers a nested page fault. The exit
344 * qualification / exit info field will incorrectly have
345 * "guest page access" as the nested page fault's cause,
346 * instead of "guest page structure access". To fix this,
347 * the x86_exception struct should be augmented with enough
348 * information to fix the exit_qualification or exit_info_1
351 if (unlikely(real_gfn == UNMAPPED_GVA))
354 real_gfn = gpa_to_gfn(real_gfn);
356 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
357 &walker->pte_writable[walker->level - 1]);
358 if (unlikely(kvm_is_error_hva(host_addr)))
361 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
362 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
364 walker->ptep_user[walker->level - 1] = ptep_user;
366 trace_kvm_mmu_paging_element(pte, walker->level);
369 * Inverting the NX it lets us AND it like other
372 pte_access = pt_access & (pte ^ walk_nx_mask);
374 if (unlikely(!FNAME(is_present_gpte)(pte)))
377 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
378 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
382 walker->ptes[walker->level - 1] = pte;
384 /* Convert to ACC_*_MASK flags for struct guest_walker. */
385 walker->pt_access[walker->level - 1] = FNAME(gpte_access)(vcpu, pt_access ^ walk_nx_mask);
386 } while (!is_last_gpte(mmu, walker->level, pte));
388 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
389 accessed_dirty = pte_access & PT_GUEST_ACCESSED_MASK;
391 /* Convert to ACC_*_MASK flags for struct guest_walker. */
392 walker->pte_access = FNAME(gpte_access)(vcpu, pte_access ^ walk_nx_mask);
393 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
394 if (unlikely(errcode))
397 gfn = gpte_to_gfn_lvl(pte, walker->level);
398 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
400 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
401 gfn += pse36_gfn_delta(pte);
403 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
404 if (real_gpa == UNMAPPED_GVA)
407 walker->gfn = real_gpa >> PAGE_SHIFT;
410 FNAME(protect_clean_gpte)(&walker->pte_access, pte);
413 * On a write fault, fold the dirty bit into accessed_dirty.
414 * For modes without A/D bits support accessed_dirty will be
417 accessed_dirty &= pte >>
418 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
420 if (unlikely(!accessed_dirty)) {
421 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
422 if (unlikely(ret < 0))
428 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
429 __func__, (u64)pte, walker->pte_access,
430 walker->pt_access[walker->level - 1]);
434 errcode |= write_fault | user_fault;
435 if (fetch_fault && (mmu->nx ||
436 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
437 errcode |= PFERR_FETCH_MASK;
439 walker->fault.vector = PF_VECTOR;
440 walker->fault.error_code_valid = true;
441 walker->fault.error_code = errcode;
443 #if PTTYPE == PTTYPE_EPT
445 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
446 * misconfiguration requires to be injected. The detection is
447 * done by is_rsvd_bits_set() above.
449 * We set up the value of exit_qualification to inject:
450 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
451 * [5:3] - Calculated by the page walk of the guest EPT page tables
452 * [7:8] - Derived from [7:8] of real exit_qualification
454 * The other bits are set to 0.
456 if (!(errcode & PFERR_RSVD_MASK)) {
457 vcpu->arch.exit_qualification &= 0x187;
458 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
461 walker->fault.address = addr;
462 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
464 trace_kvm_mmu_walker_error(walker->fault.error_code);
468 static int FNAME(walk_addr)(struct guest_walker *walker,
469 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
471 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
475 #if PTTYPE != PTTYPE_EPT
476 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
477 struct kvm_vcpu *vcpu, gva_t addr,
480 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
486 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
487 u64 *spte, pt_element_t gpte, bool no_dirty_log)
493 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
496 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
498 gfn = gpte_to_gfn(gpte);
499 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
500 FNAME(protect_clean_gpte)(&pte_access, gpte);
501 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
502 no_dirty_log && (pte_access & ACC_WRITE_MASK));
503 if (is_error_pfn(pfn))
507 * we call mmu_set_spte() with host_writable = true because
508 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
510 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
513 kvm_release_pfn_clean(pfn);
517 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
518 u64 *spte, const void *pte)
520 pt_element_t gpte = *(const pt_element_t *)pte;
522 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
525 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
526 struct guest_walker *gw, int level)
528 pt_element_t curr_pte;
529 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
533 if (level == PT_PAGE_TABLE_LEVEL) {
534 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
535 base_gpa = pte_gpa & ~mask;
536 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
538 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
539 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
540 curr_pte = gw->prefetch_ptes[index];
542 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
543 &curr_pte, sizeof(curr_pte));
545 return r || curr_pte != gw->ptes[level - 1];
548 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
551 struct kvm_mmu_page *sp;
552 pt_element_t *gptep = gw->prefetch_ptes;
556 sp = page_header(__pa(sptep));
558 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
562 return __direct_pte_prefetch(vcpu, sp, sptep);
564 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
567 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
571 if (is_shadow_present_pte(*spte))
574 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
580 * Fetch a shadow pte for a specific level in the paging hierarchy.
581 * If the guest tries to write a write-protected page, we need to
582 * emulate this operation, return 1 to indicate this case.
584 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
585 struct guest_walker *gw,
586 int write_fault, int hlevel,
587 kvm_pfn_t pfn, bool map_writable, bool prefault,
588 bool lpage_disallowed)
590 struct kvm_mmu_page *sp = NULL;
591 struct kvm_shadow_walk_iterator it;
592 unsigned int direct_access, access;
596 direct_access = gw->pte_access;
598 top_level = vcpu->arch.mmu.root_level;
599 if (top_level == PT32E_ROOT_LEVEL)
600 top_level = PT32_ROOT_LEVEL;
602 * Verify that the top-level gpte is still there. Since the page
603 * is a root page, it is either write protected (and cannot be
604 * changed from now on) or it is invalid (in which case, we don't
605 * really care if it changes underneath us after this point).
607 if (FNAME(gpte_changed)(vcpu, gw, top_level))
608 goto out_gpte_changed;
610 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
611 goto out_gpte_changed;
613 for (shadow_walk_init(&it, vcpu, addr);
614 shadow_walk_okay(&it) && it.level > gw->level;
615 shadow_walk_next(&it)) {
618 clear_sp_write_flooding_count(it.sptep);
619 drop_large_spte(vcpu, it.sptep);
622 if (!is_shadow_present_pte(*it.sptep)) {
623 table_gfn = gw->table_gfn[it.level - 2];
624 access = gw->pt_access[it.level - 2];
625 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
630 * Verify that the gpte in the page we've just write
631 * protected is still there.
633 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
634 goto out_gpte_changed;
637 link_shadow_page(vcpu, it.sptep, sp);
641 * FNAME(page_fault) might have clobbered the bottom bits of
642 * gw->gfn, restore them from the virtual address.
644 gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT);
647 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
649 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
650 clear_sp_write_flooding_count(it.sptep);
653 * We cannot overwrite existing page tables with an NX
654 * large page, as the leaf could be executable.
656 disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel);
658 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
659 if (it.level == hlevel)
662 validate_direct_spte(vcpu, it.sptep, direct_access);
664 drop_large_spte(vcpu, it.sptep);
666 if (!is_shadow_present_pte(*it.sptep)) {
667 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
668 it.level - 1, true, direct_access);
669 link_shadow_page(vcpu, it.sptep, sp);
670 if (lpage_disallowed)
671 account_huge_nx_page(vcpu->kvm, sp);
675 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
676 it.level, base_gfn, pfn, prefault, map_writable);
677 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
678 ++vcpu->stat.pf_fixed;
686 * To see whether the mapped gfn can write its page table in the current
689 * It is the helper function of FNAME(page_fault). When guest uses large page
690 * size to map the writable gfn which is used as current page table, we should
691 * force kvm to use small page size to map it because new shadow page will be
692 * created when kvm establishes shadow page table that stop kvm using large
693 * page size. Do it early can avoid unnecessary #PF and emulation.
695 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
696 * currently used as its page table.
698 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
699 * since the PDPT is always shadowed, that means, we can not use large page
700 * size to map the gfn which is used as PDPT.
703 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
704 struct guest_walker *walker, int user_fault,
705 bool *write_fault_to_shadow_pgtable)
708 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
709 bool self_changed = false;
711 if (!(walker->pte_access & ACC_WRITE_MASK ||
712 (!is_write_protection(vcpu) && !user_fault)))
715 for (level = walker->level; level <= walker->max_level; level++) {
716 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
718 self_changed |= !(gfn & mask);
719 *write_fault_to_shadow_pgtable |= !gfn;
726 * Page fault handler. There are several causes for a page fault:
727 * - there is no shadow pte for the guest pte
728 * - write access through a shadow pte marked read only so that we can set
730 * - write access to a shadow pte marked read only so we can update the page
731 * dirty bitmap, when userspace requests it
732 * - mmio access; in this case we will never install a present shadow pte
733 * - normal guest page fault due to the guest pte marked not present, not
734 * writable, or not executable
736 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
737 * a negative value on error.
739 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
742 int write_fault = error_code & PFERR_WRITE_MASK;
743 int user_fault = error_code & PFERR_USER_MASK;
744 struct guest_walker walker;
747 int level = PT_PAGE_TABLE_LEVEL;
748 unsigned long mmu_seq;
749 bool map_writable, is_self_change_mapping;
750 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
751 is_nx_huge_page_enabled();
752 bool force_pt_level = lpage_disallowed;
754 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
756 r = mmu_topup_memory_caches(vcpu);
761 * If PFEC.RSVD is set, this is a shadow page fault.
762 * The bit needs to be cleared before walking guest page tables.
764 error_code &= ~PFERR_RSVD_MASK;
767 * Look up the guest pte for the faulting address.
769 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
772 * The page is not mapped by the guest. Let the guest handle it.
775 pgprintk("%s: guest page fault\n", __func__);
777 inject_page_fault(vcpu, &walker.fault);
782 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
783 shadow_page_table_clear_flood(vcpu, addr);
784 return RET_PF_EMULATE;
787 vcpu->arch.write_fault_to_shadow_pgtable = false;
789 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
790 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
792 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
793 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
794 if (likely(!force_pt_level)) {
795 level = min(walker.level, level);
796 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
799 force_pt_level = true;
801 mmu_seq = vcpu->kvm->mmu_notifier_seq;
804 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
808 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
809 walker.gfn, pfn, walker.pte_access, &r))
813 * Do not change pte_access if the pfn is a mmio page, otherwise
814 * we will cache the incorrect access into mmio spte.
816 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
817 !is_write_protection(vcpu) && !user_fault &&
818 !is_noslot_pfn(pfn)) {
819 walker.pte_access |= ACC_WRITE_MASK;
820 walker.pte_access &= ~ACC_USER_MASK;
823 * If we converted a user page to a kernel page,
824 * so that the kernel can write to it when cr0.wp=0,
825 * then we should prevent the kernel from executing it
826 * if SMEP is enabled.
828 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
829 walker.pte_access &= ~ACC_EXEC_MASK;
833 spin_lock(&vcpu->kvm->mmu_lock);
834 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
837 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
838 make_mmu_pages_available(vcpu);
840 transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level);
841 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
842 level, pfn, map_writable, prefault, lpage_disallowed);
843 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
846 spin_unlock(&vcpu->kvm->mmu_lock);
847 kvm_release_pfn_clean(pfn);
851 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
855 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
858 offset = sp->role.quadrant << PT64_LEVEL_BITS;
860 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
863 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
865 struct kvm_shadow_walk_iterator iterator;
866 struct kvm_mmu_page *sp;
870 vcpu_clear_mmio_info(vcpu, gva);
873 * No need to check return value here, rmap_can_add() can
874 * help us to skip pte prefetch later.
876 mmu_topup_memory_caches(vcpu);
878 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
883 spin_lock(&vcpu->kvm->mmu_lock);
884 for_each_shadow_entry(vcpu, gva, iterator) {
885 level = iterator.level;
886 sptep = iterator.sptep;
888 sp = page_header(__pa(sptep));
889 if (is_last_spte(*sptep, level)) {
896 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
897 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
899 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
900 kvm_flush_remote_tlbs(vcpu->kvm);
902 if (!rmap_can_add(vcpu))
905 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
906 sizeof(pt_element_t)))
909 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
912 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
915 spin_unlock(&vcpu->kvm->mmu_lock);
918 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
919 struct x86_exception *exception)
921 struct guest_walker walker;
922 gpa_t gpa = UNMAPPED_GVA;
925 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
928 gpa = gfn_to_gpa(walker.gfn);
929 gpa |= vaddr & ~PAGE_MASK;
930 } else if (exception)
931 *exception = walker.fault;
936 #if PTTYPE != PTTYPE_EPT
937 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
939 struct x86_exception *exception)
941 struct guest_walker walker;
942 gpa_t gpa = UNMAPPED_GVA;
945 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
948 gpa = gfn_to_gpa(walker.gfn);
949 gpa |= vaddr & ~PAGE_MASK;
950 } else if (exception)
951 *exception = walker.fault;
958 * Using the cached information from sp->gfns is safe because:
959 * - The spte has a reference to the struct page, so the pfn for a given gfn
960 * can't change unless all sptes pointing to it are nuked first.
963 * We should flush all tlbs if spte is dropped even though guest is
964 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
965 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
966 * used by guest then tlbs are not flushed, so guest is allowed to access the
968 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
970 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
972 int i, nr_present = 0;
976 /* direct kvm_mmu_page can not be unsync. */
977 BUG_ON(sp->role.direct);
979 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
981 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
990 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
992 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
993 sizeof(pt_element_t)))
996 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
998 * Update spte before increasing tlbs_dirty to make
999 * sure no tlb flush is lost after spte is zapped; see
1000 * the comments in kvm_flush_remote_tlbs().
1003 vcpu->kvm->tlbs_dirty++;
1007 gfn = gpte_to_gfn(gpte);
1008 pte_access = sp->role.access;
1009 pte_access &= FNAME(gpte_access)(vcpu, gpte);
1010 FNAME(protect_clean_gpte)(&pte_access, gpte);
1012 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1016 if (gfn != sp->gfns[i]) {
1017 drop_spte(vcpu->kvm, &sp->spt[i]);
1019 * The same as above where we are doing
1020 * prefetch_invalid_gpte().
1023 vcpu->kvm->tlbs_dirty++;
1029 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1031 set_spte(vcpu, &sp->spt[i], pte_access,
1032 PT_PAGE_TABLE_LEVEL, gfn,
1033 spte_to_pfn(sp->spt[i]), true, false,
1043 #undef PT_BASE_ADDR_MASK
1045 #undef PT_LVL_ADDR_MASK
1046 #undef PT_LVL_OFFSET_MASK
1047 #undef PT_LEVEL_BITS
1048 #undef PT_MAX_FULL_LEVELS
1050 #undef gpte_to_gfn_lvl
1052 #undef PT_GUEST_ACCESSED_MASK
1053 #undef PT_GUEST_DIRTY_MASK
1054 #undef PT_GUEST_DIRTY_SHIFT
1055 #undef PT_GUEST_ACCESSED_SHIFT