2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
36 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
37 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
39 #define PT_MAX_FULL_LEVELS 4
40 #define CMPXCHG cmpxchg
42 #define CMPXCHG cmpxchg64
43 #define PT_MAX_FULL_LEVELS 2
46 #define pt_element_t u32
47 #define guest_walker guest_walker32
48 #define FNAME(name) paging##32_##name
49 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
50 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
51 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
52 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
53 #define PT_LEVEL_BITS PT32_LEVEL_BITS
54 #define PT_MAX_FULL_LEVELS 2
55 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
56 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
57 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
58 #define CMPXCHG cmpxchg
59 #elif PTTYPE == PTTYPE_EPT
60 #define pt_element_t u64
61 #define guest_walker guest_walkerEPT
62 #define FNAME(name) ept_##name
63 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
64 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
65 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
66 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
67 #define PT_LEVEL_BITS PT64_LEVEL_BITS
68 #define PT_GUEST_DIRTY_SHIFT 9
69 #define PT_GUEST_ACCESSED_SHIFT 8
70 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
71 #define CMPXCHG cmpxchg64
72 #define PT_MAX_FULL_LEVELS 4
74 #error Invalid PTTYPE value
77 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
78 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
80 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
81 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
84 * The guest_walker structure emulates the behavior of the hardware page
90 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
91 pt_element_t ptes[PT_MAX_FULL_LEVELS];
92 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
93 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
94 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
95 bool pte_writable[PT_MAX_FULL_LEVELS];
96 unsigned int pt_access[PT_MAX_FULL_LEVELS];
97 unsigned int pte_access;
99 struct x86_exception fault;
102 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
104 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
107 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
112 /* dirty bit is not supported, so no need to track it */
113 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
116 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
118 mask = (unsigned)~ACC_WRITE_MASK;
119 /* Allow write access to dirty gptes */
120 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
125 static inline int FNAME(is_present_gpte)(unsigned long pte)
127 #if PTTYPE != PTTYPE_EPT
128 return pte & PT_PRESENT_MASK;
134 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
135 pt_element_t __user *ptep_user, unsigned index,
136 pt_element_t orig_pte, pt_element_t new_pte)
143 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
144 /* Check if the user is doing something meaningless. */
145 if (unlikely(npages != 1))
148 table = kmap_atomic(page);
149 ret = CMPXCHG(&table[index], orig_pte, new_pte);
150 kunmap_atomic(table);
152 kvm_release_page_dirty(page);
154 return (ret != orig_pte);
157 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
158 struct kvm_mmu_page *sp, u64 *spte,
161 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
164 if (!FNAME(is_present_gpte)(gpte))
167 /* if accessed bit is not supported prefetch non accessed gpte */
168 if (PT_HAVE_ACCESSED_DIRTY(&vcpu->arch.mmu) && !(gpte & PT_GUEST_ACCESSED_MASK))
174 drop_spte(vcpu->kvm, spte);
179 * For PTTYPE_EPT, a page table can be executable but not readable
180 * on supported processors. Therefore, set_spte does not automatically
181 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
182 * to signify readability since it isn't used in the EPT case
184 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
187 #if PTTYPE == PTTYPE_EPT
188 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
189 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
190 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
192 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
193 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
194 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
195 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
196 access ^= (gpte >> PT64_NX_SHIFT);
202 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
204 struct guest_walker *walker,
205 gpa_t addr, int write_fault)
207 unsigned level, index;
208 pt_element_t pte, orig_pte;
209 pt_element_t __user *ptep_user;
213 /* dirty/accessed bits are not supported, so no need to update them */
214 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
217 for (level = walker->max_level; level >= walker->level; --level) {
218 pte = orig_pte = walker->ptes[level - 1];
219 table_gfn = walker->table_gfn[level - 1];
220 ptep_user = walker->ptep_user[level - 1];
221 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
222 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
223 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
224 pte |= PT_GUEST_ACCESSED_MASK;
226 if (level == walker->level && write_fault &&
227 !(pte & PT_GUEST_DIRTY_MASK)) {
228 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
229 #if PTTYPE == PTTYPE_EPT
230 if (kvm_arch_write_log_dirty(vcpu, addr))
233 pte |= PT_GUEST_DIRTY_MASK;
239 * If the slot is read-only, simply do not process the accessed
240 * and dirty bits. This is the correct thing to do if the slot
241 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
242 * are only supported if the accessed and dirty bits are already
243 * set in the ROM (so that MMIO writes are never needed).
245 * Note that NPT does not allow this at all and faults, since
246 * it always wants nested page table entries for the guest
247 * page tables to be writable. And EPT works but will simply
248 * overwrite the read-only memory to set the accessed and dirty
251 if (unlikely(!walker->pte_writable[level - 1]))
254 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
258 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
259 walker->ptes[level - 1] = pte;
264 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
268 pte_t pte = {.pte = gpte};
270 pkeys = pte_flags_pkey(pte_flags(pte));
276 * Fetch a guest pte for a guest virtual address
278 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
279 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
280 gva_t addr, u32 access)
284 pt_element_t __user *uninitialized_var(ptep_user);
286 u64 pt_access, pte_access;
287 unsigned index, accessed_dirty, pte_pkey;
288 unsigned nested_access;
292 u64 walk_nx_mask = 0;
293 const int write_fault = access & PFERR_WRITE_MASK;
294 const int user_fault = access & PFERR_USER_MASK;
295 const int fetch_fault = access & PFERR_FETCH_MASK;
300 trace_kvm_mmu_pagetable_walk(addr, access);
302 walker->level = mmu->root_level;
303 pte = mmu->get_cr3(vcpu);
304 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
307 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
308 if (walker->level == PT32E_ROOT_LEVEL) {
309 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
310 trace_kvm_mmu_paging_element(pte, walker->level);
311 if (!FNAME(is_present_gpte)(pte))
316 walker->max_level = walker->level;
317 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
320 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
321 * by the MOV to CR instruction are treated as reads and do not cause the
322 * processor to set the dirty flag in any EPT paging-structure entry.
324 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
331 unsigned long host_addr;
333 pt_access = pte_access;
336 index = PT_INDEX(addr, walker->level);
337 table_gfn = gpte_to_gfn(pte);
338 offset = index * sizeof(pt_element_t);
339 pte_gpa = gfn_to_gpa(table_gfn) + offset;
341 BUG_ON(walker->level < 1);
342 walker->table_gfn[walker->level - 1] = table_gfn;
343 walker->pte_gpa[walker->level - 1] = pte_gpa;
345 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
350 * FIXME: This can happen if emulation (for of an INS/OUTS
351 * instruction) triggers a nested page fault. The exit
352 * qualification / exit info field will incorrectly have
353 * "guest page access" as the nested page fault's cause,
354 * instead of "guest page structure access". To fix this,
355 * the x86_exception struct should be augmented with enough
356 * information to fix the exit_qualification or exit_info_1
359 if (unlikely(real_gfn == UNMAPPED_GVA))
362 real_gfn = gpa_to_gfn(real_gfn);
364 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
365 &walker->pte_writable[walker->level - 1]);
366 if (unlikely(kvm_is_error_hva(host_addr)))
369 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
370 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
372 walker->ptep_user[walker->level - 1] = ptep_user;
374 trace_kvm_mmu_paging_element(pte, walker->level);
377 * Inverting the NX it lets us AND it like other
380 pte_access = pt_access & (pte ^ walk_nx_mask);
382 if (unlikely(!FNAME(is_present_gpte)(pte)))
385 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
386 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
390 walker->ptes[walker->level - 1] = pte;
392 /* Convert to ACC_*_MASK flags for struct guest_walker. */
393 walker->pt_access[walker->level - 1] = FNAME(gpte_access)(vcpu, pt_access ^ walk_nx_mask);
394 } while (!is_last_gpte(mmu, walker->level, pte));
396 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
397 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
399 /* Convert to ACC_*_MASK flags for struct guest_walker. */
400 walker->pte_access = FNAME(gpte_access)(vcpu, pte_access ^ walk_nx_mask);
401 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
402 if (unlikely(errcode))
405 gfn = gpte_to_gfn_lvl(pte, walker->level);
406 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
408 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
409 gfn += pse36_gfn_delta(pte);
411 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
412 if (real_gpa == UNMAPPED_GVA)
415 walker->gfn = real_gpa >> PAGE_SHIFT;
418 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
421 * On a write fault, fold the dirty bit into accessed_dirty.
422 * For modes without A/D bits support accessed_dirty will be
425 accessed_dirty &= pte >>
426 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
428 if (unlikely(!accessed_dirty)) {
429 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
431 if (unlikely(ret < 0))
437 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
438 __func__, (u64)pte, walker->pte_access,
439 walker->pt_access[walker->level - 1]);
443 errcode |= write_fault | user_fault;
444 if (fetch_fault && (mmu->nx ||
445 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
446 errcode |= PFERR_FETCH_MASK;
448 walker->fault.vector = PF_VECTOR;
449 walker->fault.error_code_valid = true;
450 walker->fault.error_code = errcode;
452 #if PTTYPE == PTTYPE_EPT
454 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
455 * misconfiguration requires to be injected. The detection is
456 * done by is_rsvd_bits_set() above.
458 * We set up the value of exit_qualification to inject:
459 * [2:0] - Derive from the access bits. The exit_qualification might be
460 * out of date if it is serving an EPT misconfiguration.
461 * [5:3] - Calculated by the page walk of the guest EPT page tables
462 * [7:8] - Derived from [7:8] of real exit_qualification
464 * The other bits are set to 0.
466 if (!(errcode & PFERR_RSVD_MASK)) {
467 vcpu->arch.exit_qualification &= 0x180;
469 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
471 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
473 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
474 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
477 walker->fault.address = addr;
478 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
480 trace_kvm_mmu_walker_error(walker->fault.error_code);
484 static int FNAME(walk_addr)(struct guest_walker *walker,
485 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
487 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
491 #if PTTYPE != PTTYPE_EPT
492 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
493 struct kvm_vcpu *vcpu, gva_t addr,
496 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
502 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
503 u64 *spte, pt_element_t gpte, bool no_dirty_log)
509 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
512 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
514 gfn = gpte_to_gfn(gpte);
515 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
516 FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte);
517 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
518 no_dirty_log && (pte_access & ACC_WRITE_MASK));
519 if (is_error_pfn(pfn))
523 * we call mmu_set_spte() with host_writable = true because
524 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
526 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
529 kvm_release_pfn_clean(pfn);
533 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
534 u64 *spte, const void *pte)
536 pt_element_t gpte = *(const pt_element_t *)pte;
538 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
541 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
542 struct guest_walker *gw, int level)
544 pt_element_t curr_pte;
545 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
549 if (level == PT_PAGE_TABLE_LEVEL) {
550 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
551 base_gpa = pte_gpa & ~mask;
552 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
554 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
555 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
556 curr_pte = gw->prefetch_ptes[index];
558 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
559 &curr_pte, sizeof(curr_pte));
561 return r || curr_pte != gw->ptes[level - 1];
564 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
567 struct kvm_mmu_page *sp;
568 pt_element_t *gptep = gw->prefetch_ptes;
572 sp = page_header(__pa(sptep));
574 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
578 return __direct_pte_prefetch(vcpu, sp, sptep);
580 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
583 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
587 if (is_shadow_present_pte(*spte))
590 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
596 * Fetch a shadow pte for a specific level in the paging hierarchy.
597 * If the guest tries to write a write-protected page, we need to
598 * emulate this operation, return 1 to indicate this case.
600 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
601 struct guest_walker *gw,
602 int write_fault, int hlevel,
603 kvm_pfn_t pfn, bool map_writable, bool prefault,
604 bool lpage_disallowed)
606 struct kvm_mmu_page *sp = NULL;
607 struct kvm_shadow_walk_iterator it;
608 unsigned int direct_access, access;
612 direct_access = gw->pte_access;
614 top_level = vcpu->arch.mmu.root_level;
615 if (top_level == PT32E_ROOT_LEVEL)
616 top_level = PT32_ROOT_LEVEL;
618 * Verify that the top-level gpte is still there. Since the page
619 * is a root page, it is either write protected (and cannot be
620 * changed from now on) or it is invalid (in which case, we don't
621 * really care if it changes underneath us after this point).
623 if (FNAME(gpte_changed)(vcpu, gw, top_level))
624 goto out_gpte_changed;
626 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
627 goto out_gpte_changed;
629 for (shadow_walk_init(&it, vcpu, addr);
630 shadow_walk_okay(&it) && it.level > gw->level;
631 shadow_walk_next(&it)) {
634 clear_sp_write_flooding_count(it.sptep);
635 drop_large_spte(vcpu, it.sptep);
638 if (!is_shadow_present_pte(*it.sptep)) {
639 table_gfn = gw->table_gfn[it.level - 2];
640 access = gw->pt_access[it.level - 2];
641 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
646 * Verify that the gpte in the page we've just write
647 * protected is still there.
649 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
650 goto out_gpte_changed;
653 link_shadow_page(vcpu, it.sptep, sp);
657 * FNAME(page_fault) might have clobbered the bottom bits of
658 * gw->gfn, restore them from the virtual address.
660 gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT);
663 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
665 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
666 clear_sp_write_flooding_count(it.sptep);
669 * We cannot overwrite existing page tables with an NX
670 * large page, as the leaf could be executable.
672 disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel);
674 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
675 if (it.level == hlevel)
678 validate_direct_spte(vcpu, it.sptep, direct_access);
680 drop_large_spte(vcpu, it.sptep);
682 if (!is_shadow_present_pte(*it.sptep)) {
683 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
684 it.level - 1, true, direct_access);
685 link_shadow_page(vcpu, it.sptep, sp);
686 if (lpage_disallowed)
687 account_huge_nx_page(vcpu->kvm, sp);
691 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
692 it.level, base_gfn, pfn, prefault, map_writable);
693 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
694 ++vcpu->stat.pf_fixed;
702 * To see whether the mapped gfn can write its page table in the current
705 * It is the helper function of FNAME(page_fault). When guest uses large page
706 * size to map the writable gfn which is used as current page table, we should
707 * force kvm to use small page size to map it because new shadow page will be
708 * created when kvm establishes shadow page table that stop kvm using large
709 * page size. Do it early can avoid unnecessary #PF and emulation.
711 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
712 * currently used as its page table.
714 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
715 * since the PDPT is always shadowed, that means, we can not use large page
716 * size to map the gfn which is used as PDPT.
719 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
720 struct guest_walker *walker, int user_fault,
721 bool *write_fault_to_shadow_pgtable)
724 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
725 bool self_changed = false;
727 if (!(walker->pte_access & ACC_WRITE_MASK ||
728 (!is_write_protection(vcpu) && !user_fault)))
731 for (level = walker->level; level <= walker->max_level; level++) {
732 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
734 self_changed |= !(gfn & mask);
735 *write_fault_to_shadow_pgtable |= !gfn;
742 * Page fault handler. There are several causes for a page fault:
743 * - there is no shadow pte for the guest pte
744 * - write access through a shadow pte marked read only so that we can set
746 * - write access to a shadow pte marked read only so we can update the page
747 * dirty bitmap, when userspace requests it
748 * - mmio access; in this case we will never install a present shadow pte
749 * - normal guest page fault due to the guest pte marked not present, not
750 * writable, or not executable
752 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
753 * a negative value on error.
755 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
758 int write_fault = error_code & PFERR_WRITE_MASK;
759 int user_fault = error_code & PFERR_USER_MASK;
760 struct guest_walker walker;
763 int level = PT_PAGE_TABLE_LEVEL;
764 unsigned long mmu_seq;
765 bool map_writable, is_self_change_mapping;
766 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
767 is_nx_huge_page_enabled();
768 bool force_pt_level = lpage_disallowed;
770 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
772 r = mmu_topup_memory_caches(vcpu);
777 * If PFEC.RSVD is set, this is a shadow page fault.
778 * The bit needs to be cleared before walking guest page tables.
780 error_code &= ~PFERR_RSVD_MASK;
783 * Look up the guest pte for the faulting address.
785 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
788 * The page is not mapped by the guest. Let the guest handle it.
791 pgprintk("%s: guest page fault\n", __func__);
793 inject_page_fault(vcpu, &walker.fault);
798 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
799 shadow_page_table_clear_flood(vcpu, addr);
800 return RET_PF_EMULATE;
803 vcpu->arch.write_fault_to_shadow_pgtable = false;
805 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
806 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
808 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
809 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
810 if (likely(!force_pt_level)) {
811 level = min(walker.level, level);
812 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
815 force_pt_level = true;
817 mmu_seq = vcpu->kvm->mmu_notifier_seq;
820 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
824 if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
828 * Do not change pte_access if the pfn is a mmio page, otherwise
829 * we will cache the incorrect access into mmio spte.
831 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
832 !is_write_protection(vcpu) && !user_fault &&
833 !is_noslot_pfn(pfn)) {
834 walker.pte_access |= ACC_WRITE_MASK;
835 walker.pte_access &= ~ACC_USER_MASK;
838 * If we converted a user page to a kernel page,
839 * so that the kernel can write to it when cr0.wp=0,
840 * then we should prevent the kernel from executing it
841 * if SMEP is enabled.
843 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
844 walker.pte_access &= ~ACC_EXEC_MASK;
848 spin_lock(&vcpu->kvm->mmu_lock);
849 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
852 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
853 if (make_mmu_pages_available(vcpu) < 0)
856 transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level);
857 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
858 level, pfn, map_writable, prefault, lpage_disallowed);
859 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
862 spin_unlock(&vcpu->kvm->mmu_lock);
863 kvm_release_pfn_clean(pfn);
867 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
871 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
874 offset = sp->role.quadrant << PT64_LEVEL_BITS;
876 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
879 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
881 struct kvm_shadow_walk_iterator iterator;
882 struct kvm_mmu_page *sp;
886 vcpu_clear_mmio_info(vcpu, gva);
889 * No need to check return value here, rmap_can_add() can
890 * help us to skip pte prefetch later.
892 mmu_topup_memory_caches(vcpu);
894 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
899 spin_lock(&vcpu->kvm->mmu_lock);
900 for_each_shadow_entry(vcpu, gva, iterator) {
901 level = iterator.level;
902 sptep = iterator.sptep;
904 sp = page_header(__pa(sptep));
905 if (is_last_spte(*sptep, level)) {
912 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
913 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
915 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
916 kvm_flush_remote_tlbs(vcpu->kvm);
918 if (!rmap_can_add(vcpu))
921 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
922 sizeof(pt_element_t)))
925 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
928 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
931 spin_unlock(&vcpu->kvm->mmu_lock);
934 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
935 struct x86_exception *exception)
937 struct guest_walker walker;
938 gpa_t gpa = UNMAPPED_GVA;
941 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
944 gpa = gfn_to_gpa(walker.gfn);
945 gpa |= vaddr & ~PAGE_MASK;
946 } else if (exception)
947 *exception = walker.fault;
952 #if PTTYPE != PTTYPE_EPT
953 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
955 struct x86_exception *exception)
957 struct guest_walker walker;
958 gpa_t gpa = UNMAPPED_GVA;
961 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
964 gpa = gfn_to_gpa(walker.gfn);
965 gpa |= vaddr & ~PAGE_MASK;
966 } else if (exception)
967 *exception = walker.fault;
974 * Using the cached information from sp->gfns is safe because:
975 * - The spte has a reference to the struct page, so the pfn for a given gfn
976 * can't change unless all sptes pointing to it are nuked first.
979 * We should flush all tlbs if spte is dropped even though guest is
980 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
981 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
982 * used by guest then tlbs are not flushed, so guest is allowed to access the
984 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
986 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
988 int i, nr_present = 0;
992 /* direct kvm_mmu_page can not be unsync. */
993 BUG_ON(sp->role.direct);
995 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
997 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1006 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1008 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1009 sizeof(pt_element_t)))
1012 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1014 * Update spte before increasing tlbs_dirty to make
1015 * sure no tlb flush is lost after spte is zapped; see
1016 * the comments in kvm_flush_remote_tlbs().
1019 vcpu->kvm->tlbs_dirty++;
1023 gfn = gpte_to_gfn(gpte);
1024 pte_access = sp->role.access;
1025 pte_access &= FNAME(gpte_access)(vcpu, gpte);
1026 FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte);
1028 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1032 if (gfn != sp->gfns[i]) {
1033 drop_spte(vcpu->kvm, &sp->spt[i]);
1035 * The same as above where we are doing
1036 * prefetch_invalid_gpte().
1039 vcpu->kvm->tlbs_dirty++;
1045 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1047 set_spte(vcpu, &sp->spt[i], pte_access,
1048 PT_PAGE_TABLE_LEVEL, gfn,
1049 spte_to_pfn(sp->spt[i]), true, false,
1059 #undef PT_BASE_ADDR_MASK
1061 #undef PT_LVL_ADDR_MASK
1062 #undef PT_LVL_OFFSET_MASK
1063 #undef PT_LEVEL_BITS
1064 #undef PT_MAX_FULL_LEVELS
1066 #undef gpte_to_gfn_lvl
1068 #undef PT_GUEST_ACCESSED_MASK
1069 #undef PT_GUEST_DIRTY_MASK
1070 #undef PT_GUEST_DIRTY_SHIFT
1071 #undef PT_GUEST_ACCESSED_SHIFT
1072 #undef PT_HAVE_ACCESSED_DIRTY