1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_MMU_H
3 #define __KVM_X86_MMU_H
5 #include <linux/kvm_host.h>
6 #include "kvm_cache_regs.h"
10 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
11 #define PT32_PT_BITS 10
12 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
14 #define PT_WRITABLE_SHIFT 1
15 #define PT_USER_SHIFT 2
17 #define PT_PRESENT_MASK (1ULL << 0)
18 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
19 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
20 #define PT_PWT_MASK (1ULL << 3)
21 #define PT_PCD_MASK (1ULL << 4)
22 #define PT_ACCESSED_SHIFT 5
23 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
24 #define PT_DIRTY_SHIFT 6
25 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
26 #define PT_PAGE_SIZE_SHIFT 7
27 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
28 #define PT_PAT_MASK (1ULL << 7)
29 #define PT_GLOBAL_MASK (1ULL << 8)
30 #define PT64_NX_SHIFT 63
31 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
33 #define PT_PAT_SHIFT 7
34 #define PT_DIR_PAT_SHIFT 12
35 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
37 #define PT32_DIR_PSE36_SIZE 4
38 #define PT32_DIR_PSE36_SHIFT 13
39 #define PT32_DIR_PSE36_MASK \
40 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
42 #define PT64_ROOT_5LEVEL 5
43 #define PT64_ROOT_4LEVEL 4
44 #define PT32_ROOT_LEVEL 2
45 #define PT32E_ROOT_LEVEL 3
47 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
48 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
50 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
51 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
53 static __always_inline u64 rsvd_bits(int s, int e)
55 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
57 if (__builtin_constant_p(e))
65 return ((2ULL << (e - s)) - 1) << s;
69 * The number of non-reserved physical address bits irrespective of features
70 * that repurpose legal bits, e.g. MKTME.
72 extern u8 __read_mostly shadow_phys_bits;
74 static inline gfn_t kvm_mmu_max_gfn(void)
77 * Note that this uses the host MAXPHYADDR, not the guest's.
78 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
79 * assuming KVM is running on bare metal, guest accesses beyond
80 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
81 * (either EPT Violation/Misconfig or #NPF), and so KVM will never
82 * install a SPTE for such addresses. If KVM is running as a VM
83 * itself, on the other hand, it might see a MAXPHYADDR that is less
84 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
85 * disallows such SPTEs entirely and simplifies the TDP MMU.
87 int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52;
89 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
92 static inline u8 kvm_get_shadow_phys_bits(void)
95 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
96 * in CPU detection code, but the processor treats those reduced bits as
97 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
98 * the physical address bits reported by CPUID.
100 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
101 return cpuid_eax(0x80000008) & 0xff;
104 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
105 * custom CPUID. Proceed with whatever the kernel found since these features
106 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
108 return boot_cpu_data.x86_phys_bits;
111 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
112 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
113 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
115 void kvm_init_mmu(struct kvm_vcpu *vcpu);
116 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
117 unsigned long cr4, u64 efer, gpa_t nested_cr3);
118 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
119 int huge_page_level, bool accessed_dirty,
121 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
122 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
123 u64 fault_address, char *insn, int insn_len);
125 int kvm_mmu_load(struct kvm_vcpu *vcpu);
126 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
127 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
128 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
129 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
131 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
133 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
136 return kvm_mmu_load(vcpu);
139 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
141 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
143 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
144 ? cr3 & X86_CR3_PCID_MASK
148 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
150 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
153 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
155 u64 root_hpa = vcpu->arch.mmu->root.hpa;
157 if (!VALID_PAGE(root_hpa))
160 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
161 vcpu->arch.mmu->root_role.level);
165 * Check if a given access (described through the I/D, W/R and U/S bits of a
166 * page fault error code pfec) causes a permission fault with the given PTE
167 * access rights (in ACC_* format).
169 * Return zero if the access does not fault; return the page fault error code
170 * if the access faults.
172 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
173 unsigned pte_access, unsigned pte_pkey,
176 /* strip nested paging fault error codes */
177 unsigned int pfec = access;
178 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
181 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
182 * For implicit supervisor accesses, SMAP cannot be overridden.
184 * SMAP works on supervisor accesses only, and not_smap can
185 * be set or not set when user access with neither has any bearing
188 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
189 * this bit will always be zero in pfec, but it will be one in index
190 * if SMAP checks are being disabled.
192 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
193 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
194 int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1;
195 bool fault = (mmu->permissions[index] >> pte_access) & 1;
196 u32 errcode = PFERR_PRESENT_MASK;
198 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
199 if (unlikely(mmu->pkru_mask)) {
200 u32 pkru_bits, offset;
203 * PKRU defines 32 bits, there are 16 domains and 2
204 * attribute bits per domain in pkru. pte_pkey is the
205 * index of the protection domain, so pte_pkey * 2 is
206 * is the index of the first bit for the domain.
208 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
210 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
211 offset = (pfec & ~1) +
212 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
214 pkru_bits &= mmu->pkru_mask >> offset;
215 errcode |= -pkru_bits & PFERR_PK_MASK;
216 fault |= (pkru_bits != 0);
219 return -(u32)fault & errcode;
222 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
224 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
226 int kvm_mmu_post_init_vm(struct kvm *kvm);
227 void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
229 static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
232 * Read shadow_root_allocated before related pointers. Hence, threads
233 * reading shadow_root_allocated in any lock context are guaranteed to
234 * see the pointers. Pairs with smp_store_release in
235 * mmu_first_shadow_root_alloc.
237 return smp_load_acquire(&kvm->arch.shadow_root_allocated);
241 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; }
243 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; }
246 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
248 return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm);
251 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
253 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
254 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
255 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
258 static inline unsigned long
259 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
262 return gfn_to_index(slot->base_gfn + npages - 1,
263 slot->base_gfn, level) + 1;
266 static inline unsigned long
267 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
269 return __kvm_mmu_slot_lpages(slot, slot->npages, level);
272 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
274 atomic64_add(count, &kvm->stat.pages[level - 1]);
277 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
278 struct x86_exception *exception);
280 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
282 gpa_t gpa, u64 access,
283 struct x86_exception *exception)
285 if (mmu != &vcpu->arch.nested_mmu)
287 return translate_nested_gpa(vcpu, gpa, access, exception);