1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
58 extern bool itlb_multihit_kvm_mitigation;
60 int __read_mostly nx_huge_pages = -1;
61 #ifdef CONFIG_PREEMPT_RT
62 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
65 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
68 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
69 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
71 static const struct kernel_param_ops nx_huge_pages_ops = {
72 .set = set_nx_huge_pages,
73 .get = param_get_bool,
76 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
77 .set = set_nx_huge_pages_recovery_ratio,
78 .get = param_get_uint,
81 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
83 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
84 &nx_huge_pages_recovery_ratio, 0644);
85 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
87 static bool __read_mostly force_flush_and_sync_on_reuse;
88 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
91 * When setting this variable to true it enables Two-Dimensional-Paging
92 * where the hardware walks 2 page tables:
93 * 1. the guest-virtual to guest-physical
94 * 2. while doing 1. it walks guest-physical to host-physical
95 * If the hardware supports that we don't need to do shadow paging.
97 bool tdp_enabled = false;
99 static int max_huge_page_level __read_mostly;
100 static int tdp_root_level __read_mostly;
101 static int max_tdp_level __read_mostly;
104 AUDIT_PRE_PAGE_FAULT,
105 AUDIT_POST_PAGE_FAULT,
107 AUDIT_POST_PTE_WRITE,
114 module_param(dbg, bool, 0644);
117 #define PTE_PREFETCH_NUM 8
119 #define PT32_LEVEL_BITS 10
121 #define PT32_LEVEL_SHIFT(level) \
122 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
124 #define PT32_LVL_OFFSET_MASK(level) \
125 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT32_LEVEL_BITS))) - 1))
128 #define PT32_INDEX(address, level)\
129 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
132 #define PT32_BASE_ADDR_MASK PAGE_MASK
133 #define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
135 #define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
139 #include <trace/events/kvm.h>
141 /* make pte_list_desc fit well in cache lines */
142 #define PTE_LIST_EXT 14
145 * Slight optimization of cacheline layout, by putting `more' and `spte_count'
146 * at the start; then accessing it will only use one single cacheline for
147 * either full (entries==PTE_LIST_EXT) case or entries<=6.
149 struct pte_list_desc {
150 struct pte_list_desc *more;
152 * Stores number of entries stored in the pte_list_desc. No need to be
153 * u64 but just for easier alignment. When PTE_LIST_EXT, means full.
156 u64 *sptes[PTE_LIST_EXT];
159 struct kvm_shadow_walk_iterator {
167 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
168 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
170 shadow_walk_okay(&(_walker)); \
171 shadow_walk_next(&(_walker)))
173 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
174 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
175 shadow_walk_okay(&(_walker)); \
176 shadow_walk_next(&(_walker)))
178 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
179 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
180 shadow_walk_okay(&(_walker)) && \
181 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
182 __shadow_walk_next(&(_walker), spte))
184 static struct kmem_cache *pte_list_desc_cache;
185 struct kmem_cache *mmu_page_header_cache;
186 static struct percpu_counter kvm_total_used_mmu_pages;
188 static void mmu_spte_set(u64 *sptep, u64 spte);
189 static union kvm_mmu_page_role
190 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
192 struct kvm_mmu_role_regs {
193 const unsigned long cr0;
194 const unsigned long cr4;
198 #define CREATE_TRACE_POINTS
199 #include "mmutrace.h"
202 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
203 * reading from the role_regs. Once the mmu_role is constructed, it becomes
204 * the single source of truth for the MMU's state.
206 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
207 static inline bool __maybe_unused ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
209 return !!(regs->reg & flag); \
211 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
212 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
213 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
214 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
215 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
216 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
217 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
218 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
219 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
220 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
223 * The MMU itself (with a valid role) is the single source of truth for the
224 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
225 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
226 * and the vCPU may be incorrect/irrelevant.
228 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
229 static inline bool __maybe_unused is_##reg##_##name(struct kvm_mmu *mmu) \
231 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
233 BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
234 BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
235 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
236 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
237 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
238 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
239 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
240 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
241 BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
243 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
245 struct kvm_mmu_role_regs regs = {
246 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
247 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
248 .efer = vcpu->arch.efer,
254 static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs)
256 if (!____is_cr0_pg(regs))
258 else if (____is_efer_lma(regs))
259 return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
261 else if (____is_cr4_pae(regs))
262 return PT32E_ROOT_LEVEL;
264 return PT32_ROOT_LEVEL;
267 static inline bool kvm_available_flush_tlb_with_range(void)
269 return kvm_x86_ops.tlb_remote_flush_with_range;
272 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
273 struct kvm_tlb_range *range)
277 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
278 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
281 kvm_flush_remote_tlbs(kvm);
284 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
285 u64 start_gfn, u64 pages)
287 struct kvm_tlb_range range;
289 range.start_gfn = start_gfn;
292 kvm_flush_remote_tlbs_with_range(kvm, &range);
295 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
298 u64 spte = make_mmio_spte(vcpu, gfn, access);
300 trace_mark_mmio_spte(sptep, gfn, spte);
301 mmu_spte_set(sptep, spte);
304 static gfn_t get_mmio_spte_gfn(u64 spte)
306 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
308 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
309 & shadow_nonpresent_or_rsvd_mask;
311 return gpa >> PAGE_SHIFT;
314 static unsigned get_mmio_spte_access(u64 spte)
316 return spte & shadow_mmio_access_mask;
319 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
321 u64 kvm_gen, spte_gen, gen;
323 gen = kvm_vcpu_memslots(vcpu)->generation;
324 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
327 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
328 spte_gen = get_mmio_spte_generation(spte);
330 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
331 return likely(kvm_gen == spte_gen);
334 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
335 struct x86_exception *exception)
340 static int is_cpuid_PSE36(void)
345 static gfn_t pse36_gfn_delta(u32 gpte)
347 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
349 return (gpte & PT32_DIR_PSE36_MASK) << shift;
353 static void __set_spte(u64 *sptep, u64 spte)
355 WRITE_ONCE(*sptep, spte);
358 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
360 WRITE_ONCE(*sptep, spte);
363 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
365 return xchg(sptep, spte);
368 static u64 __get_spte_lockless(u64 *sptep)
370 return READ_ONCE(*sptep);
381 static void count_spte_clear(u64 *sptep, u64 spte)
383 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
385 if (is_shadow_present_pte(spte))
388 /* Ensure the spte is completely set before we increase the count */
390 sp->clear_spte_count++;
393 static void __set_spte(u64 *sptep, u64 spte)
395 union split_spte *ssptep, sspte;
397 ssptep = (union split_spte *)sptep;
398 sspte = (union split_spte)spte;
400 ssptep->spte_high = sspte.spte_high;
403 * If we map the spte from nonpresent to present, We should store
404 * the high bits firstly, then set present bit, so cpu can not
405 * fetch this spte while we are setting the spte.
409 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
412 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
414 union split_spte *ssptep, sspte;
416 ssptep = (union split_spte *)sptep;
417 sspte = (union split_spte)spte;
419 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
422 * If we map the spte from present to nonpresent, we should clear
423 * present bit firstly to avoid vcpu fetch the old high bits.
427 ssptep->spte_high = sspte.spte_high;
428 count_spte_clear(sptep, spte);
431 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
433 union split_spte *ssptep, sspte, orig;
435 ssptep = (union split_spte *)sptep;
436 sspte = (union split_spte)spte;
438 /* xchg acts as a barrier before the setting of the high bits */
439 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
440 orig.spte_high = ssptep->spte_high;
441 ssptep->spte_high = sspte.spte_high;
442 count_spte_clear(sptep, spte);
448 * The idea using the light way get the spte on x86_32 guest is from
449 * gup_get_pte (mm/gup.c).
451 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
452 * coalesces them and we are running out of the MMU lock. Therefore
453 * we need to protect against in-progress updates of the spte.
455 * Reading the spte while an update is in progress may get the old value
456 * for the high part of the spte. The race is fine for a present->non-present
457 * change (because the high part of the spte is ignored for non-present spte),
458 * but for a present->present change we must reread the spte.
460 * All such changes are done in two steps (present->non-present and
461 * non-present->present), hence it is enough to count the number of
462 * present->non-present updates: if it changed while reading the spte,
463 * we might have hit the race. This is done using clear_spte_count.
465 static u64 __get_spte_lockless(u64 *sptep)
467 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
468 union split_spte spte, *orig = (union split_spte *)sptep;
472 count = sp->clear_spte_count;
475 spte.spte_low = orig->spte_low;
478 spte.spte_high = orig->spte_high;
481 if (unlikely(spte.spte_low != orig->spte_low ||
482 count != sp->clear_spte_count))
489 static bool spte_has_volatile_bits(u64 spte)
491 if (!is_shadow_present_pte(spte))
495 * Always atomically update spte if it can be updated
496 * out of mmu-lock, it can ensure dirty bit is not lost,
497 * also, it can help us to get a stable is_writable_pte()
498 * to ensure tlb flush is not missed.
500 if (spte_can_locklessly_be_made_writable(spte) ||
501 is_access_track_spte(spte))
504 if (spte_ad_enabled(spte)) {
505 if ((spte & shadow_accessed_mask) == 0 ||
506 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
513 /* Rules for using mmu_spte_set:
514 * Set the sptep from nonpresent to present.
515 * Note: the sptep being assigned *must* be either not present
516 * or in a state where the hardware will not attempt to update
519 static void mmu_spte_set(u64 *sptep, u64 new_spte)
521 WARN_ON(is_shadow_present_pte(*sptep));
522 __set_spte(sptep, new_spte);
526 * Update the SPTE (excluding the PFN), but do not track changes in its
527 * accessed/dirty status.
529 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
531 u64 old_spte = *sptep;
533 WARN_ON(!is_shadow_present_pte(new_spte));
535 if (!is_shadow_present_pte(old_spte)) {
536 mmu_spte_set(sptep, new_spte);
540 if (!spte_has_volatile_bits(old_spte))
541 __update_clear_spte_fast(sptep, new_spte);
543 old_spte = __update_clear_spte_slow(sptep, new_spte);
545 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
550 /* Rules for using mmu_spte_update:
551 * Update the state bits, it means the mapped pfn is not changed.
553 * Whenever we overwrite a writable spte with a read-only one we
554 * should flush remote TLBs. Otherwise rmap_write_protect
555 * will find a read-only spte, even though the writable spte
556 * might be cached on a CPU's TLB, the return value indicates this
559 * Returns true if the TLB needs to be flushed
561 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
564 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
566 if (!is_shadow_present_pte(old_spte))
570 * For the spte updated out of mmu-lock is safe, since
571 * we always atomically update it, see the comments in
572 * spte_has_volatile_bits().
574 if (spte_can_locklessly_be_made_writable(old_spte) &&
575 !is_writable_pte(new_spte))
579 * Flush TLB when accessed/dirty states are changed in the page tables,
580 * to guarantee consistency between TLB and page tables.
583 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
585 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
588 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
590 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
597 * Rules for using mmu_spte_clear_track_bits:
598 * It sets the sptep from present to nonpresent, and track the
599 * state bits, it is used to clear the last level sptep.
600 * Returns the old PTE.
602 static int mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
605 u64 old_spte = *sptep;
606 int level = sptep_to_sp(sptep)->role.level;
608 if (!spte_has_volatile_bits(old_spte))
609 __update_clear_spte_fast(sptep, 0ull);
611 old_spte = __update_clear_spte_slow(sptep, 0ull);
613 if (!is_shadow_present_pte(old_spte))
616 kvm_update_page_stats(kvm, level, -1);
618 pfn = spte_to_pfn(old_spte);
621 * KVM does not hold the refcount of the page used by
622 * kvm mmu, before reclaiming the page, we should
623 * unmap it from mmu first.
625 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
627 if (is_accessed_spte(old_spte))
628 kvm_set_pfn_accessed(pfn);
630 if (is_dirty_spte(old_spte))
631 kvm_set_pfn_dirty(pfn);
637 * Rules for using mmu_spte_clear_no_track:
638 * Directly clear spte without caring the state bits of sptep,
639 * it is used to set the upper level spte.
641 static void mmu_spte_clear_no_track(u64 *sptep)
643 __update_clear_spte_fast(sptep, 0ull);
646 static u64 mmu_spte_get_lockless(u64 *sptep)
648 return __get_spte_lockless(sptep);
651 /* Restore an acc-track PTE back to a regular PTE */
652 static u64 restore_acc_track_spte(u64 spte)
655 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
656 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
658 WARN_ON_ONCE(spte_ad_enabled(spte));
659 WARN_ON_ONCE(!is_access_track_spte(spte));
661 new_spte &= ~shadow_acc_track_mask;
662 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
663 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
664 new_spte |= saved_bits;
669 /* Returns the Accessed status of the PTE and resets it at the same time. */
670 static bool mmu_spte_age(u64 *sptep)
672 u64 spte = mmu_spte_get_lockless(sptep);
674 if (!is_accessed_spte(spte))
677 if (spte_ad_enabled(spte)) {
678 clear_bit((ffs(shadow_accessed_mask) - 1),
679 (unsigned long *)sptep);
682 * Capture the dirty status of the page, so that it doesn't get
683 * lost when the SPTE is marked for access tracking.
685 if (is_writable_pte(spte))
686 kvm_set_pfn_dirty(spte_to_pfn(spte));
688 spte = mark_spte_for_access_track(spte);
689 mmu_spte_update_no_track(sptep, spte);
695 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
697 if (is_tdp_mmu(vcpu->arch.mmu)) {
698 kvm_tdp_mmu_walk_lockless_begin();
701 * Prevent page table teardown by making any free-er wait during
702 * kvm_flush_remote_tlbs() IPI to all active vcpus.
707 * Make sure a following spte read is not reordered ahead of the write
710 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
714 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
716 if (is_tdp_mmu(vcpu->arch.mmu)) {
717 kvm_tdp_mmu_walk_lockless_end();
720 * Make sure the write to vcpu->mode is not reordered in front of
721 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
722 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
724 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
729 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
733 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
734 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
735 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
738 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
739 PT64_ROOT_MAX_LEVEL);
742 if (maybe_indirect) {
743 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
744 PT64_ROOT_MAX_LEVEL);
748 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
749 PT64_ROOT_MAX_LEVEL);
752 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
754 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
755 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
756 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
757 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
760 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
762 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
765 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
767 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
770 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
772 if (!sp->role.direct)
773 return sp->gfns[index];
775 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
778 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
780 if (!sp->role.direct) {
781 sp->gfns[index] = gfn;
785 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
786 pr_err_ratelimited("gfn mismatch under direct page %llx "
787 "(expected %llx, got %llx)\n",
789 kvm_mmu_page_get_gfn(sp, index), gfn);
793 * Return the pointer to the large page information for a given gfn,
794 * handling slots that are not large page aligned.
796 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
797 const struct kvm_memory_slot *slot, int level)
801 idx = gfn_to_index(gfn, slot->base_gfn, level);
802 return &slot->arch.lpage_info[level - 2][idx];
805 static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot *slot,
806 gfn_t gfn, int count)
808 struct kvm_lpage_info *linfo;
811 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
812 linfo = lpage_info_slot(gfn, slot, i);
813 linfo->disallow_lpage += count;
814 WARN_ON(linfo->disallow_lpage < 0);
818 void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
820 update_gfn_disallow_lpage_count(slot, gfn, 1);
823 void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
825 update_gfn_disallow_lpage_count(slot, gfn, -1);
828 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
830 struct kvm_memslots *slots;
831 struct kvm_memory_slot *slot;
834 kvm->arch.indirect_shadow_pages++;
836 slots = kvm_memslots_for_spte_role(kvm, sp->role);
837 slot = __gfn_to_memslot(slots, gfn);
839 /* the non-leaf shadow pages are keeping readonly. */
840 if (sp->role.level > PG_LEVEL_4K)
841 return kvm_slot_page_track_add_page(kvm, slot, gfn,
842 KVM_PAGE_TRACK_WRITE);
844 kvm_mmu_gfn_disallow_lpage(slot, gfn);
847 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
849 if (sp->lpage_disallowed)
852 ++kvm->stat.nx_lpage_splits;
853 list_add_tail(&sp->lpage_disallowed_link,
854 &kvm->arch.lpage_disallowed_mmu_pages);
855 sp->lpage_disallowed = true;
858 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
860 struct kvm_memslots *slots;
861 struct kvm_memory_slot *slot;
864 kvm->arch.indirect_shadow_pages--;
866 slots = kvm_memslots_for_spte_role(kvm, sp->role);
867 slot = __gfn_to_memslot(slots, gfn);
868 if (sp->role.level > PG_LEVEL_4K)
869 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
870 KVM_PAGE_TRACK_WRITE);
872 kvm_mmu_gfn_allow_lpage(slot, gfn);
875 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
877 --kvm->stat.nx_lpage_splits;
878 sp->lpage_disallowed = false;
879 list_del(&sp->lpage_disallowed_link);
882 static struct kvm_memory_slot *
883 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
886 struct kvm_memory_slot *slot;
888 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
889 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
891 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
898 * About rmap_head encoding:
900 * If the bit zero of rmap_head->val is clear, then it points to the only spte
901 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
902 * pte_list_desc containing more mappings.
906 * Returns the number of pointers in the rmap chain, not counting the new one.
908 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
909 struct kvm_rmap_head *rmap_head)
911 struct pte_list_desc *desc;
914 if (!rmap_head->val) {
915 rmap_printk("%p %llx 0->1\n", spte, *spte);
916 rmap_head->val = (unsigned long)spte;
917 } else if (!(rmap_head->val & 1)) {
918 rmap_printk("%p %llx 1->many\n", spte, *spte);
919 desc = mmu_alloc_pte_list_desc(vcpu);
920 desc->sptes[0] = (u64 *)rmap_head->val;
921 desc->sptes[1] = spte;
922 desc->spte_count = 2;
923 rmap_head->val = (unsigned long)desc | 1;
926 rmap_printk("%p %llx many->many\n", spte, *spte);
927 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
928 while (desc->spte_count == PTE_LIST_EXT) {
929 count += PTE_LIST_EXT;
931 desc->more = mmu_alloc_pte_list_desc(vcpu);
933 desc->spte_count = 0;
938 count += desc->spte_count;
939 desc->sptes[desc->spte_count++] = spte;
945 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
946 struct pte_list_desc *desc, int i,
947 struct pte_list_desc *prev_desc)
949 int j = desc->spte_count - 1;
951 desc->sptes[i] = desc->sptes[j];
952 desc->sptes[j] = NULL;
954 if (desc->spte_count)
956 if (!prev_desc && !desc->more)
960 prev_desc->more = desc->more;
962 rmap_head->val = (unsigned long)desc->more | 1;
963 mmu_free_pte_list_desc(desc);
966 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
968 struct pte_list_desc *desc;
969 struct pte_list_desc *prev_desc;
972 if (!rmap_head->val) {
973 pr_err("%s: %p 0->BUG\n", __func__, spte);
975 } else if (!(rmap_head->val & 1)) {
976 rmap_printk("%p 1->0\n", spte);
977 if ((u64 *)rmap_head->val != spte) {
978 pr_err("%s: %p 1->BUG\n", __func__, spte);
983 rmap_printk("%p many->many\n", spte);
984 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
987 for (i = 0; i < desc->spte_count; ++i) {
988 if (desc->sptes[i] == spte) {
989 pte_list_desc_remove_entry(rmap_head,
997 pr_err("%s: %p many->many\n", __func__, spte);
1002 static void pte_list_remove(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1005 mmu_spte_clear_track_bits(kvm, sptep);
1006 __pte_list_remove(sptep, rmap_head);
1009 /* Return true if rmap existed, false otherwise */
1010 static bool pte_list_destroy(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1012 struct pte_list_desc *desc, *next;
1015 if (!rmap_head->val)
1018 if (!(rmap_head->val & 1)) {
1019 mmu_spte_clear_track_bits(kvm, (u64 *)rmap_head->val);
1023 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1025 for (; desc; desc = next) {
1026 for (i = 0; i < desc->spte_count; i++)
1027 mmu_spte_clear_track_bits(kvm, desc->sptes[i]);
1029 mmu_free_pte_list_desc(desc);
1032 /* rmap_head is meaningless now, remember to reset it */
1037 unsigned int pte_list_count(struct kvm_rmap_head *rmap_head)
1039 struct pte_list_desc *desc;
1040 unsigned int count = 0;
1042 if (!rmap_head->val)
1044 else if (!(rmap_head->val & 1))
1047 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1050 count += desc->spte_count;
1057 static struct kvm_rmap_head *gfn_to_rmap(gfn_t gfn, int level,
1058 const struct kvm_memory_slot *slot)
1062 idx = gfn_to_index(gfn, slot->base_gfn, level);
1063 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
1066 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1068 struct kvm_mmu_memory_cache *mc;
1070 mc = &vcpu->arch.mmu_pte_list_desc_cache;
1071 return kvm_mmu_memory_cache_nr_free_objects(mc);
1074 static void rmap_remove(struct kvm *kvm, u64 *spte)
1076 struct kvm_memslots *slots;
1077 struct kvm_memory_slot *slot;
1078 struct kvm_mmu_page *sp;
1080 struct kvm_rmap_head *rmap_head;
1082 sp = sptep_to_sp(spte);
1083 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1086 * Unlike rmap_add, rmap_remove does not run in the context of a vCPU
1087 * so we have to determine which memslots to use based on context
1088 * information in sp->role.
1090 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1092 slot = __gfn_to_memslot(slots, gfn);
1093 rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
1095 __pte_list_remove(spte, rmap_head);
1099 * Used by the following functions to iterate through the sptes linked by a
1100 * rmap. All fields are private and not assumed to be used outside.
1102 struct rmap_iterator {
1103 /* private fields */
1104 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1105 int pos; /* index of the sptep */
1109 * Iteration must be started by this function. This should also be used after
1110 * removing/dropping sptes from the rmap link because in such cases the
1111 * information in the iterator may not be valid.
1113 * Returns sptep if found, NULL otherwise.
1115 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1116 struct rmap_iterator *iter)
1120 if (!rmap_head->val)
1123 if (!(rmap_head->val & 1)) {
1125 sptep = (u64 *)rmap_head->val;
1129 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1131 sptep = iter->desc->sptes[iter->pos];
1133 BUG_ON(!is_shadow_present_pte(*sptep));
1138 * Must be used with a valid iterator: e.g. after rmap_get_first().
1140 * Returns sptep if found, NULL otherwise.
1142 static u64 *rmap_get_next(struct rmap_iterator *iter)
1147 if (iter->pos < PTE_LIST_EXT - 1) {
1149 sptep = iter->desc->sptes[iter->pos];
1154 iter->desc = iter->desc->more;
1158 /* desc->sptes[0] cannot be NULL */
1159 sptep = iter->desc->sptes[iter->pos];
1166 BUG_ON(!is_shadow_present_pte(*sptep));
1170 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1171 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1172 _spte_; _spte_ = rmap_get_next(_iter_))
1174 static void drop_spte(struct kvm *kvm, u64 *sptep)
1176 u64 old_spte = mmu_spte_clear_track_bits(kvm, sptep);
1178 if (is_shadow_present_pte(old_spte))
1179 rmap_remove(kvm, sptep);
1183 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1185 if (is_large_pte(*sptep)) {
1186 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1187 drop_spte(kvm, sptep);
1194 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1196 if (__drop_large_spte(vcpu->kvm, sptep)) {
1197 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1199 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1200 KVM_PAGES_PER_HPAGE(sp->role.level));
1205 * Write-protect on the specified @sptep, @pt_protect indicates whether
1206 * spte write-protection is caused by protecting shadow page table.
1208 * Note: write protection is difference between dirty logging and spte
1210 * - for dirty logging, the spte can be set to writable at anytime if
1211 * its dirty bitmap is properly set.
1212 * - for spte protection, the spte can be writable only after unsync-ing
1215 * Return true if tlb need be flushed.
1217 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1221 if (!is_writable_pte(spte) &&
1222 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1225 rmap_printk("spte %p %llx\n", sptep, *sptep);
1228 spte &= ~shadow_mmu_writable_mask;
1229 spte = spte & ~PT_WRITABLE_MASK;
1231 return mmu_spte_update(sptep, spte);
1234 static bool __rmap_write_protect(struct kvm *kvm,
1235 struct kvm_rmap_head *rmap_head,
1239 struct rmap_iterator iter;
1242 for_each_rmap_spte(rmap_head, &iter, sptep)
1243 flush |= spte_write_protect(sptep, pt_protect);
1248 static bool spte_clear_dirty(u64 *sptep)
1252 rmap_printk("spte %p %llx\n", sptep, *sptep);
1254 MMU_WARN_ON(!spte_ad_enabled(spte));
1255 spte &= ~shadow_dirty_mask;
1256 return mmu_spte_update(sptep, spte);
1259 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1261 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1262 (unsigned long *)sptep);
1263 if (was_writable && !spte_ad_enabled(*sptep))
1264 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1266 return was_writable;
1270 * Gets the GFN ready for another round of dirty logging by clearing the
1271 * - D bit on ad-enabled SPTEs, and
1272 * - W bit on ad-disabled SPTEs.
1273 * Returns true iff any D or W bits were cleared.
1275 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1276 const struct kvm_memory_slot *slot)
1279 struct rmap_iterator iter;
1282 for_each_rmap_spte(rmap_head, &iter, sptep)
1283 if (spte_ad_need_write_protect(*sptep))
1284 flush |= spte_wrprot_for_clear_dirty(sptep);
1286 flush |= spte_clear_dirty(sptep);
1292 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1293 * @kvm: kvm instance
1294 * @slot: slot to protect
1295 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1296 * @mask: indicates which pages we should protect
1298 * Used when we do not need to care about huge page mappings.
1300 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1301 struct kvm_memory_slot *slot,
1302 gfn_t gfn_offset, unsigned long mask)
1304 struct kvm_rmap_head *rmap_head;
1306 if (is_tdp_mmu_enabled(kvm))
1307 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1308 slot->base_gfn + gfn_offset, mask, true);
1310 if (!kvm_memslots_have_rmaps(kvm))
1314 rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1316 __rmap_write_protect(kvm, rmap_head, false);
1318 /* clear the first set bit */
1324 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1325 * protect the page if the D-bit isn't supported.
1326 * @kvm: kvm instance
1327 * @slot: slot to clear D-bit
1328 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1329 * @mask: indicates which pages we should clear D-bit
1331 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1333 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1334 struct kvm_memory_slot *slot,
1335 gfn_t gfn_offset, unsigned long mask)
1337 struct kvm_rmap_head *rmap_head;
1339 if (is_tdp_mmu_enabled(kvm))
1340 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1341 slot->base_gfn + gfn_offset, mask, false);
1343 if (!kvm_memslots_have_rmaps(kvm))
1347 rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1349 __rmap_clear_dirty(kvm, rmap_head, slot);
1351 /* clear the first set bit */
1357 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1360 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1361 * enable dirty logging for them.
1363 * We need to care about huge page mappings: e.g. during dirty logging we may
1364 * have such mappings.
1366 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1367 struct kvm_memory_slot *slot,
1368 gfn_t gfn_offset, unsigned long mask)
1371 * Huge pages are NOT write protected when we start dirty logging in
1372 * initially-all-set mode; must write protect them here so that they
1373 * are split to 4K on the first write.
1375 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1376 * of memslot has no such restriction, so the range can cross two large
1379 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1380 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1381 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1383 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1385 /* Cross two large pages? */
1386 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1387 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1388 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1392 /* Now handle 4K PTEs. */
1393 if (kvm_x86_ops.cpu_dirty_log_size)
1394 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1396 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1399 int kvm_cpu_dirty_log_size(void)
1401 return kvm_x86_ops.cpu_dirty_log_size;
1404 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1405 struct kvm_memory_slot *slot, u64 gfn,
1408 struct kvm_rmap_head *rmap_head;
1410 bool write_protected = false;
1412 if (kvm_memslots_have_rmaps(kvm)) {
1413 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1414 rmap_head = gfn_to_rmap(gfn, i, slot);
1415 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1419 if (is_tdp_mmu_enabled(kvm))
1421 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1423 return write_protected;
1426 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1428 struct kvm_memory_slot *slot;
1430 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1431 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1434 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1435 const struct kvm_memory_slot *slot)
1437 return pte_list_destroy(kvm, rmap_head);
1440 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1441 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1444 return kvm_zap_rmapp(kvm, rmap_head, slot);
1447 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1448 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1452 struct rmap_iterator iter;
1457 WARN_ON(pte_huge(pte));
1458 new_pfn = pte_pfn(pte);
1461 for_each_rmap_spte(rmap_head, &iter, sptep) {
1462 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1463 sptep, *sptep, gfn, level);
1467 if (pte_write(pte)) {
1468 pte_list_remove(kvm, rmap_head, sptep);
1471 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1474 mmu_spte_clear_track_bits(kvm, sptep);
1475 mmu_spte_set(sptep, new_spte);
1479 if (need_flush && kvm_available_flush_tlb_with_range()) {
1480 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1487 struct slot_rmap_walk_iterator {
1489 const struct kvm_memory_slot *slot;
1495 /* output fields. */
1497 struct kvm_rmap_head *rmap;
1500 /* private field. */
1501 struct kvm_rmap_head *end_rmap;
1505 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1507 iterator->level = level;
1508 iterator->gfn = iterator->start_gfn;
1509 iterator->rmap = gfn_to_rmap(iterator->gfn, level, iterator->slot);
1510 iterator->end_rmap = gfn_to_rmap(iterator->end_gfn, level, iterator->slot);
1514 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1515 const struct kvm_memory_slot *slot, int start_level,
1516 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1518 iterator->slot = slot;
1519 iterator->start_level = start_level;
1520 iterator->end_level = end_level;
1521 iterator->start_gfn = start_gfn;
1522 iterator->end_gfn = end_gfn;
1524 rmap_walk_init_level(iterator, iterator->start_level);
1527 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1529 return !!iterator->rmap;
1532 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1534 if (++iterator->rmap <= iterator->end_rmap) {
1535 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1539 if (++iterator->level > iterator->end_level) {
1540 iterator->rmap = NULL;
1544 rmap_walk_init_level(iterator, iterator->level);
1547 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1548 _start_gfn, _end_gfn, _iter_) \
1549 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1550 _end_level_, _start_gfn, _end_gfn); \
1551 slot_rmap_walk_okay(_iter_); \
1552 slot_rmap_walk_next(_iter_))
1554 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1555 struct kvm_memory_slot *slot, gfn_t gfn,
1556 int level, pte_t pte);
1558 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1559 struct kvm_gfn_range *range,
1560 rmap_handler_t handler)
1562 struct slot_rmap_walk_iterator iterator;
1565 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1566 range->start, range->end - 1, &iterator)
1567 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1568 iterator.level, range->pte);
1573 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1577 if (kvm_memslots_have_rmaps(kvm))
1578 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1580 if (is_tdp_mmu_enabled(kvm))
1581 flush = kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1586 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1590 if (kvm_memslots_have_rmaps(kvm))
1591 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1593 if (is_tdp_mmu_enabled(kvm))
1594 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1599 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1600 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1604 struct rmap_iterator iter;
1607 for_each_rmap_spte(rmap_head, &iter, sptep)
1608 young |= mmu_spte_age(sptep);
1613 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1614 struct kvm_memory_slot *slot, gfn_t gfn,
1615 int level, pte_t unused)
1618 struct rmap_iterator iter;
1620 for_each_rmap_spte(rmap_head, &iter, sptep)
1621 if (is_accessed_spte(*sptep))
1626 #define RMAP_RECYCLE_THRESHOLD 1000
1628 static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1630 struct kvm_memory_slot *slot;
1631 struct kvm_mmu_page *sp;
1632 struct kvm_rmap_head *rmap_head;
1635 sp = sptep_to_sp(spte);
1636 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1637 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1638 rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
1639 rmap_count = pte_list_add(vcpu, spte, rmap_head);
1641 if (rmap_count > RMAP_RECYCLE_THRESHOLD) {
1642 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1643 kvm_flush_remote_tlbs_with_address(
1644 vcpu->kvm, sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
1648 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1652 if (kvm_memslots_have_rmaps(kvm))
1653 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1655 if (is_tdp_mmu_enabled(kvm))
1656 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1661 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1665 if (kvm_memslots_have_rmaps(kvm))
1666 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1668 if (is_tdp_mmu_enabled(kvm))
1669 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1675 static int is_empty_shadow_page(u64 *spt)
1680 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1681 if (is_shadow_present_pte(*pos)) {
1682 printk(KERN_ERR "%s: %p %llx\n", __func__,
1691 * This value is the sum of all of the kvm instances's
1692 * kvm->arch.n_used_mmu_pages values. We need a global,
1693 * aggregate version in order to make the slab shrinker
1696 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr)
1698 kvm->arch.n_used_mmu_pages += nr;
1699 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1702 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1704 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1705 hlist_del(&sp->hash_link);
1706 list_del(&sp->link);
1707 free_page((unsigned long)sp->spt);
1708 if (!sp->role.direct)
1709 free_page((unsigned long)sp->gfns);
1710 kmem_cache_free(mmu_page_header_cache, sp);
1713 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1715 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1718 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1719 struct kvm_mmu_page *sp, u64 *parent_pte)
1724 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1727 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1730 __pte_list_remove(parent_pte, &sp->parent_ptes);
1733 static void drop_parent_pte(struct kvm_mmu_page *sp,
1736 mmu_page_remove_parent_pte(sp, parent_pte);
1737 mmu_spte_clear_no_track(parent_pte);
1740 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1742 struct kvm_mmu_page *sp;
1744 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1745 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1747 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1748 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1751 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1752 * depends on valid pages being added to the head of the list. See
1753 * comments in kvm_zap_obsolete_pages().
1755 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1756 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1757 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1761 static void mark_unsync(u64 *spte);
1762 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1765 struct rmap_iterator iter;
1767 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1772 static void mark_unsync(u64 *spte)
1774 struct kvm_mmu_page *sp;
1777 sp = sptep_to_sp(spte);
1778 index = spte - sp->spt;
1779 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1781 if (sp->unsync_children++)
1783 kvm_mmu_mark_parents_unsync(sp);
1786 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1787 struct kvm_mmu_page *sp)
1792 #define KVM_PAGE_ARRAY_NR 16
1794 struct kvm_mmu_pages {
1795 struct mmu_page_and_offset {
1796 struct kvm_mmu_page *sp;
1798 } page[KVM_PAGE_ARRAY_NR];
1802 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1808 for (i=0; i < pvec->nr; i++)
1809 if (pvec->page[i].sp == sp)
1812 pvec->page[pvec->nr].sp = sp;
1813 pvec->page[pvec->nr].idx = idx;
1815 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1818 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1820 --sp->unsync_children;
1821 WARN_ON((int)sp->unsync_children < 0);
1822 __clear_bit(idx, sp->unsync_child_bitmap);
1825 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1826 struct kvm_mmu_pages *pvec)
1828 int i, ret, nr_unsync_leaf = 0;
1830 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1831 struct kvm_mmu_page *child;
1832 u64 ent = sp->spt[i];
1834 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1835 clear_unsync_child_bit(sp, i);
1839 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1841 if (child->unsync_children) {
1842 if (mmu_pages_add(pvec, child, i))
1845 ret = __mmu_unsync_walk(child, pvec);
1847 clear_unsync_child_bit(sp, i);
1849 } else if (ret > 0) {
1850 nr_unsync_leaf += ret;
1853 } else if (child->unsync) {
1855 if (mmu_pages_add(pvec, child, i))
1858 clear_unsync_child_bit(sp, i);
1861 return nr_unsync_leaf;
1864 #define INVALID_INDEX (-1)
1866 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1867 struct kvm_mmu_pages *pvec)
1870 if (!sp->unsync_children)
1873 mmu_pages_add(pvec, sp, INVALID_INDEX);
1874 return __mmu_unsync_walk(sp, pvec);
1877 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1879 WARN_ON(!sp->unsync);
1880 trace_kvm_mmu_sync_page(sp);
1882 --kvm->stat.mmu_unsync;
1885 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1886 struct list_head *invalid_list);
1887 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1888 struct list_head *invalid_list);
1890 #define for_each_valid_sp(_kvm, _sp, _list) \
1891 hlist_for_each_entry(_sp, _list, hash_link) \
1892 if (is_obsolete_sp((_kvm), (_sp))) { \
1895 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1896 for_each_valid_sp(_kvm, _sp, \
1897 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1898 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1900 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1901 struct list_head *invalid_list)
1903 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1904 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1911 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1912 struct list_head *invalid_list,
1915 if (!remote_flush && list_empty(invalid_list))
1918 if (!list_empty(invalid_list))
1919 kvm_mmu_commit_zap_page(kvm, invalid_list);
1921 kvm_flush_remote_tlbs(kvm);
1925 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1926 struct list_head *invalid_list,
1927 bool remote_flush, bool local_flush)
1929 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1933 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1936 #ifdef CONFIG_KVM_MMU_AUDIT
1937 #include "mmu_audit.c"
1939 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1940 static void mmu_audit_disable(void) { }
1943 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1945 return sp->role.invalid ||
1946 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1949 struct mmu_page_path {
1950 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1951 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1954 #define for_each_sp(pvec, sp, parents, i) \
1955 for (i = mmu_pages_first(&pvec, &parents); \
1956 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1957 i = mmu_pages_next(&pvec, &parents, i))
1959 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1960 struct mmu_page_path *parents,
1965 for (n = i+1; n < pvec->nr; n++) {
1966 struct kvm_mmu_page *sp = pvec->page[n].sp;
1967 unsigned idx = pvec->page[n].idx;
1968 int level = sp->role.level;
1970 parents->idx[level-1] = idx;
1971 if (level == PG_LEVEL_4K)
1974 parents->parent[level-2] = sp;
1980 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1981 struct mmu_page_path *parents)
1983 struct kvm_mmu_page *sp;
1989 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1991 sp = pvec->page[0].sp;
1992 level = sp->role.level;
1993 WARN_ON(level == PG_LEVEL_4K);
1995 parents->parent[level-2] = sp;
1997 /* Also set up a sentinel. Further entries in pvec are all
1998 * children of sp, so this element is never overwritten.
2000 parents->parent[level-1] = NULL;
2001 return mmu_pages_next(pvec, parents, 0);
2004 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2006 struct kvm_mmu_page *sp;
2007 unsigned int level = 0;
2010 unsigned int idx = parents->idx[level];
2011 sp = parents->parent[level];
2015 WARN_ON(idx == INVALID_INDEX);
2016 clear_unsync_child_bit(sp, idx);
2018 } while (!sp->unsync_children);
2021 static int mmu_sync_children(struct kvm_vcpu *vcpu,
2022 struct kvm_mmu_page *parent, bool can_yield)
2025 struct kvm_mmu_page *sp;
2026 struct mmu_page_path parents;
2027 struct kvm_mmu_pages pages;
2028 LIST_HEAD(invalid_list);
2031 while (mmu_unsync_walk(parent, &pages)) {
2032 bool protected = false;
2034 for_each_sp(pages, sp, parents, i)
2035 protected |= rmap_write_protect(vcpu, sp->gfn);
2038 kvm_flush_remote_tlbs(vcpu->kvm);
2042 for_each_sp(pages, sp, parents, i) {
2043 kvm_unlink_unsync_page(vcpu->kvm, sp);
2044 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2045 mmu_pages_clear_parents(&parents);
2047 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
2048 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2050 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2054 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
2059 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2063 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2065 atomic_set(&sp->write_flooding_count, 0);
2068 static void clear_sp_write_flooding_count(u64 *spte)
2070 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2073 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2078 unsigned int access)
2080 bool direct_mmu = vcpu->arch.mmu->direct_map;
2081 union kvm_mmu_page_role role;
2082 struct hlist_head *sp_list;
2084 struct kvm_mmu_page *sp;
2086 LIST_HEAD(invalid_list);
2088 role = vcpu->arch.mmu->mmu_role.base;
2090 role.direct = direct;
2092 role.gpte_is_8_bytes = true;
2093 role.access = access;
2094 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2095 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2096 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2097 role.quadrant = quadrant;
2100 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2101 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2102 if (sp->gfn != gfn) {
2107 if (sp->role.word != role.word) {
2109 * If the guest is creating an upper-level page, zap
2110 * unsync pages for the same gfn. While it's possible
2111 * the guest is using recursive page tables, in all
2112 * likelihood the guest has stopped using the unsync
2113 * page and is installing a completely unrelated page.
2114 * Unsync pages must not be left as is, because the new
2115 * upper-level page will be write-protected.
2117 if (level > PG_LEVEL_4K && sp->unsync)
2118 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2124 goto trace_get_page;
2128 * The page is good, but is stale. kvm_sync_page does
2129 * get the latest guest state, but (unlike mmu_unsync_children)
2130 * it doesn't write-protect the page or mark it synchronized!
2131 * This way the validity of the mapping is ensured, but the
2132 * overhead of write protection is not incurred until the
2133 * guest invalidates the TLB mapping. This allows multiple
2134 * SPs for a single gfn to be unsync.
2136 * If the sync fails, the page is zapped. If so, break
2137 * in order to rebuild it.
2139 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2142 WARN_ON(!list_empty(&invalid_list));
2143 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2146 __clear_sp_write_flooding_count(sp);
2149 trace_kvm_mmu_get_page(sp, false);
2153 ++vcpu->kvm->stat.mmu_cache_miss;
2155 sp = kvm_mmu_alloc_page(vcpu, direct);
2159 hlist_add_head(&sp->hash_link, sp_list);
2161 account_shadowed(vcpu->kvm, sp);
2162 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2163 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2165 trace_kvm_mmu_get_page(sp, true);
2167 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2169 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2170 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2174 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2175 struct kvm_vcpu *vcpu, hpa_t root,
2178 iterator->addr = addr;
2179 iterator->shadow_addr = root;
2180 iterator->level = vcpu->arch.mmu->shadow_root_level;
2182 if (iterator->level >= PT64_ROOT_4LEVEL &&
2183 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2184 !vcpu->arch.mmu->direct_map)
2185 iterator->level = PT32E_ROOT_LEVEL;
2187 if (iterator->level == PT32E_ROOT_LEVEL) {
2189 * prev_root is currently only used for 64-bit hosts. So only
2190 * the active root_hpa is valid here.
2192 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2194 iterator->shadow_addr
2195 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2196 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2198 if (!iterator->shadow_addr)
2199 iterator->level = 0;
2203 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2204 struct kvm_vcpu *vcpu, u64 addr)
2206 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2210 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2212 if (iterator->level < PG_LEVEL_4K)
2215 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2216 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2220 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2223 if (is_last_spte(spte, iterator->level)) {
2224 iterator->level = 0;
2228 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2232 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2234 __shadow_walk_next(iterator, *iterator->sptep);
2237 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2238 struct kvm_mmu_page *sp)
2242 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2244 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2246 mmu_spte_set(sptep, spte);
2248 mmu_page_add_parent_pte(vcpu, sp, sptep);
2250 if (sp->unsync_children || sp->unsync)
2254 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2255 unsigned direct_access)
2257 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2258 struct kvm_mmu_page *child;
2261 * For the direct sp, if the guest pte's dirty bit
2262 * changed form clean to dirty, it will corrupt the
2263 * sp's access: allow writable in the read-only sp,
2264 * so we should update the spte at this point to get
2265 * a new sp with the correct access.
2267 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2268 if (child->role.access == direct_access)
2271 drop_parent_pte(child, sptep);
2272 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2276 /* Returns the number of zapped non-leaf child shadow pages. */
2277 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2278 u64 *spte, struct list_head *invalid_list)
2281 struct kvm_mmu_page *child;
2284 if (is_shadow_present_pte(pte)) {
2285 if (is_last_spte(pte, sp->role.level)) {
2286 drop_spte(kvm, spte);
2288 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2289 drop_parent_pte(child, spte);
2292 * Recursively zap nested TDP SPs, parentless SPs are
2293 * unlikely to be used again in the near future. This
2294 * avoids retaining a large number of stale nested SPs.
2296 if (tdp_enabled && invalid_list &&
2297 child->role.guest_mode && !child->parent_ptes.val)
2298 return kvm_mmu_prepare_zap_page(kvm, child,
2301 } else if (is_mmio_spte(pte)) {
2302 mmu_spte_clear_no_track(spte);
2307 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2308 struct kvm_mmu_page *sp,
2309 struct list_head *invalid_list)
2314 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2315 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2320 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2323 struct rmap_iterator iter;
2325 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2326 drop_parent_pte(sp, sptep);
2329 static int mmu_zap_unsync_children(struct kvm *kvm,
2330 struct kvm_mmu_page *parent,
2331 struct list_head *invalid_list)
2334 struct mmu_page_path parents;
2335 struct kvm_mmu_pages pages;
2337 if (parent->role.level == PG_LEVEL_4K)
2340 while (mmu_unsync_walk(parent, &pages)) {
2341 struct kvm_mmu_page *sp;
2343 for_each_sp(pages, sp, parents, i) {
2344 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2345 mmu_pages_clear_parents(&parents);
2353 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2354 struct kvm_mmu_page *sp,
2355 struct list_head *invalid_list,
2360 lockdep_assert_held_write(&kvm->mmu_lock);
2361 trace_kvm_mmu_prepare_zap_page(sp);
2362 ++kvm->stat.mmu_shadow_zapped;
2363 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2364 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2365 kvm_mmu_unlink_parents(kvm, sp);
2367 /* Zapping children means active_mmu_pages has become unstable. */
2368 list_unstable = *nr_zapped;
2370 if (!sp->role.invalid && !sp->role.direct)
2371 unaccount_shadowed(kvm, sp);
2374 kvm_unlink_unsync_page(kvm, sp);
2375 if (!sp->root_count) {
2380 * Already invalid pages (previously active roots) are not on
2381 * the active page list. See list_del() in the "else" case of
2384 if (sp->role.invalid)
2385 list_add(&sp->link, invalid_list);
2387 list_move(&sp->link, invalid_list);
2388 kvm_mod_used_mmu_pages(kvm, -1);
2391 * Remove the active root from the active page list, the root
2392 * will be explicitly freed when the root_count hits zero.
2394 list_del(&sp->link);
2397 * Obsolete pages cannot be used on any vCPUs, see the comment
2398 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2399 * treats invalid shadow pages as being obsolete.
2401 if (!is_obsolete_sp(kvm, sp))
2402 kvm_reload_remote_mmus(kvm);
2405 if (sp->lpage_disallowed)
2406 unaccount_huge_nx_page(kvm, sp);
2408 sp->role.invalid = 1;
2409 return list_unstable;
2412 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2413 struct list_head *invalid_list)
2417 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2421 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2422 struct list_head *invalid_list)
2424 struct kvm_mmu_page *sp, *nsp;
2426 if (list_empty(invalid_list))
2430 * We need to make sure everyone sees our modifications to
2431 * the page tables and see changes to vcpu->mode here. The barrier
2432 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2433 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2435 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2436 * guest mode and/or lockless shadow page table walks.
2438 kvm_flush_remote_tlbs(kvm);
2440 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2441 WARN_ON(!sp->role.invalid || sp->root_count);
2442 kvm_mmu_free_page(sp);
2446 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2447 unsigned long nr_to_zap)
2449 unsigned long total_zapped = 0;
2450 struct kvm_mmu_page *sp, *tmp;
2451 LIST_HEAD(invalid_list);
2455 if (list_empty(&kvm->arch.active_mmu_pages))
2459 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2461 * Don't zap active root pages, the page itself can't be freed
2462 * and zapping it will just force vCPUs to realloc and reload.
2467 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2469 total_zapped += nr_zapped;
2470 if (total_zapped >= nr_to_zap)
2477 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2479 kvm->stat.mmu_recycled += total_zapped;
2480 return total_zapped;
2483 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2485 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2486 return kvm->arch.n_max_mmu_pages -
2487 kvm->arch.n_used_mmu_pages;
2492 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2494 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2496 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2499 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2502 * Note, this check is intentionally soft, it only guarantees that one
2503 * page is available, while the caller may end up allocating as many as
2504 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2505 * exceeding the (arbitrary by default) limit will not harm the host,
2506 * being too aggressive may unnecessarily kill the guest, and getting an
2507 * exact count is far more trouble than it's worth, especially in the
2510 if (!kvm_mmu_available_pages(vcpu->kvm))
2516 * Changing the number of mmu pages allocated to the vm
2517 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2519 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2521 write_lock(&kvm->mmu_lock);
2523 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2524 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2527 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2530 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2532 write_unlock(&kvm->mmu_lock);
2535 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2537 struct kvm_mmu_page *sp;
2538 LIST_HEAD(invalid_list);
2541 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2543 write_lock(&kvm->mmu_lock);
2544 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2545 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2548 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2550 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2551 write_unlock(&kvm->mmu_lock);
2556 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2561 if (vcpu->arch.mmu->direct_map)
2564 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2566 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2571 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2573 trace_kvm_mmu_unsync_page(sp);
2574 ++vcpu->kvm->stat.mmu_unsync;
2577 kvm_mmu_mark_parents_unsync(sp);
2581 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2582 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2583 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2584 * be write-protected.
2586 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
2588 struct kvm_mmu_page *sp;
2589 bool locked = false;
2592 * Force write-protection if the page is being tracked. Note, the page
2593 * track machinery is used to write-protect upper-level shadow pages,
2594 * i.e. this guards the role.level == 4K assertion below!
2596 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2600 * The page is not write-tracked, mark existing shadow pages unsync
2601 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2602 * that case, KVM must complete emulation of the guest TLB flush before
2603 * allowing shadow pages to become unsync (writable by the guest).
2605 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2613 * TDP MMU page faults require an additional spinlock as they
2614 * run with mmu_lock held for read, not write, and the unsync
2615 * logic is not thread safe. Take the spinklock regardless of
2616 * the MMU type to avoid extra conditionals/parameters, there's
2617 * no meaningful penalty if mmu_lock is held for write.
2621 spin_lock(&vcpu->kvm->arch.mmu_unsync_pages_lock);
2624 * Recheck after taking the spinlock, a different vCPU
2625 * may have since marked the page unsync. A false
2626 * positive on the unprotected check above is not
2627 * possible as clearing sp->unsync _must_ hold mmu_lock
2628 * for write, i.e. unsync cannot transition from 0->1
2629 * while this CPU holds mmu_lock for read (or write).
2631 if (READ_ONCE(sp->unsync))
2635 WARN_ON(sp->role.level != PG_LEVEL_4K);
2636 kvm_unsync_page(vcpu, sp);
2639 spin_unlock(&vcpu->kvm->arch.mmu_unsync_pages_lock);
2642 * We need to ensure that the marking of unsync pages is visible
2643 * before the SPTE is updated to allow writes because
2644 * kvm_mmu_sync_roots() checks the unsync flags without holding
2645 * the MMU lock and so can race with this. If the SPTE was updated
2646 * before the page had been marked as unsync-ed, something like the
2647 * following could happen:
2650 * ---------------------------------------------------------------------
2651 * 1.2 Host updates SPTE
2653 * 2.1 Guest writes a GPTE for GVA X.
2654 * (GPTE being in the guest page table shadowed
2655 * by the SP from CPU 1.)
2656 * This reads SPTE during the page table walk.
2657 * Since SPTE.W is read as 1, there is no
2660 * 2.2 Guest issues TLB flush.
2661 * That causes a VM Exit.
2663 * 2.3 Walking of unsync pages sees sp->unsync is
2664 * false and skips the page.
2666 * 2.4 Guest accesses GVA X.
2667 * Since the mapping in the SP was not updated,
2668 * so the old mapping for GVA X incorrectly
2672 * (sp->unsync = true)
2674 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2675 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2676 * pairs with this write barrier.
2683 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2684 unsigned int pte_access, int level,
2685 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2686 bool can_unsync, bool host_writable)
2689 struct kvm_mmu_page *sp;
2692 sp = sptep_to_sp(sptep);
2694 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2695 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2697 if (spte & PT_WRITABLE_MASK)
2698 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2701 ret |= SET_SPTE_SPURIOUS;
2702 else if (mmu_spte_update(sptep, spte))
2703 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2707 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2708 unsigned int pte_access, bool write_fault, int level,
2709 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2712 int was_rmapped = 0;
2714 int ret = RET_PF_FIXED;
2717 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2718 *sptep, write_fault, gfn);
2720 if (unlikely(is_noslot_pfn(pfn))) {
2721 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2722 return RET_PF_EMULATE;
2725 if (is_shadow_present_pte(*sptep)) {
2727 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2728 * the parent of the now unreachable PTE.
2730 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2731 struct kvm_mmu_page *child;
2734 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2735 drop_parent_pte(child, sptep);
2737 } else if (pfn != spte_to_pfn(*sptep)) {
2738 pgprintk("hfn old %llx new %llx\n",
2739 spte_to_pfn(*sptep), pfn);
2740 drop_spte(vcpu->kvm, sptep);
2746 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2747 speculative, true, host_writable);
2748 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2750 ret = RET_PF_EMULATE;
2751 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2754 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2755 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2756 KVM_PAGES_PER_HPAGE(level));
2759 * The fault is fully spurious if and only if the new SPTE and old SPTE
2760 * are identical, and emulation is not required.
2762 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2763 WARN_ON_ONCE(!was_rmapped);
2764 return RET_PF_SPURIOUS;
2767 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2768 trace_kvm_mmu_set_spte(level, gfn, sptep);
2771 kvm_update_page_stats(vcpu->kvm, level, 1);
2772 rmap_add(vcpu, sptep, gfn);
2778 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2781 struct kvm_memory_slot *slot;
2783 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2785 return KVM_PFN_ERR_FAULT;
2787 return gfn_to_pfn_memslot_atomic(slot, gfn);
2790 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2791 struct kvm_mmu_page *sp,
2792 u64 *start, u64 *end)
2794 struct page *pages[PTE_PREFETCH_NUM];
2795 struct kvm_memory_slot *slot;
2796 unsigned int access = sp->role.access;
2800 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2801 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2805 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2809 for (i = 0; i < ret; i++, gfn++, start++) {
2810 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2811 page_to_pfn(pages[i]), true, true);
2818 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2819 struct kvm_mmu_page *sp, u64 *sptep)
2821 u64 *spte, *start = NULL;
2824 WARN_ON(!sp->role.direct);
2826 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2829 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2830 if (is_shadow_present_pte(*spte) || spte == sptep) {
2833 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2841 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2843 struct kvm_mmu_page *sp;
2845 sp = sptep_to_sp(sptep);
2848 * Without accessed bits, there's no way to distinguish between
2849 * actually accessed translations and prefetched, so disable pte
2850 * prefetch if accessed bits aren't available.
2852 if (sp_ad_disabled(sp))
2855 if (sp->role.level > PG_LEVEL_4K)
2859 * If addresses are being invalidated, skip prefetching to avoid
2860 * accidentally prefetching those addresses.
2862 if (unlikely(vcpu->kvm->mmu_notifier_count))
2865 __direct_pte_prefetch(vcpu, sp, sptep);
2868 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2869 const struct kvm_memory_slot *slot)
2875 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2879 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2880 * is not solely for performance, it's also necessary to avoid the
2881 * "writable" check in __gfn_to_hva_many(), which will always fail on
2882 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2883 * page fault steps have already verified the guest isn't writing a
2884 * read-only memslot.
2886 hva = __gfn_to_hva_memslot(slot, gfn);
2888 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2895 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2896 const struct kvm_memory_slot *slot, gfn_t gfn,
2897 kvm_pfn_t pfn, int max_level)
2899 struct kvm_lpage_info *linfo;
2902 max_level = min(max_level, max_huge_page_level);
2903 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2904 linfo = lpage_info_slot(gfn, slot, max_level);
2905 if (!linfo->disallow_lpage)
2909 if (max_level == PG_LEVEL_4K)
2912 host_level = host_pfn_mapping_level(kvm, gfn, pfn, slot);
2913 return min(host_level, max_level);
2916 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2917 int max_level, kvm_pfn_t *pfnp,
2918 bool huge_page_disallowed, int *req_level)
2920 struct kvm_memory_slot *slot;
2921 kvm_pfn_t pfn = *pfnp;
2925 *req_level = PG_LEVEL_4K;
2927 if (unlikely(max_level == PG_LEVEL_4K))
2930 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2933 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2938 * Enforce the iTLB multihit workaround after capturing the requested
2939 * level, which will be used to do precise, accurate accounting.
2941 *req_level = level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2942 if (level == PG_LEVEL_4K || huge_page_disallowed)
2946 * mmu_notifier_retry() was successful and mmu_lock is held, so
2947 * the pmd can't be split from under us.
2949 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2950 VM_BUG_ON((gfn & mask) != (pfn & mask));
2951 *pfnp = pfn & ~mask;
2956 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2957 kvm_pfn_t *pfnp, int *goal_levelp)
2959 int level = *goal_levelp;
2961 if (cur_level == level && level > PG_LEVEL_4K &&
2962 is_shadow_present_pte(spte) &&
2963 !is_large_pte(spte)) {
2965 * A small SPTE exists for this pfn, but FNAME(fetch)
2966 * and __direct_map would like to create a large PTE
2967 * instead: just force them to go down another level,
2968 * patching back for them into pfn the next 9 bits of
2971 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2972 KVM_PAGES_PER_HPAGE(level - 1);
2973 *pfnp |= gfn & page_mask;
2978 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2979 int map_writable, int max_level, kvm_pfn_t pfn,
2980 bool prefault, bool is_tdp)
2982 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2983 bool write = error_code & PFERR_WRITE_MASK;
2984 bool exec = error_code & PFERR_FETCH_MASK;
2985 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2986 struct kvm_shadow_walk_iterator it;
2987 struct kvm_mmu_page *sp;
2988 int level, req_level, ret;
2989 gfn_t gfn = gpa >> PAGE_SHIFT;
2990 gfn_t base_gfn = gfn;
2992 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2993 huge_page_disallowed, &req_level);
2995 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2996 for_each_shadow_entry(vcpu, gpa, it) {
2998 * We cannot overwrite existing page tables with an NX
2999 * large page, as the leaf could be executable.
3001 if (nx_huge_page_workaround_enabled)
3002 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
3005 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
3006 if (it.level == level)
3009 drop_large_spte(vcpu, it.sptep);
3010 if (is_shadow_present_pte(*it.sptep))
3013 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
3014 it.level - 1, true, ACC_ALL);
3016 link_shadow_page(vcpu, it.sptep, sp);
3017 if (is_tdp && huge_page_disallowed &&
3018 req_level >= it.level)
3019 account_huge_nx_page(vcpu->kvm, sp);
3022 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
3023 write, level, base_gfn, pfn, prefault,
3025 if (ret == RET_PF_SPURIOUS)
3028 direct_pte_prefetch(vcpu, it.sptep);
3029 ++vcpu->stat.pf_fixed;
3033 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3035 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3038 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3041 * Do not cache the mmio info caused by writing the readonly gfn
3042 * into the spte otherwise read access on readonly gfn also can
3043 * caused mmio page fault and treat it as mmio access.
3045 if (pfn == KVM_PFN_ERR_RO_FAULT)
3046 return RET_PF_EMULATE;
3048 if (pfn == KVM_PFN_ERR_HWPOISON) {
3049 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3050 return RET_PF_RETRY;
3056 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3057 kvm_pfn_t pfn, unsigned int access,
3060 /* The pfn is invalid, report the error! */
3061 if (unlikely(is_error_pfn(pfn))) {
3062 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3066 if (unlikely(is_noslot_pfn(pfn))) {
3067 vcpu_cache_mmio_info(vcpu, gva, gfn,
3068 access & shadow_mmio_access_mask);
3070 * If MMIO caching is disabled, emulate immediately without
3071 * touching the shadow page tables as attempting to install an
3072 * MMIO SPTE will just be an expensive nop.
3074 if (unlikely(!shadow_mmio_value)) {
3075 *ret_val = RET_PF_EMULATE;
3083 static bool page_fault_can_be_fast(u32 error_code)
3086 * Do not fix the mmio spte with invalid generation number which
3087 * need to be updated by slow page fault path.
3089 if (unlikely(error_code & PFERR_RSVD_MASK))
3092 /* See if the page fault is due to an NX violation */
3093 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3094 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3098 * #PF can be fast if:
3099 * 1. The shadow page table entry is not present, which could mean that
3100 * the fault is potentially caused by access tracking (if enabled).
3101 * 2. The shadow page table entry is present and the fault
3102 * is caused by write-protect, that means we just need change the W
3103 * bit of the spte which can be done out of mmu-lock.
3105 * However, if access tracking is disabled we know that a non-present
3106 * page must be a genuine page fault where we have to create a new SPTE.
3107 * So, if access tracking is disabled, we return true only for write
3108 * accesses to a present page.
3111 return shadow_acc_track_mask != 0 ||
3112 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3113 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3117 * Returns true if the SPTE was fixed successfully. Otherwise,
3118 * someone else modified the SPTE from its original value.
3121 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3122 u64 *sptep, u64 old_spte, u64 new_spte)
3126 WARN_ON(!sp->role.direct);
3129 * Theoretically we could also set dirty bit (and flush TLB) here in
3130 * order to eliminate unnecessary PML logging. See comments in
3131 * set_spte. But fast_page_fault is very unlikely to happen with PML
3132 * enabled, so we do not do this. This might result in the same GPA
3133 * to be logged in PML buffer again when the write really happens, and
3134 * eventually to be called by mark_page_dirty twice. But it's also no
3135 * harm. This also avoids the TLB flush needed after setting dirty bit
3136 * so non-PML cases won't be impacted.
3138 * Compare with set_spte where instead shadow_dirty_mask is set.
3140 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3143 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3145 * The gfn of direct spte is stable since it is
3146 * calculated by sp->gfn.
3148 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3149 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3155 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3157 if (fault_err_code & PFERR_FETCH_MASK)
3158 return is_executable_pte(spte);
3160 if (fault_err_code & PFERR_WRITE_MASK)
3161 return is_writable_pte(spte);
3163 /* Fault was on Read access */
3164 return spte & PT_PRESENT_MASK;
3168 * Returns the last level spte pointer of the shadow page walk for the given
3169 * gpa, and sets *spte to the spte value. This spte may be non-preset. If no
3170 * walk could be performed, returns NULL and *spte does not contain valid data.
3173 * - Must be called between walk_shadow_page_lockless_{begin,end}.
3174 * - The returned sptep must not be used after walk_shadow_page_lockless_end.
3176 static u64 *fast_pf_get_last_sptep(struct kvm_vcpu *vcpu, gpa_t gpa, u64 *spte)
3178 struct kvm_shadow_walk_iterator iterator;
3182 for_each_shadow_entry_lockless(vcpu, gpa, iterator, old_spte) {
3183 sptep = iterator.sptep;
3186 if (!is_shadow_present_pte(old_spte))
3194 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3196 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code)
3198 struct kvm_mmu_page *sp;
3199 int ret = RET_PF_INVALID;
3202 uint retry_count = 0;
3204 if (!page_fault_can_be_fast(error_code))
3207 walk_shadow_page_lockless_begin(vcpu);
3212 if (is_tdp_mmu(vcpu->arch.mmu))
3213 sptep = kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu, gpa, &spte);
3215 sptep = fast_pf_get_last_sptep(vcpu, gpa, &spte);
3217 if (!is_shadow_present_pte(spte))
3220 sp = sptep_to_sp(sptep);
3221 if (!is_last_spte(spte, sp->role.level))
3225 * Check whether the memory access that caused the fault would
3226 * still cause it if it were to be performed right now. If not,
3227 * then this is a spurious fault caused by TLB lazily flushed,
3228 * or some other CPU has already fixed the PTE after the
3229 * current CPU took the fault.
3231 * Need not check the access of upper level table entries since
3232 * they are always ACC_ALL.
3234 if (is_access_allowed(error_code, spte)) {
3235 ret = RET_PF_SPURIOUS;
3241 if (is_access_track_spte(spte))
3242 new_spte = restore_acc_track_spte(new_spte);
3245 * Currently, to simplify the code, write-protection can
3246 * be removed in the fast path only if the SPTE was
3247 * write-protected for dirty-logging or access tracking.
3249 if ((error_code & PFERR_WRITE_MASK) &&
3250 spte_can_locklessly_be_made_writable(spte)) {
3251 new_spte |= PT_WRITABLE_MASK;
3254 * Do not fix write-permission on the large spte. Since
3255 * we only dirty the first page into the dirty-bitmap in
3256 * fast_pf_fix_direct_spte(), other pages are missed
3257 * if its slot has dirty logging enabled.
3259 * Instead, we let the slow page fault path create a
3260 * normal spte to fix the access.
3262 * See the comments in kvm_arch_commit_memory_region().
3264 if (sp->role.level > PG_LEVEL_4K)
3268 /* Verify that the fault can be handled in the fast path */
3269 if (new_spte == spte ||
3270 !is_access_allowed(error_code, new_spte))
3274 * Currently, fast page fault only works for direct mapping
3275 * since the gfn is not stable for indirect shadow page. See
3276 * Documentation/virt/kvm/locking.rst to get more detail.
3278 if (fast_pf_fix_direct_spte(vcpu, sp, sptep, spte, new_spte)) {
3283 if (++retry_count > 4) {
3284 printk_once(KERN_WARNING
3285 "kvm: Fast #PF retrying more than 4 times.\n");
3291 trace_fast_page_fault(vcpu, gpa, error_code, sptep, spte, ret);
3292 walk_shadow_page_lockless_end(vcpu);
3297 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3298 struct list_head *invalid_list)
3300 struct kvm_mmu_page *sp;
3302 if (!VALID_PAGE(*root_hpa))
3305 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3309 if (is_tdp_mmu_page(sp))
3310 kvm_tdp_mmu_put_root(kvm, sp, false);
3311 else if (!--sp->root_count && sp->role.invalid)
3312 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3314 *root_hpa = INVALID_PAGE;
3317 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3318 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3319 ulong roots_to_free)
3321 struct kvm *kvm = vcpu->kvm;
3323 LIST_HEAD(invalid_list);
3324 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3326 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3328 /* Before acquiring the MMU lock, see if we need to do any real work. */
3329 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3330 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3331 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3332 VALID_PAGE(mmu->prev_roots[i].hpa))
3335 if (i == KVM_MMU_NUM_PREV_ROOTS)
3339 write_lock(&kvm->mmu_lock);
3341 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3342 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3343 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3346 if (free_active_root) {
3347 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3348 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3349 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3350 } else if (mmu->pae_root) {
3351 for (i = 0; i < 4; ++i) {
3352 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3355 mmu_free_root_page(kvm, &mmu->pae_root[i],
3357 mmu->pae_root[i] = INVALID_PAE_ROOT;
3360 mmu->root_hpa = INVALID_PAGE;
3364 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3365 write_unlock(&kvm->mmu_lock);
3367 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3369 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3371 unsigned long roots_to_free = 0;
3376 * This should not be called while L2 is active, L2 can't invalidate
3377 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3379 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3381 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3382 root_hpa = mmu->prev_roots[i].hpa;
3383 if (!VALID_PAGE(root_hpa))
3386 if (!to_shadow_page(root_hpa) ||
3387 to_shadow_page(root_hpa)->role.guest_mode)
3388 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3391 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3393 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3396 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3400 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3401 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3408 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3409 u8 level, bool direct)
3411 struct kvm_mmu_page *sp;
3413 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3416 return __pa(sp->spt);
3419 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3421 struct kvm_mmu *mmu = vcpu->arch.mmu;
3422 u8 shadow_root_level = mmu->shadow_root_level;
3427 write_lock(&vcpu->kvm->mmu_lock);
3428 r = make_mmu_pages_available(vcpu);
3432 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3433 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3434 mmu->root_hpa = root;
3435 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3436 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3437 mmu->root_hpa = root;
3438 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3439 if (WARN_ON_ONCE(!mmu->pae_root)) {
3444 for (i = 0; i < 4; ++i) {
3445 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3447 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3448 i << 30, PT32_ROOT_LEVEL, true);
3449 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3452 mmu->root_hpa = __pa(mmu->pae_root);
3454 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3459 /* root_pgd is ignored for direct MMUs. */
3462 write_unlock(&vcpu->kvm->mmu_lock);
3466 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3468 struct kvm_mmu *mmu = vcpu->arch.mmu;
3469 u64 pdptrs[4], pm_mask;
3470 gfn_t root_gfn, root_pgd;
3475 root_pgd = mmu->get_guest_pgd(vcpu);
3476 root_gfn = root_pgd >> PAGE_SHIFT;
3478 if (mmu_check_root(vcpu, root_gfn))
3482 * On SVM, reading PDPTRs might access guest memory, which might fault
3483 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3485 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3486 for (i = 0; i < 4; ++i) {
3487 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3488 if (!(pdptrs[i] & PT_PRESENT_MASK))
3491 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3496 r = alloc_all_memslots_rmaps(vcpu->kvm);
3500 write_lock(&vcpu->kvm->mmu_lock);
3501 r = make_mmu_pages_available(vcpu);
3506 * Do we shadow a long mode page table? If so we need to
3507 * write-protect the guests page table root.
3509 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3510 root = mmu_alloc_root(vcpu, root_gfn, 0,
3511 mmu->shadow_root_level, false);
3512 mmu->root_hpa = root;
3516 if (WARN_ON_ONCE(!mmu->pae_root)) {
3522 * We shadow a 32 bit page table. This may be a legacy 2-level
3523 * or a PAE 3-level page table. In either case we need to be aware that
3524 * the shadow page table may be a PAE or a long mode page table.
3526 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3527 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3528 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3530 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3534 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3536 if (mmu->shadow_root_level == PT64_ROOT_5LEVEL) {
3537 if (WARN_ON_ONCE(!mmu->pml5_root)) {
3541 mmu->pml5_root[0] = __pa(mmu->pml4_root) | pm_mask;
3545 for (i = 0; i < 4; ++i) {
3546 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3548 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3549 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3550 mmu->pae_root[i] = INVALID_PAE_ROOT;
3553 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3556 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3557 PT32_ROOT_LEVEL, false);
3558 mmu->pae_root[i] = root | pm_mask;
3561 if (mmu->shadow_root_level == PT64_ROOT_5LEVEL)
3562 mmu->root_hpa = __pa(mmu->pml5_root);
3563 else if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3564 mmu->root_hpa = __pa(mmu->pml4_root);
3566 mmu->root_hpa = __pa(mmu->pae_root);
3569 mmu->root_pgd = root_pgd;
3571 write_unlock(&vcpu->kvm->mmu_lock);
3576 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3578 struct kvm_mmu *mmu = vcpu->arch.mmu;
3579 bool need_pml5 = mmu->shadow_root_level > PT64_ROOT_4LEVEL;
3580 u64 *pml5_root = NULL;
3581 u64 *pml4_root = NULL;
3585 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3586 * tables are allocated and initialized at root creation as there is no
3587 * equivalent level in the guest's NPT to shadow. Allocate the tables
3588 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3590 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3591 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3595 * NPT, the only paging mode that uses this horror, uses a fixed number
3596 * of levels for the shadow page tables, e.g. all MMUs are 4-level or
3597 * all MMus are 5-level. Thus, this can safely require that pml5_root
3598 * is allocated if the other roots are valid and pml5 is needed, as any
3599 * prior MMU would also have required pml5.
3601 if (mmu->pae_root && mmu->pml4_root && (!need_pml5 || mmu->pml5_root))
3605 * The special roots should always be allocated in concert. Yell and
3606 * bail if KVM ends up in a state where only one of the roots is valid.
3608 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root ||
3609 (need_pml5 && mmu->pml5_root)))
3613 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3614 * doesn't need to be decrypted.
3616 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3620 #ifdef CONFIG_X86_64
3621 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3626 pml5_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3632 mmu->pae_root = pae_root;
3633 mmu->pml4_root = pml4_root;
3634 mmu->pml5_root = pml5_root;
3638 #ifdef CONFIG_X86_64
3640 free_page((unsigned long)pml4_root);
3642 free_page((unsigned long)pae_root);
3647 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3650 struct kvm_mmu_page *sp;
3652 if (vcpu->arch.mmu->direct_map)
3655 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3658 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3660 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3661 hpa_t root = vcpu->arch.mmu->root_hpa;
3662 sp = to_shadow_page(root);
3665 * Even if another CPU was marking the SP as unsync-ed
3666 * simultaneously, any guest page table changes are not
3667 * guaranteed to be visible anyway until this VCPU issues a TLB
3668 * flush strictly after those changes are made. We only need to
3669 * ensure that the other CPU sets these flags before any actual
3670 * changes to the page tables are made. The comments in
3671 * mmu_try_to_unsync_pages() describe what could go wrong if
3672 * this requirement isn't satisfied.
3674 if (!smp_load_acquire(&sp->unsync) &&
3675 !smp_load_acquire(&sp->unsync_children))
3678 write_lock(&vcpu->kvm->mmu_lock);
3679 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3681 mmu_sync_children(vcpu, sp, true);
3683 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3684 write_unlock(&vcpu->kvm->mmu_lock);
3688 write_lock(&vcpu->kvm->mmu_lock);
3689 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3691 for (i = 0; i < 4; ++i) {
3692 hpa_t root = vcpu->arch.mmu->pae_root[i];
3694 if (IS_VALID_PAE_ROOT(root)) {
3695 root &= PT64_BASE_ADDR_MASK;
3696 sp = to_shadow_page(root);
3697 mmu_sync_children(vcpu, sp, true);
3701 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3702 write_unlock(&vcpu->kvm->mmu_lock);
3705 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3706 u32 access, struct x86_exception *exception)
3709 exception->error_code = 0;
3713 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3715 struct x86_exception *exception)
3718 exception->error_code = 0;
3719 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3722 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3725 * A nested guest cannot use the MMIO cache if it is using nested
3726 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3728 if (mmu_is_nested(vcpu))
3732 return vcpu_match_mmio_gpa(vcpu, addr);
3734 return vcpu_match_mmio_gva(vcpu, addr);
3738 * Return the level of the lowest level SPTE added to sptes.
3739 * That SPTE may be non-present.
3741 * Must be called between walk_shadow_page_lockless_{begin,end}.
3743 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3745 struct kvm_shadow_walk_iterator iterator;
3749 for (shadow_walk_init(&iterator, vcpu, addr),
3750 *root_level = iterator.level;
3751 shadow_walk_okay(&iterator);
3752 __shadow_walk_next(&iterator, spte)) {
3753 leaf = iterator.level;
3754 spte = mmu_spte_get_lockless(iterator.sptep);
3758 if (!is_shadow_present_pte(spte))
3765 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3766 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3768 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3769 struct rsvd_bits_validate *rsvd_check;
3770 int root, leaf, level;
3771 bool reserved = false;
3773 walk_shadow_page_lockless_begin(vcpu);
3775 if (is_tdp_mmu(vcpu->arch.mmu))
3776 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3778 leaf = get_walk(vcpu, addr, sptes, &root);
3780 walk_shadow_page_lockless_end(vcpu);
3782 if (unlikely(leaf < 0)) {
3787 *sptep = sptes[leaf];
3790 * Skip reserved bits checks on the terminal leaf if it's not a valid
3791 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3792 * design, always have reserved bits set. The purpose of the checks is
3793 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3795 if (!is_shadow_present_pte(sptes[leaf]))
3798 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3800 for (level = root; level >= leaf; level--)
3801 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
3804 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3806 for (level = root; level >= leaf; level--)
3807 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3808 sptes[level], level,
3809 get_rsvd_bits(rsvd_check, sptes[level], level));
3815 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3820 if (mmio_info_in_cache(vcpu, addr, direct))
3821 return RET_PF_EMULATE;
3823 reserved = get_mmio_spte(vcpu, addr, &spte);
3824 if (WARN_ON(reserved))
3827 if (is_mmio_spte(spte)) {
3828 gfn_t gfn = get_mmio_spte_gfn(spte);
3829 unsigned int access = get_mmio_spte_access(spte);
3831 if (!check_mmio_spte(vcpu, spte))
3832 return RET_PF_INVALID;
3837 trace_handle_mmio_page_fault(addr, gfn, access);
3838 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3839 return RET_PF_EMULATE;
3843 * If the page table is zapped by other cpus, let CPU fault again on
3846 return RET_PF_RETRY;
3849 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3850 u32 error_code, gfn_t gfn)
3852 if (unlikely(error_code & PFERR_RSVD_MASK))
3855 if (!(error_code & PFERR_PRESENT_MASK) ||
3856 !(error_code & PFERR_WRITE_MASK))
3860 * guest is writing the page which is write tracked which can
3861 * not be fixed by page fault handler.
3863 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3869 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3871 struct kvm_shadow_walk_iterator iterator;
3874 walk_shadow_page_lockless_begin(vcpu);
3875 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3876 clear_sp_write_flooding_count(iterator.sptep);
3877 if (!is_shadow_present_pte(spte))
3880 walk_shadow_page_lockless_end(vcpu);
3883 static u32 alloc_apf_token(struct kvm_vcpu *vcpu)
3885 /* make sure the token value is not 0 */
3886 u32 id = vcpu->arch.apf.id;
3889 vcpu->arch.apf.id = 1;
3891 return (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3894 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3897 struct kvm_arch_async_pf arch;
3899 arch.token = alloc_apf_token(vcpu);
3901 arch.direct_map = vcpu->arch.mmu->direct_map;
3902 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3904 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3905 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3908 static bool kvm_faultin_pfn(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3909 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3910 bool write, bool *writable, int *r)
3912 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3916 * Retry the page fault if the gfn hit a memslot that is being deleted
3917 * or moved. This ensures any existing SPTEs for the old memslot will
3918 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3920 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3923 if (!kvm_is_visible_memslot(slot)) {
3924 /* Don't expose private memslots to L2. */
3925 if (is_guest_mode(vcpu)) {
3926 *pfn = KVM_PFN_NOSLOT;
3931 * If the APIC access page exists but is disabled, go directly
3932 * to emulation without caching the MMIO access or creating a
3933 * MMIO SPTE. That way the cache doesn't need to be purged
3934 * when the AVIC is re-enabled.
3936 if (slot && slot->id == APIC_ACCESS_PAGE_PRIVATE_MEMSLOT &&
3937 !kvm_apicv_activated(vcpu->kvm)) {
3938 *r = RET_PF_EMULATE;
3944 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3945 write, writable, hva);
3947 return false; /* *pfn has correct page already */
3949 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3950 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3951 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3952 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3953 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3955 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3959 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3960 write, writable, hva);
3968 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3969 bool prefault, int max_level, bool is_tdp)
3971 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3972 bool write = error_code & PFERR_WRITE_MASK;
3975 gfn_t gfn = gpa >> PAGE_SHIFT;
3976 unsigned long mmu_seq;
3981 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3982 return RET_PF_EMULATE;
3984 r = fast_page_fault(vcpu, gpa, error_code);
3985 if (r != RET_PF_INVALID)
3988 r = mmu_topup_memory_caches(vcpu, false);
3992 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3995 if (kvm_faultin_pfn(vcpu, prefault, gfn, gpa, &pfn, &hva,
3996 write, &map_writable, &r))
3999 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
4004 if (is_tdp_mmu_fault)
4005 read_lock(&vcpu->kvm->mmu_lock);
4007 write_lock(&vcpu->kvm->mmu_lock);
4009 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
4012 if (is_tdp_mmu_fault) {
4013 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
4016 r = make_mmu_pages_available(vcpu);
4019 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
4024 if (is_tdp_mmu_fault)
4025 read_unlock(&vcpu->kvm->mmu_lock);
4027 write_unlock(&vcpu->kvm->mmu_lock);
4028 kvm_release_pfn_clean(pfn);
4032 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
4033 u32 error_code, bool prefault)
4035 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
4037 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4038 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
4039 PG_LEVEL_2M, false);
4042 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4043 u64 fault_address, char *insn, int insn_len)
4046 u32 flags = vcpu->arch.apf.host_apf_flags;
4048 #ifndef CONFIG_X86_64
4049 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4050 if (WARN_ON_ONCE(fault_address >> 32))
4054 vcpu->arch.l1tf_flush_l1d = true;
4056 trace_kvm_page_fault(fault_address, error_code);
4058 if (kvm_event_needs_reinjection(vcpu))
4059 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4060 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4062 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
4063 vcpu->arch.apf.host_apf_flags = 0;
4064 local_irq_disable();
4065 kvm_async_pf_task_wait_schedule(fault_address);
4068 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
4073 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4075 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4080 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
4081 max_level > PG_LEVEL_4K;
4083 int page_num = KVM_PAGES_PER_HPAGE(max_level);
4084 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
4086 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4090 return direct_page_fault(vcpu, gpa, error_code, prefault,
4094 static void nonpaging_init_context(struct kvm_mmu *context)
4096 context->page_fault = nonpaging_page_fault;
4097 context->gva_to_gpa = nonpaging_gva_to_gpa;
4098 context->sync_page = nonpaging_sync_page;
4099 context->invlpg = NULL;
4100 context->direct_map = true;
4103 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
4104 union kvm_mmu_page_role role)
4106 return (role.direct || pgd == root->pgd) &&
4107 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
4108 role.word == to_shadow_page(root->hpa)->role.word;
4112 * Find out if a previously cached root matching the new pgd/role is available.
4113 * The current root is also inserted into the cache.
4114 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4116 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4117 * false is returned. This root should now be freed by the caller.
4119 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4120 union kvm_mmu_page_role new_role)
4123 struct kvm_mmu_root_info root;
4124 struct kvm_mmu *mmu = vcpu->arch.mmu;
4126 root.pgd = mmu->root_pgd;
4127 root.hpa = mmu->root_hpa;
4129 if (is_root_usable(&root, new_pgd, new_role))
4132 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4133 swap(root, mmu->prev_roots[i]);
4135 if (is_root_usable(&root, new_pgd, new_role))
4139 mmu->root_hpa = root.hpa;
4140 mmu->root_pgd = root.pgd;
4142 return i < KVM_MMU_NUM_PREV_ROOTS;
4145 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4146 union kvm_mmu_page_role new_role)
4148 struct kvm_mmu *mmu = vcpu->arch.mmu;
4151 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4152 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4153 * later if necessary.
4155 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4156 mmu->root_level >= PT64_ROOT_4LEVEL)
4157 return cached_root_available(vcpu, new_pgd, new_role);
4162 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4163 union kvm_mmu_page_role new_role)
4165 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4166 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4171 * It's possible that the cached previous root page is obsolete because
4172 * of a change in the MMU generation number. However, changing the
4173 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4174 * free the root set here and allocate a new one.
4176 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4178 if (force_flush_and_sync_on_reuse) {
4179 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4180 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4184 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4185 * switching to a new CR3, that GVA->GPA mapping may no longer be
4186 * valid. So clear any cached MMIO info even when we don't need to sync
4187 * the shadow page tables.
4189 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4192 * If this is a direct root page, it doesn't have a write flooding
4193 * count. Otherwise, clear the write flooding count.
4195 if (!new_role.direct)
4196 __clear_sp_write_flooding_count(
4197 to_shadow_page(vcpu->arch.mmu->root_hpa));
4200 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4202 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4204 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4206 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4208 return kvm_read_cr3(vcpu);
4211 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4212 unsigned int access, int *nr_present)
4214 if (unlikely(is_mmio_spte(*sptep))) {
4215 if (gfn != get_mmio_spte_gfn(*sptep)) {
4216 mmu_spte_clear_no_track(sptep);
4221 mark_mmio_spte(vcpu, sptep, gfn, access);
4228 #define PTTYPE_EPT 18 /* arbitrary */
4229 #define PTTYPE PTTYPE_EPT
4230 #include "paging_tmpl.h"
4234 #include "paging_tmpl.h"
4238 #include "paging_tmpl.h"
4242 __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
4243 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4246 u64 gbpages_bit_rsvd = 0;
4247 u64 nonleaf_bit8_rsvd = 0;
4250 rsvd_check->bad_mt_xwr = 0;
4253 gbpages_bit_rsvd = rsvd_bits(7, 7);
4255 if (level == PT32E_ROOT_LEVEL)
4256 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4258 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4260 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4262 high_bits_rsvd |= rsvd_bits(63, 63);
4265 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4266 * leaf entries) on AMD CPUs only.
4269 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4272 case PT32_ROOT_LEVEL:
4273 /* no rsvd bits for 2 level 4K page table entries */
4274 rsvd_check->rsvd_bits_mask[0][1] = 0;
4275 rsvd_check->rsvd_bits_mask[0][0] = 0;
4276 rsvd_check->rsvd_bits_mask[1][0] =
4277 rsvd_check->rsvd_bits_mask[0][0];
4280 rsvd_check->rsvd_bits_mask[1][1] = 0;
4284 if (is_cpuid_PSE36())
4285 /* 36bits PSE 4MB page */
4286 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4288 /* 32 bits PSE 4MB page */
4289 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4291 case PT32E_ROOT_LEVEL:
4292 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4295 rsvd_bits(1, 2); /* PDPTE */
4296 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4297 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4298 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4299 rsvd_bits(13, 20); /* large page */
4300 rsvd_check->rsvd_bits_mask[1][0] =
4301 rsvd_check->rsvd_bits_mask[0][0];
4303 case PT64_ROOT_5LEVEL:
4304 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4307 rsvd_check->rsvd_bits_mask[1][4] =
4308 rsvd_check->rsvd_bits_mask[0][4];
4310 case PT64_ROOT_4LEVEL:
4311 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4314 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4316 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4317 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4318 rsvd_check->rsvd_bits_mask[1][3] =
4319 rsvd_check->rsvd_bits_mask[0][3];
4320 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4323 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4324 rsvd_bits(13, 20); /* large page */
4325 rsvd_check->rsvd_bits_mask[1][0] =
4326 rsvd_check->rsvd_bits_mask[0][0];
4331 static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu)
4334 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4335 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4336 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4337 * walk for performance and complexity reasons. Not to mention KVM
4338 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4339 * KVM once a TDP translation is installed. Mimic hardware behavior so
4340 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4342 return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
4343 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
4346 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4347 struct kvm_mmu *context)
4349 __reset_rsvds_bits_mask(&context->guest_rsvd_check,
4350 vcpu->arch.reserved_gpa_bits,
4351 context->root_level, is_efer_nx(context),
4352 guest_can_use_gbpages(vcpu),
4353 is_cr4_pse(context),
4354 guest_cpuid_is_amd_or_hygon(vcpu));
4358 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4359 u64 pa_bits_rsvd, bool execonly)
4361 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4364 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4365 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4366 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4367 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4368 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4371 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4372 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4373 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4374 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4375 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4377 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4378 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4379 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4380 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4381 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4383 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4384 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4386 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4389 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4390 struct kvm_mmu *context, bool execonly)
4392 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4393 vcpu->arch.reserved_gpa_bits, execonly);
4396 static inline u64 reserved_hpa_bits(void)
4398 return rsvd_bits(shadow_phys_bits, 63);
4402 * the page table on host is the shadow page table for the page
4403 * table in guest or amd nested guest, its mmu features completely
4404 * follow the features in guest.
4406 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4407 struct kvm_mmu *context)
4410 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4411 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4412 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4413 * The iTLB multi-hit workaround can be toggled at any time, so assume
4414 * NX can be used by any non-nested shadow MMU to avoid having to reset
4415 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4417 bool uses_nx = is_efer_nx(context) || !tdp_enabled;
4419 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4421 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4422 bool is_pse = false;
4423 struct rsvd_bits_validate *shadow_zero_check;
4426 WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL);
4428 shadow_zero_check = &context->shadow_zero_check;
4429 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4430 context->shadow_root_level, uses_nx,
4431 guest_can_use_gbpages(vcpu), is_pse, is_amd);
4433 if (!shadow_me_mask)
4436 for (i = context->shadow_root_level; --i >= 0;) {
4437 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4438 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4443 static inline bool boot_cpu_is_amd(void)
4445 WARN_ON_ONCE(!tdp_enabled);
4446 return shadow_x_mask == 0;
4450 * the direct page table on host, use as much mmu features as
4451 * possible, however, kvm currently does not do execution-protection.
4454 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4455 struct kvm_mmu *context)
4457 struct rsvd_bits_validate *shadow_zero_check;
4460 shadow_zero_check = &context->shadow_zero_check;
4462 if (boot_cpu_is_amd())
4463 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4464 context->shadow_root_level, false,
4465 boot_cpu_has(X86_FEATURE_GBPAGES),
4468 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4469 reserved_hpa_bits(), false);
4471 if (!shadow_me_mask)
4474 for (i = context->shadow_root_level; --i >= 0;) {
4475 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4476 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4481 * as the comments in reset_shadow_zero_bits_mask() except it
4482 * is the shadow page table for intel nested guest.
4485 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4486 struct kvm_mmu *context, bool execonly)
4488 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4489 reserved_hpa_bits(), execonly);
4492 #define BYTE_MASK(access) \
4493 ((1 & (access) ? 2 : 0) | \
4494 (2 & (access) ? 4 : 0) | \
4495 (3 & (access) ? 8 : 0) | \
4496 (4 & (access) ? 16 : 0) | \
4497 (5 & (access) ? 32 : 0) | \
4498 (6 & (access) ? 64 : 0) | \
4499 (7 & (access) ? 128 : 0))
4502 static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
4506 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4507 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4508 const u8 u = BYTE_MASK(ACC_USER_MASK);
4510 bool cr4_smep = is_cr4_smep(mmu);
4511 bool cr4_smap = is_cr4_smap(mmu);
4512 bool cr0_wp = is_cr0_wp(mmu);
4513 bool efer_nx = is_efer_nx(mmu);
4515 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4516 unsigned pfec = byte << 1;
4519 * Each "*f" variable has a 1 bit for each UWX value
4520 * that causes a fault with the given PFEC.
4523 /* Faults from writes to non-writable pages */
4524 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4525 /* Faults from user mode accesses to supervisor pages */
4526 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4527 /* Faults from fetches of non-executable pages*/
4528 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4529 /* Faults from kernel mode fetches of user pages */
4531 /* Faults from kernel mode accesses of user pages */
4535 /* Faults from kernel mode accesses to user pages */
4536 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4538 /* Not really needed: !nx will cause pte.nx to fault */
4542 /* Allow supervisor writes if !cr0.wp */
4544 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4546 /* Disallow supervisor fetches of user code if cr4.smep */
4548 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4551 * SMAP:kernel-mode data accesses from user-mode
4552 * mappings should fault. A fault is considered
4553 * as a SMAP violation if all of the following
4554 * conditions are true:
4555 * - X86_CR4_SMAP is set in CR4
4556 * - A user page is accessed
4557 * - The access is not a fetch
4558 * - Page fault in kernel mode
4559 * - if CPL = 3 or X86_EFLAGS_AC is clear
4561 * Here, we cover the first three conditions.
4562 * The fourth is computed dynamically in permission_fault();
4563 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4564 * *not* subject to SMAP restrictions.
4567 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4570 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4575 * PKU is an additional mechanism by which the paging controls access to
4576 * user-mode addresses based on the value in the PKRU register. Protection
4577 * key violations are reported through a bit in the page fault error code.
4578 * Unlike other bits of the error code, the PK bit is not known at the
4579 * call site of e.g. gva_to_gpa; it must be computed directly in
4580 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4581 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4583 * In particular the following conditions come from the error code, the
4584 * page tables and the machine state:
4585 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4586 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4587 * - PK is always zero if U=0 in the page tables
4588 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4590 * The PKRU bitmask caches the result of these four conditions. The error
4591 * code (minus the P bit) and the page table's U bit form an index into the
4592 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4593 * with the two bits of the PKRU register corresponding to the protection key.
4594 * For the first three conditions above the bits will be 00, thus masking
4595 * away both AD and WD. For all reads or if the last condition holds, WD
4596 * only will be masked away.
4598 static void update_pkru_bitmask(struct kvm_mmu *mmu)
4605 if (!is_cr4_pke(mmu))
4608 wp = is_cr0_wp(mmu);
4610 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4611 unsigned pfec, pkey_bits;
4612 bool check_pkey, check_write, ff, uf, wf, pte_user;
4615 ff = pfec & PFERR_FETCH_MASK;
4616 uf = pfec & PFERR_USER_MASK;
4617 wf = pfec & PFERR_WRITE_MASK;
4619 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4620 pte_user = pfec & PFERR_RSVD_MASK;
4623 * Only need to check the access which is not an
4624 * instruction fetch and is to a user page.
4626 check_pkey = (!ff && pte_user);
4628 * write access is controlled by PKRU if it is a
4629 * user access or CR0.WP = 1.
4631 check_write = check_pkey && wf && (uf || wp);
4633 /* PKRU.AD stops both read and write access. */
4634 pkey_bits = !!check_pkey;
4635 /* PKRU.WD stops write access. */
4636 pkey_bits |= (!!check_write) << 1;
4638 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4642 static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu,
4643 struct kvm_mmu *mmu)
4645 if (!is_cr0_pg(mmu))
4648 reset_rsvds_bits_mask(vcpu, mmu);
4649 update_permission_bitmask(mmu, false);
4650 update_pkru_bitmask(mmu);
4653 static void paging64_init_context(struct kvm_mmu *context)
4655 context->page_fault = paging64_page_fault;
4656 context->gva_to_gpa = paging64_gva_to_gpa;
4657 context->sync_page = paging64_sync_page;
4658 context->invlpg = paging64_invlpg;
4659 context->direct_map = false;
4662 static void paging32_init_context(struct kvm_mmu *context)
4664 context->page_fault = paging32_page_fault;
4665 context->gva_to_gpa = paging32_gva_to_gpa;
4666 context->sync_page = paging32_sync_page;
4667 context->invlpg = paging32_invlpg;
4668 context->direct_map = false;
4671 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4672 struct kvm_mmu_role_regs *regs)
4674 union kvm_mmu_extended_role ext = {0};
4676 if (____is_cr0_pg(regs)) {
4678 ext.cr4_pae = ____is_cr4_pae(regs);
4679 ext.cr4_smep = ____is_cr4_smep(regs);
4680 ext.cr4_smap = ____is_cr4_smap(regs);
4681 ext.cr4_pse = ____is_cr4_pse(regs);
4683 /* PKEY and LA57 are active iff long mode is active. */
4684 ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
4685 ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
4686 ext.efer_lma = ____is_efer_lma(regs);
4694 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4695 struct kvm_mmu_role_regs *regs,
4698 union kvm_mmu_role role = {0};
4700 role.base.access = ACC_ALL;
4701 if (____is_cr0_pg(regs)) {
4702 role.base.efer_nx = ____is_efer_nx(regs);
4703 role.base.cr0_wp = ____is_cr0_wp(regs);
4705 role.base.smm = is_smm(vcpu);
4706 role.base.guest_mode = is_guest_mode(vcpu);
4711 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
4716 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4718 /* tdp_root_level is architecture forced level, use it if nonzero */
4720 return tdp_root_level;
4722 /* Use 5-level TDP if and only if it's useful/necessary. */
4723 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4726 return max_tdp_level;
4729 static union kvm_mmu_role
4730 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4731 struct kvm_mmu_role_regs *regs, bool base_only)
4733 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4735 role.base.ad_disabled = (shadow_accessed_mask == 0);
4736 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4737 role.base.direct = true;
4738 role.base.gpte_is_8_bytes = true;
4743 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4745 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4746 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4747 union kvm_mmu_role new_role =
4748 kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false);
4750 if (new_role.as_u64 == context->mmu_role.as_u64)
4753 context->mmu_role.as_u64 = new_role.as_u64;
4754 context->page_fault = kvm_tdp_page_fault;
4755 context->sync_page = nonpaging_sync_page;
4756 context->invlpg = NULL;
4757 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4758 context->direct_map = true;
4759 context->get_guest_pgd = get_cr3;
4760 context->get_pdptr = kvm_pdptr_read;
4761 context->inject_page_fault = kvm_inject_page_fault;
4762 context->root_level = role_regs_to_root_level(®s);
4764 if (!is_cr0_pg(context))
4765 context->gva_to_gpa = nonpaging_gva_to_gpa;
4766 else if (is_cr4_pae(context))
4767 context->gva_to_gpa = paging64_gva_to_gpa;
4769 context->gva_to_gpa = paging32_gva_to_gpa;
4771 reset_guest_paging_metadata(vcpu, context);
4772 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4775 static union kvm_mmu_role
4776 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4777 struct kvm_mmu_role_regs *regs, bool base_only)
4779 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4781 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4782 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
4783 role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs);
4788 static union kvm_mmu_role
4789 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4790 struct kvm_mmu_role_regs *regs, bool base_only)
4792 union kvm_mmu_role role =
4793 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
4795 role.base.direct = !____is_cr0_pg(regs);
4797 if (!____is_efer_lma(regs))
4798 role.base.level = PT32E_ROOT_LEVEL;
4799 else if (____is_cr4_la57(regs))
4800 role.base.level = PT64_ROOT_5LEVEL;
4802 role.base.level = PT64_ROOT_4LEVEL;
4807 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4808 struct kvm_mmu_role_regs *regs,
4809 union kvm_mmu_role new_role)
4811 if (new_role.as_u64 == context->mmu_role.as_u64)
4814 context->mmu_role.as_u64 = new_role.as_u64;
4816 if (!is_cr0_pg(context))
4817 nonpaging_init_context(context);
4818 else if (is_cr4_pae(context))
4819 paging64_init_context(context);
4821 paging32_init_context(context);
4822 context->root_level = role_regs_to_root_level(regs);
4824 reset_guest_paging_metadata(vcpu, context);
4825 context->shadow_root_level = new_role.base.level;
4827 reset_shadow_zero_bits_mask(vcpu, context);
4830 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4831 struct kvm_mmu_role_regs *regs)
4833 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4834 union kvm_mmu_role new_role =
4835 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
4837 shadow_mmu_init_context(vcpu, context, regs, new_role);
4840 static union kvm_mmu_role
4841 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4842 struct kvm_mmu_role_regs *regs)
4844 union kvm_mmu_role role =
4845 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4847 role.base.direct = false;
4848 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4853 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4854 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4856 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4857 struct kvm_mmu_role_regs regs = {
4859 .cr4 = cr4 & ~X86_CR4_PKE,
4862 union kvm_mmu_role new_role;
4864 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s);
4866 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4868 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4870 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4872 static union kvm_mmu_role
4873 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4874 bool execonly, u8 level)
4876 union kvm_mmu_role role = {0};
4878 /* SMM flag is inherited from root_mmu */
4879 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4881 role.base.level = level;
4882 role.base.gpte_is_8_bytes = true;
4883 role.base.direct = false;
4884 role.base.ad_disabled = !accessed_dirty;
4885 role.base.guest_mode = true;
4886 role.base.access = ACC_ALL;
4888 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4890 role.ext.execonly = execonly;
4896 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4897 bool accessed_dirty, gpa_t new_eptp)
4899 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4900 u8 level = vmx_eptp_page_walk_level(new_eptp);
4901 union kvm_mmu_role new_role =
4902 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4905 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4907 if (new_role.as_u64 == context->mmu_role.as_u64)
4910 context->mmu_role.as_u64 = new_role.as_u64;
4912 context->shadow_root_level = level;
4914 context->ept_ad = accessed_dirty;
4915 context->page_fault = ept_page_fault;
4916 context->gva_to_gpa = ept_gva_to_gpa;
4917 context->sync_page = ept_sync_page;
4918 context->invlpg = ept_invlpg;
4919 context->root_level = level;
4920 context->direct_map = false;
4922 update_permission_bitmask(context, true);
4923 context->pkru_mask = 0;
4924 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4925 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4927 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4929 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4931 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4932 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4934 kvm_init_shadow_mmu(vcpu, ®s);
4936 context->get_guest_pgd = get_cr3;
4937 context->get_pdptr = kvm_pdptr_read;
4938 context->inject_page_fault = kvm_inject_page_fault;
4941 static union kvm_mmu_role
4942 kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
4944 union kvm_mmu_role role;
4946 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4949 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4950 * shadow pages of their own and so "direct" has no meaning. Set it
4951 * to "true" to try to detect bogus usage of the nested MMU.
4953 role.base.direct = true;
4954 role.base.level = role_regs_to_root_level(regs);
4958 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4960 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4961 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s);
4962 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4964 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4967 g_context->mmu_role.as_u64 = new_role.as_u64;
4968 g_context->get_guest_pgd = get_cr3;
4969 g_context->get_pdptr = kvm_pdptr_read;
4970 g_context->inject_page_fault = kvm_inject_page_fault;
4971 g_context->root_level = new_role.base.level;
4974 * L2 page tables are never shadowed, so there is no need to sync
4977 g_context->invlpg = NULL;
4980 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4981 * L1's nested page tables (e.g. EPT12). The nested translation
4982 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4983 * L2's page tables as the first level of translation and L1's
4984 * nested page tables as the second level of translation. Basically
4985 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4987 if (!is_paging(vcpu))
4988 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4989 else if (is_long_mode(vcpu))
4990 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4991 else if (is_pae(vcpu))
4992 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4994 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4996 reset_guest_paging_metadata(vcpu, g_context);
4999 void kvm_init_mmu(struct kvm_vcpu *vcpu)
5001 if (mmu_is_nested(vcpu))
5002 init_kvm_nested_mmu(vcpu);
5003 else if (tdp_enabled)
5004 init_kvm_tdp_mmu(vcpu);
5006 init_kvm_softmmu(vcpu);
5008 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5010 static union kvm_mmu_page_role
5011 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5013 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
5014 union kvm_mmu_role role;
5017 role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true);
5019 role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true);
5024 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
5027 * Invalidate all MMU roles to force them to reinitialize as CPUID
5028 * information is factored into reserved bit calculations.
5030 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
5031 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
5032 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
5033 kvm_mmu_reset_context(vcpu);
5036 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
5037 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
5038 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
5039 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
5040 * sweep the problem under the rug.
5042 * KVM's horrific CPUID ABI makes the problem all but impossible to
5043 * solve, as correctly handling multiple vCPU models (with respect to
5044 * paging and physical address properties) in a single VM would require
5045 * tracking all relevant CPUID information in kvm_mmu_page_role. That
5046 * is very undesirable as it would double the memory requirements for
5047 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
5048 * no sane VMM mucks with the core vCPU model on the fly.
5050 if (vcpu->arch.last_vmentry_cpu != -1) {
5051 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
5052 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
5056 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5058 kvm_mmu_unload(vcpu);
5061 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5063 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5067 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
5070 r = mmu_alloc_special_roots(vcpu);
5073 if (vcpu->arch.mmu->direct_map)
5074 r = mmu_alloc_direct_roots(vcpu);
5076 r = mmu_alloc_shadow_roots(vcpu);
5080 kvm_mmu_sync_roots(vcpu);
5082 kvm_mmu_load_pgd(vcpu);
5083 static_call(kvm_x86_tlb_flush_current)(vcpu);
5088 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5090 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5091 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5092 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5093 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5096 static bool need_remote_flush(u64 old, u64 new)
5098 if (!is_shadow_present_pte(old))
5100 if (!is_shadow_present_pte(new))
5102 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5104 old ^= shadow_nx_mask;
5105 new ^= shadow_nx_mask;
5106 return (old & ~new & PT64_PERM_MASK) != 0;
5109 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5116 * Assume that the pte write on a page table of the same type
5117 * as the current vcpu paging mode since we update the sptes only
5118 * when they have the same mode.
5120 if (is_pae(vcpu) && *bytes == 4) {
5121 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5126 if (*bytes == 4 || *bytes == 8) {
5127 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5136 * If we're seeing too many writes to a page, it may no longer be a page table,
5137 * or we may be forking, in which case it is better to unmap the page.
5139 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5142 * Skip write-flooding detected for the sp whose level is 1, because
5143 * it can become unsync, then the guest page is not write-protected.
5145 if (sp->role.level == PG_LEVEL_4K)
5148 atomic_inc(&sp->write_flooding_count);
5149 return atomic_read(&sp->write_flooding_count) >= 3;
5153 * Misaligned accesses are too much trouble to fix up; also, they usually
5154 * indicate a page is not used as a page table.
5156 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5159 unsigned offset, pte_size, misaligned;
5161 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5162 gpa, bytes, sp->role.word);
5164 offset = offset_in_page(gpa);
5165 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5168 * Sometimes, the OS only writes the last one bytes to update status
5169 * bits, for example, in linux, andb instruction is used in clear_bit().
5171 if (!(offset & (pte_size - 1)) && bytes == 1)
5174 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5175 misaligned |= bytes < 4;
5180 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5182 unsigned page_offset, quadrant;
5186 page_offset = offset_in_page(gpa);
5187 level = sp->role.level;
5189 if (!sp->role.gpte_is_8_bytes) {
5190 page_offset <<= 1; /* 32->64 */
5192 * A 32-bit pde maps 4MB while the shadow pdes map
5193 * only 2MB. So we need to double the offset again
5194 * and zap two pdes instead of one.
5196 if (level == PT32_ROOT_LEVEL) {
5197 page_offset &= ~7; /* kill rounding error */
5201 quadrant = page_offset >> PAGE_SHIFT;
5202 page_offset &= ~PAGE_MASK;
5203 if (quadrant != sp->role.quadrant)
5207 spte = &sp->spt[page_offset / sizeof(*spte)];
5211 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5212 const u8 *new, int bytes,
5213 struct kvm_page_track_notifier_node *node)
5215 gfn_t gfn = gpa >> PAGE_SHIFT;
5216 struct kvm_mmu_page *sp;
5217 LIST_HEAD(invalid_list);
5218 u64 entry, gentry, *spte;
5220 bool remote_flush, local_flush;
5223 * If we don't have indirect shadow pages, it means no page is
5224 * write-protected, so we can exit simply.
5226 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5229 remote_flush = local_flush = false;
5231 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5234 * No need to care whether allocation memory is successful
5235 * or not since pte prefetch is skipped if it does not have
5236 * enough objects in the cache.
5238 mmu_topup_memory_caches(vcpu, true);
5240 write_lock(&vcpu->kvm->mmu_lock);
5242 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5244 ++vcpu->kvm->stat.mmu_pte_write;
5245 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5247 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5248 if (detect_write_misaligned(sp, gpa, bytes) ||
5249 detect_write_flooding(sp)) {
5250 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5251 ++vcpu->kvm->stat.mmu_flooded;
5255 spte = get_written_sptes(sp, gpa, &npte);
5262 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5263 if (gentry && sp->role.level != PG_LEVEL_4K)
5264 ++vcpu->kvm->stat.mmu_pde_zapped;
5265 if (need_remote_flush(entry, *spte))
5266 remote_flush = true;
5270 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5271 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5272 write_unlock(&vcpu->kvm->mmu_lock);
5275 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5276 void *insn, int insn_len)
5278 int r, emulation_type = EMULTYPE_PF;
5279 bool direct = vcpu->arch.mmu->direct_map;
5281 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5282 return RET_PF_RETRY;
5285 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5286 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5287 if (r == RET_PF_EMULATE)
5291 if (r == RET_PF_INVALID) {
5292 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5293 lower_32_bits(error_code), false);
5294 if (KVM_BUG_ON(r == RET_PF_INVALID, vcpu->kvm))
5300 if (r != RET_PF_EMULATE)
5304 * Before emulating the instruction, check if the error code
5305 * was due to a RO violation while translating the guest page.
5306 * This can occur when using nested virtualization with nested
5307 * paging in both guests. If true, we simply unprotect the page
5308 * and resume the guest.
5310 if (vcpu->arch.mmu->direct_map &&
5311 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5312 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5317 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5318 * optimistically try to just unprotect the page and let the processor
5319 * re-execute the instruction that caused the page fault. Do not allow
5320 * retrying MMIO emulation, as it's not only pointless but could also
5321 * cause us to enter an infinite loop because the processor will keep
5322 * faulting on the non-existent MMIO address. Retrying an instruction
5323 * from a nested guest is also pointless and dangerous as we are only
5324 * explicitly shadowing L1's page tables, i.e. unprotecting something
5325 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5327 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5328 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5330 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5333 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5335 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5336 gva_t gva, hpa_t root_hpa)
5340 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5341 if (mmu != &vcpu->arch.guest_mmu) {
5342 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5343 if (is_noncanonical_address(gva, vcpu))
5346 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5352 if (root_hpa == INVALID_PAGE) {
5353 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5356 * INVLPG is required to invalidate any global mappings for the VA,
5357 * irrespective of PCID. Since it would take us roughly similar amount
5358 * of work to determine whether any of the prev_root mappings of the VA
5359 * is marked global, or to just sync it blindly, so we might as well
5360 * just always sync it.
5362 * Mappings not reachable via the current cr3 or the prev_roots will be
5363 * synced when switching to that cr3, so nothing needs to be done here
5366 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5367 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5368 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5370 mmu->invlpg(vcpu, gva, root_hpa);
5374 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5376 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.walk_mmu, gva, INVALID_PAGE);
5377 ++vcpu->stat.invlpg;
5379 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5382 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5384 struct kvm_mmu *mmu = vcpu->arch.mmu;
5385 bool tlb_flush = false;
5388 if (pcid == kvm_get_active_pcid(vcpu)) {
5390 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5394 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5395 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5396 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5398 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5404 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5406 ++vcpu->stat.invlpg;
5409 * Mappings not reachable via the current cr3 or the prev_roots will be
5410 * synced when switching to that cr3, so nothing needs to be done here
5415 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
5416 int tdp_max_root_level, int tdp_huge_page_level)
5418 tdp_enabled = enable_tdp;
5419 tdp_root_level = tdp_forced_root_level;
5420 max_tdp_level = tdp_max_root_level;
5423 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5424 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5425 * the kernel is not. But, KVM never creates a page size greater than
5426 * what is used by the kernel for any given HVA, i.e. the kernel's
5427 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5430 max_huge_page_level = tdp_huge_page_level;
5431 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5432 max_huge_page_level = PG_LEVEL_1G;
5434 max_huge_page_level = PG_LEVEL_2M;
5436 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5438 /* The return value indicates if tlb flush on all vcpus is needed. */
5439 typedef bool (*slot_level_handler) (struct kvm *kvm,
5440 struct kvm_rmap_head *rmap_head,
5441 const struct kvm_memory_slot *slot);
5443 /* The caller should hold mmu-lock before calling this function. */
5444 static __always_inline bool
5445 slot_handle_level_range(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5446 slot_level_handler fn, int start_level, int end_level,
5447 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5450 struct slot_rmap_walk_iterator iterator;
5452 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5453 end_gfn, &iterator) {
5455 flush |= fn(kvm, iterator.rmap, memslot);
5457 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5458 if (flush && flush_on_yield) {
5459 kvm_flush_remote_tlbs_with_address(kvm,
5461 iterator.gfn - start_gfn + 1);
5464 cond_resched_rwlock_write(&kvm->mmu_lock);
5471 static __always_inline bool
5472 slot_handle_level(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5473 slot_level_handler fn, int start_level, int end_level,
5474 bool flush_on_yield)
5476 return slot_handle_level_range(kvm, memslot, fn, start_level,
5477 end_level, memslot->base_gfn,
5478 memslot->base_gfn + memslot->npages - 1,
5479 flush_on_yield, false);
5482 static __always_inline bool
5483 slot_handle_level_4k(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5484 slot_level_handler fn, bool flush_on_yield)
5486 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5487 PG_LEVEL_4K, flush_on_yield);
5490 static void free_mmu_pages(struct kvm_mmu *mmu)
5492 if (!tdp_enabled && mmu->pae_root)
5493 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5494 free_page((unsigned long)mmu->pae_root);
5495 free_page((unsigned long)mmu->pml4_root);
5496 free_page((unsigned long)mmu->pml5_root);
5499 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5504 mmu->root_hpa = INVALID_PAGE;
5506 mmu->translate_gpa = translate_gpa;
5507 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5508 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5511 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5512 * while the PDP table is a per-vCPU construct that's allocated at MMU
5513 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5514 * x86_64. Therefore we need to allocate the PDP table in the first
5515 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5516 * generally doesn't use PAE paging and can skip allocating the PDP
5517 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5518 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5519 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5521 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5524 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5528 mmu->pae_root = page_address(page);
5531 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5532 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5533 * that KVM's writes and the CPU's reads get along. Note, this is
5534 * only necessary when using shadow paging, as 64-bit NPT can get at
5535 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5536 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5539 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5541 WARN_ON_ONCE(shadow_me_mask);
5543 for (i = 0; i < 4; ++i)
5544 mmu->pae_root[i] = INVALID_PAE_ROOT;
5549 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5553 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5554 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5556 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5557 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5559 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5561 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5562 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5564 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5566 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5570 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5572 goto fail_allocate_root;
5576 free_mmu_pages(&vcpu->arch.guest_mmu);
5580 #define BATCH_ZAP_PAGES 10
5581 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5583 struct kvm_mmu_page *sp, *node;
5584 int nr_zapped, batch = 0;
5588 list_for_each_entry_safe_reverse(sp, node,
5589 &kvm->arch.active_mmu_pages, link) {
5591 * No obsolete valid page exists before a newly created page
5592 * since active_mmu_pages is a FIFO list.
5594 if (!is_obsolete_sp(kvm, sp))
5598 * Invalid pages should never land back on the list of active
5599 * pages. Skip the bogus page, otherwise we'll get stuck in an
5600 * infinite loop if the page gets put back on the list (again).
5602 if (WARN_ON(sp->role.invalid))
5606 * No need to flush the TLB since we're only zapping shadow
5607 * pages with an obsolete generation number and all vCPUS have
5608 * loaded a new root, i.e. the shadow pages being zapped cannot
5609 * be in active use by the guest.
5611 if (batch >= BATCH_ZAP_PAGES &&
5612 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5617 unstable = __kvm_mmu_prepare_zap_page(kvm, sp,
5618 &kvm->arch.zapped_obsolete_pages, &nr_zapped);
5626 * Trigger a remote TLB flush before freeing the page tables to ensure
5627 * KVM is not in the middle of a lockless shadow page table walk, which
5628 * may reference the pages.
5630 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5634 * Fast invalidate all shadow pages and use lock-break technique
5635 * to zap obsolete pages.
5637 * It's required when memslot is being deleted or VM is being
5638 * destroyed, in these cases, we should ensure that KVM MMU does
5639 * not use any resource of the being-deleted slot or all slots
5640 * after calling the function.
5642 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5644 lockdep_assert_held(&kvm->slots_lock);
5646 write_lock(&kvm->mmu_lock);
5647 trace_kvm_mmu_zap_all_fast(kvm);
5650 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5651 * held for the entire duration of zapping obsolete pages, it's
5652 * impossible for there to be multiple invalid generations associated
5653 * with *valid* shadow pages at any given time, i.e. there is exactly
5654 * one valid generation and (at most) one invalid generation.
5656 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5658 /* In order to ensure all threads see this change when
5659 * handling the MMU reload signal, this must happen in the
5660 * same critical section as kvm_reload_remote_mmus, and
5661 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5662 * could drop the MMU lock and yield.
5664 if (is_tdp_mmu_enabled(kvm))
5665 kvm_tdp_mmu_invalidate_all_roots(kvm);
5668 * Notify all vcpus to reload its shadow page table and flush TLB.
5669 * Then all vcpus will switch to new shadow page table with the new
5672 * Note: we need to do this under the protection of mmu_lock,
5673 * otherwise, vcpu would purge shadow page but miss tlb flush.
5675 kvm_reload_remote_mmus(kvm);
5677 kvm_zap_obsolete_pages(kvm);
5679 write_unlock(&kvm->mmu_lock);
5681 if (is_tdp_mmu_enabled(kvm)) {
5682 read_lock(&kvm->mmu_lock);
5683 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5684 read_unlock(&kvm->mmu_lock);
5688 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5690 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5693 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5694 struct kvm_memory_slot *slot,
5695 struct kvm_page_track_notifier_node *node)
5697 kvm_mmu_zap_all_fast(kvm);
5700 void kvm_mmu_init_vm(struct kvm *kvm)
5702 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5704 spin_lock_init(&kvm->arch.mmu_unsync_pages_lock);
5706 if (!kvm_mmu_init_tdp_mmu(kvm))
5708 * No smp_load/store wrappers needed here as we are in
5709 * VM init and there cannot be any memslots / other threads
5710 * accessing this struct kvm yet.
5712 kvm->arch.memslots_have_rmaps = true;
5714 node->track_write = kvm_mmu_pte_write;
5715 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5716 kvm_page_track_register_notifier(kvm, node);
5719 void kvm_mmu_uninit_vm(struct kvm *kvm)
5721 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5723 kvm_page_track_unregister_notifier(kvm, node);
5725 kvm_mmu_uninit_tdp_mmu(kvm);
5729 * Invalidate (zap) SPTEs that cover GFNs from gfn_start and up to gfn_end
5730 * (not including it)
5732 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5734 struct kvm_memslots *slots;
5735 struct kvm_memory_slot *memslot;
5739 write_lock(&kvm->mmu_lock);
5741 kvm_inc_notifier_count(kvm, gfn_start, gfn_end);
5743 if (kvm_memslots_have_rmaps(kvm)) {
5744 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5745 slots = __kvm_memslots(kvm, i);
5746 kvm_for_each_memslot(memslot, slots) {
5749 start = max(gfn_start, memslot->base_gfn);
5750 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5754 flush = slot_handle_level_range(kvm,
5755 (const struct kvm_memory_slot *) memslot,
5756 kvm_zap_rmapp, PG_LEVEL_4K,
5757 KVM_MAX_HUGEPAGE_LEVEL, start,
5758 end - 1, true, flush);
5762 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5763 gfn_end - gfn_start);
5766 if (is_tdp_mmu_enabled(kvm)) {
5767 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5768 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5773 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5774 gfn_end - gfn_start);
5776 kvm_dec_notifier_count(kvm, gfn_start, gfn_end);
5778 write_unlock(&kvm->mmu_lock);
5781 static bool slot_rmap_write_protect(struct kvm *kvm,
5782 struct kvm_rmap_head *rmap_head,
5783 const struct kvm_memory_slot *slot)
5785 return __rmap_write_protect(kvm, rmap_head, false);
5788 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5789 const struct kvm_memory_slot *memslot,
5794 if (kvm_memslots_have_rmaps(kvm)) {
5795 write_lock(&kvm->mmu_lock);
5796 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5797 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5799 write_unlock(&kvm->mmu_lock);
5802 if (is_tdp_mmu_enabled(kvm)) {
5803 read_lock(&kvm->mmu_lock);
5804 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5805 read_unlock(&kvm->mmu_lock);
5809 * We can flush all the TLBs out of the mmu lock without TLB
5810 * corruption since we just change the spte from writable to
5811 * readonly so that we only need to care the case of changing
5812 * spte from present to present (changing the spte from present
5813 * to nonpresent will flush all the TLBs immediately), in other
5814 * words, the only case we care is mmu_spte_update() where we
5815 * have checked Host-writable | MMU-writable instead of
5816 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5820 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5823 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5824 struct kvm_rmap_head *rmap_head,
5825 const struct kvm_memory_slot *slot)
5828 struct rmap_iterator iter;
5829 int need_tlb_flush = 0;
5831 struct kvm_mmu_page *sp;
5834 for_each_rmap_spte(rmap_head, &iter, sptep) {
5835 sp = sptep_to_sp(sptep);
5836 pfn = spte_to_pfn(*sptep);
5839 * We cannot do huge page mapping for indirect shadow pages,
5840 * which are found on the last rmap (level = 1) when not using
5841 * tdp; such shadow pages are synced with the page table in
5842 * the guest, and the guest page table is using 4K page size
5843 * mapping if the indirect sp has level = 1.
5845 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5846 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5847 pfn, PG_LEVEL_NUM)) {
5848 pte_list_remove(kvm, rmap_head, sptep);
5850 if (kvm_available_flush_tlb_with_range())
5851 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5852 KVM_PAGES_PER_HPAGE(sp->role.level));
5860 return need_tlb_flush;
5863 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5864 const struct kvm_memory_slot *slot)
5866 if (kvm_memslots_have_rmaps(kvm)) {
5867 write_lock(&kvm->mmu_lock);
5869 * Zap only 4k SPTEs since the legacy MMU only supports dirty
5870 * logging at a 4k granularity and never creates collapsible
5871 * 2m SPTEs during dirty logging.
5873 if (slot_handle_level_4k(kvm, slot, kvm_mmu_zap_collapsible_spte, true))
5874 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5875 write_unlock(&kvm->mmu_lock);
5878 if (is_tdp_mmu_enabled(kvm)) {
5879 read_lock(&kvm->mmu_lock);
5880 kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot);
5881 read_unlock(&kvm->mmu_lock);
5885 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5886 const struct kvm_memory_slot *memslot)
5889 * All current use cases for flushing the TLBs for a specific memslot
5890 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5891 * The interaction between the various operations on memslot must be
5892 * serialized by slots_locks to ensure the TLB flush from one operation
5893 * is observed by any other operation on the same memslot.
5895 lockdep_assert_held(&kvm->slots_lock);
5896 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5900 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5901 const struct kvm_memory_slot *memslot)
5905 if (kvm_memslots_have_rmaps(kvm)) {
5906 write_lock(&kvm->mmu_lock);
5908 * Clear dirty bits only on 4k SPTEs since the legacy MMU only
5909 * support dirty logging at a 4k granularity.
5911 flush = slot_handle_level_4k(kvm, memslot, __rmap_clear_dirty, false);
5912 write_unlock(&kvm->mmu_lock);
5915 if (is_tdp_mmu_enabled(kvm)) {
5916 read_lock(&kvm->mmu_lock);
5917 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5918 read_unlock(&kvm->mmu_lock);
5922 * It's also safe to flush TLBs out of mmu lock here as currently this
5923 * function is only used for dirty logging, in which case flushing TLB
5924 * out of mmu lock also guarantees no dirty pages will be lost in
5928 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5931 void kvm_mmu_zap_all(struct kvm *kvm)
5933 struct kvm_mmu_page *sp, *node;
5934 LIST_HEAD(invalid_list);
5937 write_lock(&kvm->mmu_lock);
5939 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5940 if (WARN_ON(sp->role.invalid))
5942 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5944 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5948 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5950 if (is_tdp_mmu_enabled(kvm))
5951 kvm_tdp_mmu_zap_all(kvm);
5953 write_unlock(&kvm->mmu_lock);
5956 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5958 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5960 gen &= MMIO_SPTE_GEN_MASK;
5963 * Generation numbers are incremented in multiples of the number of
5964 * address spaces in order to provide unique generations across all
5965 * address spaces. Strip what is effectively the address space
5966 * modifier prior to checking for a wrap of the MMIO generation so
5967 * that a wrap in any address space is detected.
5969 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5972 * The very rare case: if the MMIO generation number has wrapped,
5973 * zap all shadow pages.
5975 if (unlikely(gen == 0)) {
5976 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5977 kvm_mmu_zap_all_fast(kvm);
5981 static unsigned long
5982 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5985 int nr_to_scan = sc->nr_to_scan;
5986 unsigned long freed = 0;
5988 mutex_lock(&kvm_lock);
5990 list_for_each_entry(kvm, &vm_list, vm_list) {
5992 LIST_HEAD(invalid_list);
5995 * Never scan more than sc->nr_to_scan VM instances.
5996 * Will not hit this condition practically since we do not try
5997 * to shrink more than one VM and it is very unlikely to see
5998 * !n_used_mmu_pages so many times.
6003 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6004 * here. We may skip a VM instance errorneosly, but we do not
6005 * want to shrink a VM that only started to populate its MMU
6008 if (!kvm->arch.n_used_mmu_pages &&
6009 !kvm_has_zapped_obsolete_pages(kvm))
6012 idx = srcu_read_lock(&kvm->srcu);
6013 write_lock(&kvm->mmu_lock);
6015 if (kvm_has_zapped_obsolete_pages(kvm)) {
6016 kvm_mmu_commit_zap_page(kvm,
6017 &kvm->arch.zapped_obsolete_pages);
6021 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
6024 write_unlock(&kvm->mmu_lock);
6025 srcu_read_unlock(&kvm->srcu, idx);
6028 * unfair on small ones
6029 * per-vm shrinkers cry out
6030 * sadness comes quickly
6032 list_move_tail(&kvm->vm_list, &vm_list);
6036 mutex_unlock(&kvm_lock);
6040 static unsigned long
6041 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
6043 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
6046 static struct shrinker mmu_shrinker = {
6047 .count_objects = mmu_shrink_count,
6048 .scan_objects = mmu_shrink_scan,
6049 .seeks = DEFAULT_SEEKS * 10,
6052 static void mmu_destroy_caches(void)
6054 kmem_cache_destroy(pte_list_desc_cache);
6055 kmem_cache_destroy(mmu_page_header_cache);
6058 static bool get_nx_auto_mode(void)
6060 /* Return true when CPU has the bug, and mitigations are ON */
6061 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
6064 static void __set_nx_huge_pages(bool val)
6066 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
6069 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
6071 bool old_val = nx_huge_pages;
6074 /* In "auto" mode deploy workaround only if CPU has the bug. */
6075 if (sysfs_streq(val, "off"))
6077 else if (sysfs_streq(val, "force"))
6079 else if (sysfs_streq(val, "auto"))
6080 new_val = get_nx_auto_mode();
6081 else if (strtobool(val, &new_val) < 0)
6084 __set_nx_huge_pages(new_val);
6086 if (new_val != old_val) {
6089 mutex_lock(&kvm_lock);
6091 list_for_each_entry(kvm, &vm_list, vm_list) {
6092 mutex_lock(&kvm->slots_lock);
6093 kvm_mmu_zap_all_fast(kvm);
6094 mutex_unlock(&kvm->slots_lock);
6096 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6098 mutex_unlock(&kvm_lock);
6105 * nx_huge_pages needs to be resolved to true/false when kvm.ko is loaded, as
6106 * its default value of -1 is technically undefined behavior for a boolean.
6108 void __init kvm_mmu_x86_module_init(void)
6110 if (nx_huge_pages == -1)
6111 __set_nx_huge_pages(get_nx_auto_mode());
6115 * The bulk of the MMU initialization is deferred until the vendor module is
6116 * loaded as many of the masks/values may be modified by VMX or SVM, i.e. need
6117 * to be reset when a potentially different vendor module is loaded.
6119 int kvm_mmu_vendor_module_init(void)
6124 * MMU roles use union aliasing which is, generally speaking, an
6125 * undefined behavior. However, we supposedly know how compilers behave
6126 * and the current status quo is unlikely to change. Guardians below are
6127 * supposed to let us know if the assumption becomes false.
6129 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6130 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6131 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6133 kvm_mmu_reset_all_pte_masks();
6135 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6136 sizeof(struct pte_list_desc),
6137 0, SLAB_ACCOUNT, NULL);
6138 if (!pte_list_desc_cache)
6141 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6142 sizeof(struct kvm_mmu_page),
6143 0, SLAB_ACCOUNT, NULL);
6144 if (!mmu_page_header_cache)
6147 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6150 ret = register_shrinker(&mmu_shrinker);
6157 mmu_destroy_caches();
6162 * Calculate mmu pages needed for kvm.
6164 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6166 unsigned long nr_mmu_pages;
6167 unsigned long nr_pages = 0;
6168 struct kvm_memslots *slots;
6169 struct kvm_memory_slot *memslot;
6172 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6173 slots = __kvm_memslots(kvm, i);
6175 kvm_for_each_memslot(memslot, slots)
6176 nr_pages += memslot->npages;
6179 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6180 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6182 return nr_mmu_pages;
6185 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6187 kvm_mmu_unload(vcpu);
6188 free_mmu_pages(&vcpu->arch.root_mmu);
6189 free_mmu_pages(&vcpu->arch.guest_mmu);
6190 mmu_free_memory_caches(vcpu);
6193 void kvm_mmu_vendor_module_exit(void)
6195 mmu_destroy_caches();
6196 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6197 unregister_shrinker(&mmu_shrinker);
6198 mmu_audit_disable();
6201 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6203 unsigned int old_val;
6206 old_val = nx_huge_pages_recovery_ratio;
6207 err = param_set_uint(val, kp);
6211 if (READ_ONCE(nx_huge_pages) &&
6212 !old_val && nx_huge_pages_recovery_ratio) {
6215 mutex_lock(&kvm_lock);
6217 list_for_each_entry(kvm, &vm_list, vm_list)
6218 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6220 mutex_unlock(&kvm_lock);
6226 static void kvm_recover_nx_lpages(struct kvm *kvm)
6228 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6230 struct kvm_mmu_page *sp;
6232 LIST_HEAD(invalid_list);
6236 rcu_idx = srcu_read_lock(&kvm->srcu);
6237 write_lock(&kvm->mmu_lock);
6239 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6240 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6241 for ( ; to_zap; --to_zap) {
6242 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6246 * We use a separate list instead of just using active_mmu_pages
6247 * because the number of lpage_disallowed pages is expected to
6248 * be relatively small compared to the total.
6250 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6251 struct kvm_mmu_page,
6252 lpage_disallowed_link);
6253 WARN_ON_ONCE(!sp->lpage_disallowed);
6254 if (is_tdp_mmu_page(sp)) {
6255 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6257 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6258 WARN_ON_ONCE(sp->lpage_disallowed);
6261 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6262 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6263 cond_resched_rwlock_write(&kvm->mmu_lock);
6267 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6269 write_unlock(&kvm->mmu_lock);
6270 srcu_read_unlock(&kvm->srcu, rcu_idx);
6273 static long get_nx_lpage_recovery_timeout(u64 start_time)
6275 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6276 ? start_time + 60 * HZ - get_jiffies_64()
6277 : MAX_SCHEDULE_TIMEOUT;
6280 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6283 long remaining_time;
6286 start_time = get_jiffies_64();
6287 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6289 set_current_state(TASK_INTERRUPTIBLE);
6290 while (!kthread_should_stop() && remaining_time > 0) {
6291 schedule_timeout(remaining_time);
6292 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6293 set_current_state(TASK_INTERRUPTIBLE);
6296 set_current_state(TASK_RUNNING);
6298 if (kthread_should_stop())
6301 kvm_recover_nx_lpages(kvm);
6305 int kvm_mmu_post_init_vm(struct kvm *kvm)
6309 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6310 "kvm-nx-lpage-recovery",
6311 &kvm->arch.nx_lpage_recovery_thread);
6313 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6318 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6320 if (kvm->arch.nx_lpage_recovery_thread)
6321 kthread_stop(kvm->arch.nx_lpage_recovery_thread);