1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
52 #include <asm/kvm_page_track.h>
57 extern bool itlb_multihit_kvm_mitigation;
59 static int __read_mostly nx_huge_pages = -1;
60 #ifdef CONFIG_PREEMPT_RT
61 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
62 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
64 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
67 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
68 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
70 static const struct kernel_param_ops nx_huge_pages_ops = {
71 .set = set_nx_huge_pages,
72 .get = param_get_bool,
75 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
76 .set = set_nx_huge_pages_recovery_ratio,
77 .get = param_get_uint,
80 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
81 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
82 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
83 &nx_huge_pages_recovery_ratio, 0644);
84 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
86 static bool __read_mostly force_flush_and_sync_on_reuse;
87 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
90 * When setting this variable to true it enables Two-Dimensional-Paging
91 * where the hardware walks 2 page tables:
92 * 1. the guest-virtual to guest-physical
93 * 2. while doing 1. it walks guest-physical to host-physical
94 * If the hardware supports that we don't need to do shadow paging.
96 bool tdp_enabled = false;
98 static int max_huge_page_level __read_mostly;
99 static int max_tdp_level __read_mostly;
102 AUDIT_PRE_PAGE_FAULT,
103 AUDIT_POST_PAGE_FAULT,
105 AUDIT_POST_PTE_WRITE,
112 module_param(dbg, bool, 0644);
115 #define PTE_PREFETCH_NUM 8
117 #define PT32_LEVEL_BITS 10
119 #define PT32_LEVEL_SHIFT(level) \
120 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
122 #define PT32_LVL_OFFSET_MASK(level) \
123 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
126 #define PT32_INDEX(address, level)\
127 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
130 #define PT32_BASE_ADDR_MASK PAGE_MASK
131 #define PT32_DIR_BASE_ADDR_MASK \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
133 #define PT32_LVL_ADDR_MASK(level) \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT32_LEVEL_BITS))) - 1))
137 #include <trace/events/kvm.h>
139 /* make pte_list_desc fit well in cache line */
140 #define PTE_LIST_EXT 3
142 struct pte_list_desc {
143 u64 *sptes[PTE_LIST_EXT];
144 struct pte_list_desc *more;
147 struct kvm_shadow_walk_iterator {
155 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
156 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
158 shadow_walk_okay(&(_walker)); \
159 shadow_walk_next(&(_walker)))
161 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
162 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
163 shadow_walk_okay(&(_walker)); \
164 shadow_walk_next(&(_walker)))
166 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
167 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
168 shadow_walk_okay(&(_walker)) && \
169 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
170 __shadow_walk_next(&(_walker), spte))
172 static struct kmem_cache *pte_list_desc_cache;
173 struct kmem_cache *mmu_page_header_cache;
174 static struct percpu_counter kvm_total_used_mmu_pages;
176 static void mmu_spte_set(u64 *sptep, u64 spte);
177 static union kvm_mmu_page_role
178 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
180 #define CREATE_TRACE_POINTS
181 #include "mmutrace.h"
184 static inline bool kvm_available_flush_tlb_with_range(void)
186 return kvm_x86_ops.tlb_remote_flush_with_range;
189 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
190 struct kvm_tlb_range *range)
194 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
195 ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range);
198 kvm_flush_remote_tlbs(kvm);
201 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
202 u64 start_gfn, u64 pages)
204 struct kvm_tlb_range range;
206 range.start_gfn = start_gfn;
209 kvm_flush_remote_tlbs_with_range(kvm, &range);
212 bool is_nx_huge_page_enabled(void)
214 return READ_ONCE(nx_huge_pages);
217 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
220 u64 mask = make_mmio_spte(vcpu, gfn, access);
222 trace_mark_mmio_spte(sptep, gfn, mask);
223 mmu_spte_set(sptep, mask);
226 static gfn_t get_mmio_spte_gfn(u64 spte)
228 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
230 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
231 & shadow_nonpresent_or_rsvd_mask;
233 return gpa >> PAGE_SHIFT;
236 static unsigned get_mmio_spte_access(u64 spte)
238 return spte & shadow_mmio_access_mask;
241 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
242 kvm_pfn_t pfn, unsigned int access)
244 if (unlikely(is_noslot_pfn(pfn))) {
245 mark_mmio_spte(vcpu, sptep, gfn, access);
252 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
254 u64 kvm_gen, spte_gen, gen;
256 gen = kvm_vcpu_memslots(vcpu)->generation;
257 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
260 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
261 spte_gen = get_mmio_spte_generation(spte);
263 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
264 return likely(kvm_gen == spte_gen);
267 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
268 struct x86_exception *exception)
273 static int is_cpuid_PSE36(void)
278 static int is_nx(struct kvm_vcpu *vcpu)
280 return vcpu->arch.efer & EFER_NX;
283 static gfn_t pse36_gfn_delta(u32 gpte)
285 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
287 return (gpte & PT32_DIR_PSE36_MASK) << shift;
291 static void __set_spte(u64 *sptep, u64 spte)
293 WRITE_ONCE(*sptep, spte);
296 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
298 WRITE_ONCE(*sptep, spte);
301 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
303 return xchg(sptep, spte);
306 static u64 __get_spte_lockless(u64 *sptep)
308 return READ_ONCE(*sptep);
319 static void count_spte_clear(u64 *sptep, u64 spte)
321 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
323 if (is_shadow_present_pte(spte))
326 /* Ensure the spte is completely set before we increase the count */
328 sp->clear_spte_count++;
331 static void __set_spte(u64 *sptep, u64 spte)
333 union split_spte *ssptep, sspte;
335 ssptep = (union split_spte *)sptep;
336 sspte = (union split_spte)spte;
338 ssptep->spte_high = sspte.spte_high;
341 * If we map the spte from nonpresent to present, We should store
342 * the high bits firstly, then set present bit, so cpu can not
343 * fetch this spte while we are setting the spte.
347 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
350 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
352 union split_spte *ssptep, sspte;
354 ssptep = (union split_spte *)sptep;
355 sspte = (union split_spte)spte;
357 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
360 * If we map the spte from present to nonpresent, we should clear
361 * present bit firstly to avoid vcpu fetch the old high bits.
365 ssptep->spte_high = sspte.spte_high;
366 count_spte_clear(sptep, spte);
369 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
371 union split_spte *ssptep, sspte, orig;
373 ssptep = (union split_spte *)sptep;
374 sspte = (union split_spte)spte;
376 /* xchg acts as a barrier before the setting of the high bits */
377 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
378 orig.spte_high = ssptep->spte_high;
379 ssptep->spte_high = sspte.spte_high;
380 count_spte_clear(sptep, spte);
386 * The idea using the light way get the spte on x86_32 guest is from
387 * gup_get_pte (mm/gup.c).
389 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
390 * coalesces them and we are running out of the MMU lock. Therefore
391 * we need to protect against in-progress updates of the spte.
393 * Reading the spte while an update is in progress may get the old value
394 * for the high part of the spte. The race is fine for a present->non-present
395 * change (because the high part of the spte is ignored for non-present spte),
396 * but for a present->present change we must reread the spte.
398 * All such changes are done in two steps (present->non-present and
399 * non-present->present), hence it is enough to count the number of
400 * present->non-present updates: if it changed while reading the spte,
401 * we might have hit the race. This is done using clear_spte_count.
403 static u64 __get_spte_lockless(u64 *sptep)
405 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
406 union split_spte spte, *orig = (union split_spte *)sptep;
410 count = sp->clear_spte_count;
413 spte.spte_low = orig->spte_low;
416 spte.spte_high = orig->spte_high;
419 if (unlikely(spte.spte_low != orig->spte_low ||
420 count != sp->clear_spte_count))
427 static bool spte_has_volatile_bits(u64 spte)
429 if (!is_shadow_present_pte(spte))
433 * Always atomically update spte if it can be updated
434 * out of mmu-lock, it can ensure dirty bit is not lost,
435 * also, it can help us to get a stable is_writable_pte()
436 * to ensure tlb flush is not missed.
438 if (spte_can_locklessly_be_made_writable(spte) ||
439 is_access_track_spte(spte))
442 if (spte_ad_enabled(spte)) {
443 if ((spte & shadow_accessed_mask) == 0 ||
444 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
451 /* Rules for using mmu_spte_set:
452 * Set the sptep from nonpresent to present.
453 * Note: the sptep being assigned *must* be either not present
454 * or in a state where the hardware will not attempt to update
457 static void mmu_spte_set(u64 *sptep, u64 new_spte)
459 WARN_ON(is_shadow_present_pte(*sptep));
460 __set_spte(sptep, new_spte);
464 * Update the SPTE (excluding the PFN), but do not track changes in its
465 * accessed/dirty status.
467 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
469 u64 old_spte = *sptep;
471 WARN_ON(!is_shadow_present_pte(new_spte));
473 if (!is_shadow_present_pte(old_spte)) {
474 mmu_spte_set(sptep, new_spte);
478 if (!spte_has_volatile_bits(old_spte))
479 __update_clear_spte_fast(sptep, new_spte);
481 old_spte = __update_clear_spte_slow(sptep, new_spte);
483 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
488 /* Rules for using mmu_spte_update:
489 * Update the state bits, it means the mapped pfn is not changed.
491 * Whenever we overwrite a writable spte with a read-only one we
492 * should flush remote TLBs. Otherwise rmap_write_protect
493 * will find a read-only spte, even though the writable spte
494 * might be cached on a CPU's TLB, the return value indicates this
497 * Returns true if the TLB needs to be flushed
499 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
502 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
504 if (!is_shadow_present_pte(old_spte))
508 * For the spte updated out of mmu-lock is safe, since
509 * we always atomically update it, see the comments in
510 * spte_has_volatile_bits().
512 if (spte_can_locklessly_be_made_writable(old_spte) &&
513 !is_writable_pte(new_spte))
517 * Flush TLB when accessed/dirty states are changed in the page tables,
518 * to guarantee consistency between TLB and page tables.
521 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
523 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
526 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
528 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
535 * Rules for using mmu_spte_clear_track_bits:
536 * It sets the sptep from present to nonpresent, and track the
537 * state bits, it is used to clear the last level sptep.
538 * Returns non-zero if the PTE was previously valid.
540 static int mmu_spte_clear_track_bits(u64 *sptep)
543 u64 old_spte = *sptep;
545 if (!spte_has_volatile_bits(old_spte))
546 __update_clear_spte_fast(sptep, 0ull);
548 old_spte = __update_clear_spte_slow(sptep, 0ull);
550 if (!is_shadow_present_pte(old_spte))
553 pfn = spte_to_pfn(old_spte);
556 * KVM does not hold the refcount of the page used by
557 * kvm mmu, before reclaiming the page, we should
558 * unmap it from mmu first.
560 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
562 if (is_accessed_spte(old_spte))
563 kvm_set_pfn_accessed(pfn);
565 if (is_dirty_spte(old_spte))
566 kvm_set_pfn_dirty(pfn);
572 * Rules for using mmu_spte_clear_no_track:
573 * Directly clear spte without caring the state bits of sptep,
574 * it is used to set the upper level spte.
576 static void mmu_spte_clear_no_track(u64 *sptep)
578 __update_clear_spte_fast(sptep, 0ull);
581 static u64 mmu_spte_get_lockless(u64 *sptep)
583 return __get_spte_lockless(sptep);
586 /* Restore an acc-track PTE back to a regular PTE */
587 static u64 restore_acc_track_spte(u64 spte)
590 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
591 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
593 WARN_ON_ONCE(spte_ad_enabled(spte));
594 WARN_ON_ONCE(!is_access_track_spte(spte));
596 new_spte &= ~shadow_acc_track_mask;
597 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
598 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
599 new_spte |= saved_bits;
604 /* Returns the Accessed status of the PTE and resets it at the same time. */
605 static bool mmu_spte_age(u64 *sptep)
607 u64 spte = mmu_spte_get_lockless(sptep);
609 if (!is_accessed_spte(spte))
612 if (spte_ad_enabled(spte)) {
613 clear_bit((ffs(shadow_accessed_mask) - 1),
614 (unsigned long *)sptep);
617 * Capture the dirty status of the page, so that it doesn't get
618 * lost when the SPTE is marked for access tracking.
620 if (is_writable_pte(spte))
621 kvm_set_pfn_dirty(spte_to_pfn(spte));
623 spte = mark_spte_for_access_track(spte);
624 mmu_spte_update_no_track(sptep, spte);
630 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
633 * Prevent page table teardown by making any free-er wait during
634 * kvm_flush_remote_tlbs() IPI to all active vcpus.
639 * Make sure a following spte read is not reordered ahead of the write
642 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
645 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
648 * Make sure the write to vcpu->mode is not reordered in front of
649 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
650 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
652 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
656 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
660 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
661 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
662 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
665 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
666 PT64_ROOT_MAX_LEVEL);
669 if (maybe_indirect) {
670 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
671 PT64_ROOT_MAX_LEVEL);
675 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
676 PT64_ROOT_MAX_LEVEL);
679 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
681 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
682 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
683 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
684 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
687 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
689 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
692 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
694 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
697 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
699 if (!sp->role.direct)
700 return sp->gfns[index];
702 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
705 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
707 if (!sp->role.direct) {
708 sp->gfns[index] = gfn;
712 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
713 pr_err_ratelimited("gfn mismatch under direct page %llx "
714 "(expected %llx, got %llx)\n",
716 kvm_mmu_page_get_gfn(sp, index), gfn);
720 * Return the pointer to the large page information for a given gfn,
721 * handling slots that are not large page aligned.
723 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
724 struct kvm_memory_slot *slot,
729 idx = gfn_to_index(gfn, slot->base_gfn, level);
730 return &slot->arch.lpage_info[level - 2][idx];
733 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
734 gfn_t gfn, int count)
736 struct kvm_lpage_info *linfo;
739 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
740 linfo = lpage_info_slot(gfn, slot, i);
741 linfo->disallow_lpage += count;
742 WARN_ON(linfo->disallow_lpage < 0);
746 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
748 update_gfn_disallow_lpage_count(slot, gfn, 1);
751 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
753 update_gfn_disallow_lpage_count(slot, gfn, -1);
756 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
758 struct kvm_memslots *slots;
759 struct kvm_memory_slot *slot;
762 kvm->arch.indirect_shadow_pages++;
764 slots = kvm_memslots_for_spte_role(kvm, sp->role);
765 slot = __gfn_to_memslot(slots, gfn);
767 /* the non-leaf shadow pages are keeping readonly. */
768 if (sp->role.level > PG_LEVEL_4K)
769 return kvm_slot_page_track_add_page(kvm, slot, gfn,
770 KVM_PAGE_TRACK_WRITE);
772 kvm_mmu_gfn_disallow_lpage(slot, gfn);
775 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
777 if (sp->lpage_disallowed)
780 ++kvm->stat.nx_lpage_splits;
781 list_add_tail(&sp->lpage_disallowed_link,
782 &kvm->arch.lpage_disallowed_mmu_pages);
783 sp->lpage_disallowed = true;
786 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
788 struct kvm_memslots *slots;
789 struct kvm_memory_slot *slot;
792 kvm->arch.indirect_shadow_pages--;
794 slots = kvm_memslots_for_spte_role(kvm, sp->role);
795 slot = __gfn_to_memslot(slots, gfn);
796 if (sp->role.level > PG_LEVEL_4K)
797 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
798 KVM_PAGE_TRACK_WRITE);
800 kvm_mmu_gfn_allow_lpage(slot, gfn);
803 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
805 --kvm->stat.nx_lpage_splits;
806 sp->lpage_disallowed = false;
807 list_del(&sp->lpage_disallowed_link);
810 static struct kvm_memory_slot *
811 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
814 struct kvm_memory_slot *slot;
816 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
817 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
819 if (no_dirty_log && slot->dirty_bitmap)
826 * About rmap_head encoding:
828 * If the bit zero of rmap_head->val is clear, then it points to the only spte
829 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
830 * pte_list_desc containing more mappings.
834 * Returns the number of pointers in the rmap chain, not counting the new one.
836 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
837 struct kvm_rmap_head *rmap_head)
839 struct pte_list_desc *desc;
842 if (!rmap_head->val) {
843 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
844 rmap_head->val = (unsigned long)spte;
845 } else if (!(rmap_head->val & 1)) {
846 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
847 desc = mmu_alloc_pte_list_desc(vcpu);
848 desc->sptes[0] = (u64 *)rmap_head->val;
849 desc->sptes[1] = spte;
850 rmap_head->val = (unsigned long)desc | 1;
853 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
854 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
855 while (desc->sptes[PTE_LIST_EXT-1]) {
856 count += PTE_LIST_EXT;
859 desc->more = mmu_alloc_pte_list_desc(vcpu);
865 for (i = 0; desc->sptes[i]; ++i)
867 desc->sptes[i] = spte;
873 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
874 struct pte_list_desc *desc, int i,
875 struct pte_list_desc *prev_desc)
879 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
881 desc->sptes[i] = desc->sptes[j];
882 desc->sptes[j] = NULL;
885 if (!prev_desc && !desc->more)
889 prev_desc->more = desc->more;
891 rmap_head->val = (unsigned long)desc->more | 1;
892 mmu_free_pte_list_desc(desc);
895 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
897 struct pte_list_desc *desc;
898 struct pte_list_desc *prev_desc;
901 if (!rmap_head->val) {
902 pr_err("%s: %p 0->BUG\n", __func__, spte);
904 } else if (!(rmap_head->val & 1)) {
905 rmap_printk("%s: %p 1->0\n", __func__, spte);
906 if ((u64 *)rmap_head->val != spte) {
907 pr_err("%s: %p 1->BUG\n", __func__, spte);
912 rmap_printk("%s: %p many->many\n", __func__, spte);
913 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
916 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
917 if (desc->sptes[i] == spte) {
918 pte_list_desc_remove_entry(rmap_head,
926 pr_err("%s: %p many->many\n", __func__, spte);
931 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
933 mmu_spte_clear_track_bits(sptep);
934 __pte_list_remove(sptep, rmap_head);
937 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
938 struct kvm_memory_slot *slot)
942 idx = gfn_to_index(gfn, slot->base_gfn, level);
943 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
946 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
947 struct kvm_mmu_page *sp)
949 struct kvm_memslots *slots;
950 struct kvm_memory_slot *slot;
952 slots = kvm_memslots_for_spte_role(kvm, sp->role);
953 slot = __gfn_to_memslot(slots, gfn);
954 return __gfn_to_rmap(gfn, sp->role.level, slot);
957 static bool rmap_can_add(struct kvm_vcpu *vcpu)
959 struct kvm_mmu_memory_cache *mc;
961 mc = &vcpu->arch.mmu_pte_list_desc_cache;
962 return kvm_mmu_memory_cache_nr_free_objects(mc);
965 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
967 struct kvm_mmu_page *sp;
968 struct kvm_rmap_head *rmap_head;
970 sp = sptep_to_sp(spte);
971 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
972 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
973 return pte_list_add(vcpu, spte, rmap_head);
976 static void rmap_remove(struct kvm *kvm, u64 *spte)
978 struct kvm_mmu_page *sp;
980 struct kvm_rmap_head *rmap_head;
982 sp = sptep_to_sp(spte);
983 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
984 rmap_head = gfn_to_rmap(kvm, gfn, sp);
985 __pte_list_remove(spte, rmap_head);
989 * Used by the following functions to iterate through the sptes linked by a
990 * rmap. All fields are private and not assumed to be used outside.
992 struct rmap_iterator {
994 struct pte_list_desc *desc; /* holds the sptep if not NULL */
995 int pos; /* index of the sptep */
999 * Iteration must be started by this function. This should also be used after
1000 * removing/dropping sptes from the rmap link because in such cases the
1001 * information in the iterator may not be valid.
1003 * Returns sptep if found, NULL otherwise.
1005 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1006 struct rmap_iterator *iter)
1010 if (!rmap_head->val)
1013 if (!(rmap_head->val & 1)) {
1015 sptep = (u64 *)rmap_head->val;
1019 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1021 sptep = iter->desc->sptes[iter->pos];
1023 BUG_ON(!is_shadow_present_pte(*sptep));
1028 * Must be used with a valid iterator: e.g. after rmap_get_first().
1030 * Returns sptep if found, NULL otherwise.
1032 static u64 *rmap_get_next(struct rmap_iterator *iter)
1037 if (iter->pos < PTE_LIST_EXT - 1) {
1039 sptep = iter->desc->sptes[iter->pos];
1044 iter->desc = iter->desc->more;
1048 /* desc->sptes[0] cannot be NULL */
1049 sptep = iter->desc->sptes[iter->pos];
1056 BUG_ON(!is_shadow_present_pte(*sptep));
1060 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1061 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1062 _spte_; _spte_ = rmap_get_next(_iter_))
1064 static void drop_spte(struct kvm *kvm, u64 *sptep)
1066 if (mmu_spte_clear_track_bits(sptep))
1067 rmap_remove(kvm, sptep);
1071 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1073 if (is_large_pte(*sptep)) {
1074 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1075 drop_spte(kvm, sptep);
1083 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1085 if (__drop_large_spte(vcpu->kvm, sptep)) {
1086 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1088 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1089 KVM_PAGES_PER_HPAGE(sp->role.level));
1094 * Write-protect on the specified @sptep, @pt_protect indicates whether
1095 * spte write-protection is caused by protecting shadow page table.
1097 * Note: write protection is difference between dirty logging and spte
1099 * - for dirty logging, the spte can be set to writable at anytime if
1100 * its dirty bitmap is properly set.
1101 * - for spte protection, the spte can be writable only after unsync-ing
1104 * Return true if tlb need be flushed.
1106 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1110 if (!is_writable_pte(spte) &&
1111 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1114 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1117 spte &= ~SPTE_MMU_WRITEABLE;
1118 spte = spte & ~PT_WRITABLE_MASK;
1120 return mmu_spte_update(sptep, spte);
1123 static bool __rmap_write_protect(struct kvm *kvm,
1124 struct kvm_rmap_head *rmap_head,
1128 struct rmap_iterator iter;
1131 for_each_rmap_spte(rmap_head, &iter, sptep)
1132 flush |= spte_write_protect(sptep, pt_protect);
1137 static bool spte_clear_dirty(u64 *sptep)
1141 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1143 MMU_WARN_ON(!spte_ad_enabled(spte));
1144 spte &= ~shadow_dirty_mask;
1145 return mmu_spte_update(sptep, spte);
1148 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1150 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1151 (unsigned long *)sptep);
1152 if (was_writable && !spte_ad_enabled(*sptep))
1153 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1155 return was_writable;
1159 * Gets the GFN ready for another round of dirty logging by clearing the
1160 * - D bit on ad-enabled SPTEs, and
1161 * - W bit on ad-disabled SPTEs.
1162 * Returns true iff any D or W bits were cleared.
1164 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1167 struct rmap_iterator iter;
1170 for_each_rmap_spte(rmap_head, &iter, sptep)
1171 if (spte_ad_need_write_protect(*sptep))
1172 flush |= spte_wrprot_for_clear_dirty(sptep);
1174 flush |= spte_clear_dirty(sptep);
1179 static bool spte_set_dirty(u64 *sptep)
1183 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1186 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1187 * do not bother adding back write access to pages marked
1188 * SPTE_AD_WRPROT_ONLY_MASK.
1190 spte |= shadow_dirty_mask;
1192 return mmu_spte_update(sptep, spte);
1195 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1198 struct rmap_iterator iter;
1201 for_each_rmap_spte(rmap_head, &iter, sptep)
1202 if (spte_ad_enabled(*sptep))
1203 flush |= spte_set_dirty(sptep);
1209 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1210 * @kvm: kvm instance
1211 * @slot: slot to protect
1212 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1213 * @mask: indicates which pages we should protect
1215 * Used when we do not need to care about huge page mappings: e.g. during dirty
1216 * logging we do not have any such mappings.
1218 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1219 struct kvm_memory_slot *slot,
1220 gfn_t gfn_offset, unsigned long mask)
1222 struct kvm_rmap_head *rmap_head;
1224 if (kvm->arch.tdp_mmu_enabled)
1225 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1226 slot->base_gfn + gfn_offset, mask, true);
1228 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1230 __rmap_write_protect(kvm, rmap_head, false);
1232 /* clear the first set bit */
1238 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1239 * protect the page if the D-bit isn't supported.
1240 * @kvm: kvm instance
1241 * @slot: slot to clear D-bit
1242 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1243 * @mask: indicates which pages we should clear D-bit
1245 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1247 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1248 struct kvm_memory_slot *slot,
1249 gfn_t gfn_offset, unsigned long mask)
1251 struct kvm_rmap_head *rmap_head;
1253 if (kvm->arch.tdp_mmu_enabled)
1254 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1255 slot->base_gfn + gfn_offset, mask, false);
1257 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1259 __rmap_clear_dirty(kvm, rmap_head);
1261 /* clear the first set bit */
1265 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1268 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1271 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1272 * enable dirty logging for them.
1274 * Used when we do not need to care about huge page mappings: e.g. during dirty
1275 * logging we do not have any such mappings.
1277 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1278 struct kvm_memory_slot *slot,
1279 gfn_t gfn_offset, unsigned long mask)
1281 if (kvm_x86_ops.enable_log_dirty_pt_masked)
1282 kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1285 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1288 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1289 struct kvm_memory_slot *slot, u64 gfn)
1291 struct kvm_rmap_head *rmap_head;
1293 bool write_protected = false;
1295 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1296 rmap_head = __gfn_to_rmap(gfn, i, slot);
1297 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1300 if (kvm->arch.tdp_mmu_enabled)
1302 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn);
1304 return write_protected;
1307 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1309 struct kvm_memory_slot *slot;
1311 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1312 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1315 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1318 struct rmap_iterator iter;
1321 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1322 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1324 pte_list_remove(rmap_head, sptep);
1331 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1332 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1335 return kvm_zap_rmapp(kvm, rmap_head);
1338 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1339 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1343 struct rmap_iterator iter;
1346 pte_t *ptep = (pte_t *)data;
1349 WARN_ON(pte_huge(*ptep));
1350 new_pfn = pte_pfn(*ptep);
1353 for_each_rmap_spte(rmap_head, &iter, sptep) {
1354 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1355 sptep, *sptep, gfn, level);
1359 if (pte_write(*ptep)) {
1360 pte_list_remove(rmap_head, sptep);
1363 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1366 mmu_spte_clear_track_bits(sptep);
1367 mmu_spte_set(sptep, new_spte);
1371 if (need_flush && kvm_available_flush_tlb_with_range()) {
1372 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1379 struct slot_rmap_walk_iterator {
1381 struct kvm_memory_slot *slot;
1387 /* output fields. */
1389 struct kvm_rmap_head *rmap;
1392 /* private field. */
1393 struct kvm_rmap_head *end_rmap;
1397 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1399 iterator->level = level;
1400 iterator->gfn = iterator->start_gfn;
1401 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1402 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1407 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1408 struct kvm_memory_slot *slot, int start_level,
1409 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1411 iterator->slot = slot;
1412 iterator->start_level = start_level;
1413 iterator->end_level = end_level;
1414 iterator->start_gfn = start_gfn;
1415 iterator->end_gfn = end_gfn;
1417 rmap_walk_init_level(iterator, iterator->start_level);
1420 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1422 return !!iterator->rmap;
1425 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1427 if (++iterator->rmap <= iterator->end_rmap) {
1428 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1432 if (++iterator->level > iterator->end_level) {
1433 iterator->rmap = NULL;
1437 rmap_walk_init_level(iterator, iterator->level);
1440 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1441 _start_gfn, _end_gfn, _iter_) \
1442 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1443 _end_level_, _start_gfn, _end_gfn); \
1444 slot_rmap_walk_okay(_iter_); \
1445 slot_rmap_walk_next(_iter_))
1447 static int kvm_handle_hva_range(struct kvm *kvm,
1448 unsigned long start,
1451 int (*handler)(struct kvm *kvm,
1452 struct kvm_rmap_head *rmap_head,
1453 struct kvm_memory_slot *slot,
1456 unsigned long data))
1458 struct kvm_memslots *slots;
1459 struct kvm_memory_slot *memslot;
1460 struct slot_rmap_walk_iterator iterator;
1464 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1465 slots = __kvm_memslots(kvm, i);
1466 kvm_for_each_memslot(memslot, slots) {
1467 unsigned long hva_start, hva_end;
1468 gfn_t gfn_start, gfn_end;
1470 hva_start = max(start, memslot->userspace_addr);
1471 hva_end = min(end, memslot->userspace_addr +
1472 (memslot->npages << PAGE_SHIFT));
1473 if (hva_start >= hva_end)
1476 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1477 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1479 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1480 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1482 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1483 KVM_MAX_HUGEPAGE_LEVEL,
1484 gfn_start, gfn_end - 1,
1486 ret |= handler(kvm, iterator.rmap, memslot,
1487 iterator.gfn, iterator.level, data);
1494 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1496 int (*handler)(struct kvm *kvm,
1497 struct kvm_rmap_head *rmap_head,
1498 struct kvm_memory_slot *slot,
1499 gfn_t gfn, int level,
1500 unsigned long data))
1502 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1505 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1510 r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1512 if (kvm->arch.tdp_mmu_enabled)
1513 r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end);
1518 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1522 r = kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1524 if (kvm->arch.tdp_mmu_enabled)
1525 r |= kvm_tdp_mmu_set_spte_hva(kvm, hva, &pte);
1530 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1531 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1535 struct rmap_iterator iter;
1538 for_each_rmap_spte(rmap_head, &iter, sptep)
1539 young |= mmu_spte_age(sptep);
1541 trace_kvm_age_page(gfn, level, slot, young);
1545 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1546 struct kvm_memory_slot *slot, gfn_t gfn,
1547 int level, unsigned long data)
1550 struct rmap_iterator iter;
1552 for_each_rmap_spte(rmap_head, &iter, sptep)
1553 if (is_accessed_spte(*sptep))
1558 #define RMAP_RECYCLE_THRESHOLD 1000
1560 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1562 struct kvm_rmap_head *rmap_head;
1563 struct kvm_mmu_page *sp;
1565 sp = sptep_to_sp(spte);
1567 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1569 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1570 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1571 KVM_PAGES_PER_HPAGE(sp->role.level));
1574 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1578 young = kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1579 if (kvm->arch.tdp_mmu_enabled)
1580 young |= kvm_tdp_mmu_age_hva_range(kvm, start, end);
1585 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1589 young = kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1590 if (kvm->arch.tdp_mmu_enabled)
1591 young |= kvm_tdp_mmu_test_age_hva(kvm, hva);
1597 static int is_empty_shadow_page(u64 *spt)
1602 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1603 if (is_shadow_present_pte(*pos)) {
1604 printk(KERN_ERR "%s: %p %llx\n", __func__,
1613 * This value is the sum of all of the kvm instances's
1614 * kvm->arch.n_used_mmu_pages values. We need a global,
1615 * aggregate version in order to make the slab shrinker
1618 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr)
1620 kvm->arch.n_used_mmu_pages += nr;
1621 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1624 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1626 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1627 hlist_del(&sp->hash_link);
1628 list_del(&sp->link);
1629 free_page((unsigned long)sp->spt);
1630 if (!sp->role.direct)
1631 free_page((unsigned long)sp->gfns);
1632 kmem_cache_free(mmu_page_header_cache, sp);
1635 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1637 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1640 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1641 struct kvm_mmu_page *sp, u64 *parent_pte)
1646 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1649 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1652 __pte_list_remove(parent_pte, &sp->parent_ptes);
1655 static void drop_parent_pte(struct kvm_mmu_page *sp,
1658 mmu_page_remove_parent_pte(sp, parent_pte);
1659 mmu_spte_clear_no_track(parent_pte);
1662 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1664 struct kvm_mmu_page *sp;
1666 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1667 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1669 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1670 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1673 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1674 * depends on valid pages being added to the head of the list. See
1675 * comments in kvm_zap_obsolete_pages().
1677 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1678 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1679 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1683 static void mark_unsync(u64 *spte);
1684 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1687 struct rmap_iterator iter;
1689 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1694 static void mark_unsync(u64 *spte)
1696 struct kvm_mmu_page *sp;
1699 sp = sptep_to_sp(spte);
1700 index = spte - sp->spt;
1701 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1703 if (sp->unsync_children++)
1705 kvm_mmu_mark_parents_unsync(sp);
1708 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1709 struct kvm_mmu_page *sp)
1714 #define KVM_PAGE_ARRAY_NR 16
1716 struct kvm_mmu_pages {
1717 struct mmu_page_and_offset {
1718 struct kvm_mmu_page *sp;
1720 } page[KVM_PAGE_ARRAY_NR];
1724 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1730 for (i=0; i < pvec->nr; i++)
1731 if (pvec->page[i].sp == sp)
1734 pvec->page[pvec->nr].sp = sp;
1735 pvec->page[pvec->nr].idx = idx;
1737 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1740 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1742 --sp->unsync_children;
1743 WARN_ON((int)sp->unsync_children < 0);
1744 __clear_bit(idx, sp->unsync_child_bitmap);
1747 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1748 struct kvm_mmu_pages *pvec)
1750 int i, ret, nr_unsync_leaf = 0;
1752 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1753 struct kvm_mmu_page *child;
1754 u64 ent = sp->spt[i];
1756 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1757 clear_unsync_child_bit(sp, i);
1761 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1763 if (child->unsync_children) {
1764 if (mmu_pages_add(pvec, child, i))
1767 ret = __mmu_unsync_walk(child, pvec);
1769 clear_unsync_child_bit(sp, i);
1771 } else if (ret > 0) {
1772 nr_unsync_leaf += ret;
1775 } else if (child->unsync) {
1777 if (mmu_pages_add(pvec, child, i))
1780 clear_unsync_child_bit(sp, i);
1783 return nr_unsync_leaf;
1786 #define INVALID_INDEX (-1)
1788 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1789 struct kvm_mmu_pages *pvec)
1792 if (!sp->unsync_children)
1795 mmu_pages_add(pvec, sp, INVALID_INDEX);
1796 return __mmu_unsync_walk(sp, pvec);
1799 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1801 WARN_ON(!sp->unsync);
1802 trace_kvm_mmu_sync_page(sp);
1804 --kvm->stat.mmu_unsync;
1807 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1808 struct list_head *invalid_list);
1809 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1810 struct list_head *invalid_list);
1812 #define for_each_valid_sp(_kvm, _sp, _list) \
1813 hlist_for_each_entry(_sp, _list, hash_link) \
1814 if (is_obsolete_sp((_kvm), (_sp))) { \
1817 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1818 for_each_valid_sp(_kvm, _sp, \
1819 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1820 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1822 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1824 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1827 /* @sp->gfn should be write-protected at the call site */
1828 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1829 struct list_head *invalid_list)
1831 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1832 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1833 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1840 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1841 struct list_head *invalid_list,
1844 if (!remote_flush && list_empty(invalid_list))
1847 if (!list_empty(invalid_list))
1848 kvm_mmu_commit_zap_page(kvm, invalid_list);
1850 kvm_flush_remote_tlbs(kvm);
1854 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1855 struct list_head *invalid_list,
1856 bool remote_flush, bool local_flush)
1858 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1862 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1865 #ifdef CONFIG_KVM_MMU_AUDIT
1866 #include "mmu_audit.c"
1868 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1869 static void mmu_audit_disable(void) { }
1872 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1874 return sp->role.invalid ||
1875 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1878 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1879 struct list_head *invalid_list)
1881 kvm_unlink_unsync_page(vcpu->kvm, sp);
1882 return __kvm_sync_page(vcpu, sp, invalid_list);
1885 /* @gfn should be write-protected at the call site */
1886 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1887 struct list_head *invalid_list)
1889 struct kvm_mmu_page *s;
1892 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1896 WARN_ON(s->role.level != PG_LEVEL_4K);
1897 ret |= kvm_sync_page(vcpu, s, invalid_list);
1903 struct mmu_page_path {
1904 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1905 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1908 #define for_each_sp(pvec, sp, parents, i) \
1909 for (i = mmu_pages_first(&pvec, &parents); \
1910 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1911 i = mmu_pages_next(&pvec, &parents, i))
1913 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1914 struct mmu_page_path *parents,
1919 for (n = i+1; n < pvec->nr; n++) {
1920 struct kvm_mmu_page *sp = pvec->page[n].sp;
1921 unsigned idx = pvec->page[n].idx;
1922 int level = sp->role.level;
1924 parents->idx[level-1] = idx;
1925 if (level == PG_LEVEL_4K)
1928 parents->parent[level-2] = sp;
1934 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1935 struct mmu_page_path *parents)
1937 struct kvm_mmu_page *sp;
1943 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1945 sp = pvec->page[0].sp;
1946 level = sp->role.level;
1947 WARN_ON(level == PG_LEVEL_4K);
1949 parents->parent[level-2] = sp;
1951 /* Also set up a sentinel. Further entries in pvec are all
1952 * children of sp, so this element is never overwritten.
1954 parents->parent[level-1] = NULL;
1955 return mmu_pages_next(pvec, parents, 0);
1958 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1960 struct kvm_mmu_page *sp;
1961 unsigned int level = 0;
1964 unsigned int idx = parents->idx[level];
1965 sp = parents->parent[level];
1969 WARN_ON(idx == INVALID_INDEX);
1970 clear_unsync_child_bit(sp, idx);
1972 } while (!sp->unsync_children);
1975 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1976 struct kvm_mmu_page *parent)
1979 struct kvm_mmu_page *sp;
1980 struct mmu_page_path parents;
1981 struct kvm_mmu_pages pages;
1982 LIST_HEAD(invalid_list);
1985 while (mmu_unsync_walk(parent, &pages)) {
1986 bool protected = false;
1988 for_each_sp(pages, sp, parents, i)
1989 protected |= rmap_write_protect(vcpu, sp->gfn);
1992 kvm_flush_remote_tlbs(vcpu->kvm);
1996 for_each_sp(pages, sp, parents, i) {
1997 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1998 mmu_pages_clear_parents(&parents);
2000 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2001 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2002 cond_resched_lock(&vcpu->kvm->mmu_lock);
2007 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2010 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2012 atomic_set(&sp->write_flooding_count, 0);
2015 static void clear_sp_write_flooding_count(u64 *spte)
2017 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2020 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2025 unsigned int access)
2027 bool direct_mmu = vcpu->arch.mmu->direct_map;
2028 union kvm_mmu_page_role role;
2029 struct hlist_head *sp_list;
2031 struct kvm_mmu_page *sp;
2032 bool need_sync = false;
2035 LIST_HEAD(invalid_list);
2037 role = vcpu->arch.mmu->mmu_role.base;
2039 role.direct = direct;
2041 role.gpte_is_8_bytes = true;
2042 role.access = access;
2043 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2044 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2045 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2046 role.quadrant = quadrant;
2049 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2050 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2051 if (sp->gfn != gfn) {
2056 if (!need_sync && sp->unsync)
2059 if (sp->role.word != role.word)
2063 goto trace_get_page;
2066 /* The page is good, but __kvm_sync_page might still end
2067 * up zapping it. If so, break in order to rebuild it.
2069 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2072 WARN_ON(!list_empty(&invalid_list));
2073 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2076 if (sp->unsync_children)
2077 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2079 __clear_sp_write_flooding_count(sp);
2082 trace_kvm_mmu_get_page(sp, false);
2086 ++vcpu->kvm->stat.mmu_cache_miss;
2088 sp = kvm_mmu_alloc_page(vcpu, direct);
2092 hlist_add_head(&sp->hash_link, sp_list);
2095 * we should do write protection before syncing pages
2096 * otherwise the content of the synced shadow page may
2097 * be inconsistent with guest page table.
2099 account_shadowed(vcpu->kvm, sp);
2100 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2101 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2103 if (level > PG_LEVEL_4K && need_sync)
2104 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2106 trace_kvm_mmu_get_page(sp, true);
2108 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2110 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2111 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2115 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2116 struct kvm_vcpu *vcpu, hpa_t root,
2119 iterator->addr = addr;
2120 iterator->shadow_addr = root;
2121 iterator->level = vcpu->arch.mmu->shadow_root_level;
2123 if (iterator->level == PT64_ROOT_4LEVEL &&
2124 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2125 !vcpu->arch.mmu->direct_map)
2128 if (iterator->level == PT32E_ROOT_LEVEL) {
2130 * prev_root is currently only used for 64-bit hosts. So only
2131 * the active root_hpa is valid here.
2133 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2135 iterator->shadow_addr
2136 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2137 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2139 if (!iterator->shadow_addr)
2140 iterator->level = 0;
2144 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2145 struct kvm_vcpu *vcpu, u64 addr)
2147 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2151 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2153 if (iterator->level < PG_LEVEL_4K)
2156 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2157 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2161 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2164 if (is_last_spte(spte, iterator->level)) {
2165 iterator->level = 0;
2169 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2173 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2175 __shadow_walk_next(iterator, *iterator->sptep);
2178 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2179 struct kvm_mmu_page *sp)
2183 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2185 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2187 mmu_spte_set(sptep, spte);
2189 mmu_page_add_parent_pte(vcpu, sp, sptep);
2191 if (sp->unsync_children || sp->unsync)
2195 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2196 unsigned direct_access)
2198 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2199 struct kvm_mmu_page *child;
2202 * For the direct sp, if the guest pte's dirty bit
2203 * changed form clean to dirty, it will corrupt the
2204 * sp's access: allow writable in the read-only sp,
2205 * so we should update the spte at this point to get
2206 * a new sp with the correct access.
2208 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2209 if (child->role.access == direct_access)
2212 drop_parent_pte(child, sptep);
2213 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2217 /* Returns the number of zapped non-leaf child shadow pages. */
2218 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2219 u64 *spte, struct list_head *invalid_list)
2222 struct kvm_mmu_page *child;
2225 if (is_shadow_present_pte(pte)) {
2226 if (is_last_spte(pte, sp->role.level)) {
2227 drop_spte(kvm, spte);
2228 if (is_large_pte(pte))
2231 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2232 drop_parent_pte(child, spte);
2235 * Recursively zap nested TDP SPs, parentless SPs are
2236 * unlikely to be used again in the near future. This
2237 * avoids retaining a large number of stale nested SPs.
2239 if (tdp_enabled && invalid_list &&
2240 child->role.guest_mode && !child->parent_ptes.val)
2241 return kvm_mmu_prepare_zap_page(kvm, child,
2244 } else if (is_mmio_spte(pte)) {
2245 mmu_spte_clear_no_track(spte);
2250 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2251 struct kvm_mmu_page *sp,
2252 struct list_head *invalid_list)
2257 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2258 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2263 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2266 struct rmap_iterator iter;
2268 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2269 drop_parent_pte(sp, sptep);
2272 static int mmu_zap_unsync_children(struct kvm *kvm,
2273 struct kvm_mmu_page *parent,
2274 struct list_head *invalid_list)
2277 struct mmu_page_path parents;
2278 struct kvm_mmu_pages pages;
2280 if (parent->role.level == PG_LEVEL_4K)
2283 while (mmu_unsync_walk(parent, &pages)) {
2284 struct kvm_mmu_page *sp;
2286 for_each_sp(pages, sp, parents, i) {
2287 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2288 mmu_pages_clear_parents(&parents);
2296 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2297 struct kvm_mmu_page *sp,
2298 struct list_head *invalid_list,
2303 trace_kvm_mmu_prepare_zap_page(sp);
2304 ++kvm->stat.mmu_shadow_zapped;
2305 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2306 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2307 kvm_mmu_unlink_parents(kvm, sp);
2309 /* Zapping children means active_mmu_pages has become unstable. */
2310 list_unstable = *nr_zapped;
2312 if (!sp->role.invalid && !sp->role.direct)
2313 unaccount_shadowed(kvm, sp);
2316 kvm_unlink_unsync_page(kvm, sp);
2317 if (!sp->root_count) {
2322 * Already invalid pages (previously active roots) are not on
2323 * the active page list. See list_del() in the "else" case of
2326 if (sp->role.invalid)
2327 list_add(&sp->link, invalid_list);
2329 list_move(&sp->link, invalid_list);
2330 kvm_mod_used_mmu_pages(kvm, -1);
2333 * Remove the active root from the active page list, the root
2334 * will be explicitly freed when the root_count hits zero.
2336 list_del(&sp->link);
2339 * Obsolete pages cannot be used on any vCPUs, see the comment
2340 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2341 * treats invalid shadow pages as being obsolete.
2343 if (!is_obsolete_sp(kvm, sp))
2344 kvm_reload_remote_mmus(kvm);
2347 if (sp->lpage_disallowed)
2348 unaccount_huge_nx_page(kvm, sp);
2350 sp->role.invalid = 1;
2351 return list_unstable;
2354 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2355 struct list_head *invalid_list)
2359 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2363 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2364 struct list_head *invalid_list)
2366 struct kvm_mmu_page *sp, *nsp;
2368 if (list_empty(invalid_list))
2372 * We need to make sure everyone sees our modifications to
2373 * the page tables and see changes to vcpu->mode here. The barrier
2374 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2375 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2377 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2378 * guest mode and/or lockless shadow page table walks.
2380 kvm_flush_remote_tlbs(kvm);
2382 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2383 WARN_ON(!sp->role.invalid || sp->root_count);
2384 kvm_mmu_free_page(sp);
2388 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2389 unsigned long nr_to_zap)
2391 unsigned long total_zapped = 0;
2392 struct kvm_mmu_page *sp, *tmp;
2393 LIST_HEAD(invalid_list);
2397 if (list_empty(&kvm->arch.active_mmu_pages))
2401 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2403 * Don't zap active root pages, the page itself can't be freed
2404 * and zapping it will just force vCPUs to realloc and reload.
2409 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2411 total_zapped += nr_zapped;
2412 if (total_zapped >= nr_to_zap)
2419 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2421 kvm->stat.mmu_recycled += total_zapped;
2422 return total_zapped;
2425 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2427 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2428 return kvm->arch.n_max_mmu_pages -
2429 kvm->arch.n_used_mmu_pages;
2434 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2436 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2438 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2441 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2443 if (!kvm_mmu_available_pages(vcpu->kvm))
2449 * Changing the number of mmu pages allocated to the vm
2450 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2452 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2454 spin_lock(&kvm->mmu_lock);
2456 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2457 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2460 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2463 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2465 spin_unlock(&kvm->mmu_lock);
2468 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2470 struct kvm_mmu_page *sp;
2471 LIST_HEAD(invalid_list);
2474 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2476 spin_lock(&kvm->mmu_lock);
2477 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2478 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2481 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2483 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2484 spin_unlock(&kvm->mmu_lock);
2488 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2490 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2492 trace_kvm_mmu_unsync_page(sp);
2493 ++vcpu->kvm->stat.mmu_unsync;
2496 kvm_mmu_mark_parents_unsync(sp);
2499 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2502 struct kvm_mmu_page *sp;
2504 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2507 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2514 WARN_ON(sp->role.level != PG_LEVEL_4K);
2515 kvm_unsync_page(vcpu, sp);
2519 * We need to ensure that the marking of unsync pages is visible
2520 * before the SPTE is updated to allow writes because
2521 * kvm_mmu_sync_roots() checks the unsync flags without holding
2522 * the MMU lock and so can race with this. If the SPTE was updated
2523 * before the page had been marked as unsync-ed, something like the
2524 * following could happen:
2527 * ---------------------------------------------------------------------
2528 * 1.2 Host updates SPTE
2530 * 2.1 Guest writes a GPTE for GVA X.
2531 * (GPTE being in the guest page table shadowed
2532 * by the SP from CPU 1.)
2533 * This reads SPTE during the page table walk.
2534 * Since SPTE.W is read as 1, there is no
2537 * 2.2 Guest issues TLB flush.
2538 * That causes a VM Exit.
2540 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2541 * Since it is false, so it just returns.
2543 * 2.4 Guest accesses GVA X.
2544 * Since the mapping in the SP was not updated,
2545 * so the old mapping for GVA X incorrectly
2549 * (sp->unsync = true)
2551 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2552 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2553 * pairs with this write barrier.
2560 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2561 unsigned int pte_access, int level,
2562 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2563 bool can_unsync, bool host_writable)
2566 struct kvm_mmu_page *sp;
2569 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2572 sp = sptep_to_sp(sptep);
2574 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2575 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2577 if (spte & PT_WRITABLE_MASK)
2578 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2581 ret |= SET_SPTE_SPURIOUS;
2582 else if (mmu_spte_update(sptep, spte))
2583 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2587 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2588 unsigned int pte_access, bool write_fault, int level,
2589 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2592 int was_rmapped = 0;
2595 int ret = RET_PF_FIXED;
2598 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2599 *sptep, write_fault, gfn);
2601 if (is_shadow_present_pte(*sptep)) {
2603 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2604 * the parent of the now unreachable PTE.
2606 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2607 struct kvm_mmu_page *child;
2610 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2611 drop_parent_pte(child, sptep);
2613 } else if (pfn != spte_to_pfn(*sptep)) {
2614 pgprintk("hfn old %llx new %llx\n",
2615 spte_to_pfn(*sptep), pfn);
2616 drop_spte(vcpu->kvm, sptep);
2622 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2623 speculative, true, host_writable);
2624 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2626 ret = RET_PF_EMULATE;
2627 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2630 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2631 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2632 KVM_PAGES_PER_HPAGE(level));
2634 if (unlikely(is_mmio_spte(*sptep)))
2635 ret = RET_PF_EMULATE;
2638 * The fault is fully spurious if and only if the new SPTE and old SPTE
2639 * are identical, and emulation is not required.
2641 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2642 WARN_ON_ONCE(!was_rmapped);
2643 return RET_PF_SPURIOUS;
2646 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2647 trace_kvm_mmu_set_spte(level, gfn, sptep);
2648 if (!was_rmapped && is_large_pte(*sptep))
2649 ++vcpu->kvm->stat.lpages;
2651 if (is_shadow_present_pte(*sptep)) {
2653 rmap_count = rmap_add(vcpu, sptep, gfn);
2654 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2655 rmap_recycle(vcpu, sptep, gfn);
2662 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2665 struct kvm_memory_slot *slot;
2667 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2669 return KVM_PFN_ERR_FAULT;
2671 return gfn_to_pfn_memslot_atomic(slot, gfn);
2674 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2675 struct kvm_mmu_page *sp,
2676 u64 *start, u64 *end)
2678 struct page *pages[PTE_PREFETCH_NUM];
2679 struct kvm_memory_slot *slot;
2680 unsigned int access = sp->role.access;
2684 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2685 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2689 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2693 for (i = 0; i < ret; i++, gfn++, start++) {
2694 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2695 page_to_pfn(pages[i]), true, true);
2702 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2703 struct kvm_mmu_page *sp, u64 *sptep)
2705 u64 *spte, *start = NULL;
2708 WARN_ON(!sp->role.direct);
2710 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2713 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2714 if (is_shadow_present_pte(*spte) || spte == sptep) {
2717 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2725 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2727 struct kvm_mmu_page *sp;
2729 sp = sptep_to_sp(sptep);
2732 * Without accessed bits, there's no way to distinguish between
2733 * actually accessed translations and prefetched, so disable pte
2734 * prefetch if accessed bits aren't available.
2736 if (sp_ad_disabled(sp))
2739 if (sp->role.level > PG_LEVEL_4K)
2742 __direct_pte_prefetch(vcpu, sp, sptep);
2745 static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn,
2746 kvm_pfn_t pfn, struct kvm_memory_slot *slot)
2752 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2756 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2757 * is not solely for performance, it's also necessary to avoid the
2758 * "writable" check in __gfn_to_hva_many(), which will always fail on
2759 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2760 * page fault steps have already verified the guest isn't writing a
2761 * read-only memslot.
2763 hva = __gfn_to_hva_memslot(slot, gfn);
2765 pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level);
2772 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2773 int max_level, kvm_pfn_t *pfnp,
2774 bool huge_page_disallowed, int *req_level)
2776 struct kvm_memory_slot *slot;
2777 struct kvm_lpage_info *linfo;
2778 kvm_pfn_t pfn = *pfnp;
2782 *req_level = PG_LEVEL_4K;
2784 if (unlikely(max_level == PG_LEVEL_4K))
2787 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2790 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2794 max_level = min(max_level, max_huge_page_level);
2795 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2796 linfo = lpage_info_slot(gfn, slot, max_level);
2797 if (!linfo->disallow_lpage)
2801 if (max_level == PG_LEVEL_4K)
2804 level = host_pfn_mapping_level(vcpu, gfn, pfn, slot);
2805 if (level == PG_LEVEL_4K)
2808 *req_level = level = min(level, max_level);
2811 * Enforce the iTLB multihit workaround after capturing the requested
2812 * level, which will be used to do precise, accurate accounting.
2814 if (huge_page_disallowed)
2818 * mmu_notifier_retry() was successful and mmu_lock is held, so
2819 * the pmd can't be split from under us.
2821 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2822 VM_BUG_ON((gfn & mask) != (pfn & mask));
2823 *pfnp = pfn & ~mask;
2828 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2829 kvm_pfn_t *pfnp, int *goal_levelp)
2831 int level = *goal_levelp;
2833 if (cur_level == level && level > PG_LEVEL_4K &&
2834 is_shadow_present_pte(spte) &&
2835 !is_large_pte(spte)) {
2837 * A small SPTE exists for this pfn, but FNAME(fetch)
2838 * and __direct_map would like to create a large PTE
2839 * instead: just force them to go down another level,
2840 * patching back for them into pfn the next 9 bits of
2843 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2844 KVM_PAGES_PER_HPAGE(level - 1);
2845 *pfnp |= gfn & page_mask;
2850 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2851 int map_writable, int max_level, kvm_pfn_t pfn,
2852 bool prefault, bool is_tdp)
2854 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2855 bool write = error_code & PFERR_WRITE_MASK;
2856 bool exec = error_code & PFERR_FETCH_MASK;
2857 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2858 struct kvm_shadow_walk_iterator it;
2859 struct kvm_mmu_page *sp;
2860 int level, req_level, ret;
2861 gfn_t gfn = gpa >> PAGE_SHIFT;
2862 gfn_t base_gfn = gfn;
2864 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
2865 return RET_PF_RETRY;
2867 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2868 huge_page_disallowed, &req_level);
2870 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2871 for_each_shadow_entry(vcpu, gpa, it) {
2873 * We cannot overwrite existing page tables with an NX
2874 * large page, as the leaf could be executable.
2876 if (nx_huge_page_workaround_enabled)
2877 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2880 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2881 if (it.level == level)
2884 drop_large_spte(vcpu, it.sptep);
2885 if (!is_shadow_present_pte(*it.sptep)) {
2886 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2887 it.level - 1, true, ACC_ALL);
2889 link_shadow_page(vcpu, it.sptep, sp);
2890 if (is_tdp && huge_page_disallowed &&
2891 req_level >= it.level)
2892 account_huge_nx_page(vcpu->kvm, sp);
2896 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2897 write, level, base_gfn, pfn, prefault,
2899 if (ret == RET_PF_SPURIOUS)
2902 direct_pte_prefetch(vcpu, it.sptep);
2903 ++vcpu->stat.pf_fixed;
2907 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2909 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2912 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2915 * Do not cache the mmio info caused by writing the readonly gfn
2916 * into the spte otherwise read access on readonly gfn also can
2917 * caused mmio page fault and treat it as mmio access.
2919 if (pfn == KVM_PFN_ERR_RO_FAULT)
2920 return RET_PF_EMULATE;
2922 if (pfn == KVM_PFN_ERR_HWPOISON) {
2923 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2924 return RET_PF_RETRY;
2930 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2931 kvm_pfn_t pfn, unsigned int access,
2934 /* The pfn is invalid, report the error! */
2935 if (unlikely(is_error_pfn(pfn))) {
2936 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2940 if (unlikely(is_noslot_pfn(pfn)))
2941 vcpu_cache_mmio_info(vcpu, gva, gfn,
2942 access & shadow_mmio_access_mask);
2947 static bool page_fault_can_be_fast(u32 error_code)
2950 * Do not fix the mmio spte with invalid generation number which
2951 * need to be updated by slow page fault path.
2953 if (unlikely(error_code & PFERR_RSVD_MASK))
2956 /* See if the page fault is due to an NX violation */
2957 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2958 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2962 * #PF can be fast if:
2963 * 1. The shadow page table entry is not present, which could mean that
2964 * the fault is potentially caused by access tracking (if enabled).
2965 * 2. The shadow page table entry is present and the fault
2966 * is caused by write-protect, that means we just need change the W
2967 * bit of the spte which can be done out of mmu-lock.
2969 * However, if access tracking is disabled we know that a non-present
2970 * page must be a genuine page fault where we have to create a new SPTE.
2971 * So, if access tracking is disabled, we return true only for write
2972 * accesses to a present page.
2975 return shadow_acc_track_mask != 0 ||
2976 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2977 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2981 * Returns true if the SPTE was fixed successfully. Otherwise,
2982 * someone else modified the SPTE from its original value.
2985 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2986 u64 *sptep, u64 old_spte, u64 new_spte)
2990 WARN_ON(!sp->role.direct);
2993 * Theoretically we could also set dirty bit (and flush TLB) here in
2994 * order to eliminate unnecessary PML logging. See comments in
2995 * set_spte. But fast_page_fault is very unlikely to happen with PML
2996 * enabled, so we do not do this. This might result in the same GPA
2997 * to be logged in PML buffer again when the write really happens, and
2998 * eventually to be called by mark_page_dirty twice. But it's also no
2999 * harm. This also avoids the TLB flush needed after setting dirty bit
3000 * so non-PML cases won't be impacted.
3002 * Compare with set_spte where instead shadow_dirty_mask is set.
3004 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3007 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3009 * The gfn of direct spte is stable since it is
3010 * calculated by sp->gfn.
3012 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3013 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3019 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3021 if (fault_err_code & PFERR_FETCH_MASK)
3022 return is_executable_pte(spte);
3024 if (fault_err_code & PFERR_WRITE_MASK)
3025 return is_writable_pte(spte);
3027 /* Fault was on Read access */
3028 return spte & PT_PRESENT_MASK;
3032 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3034 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3037 struct kvm_shadow_walk_iterator iterator;
3038 struct kvm_mmu_page *sp;
3039 int ret = RET_PF_INVALID;
3041 uint retry_count = 0;
3043 if (!page_fault_can_be_fast(error_code))
3046 walk_shadow_page_lockless_begin(vcpu);
3051 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3052 if (!is_shadow_present_pte(spte))
3055 sp = sptep_to_sp(iterator.sptep);
3056 if (!is_last_spte(spte, sp->role.level))
3060 * Check whether the memory access that caused the fault would
3061 * still cause it if it were to be performed right now. If not,
3062 * then this is a spurious fault caused by TLB lazily flushed,
3063 * or some other CPU has already fixed the PTE after the
3064 * current CPU took the fault.
3066 * Need not check the access of upper level table entries since
3067 * they are always ACC_ALL.
3069 if (is_access_allowed(error_code, spte)) {
3070 ret = RET_PF_SPURIOUS;
3076 if (is_access_track_spte(spte))
3077 new_spte = restore_acc_track_spte(new_spte);
3080 * Currently, to simplify the code, write-protection can
3081 * be removed in the fast path only if the SPTE was
3082 * write-protected for dirty-logging or access tracking.
3084 if ((error_code & PFERR_WRITE_MASK) &&
3085 spte_can_locklessly_be_made_writable(spte)) {
3086 new_spte |= PT_WRITABLE_MASK;
3089 * Do not fix write-permission on the large spte. Since
3090 * we only dirty the first page into the dirty-bitmap in
3091 * fast_pf_fix_direct_spte(), other pages are missed
3092 * if its slot has dirty logging enabled.
3094 * Instead, we let the slow page fault path create a
3095 * normal spte to fix the access.
3097 * See the comments in kvm_arch_commit_memory_region().
3099 if (sp->role.level > PG_LEVEL_4K)
3103 /* Verify that the fault can be handled in the fast path */
3104 if (new_spte == spte ||
3105 !is_access_allowed(error_code, new_spte))
3109 * Currently, fast page fault only works for direct mapping
3110 * since the gfn is not stable for indirect shadow page. See
3111 * Documentation/virt/kvm/locking.rst to get more detail.
3113 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3119 if (++retry_count > 4) {
3120 printk_once(KERN_WARNING
3121 "kvm: Fast #PF retrying more than 4 times.\n");
3127 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3129 walk_shadow_page_lockless_end(vcpu);
3134 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3135 struct list_head *invalid_list)
3137 struct kvm_mmu_page *sp;
3139 if (!VALID_PAGE(*root_hpa))
3142 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3146 if (kvm_mmu_put_root(kvm, sp)) {
3147 if (sp->tdp_mmu_page)
3148 kvm_tdp_mmu_free_root(kvm, sp);
3149 else if (sp->role.invalid)
3150 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3153 *root_hpa = INVALID_PAGE;
3156 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3157 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3158 ulong roots_to_free)
3160 struct kvm *kvm = vcpu->kvm;
3162 LIST_HEAD(invalid_list);
3163 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3165 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3167 /* Before acquiring the MMU lock, see if we need to do any real work. */
3168 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3169 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3170 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3171 VALID_PAGE(mmu->prev_roots[i].hpa))
3174 if (i == KVM_MMU_NUM_PREV_ROOTS)
3178 spin_lock(&kvm->mmu_lock);
3180 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3181 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3182 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3185 if (free_active_root) {
3186 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3187 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3188 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3189 } else if (mmu->pae_root) {
3190 for (i = 0; i < 4; ++i)
3191 if (mmu->pae_root[i] != 0)
3192 mmu_free_root_page(kvm,
3196 mmu->root_hpa = INVALID_PAGE;
3200 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3201 spin_unlock(&kvm->mmu_lock);
3203 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3205 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3209 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3210 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3217 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3218 u8 level, bool direct)
3220 struct kvm_mmu_page *sp;
3222 spin_lock(&vcpu->kvm->mmu_lock);
3224 if (make_mmu_pages_available(vcpu)) {
3225 spin_unlock(&vcpu->kvm->mmu_lock);
3226 return INVALID_PAGE;
3228 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3231 spin_unlock(&vcpu->kvm->mmu_lock);
3232 return __pa(sp->spt);
3235 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3237 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3241 if (vcpu->kvm->arch.tdp_mmu_enabled) {
3242 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3244 if (!VALID_PAGE(root))
3246 vcpu->arch.mmu->root_hpa = root;
3247 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3248 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level,
3251 if (!VALID_PAGE(root))
3253 vcpu->arch.mmu->root_hpa = root;
3254 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3255 for (i = 0; i < 4; ++i) {
3256 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3258 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3259 i << 30, PT32_ROOT_LEVEL, true);
3260 if (!VALID_PAGE(root))
3262 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3264 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3268 /* root_pgd is ignored for direct MMUs. */
3269 vcpu->arch.mmu->root_pgd = 0;
3274 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3277 gfn_t root_gfn, root_pgd;
3281 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3282 root_gfn = root_pgd >> PAGE_SHIFT;
3284 if (mmu_check_root(vcpu, root_gfn))
3288 * Do we shadow a long mode page table? If so we need to
3289 * write-protect the guests page table root.
3291 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3292 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
3294 root = mmu_alloc_root(vcpu, root_gfn, 0,
3295 vcpu->arch.mmu->shadow_root_level, false);
3296 if (!VALID_PAGE(root))
3298 vcpu->arch.mmu->root_hpa = root;
3303 * We shadow a 32 bit page table. This may be a legacy 2-level
3304 * or a PAE 3-level page table. In either case we need to be aware that
3305 * the shadow page table may be a PAE or a long mode page table.
3307 pm_mask = PT_PRESENT_MASK;
3308 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3309 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3312 * Allocate the page for the PDPTEs when shadowing 32-bit NPT
3313 * with 64-bit only when needed. Unlike 32-bit NPT, it doesn't
3314 * need to be in low mem. See also lm_root below.
3316 if (!vcpu->arch.mmu->pae_root) {
3317 WARN_ON_ONCE(!tdp_enabled);
3319 vcpu->arch.mmu->pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3320 if (!vcpu->arch.mmu->pae_root)
3325 for (i = 0; i < 4; ++i) {
3326 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3327 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3328 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3329 if (!(pdptr & PT_PRESENT_MASK)) {
3330 vcpu->arch.mmu->pae_root[i] = 0;
3333 root_gfn = pdptr >> PAGE_SHIFT;
3334 if (mmu_check_root(vcpu, root_gfn))
3338 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3339 PT32_ROOT_LEVEL, false);
3340 if (!VALID_PAGE(root))
3342 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3344 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3347 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3348 * tables are allocated and initialized at MMU creation as there is no
3349 * equivalent level in the guest's NPT to shadow. Allocate the tables
3350 * on demand, as running a 32-bit L1 VMM is very rare. The PDP is
3351 * handled above (to share logic with PAE), deal with the PML4 here.
3353 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3354 if (vcpu->arch.mmu->lm_root == NULL) {
3357 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3361 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3363 vcpu->arch.mmu->lm_root = lm_root;
3366 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3370 vcpu->arch.mmu->root_pgd = root_pgd;
3375 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3377 if (vcpu->arch.mmu->direct_map)
3378 return mmu_alloc_direct_roots(vcpu);
3380 return mmu_alloc_shadow_roots(vcpu);
3383 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3386 struct kvm_mmu_page *sp;
3388 if (vcpu->arch.mmu->direct_map)
3391 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3394 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3396 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3397 hpa_t root = vcpu->arch.mmu->root_hpa;
3398 sp = to_shadow_page(root);
3401 * Even if another CPU was marking the SP as unsync-ed
3402 * simultaneously, any guest page table changes are not
3403 * guaranteed to be visible anyway until this VCPU issues a TLB
3404 * flush strictly after those changes are made. We only need to
3405 * ensure that the other CPU sets these flags before any actual
3406 * changes to the page tables are made. The comments in
3407 * mmu_need_write_protect() describe what could go wrong if this
3408 * requirement isn't satisfied.
3410 if (!smp_load_acquire(&sp->unsync) &&
3411 !smp_load_acquire(&sp->unsync_children))
3414 spin_lock(&vcpu->kvm->mmu_lock);
3415 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3417 mmu_sync_children(vcpu, sp);
3419 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3420 spin_unlock(&vcpu->kvm->mmu_lock);
3424 spin_lock(&vcpu->kvm->mmu_lock);
3425 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3427 for (i = 0; i < 4; ++i) {
3428 hpa_t root = vcpu->arch.mmu->pae_root[i];
3430 if (root && VALID_PAGE(root)) {
3431 root &= PT64_BASE_ADDR_MASK;
3432 sp = to_shadow_page(root);
3433 mmu_sync_children(vcpu, sp);
3437 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3438 spin_unlock(&vcpu->kvm->mmu_lock);
3440 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3442 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3443 u32 access, struct x86_exception *exception)
3446 exception->error_code = 0;
3450 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3452 struct x86_exception *exception)
3455 exception->error_code = 0;
3456 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3460 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3462 int bit7 = (pte >> 7) & 1;
3464 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3467 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3469 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3472 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3475 * A nested guest cannot use the MMIO cache if it is using nested
3476 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3478 if (mmu_is_nested(vcpu))
3482 return vcpu_match_mmio_gpa(vcpu, addr);
3484 return vcpu_match_mmio_gva(vcpu, addr);
3488 * Return the level of the lowest level SPTE added to sptes.
3489 * That SPTE may be non-present.
3491 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3493 struct kvm_shadow_walk_iterator iterator;
3497 walk_shadow_page_lockless_begin(vcpu);
3499 for (shadow_walk_init(&iterator, vcpu, addr),
3500 *root_level = iterator.level;
3501 shadow_walk_okay(&iterator);
3502 __shadow_walk_next(&iterator, spte)) {
3503 leaf = iterator.level;
3504 spte = mmu_spte_get_lockless(iterator.sptep);
3506 sptes[leaf - 1] = spte;
3508 if (!is_shadow_present_pte(spte))
3512 walk_shadow_page_lockless_end(vcpu);
3517 /* return true if reserved bit is detected on spte. */
3518 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3520 u64 sptes[PT64_ROOT_MAX_LEVEL];
3521 struct rsvd_bits_validate *rsvd_check;
3522 int root, leaf, level;
3523 bool reserved = false;
3525 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) {
3530 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3531 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3533 leaf = get_walk(vcpu, addr, sptes, &root);
3535 if (unlikely(leaf < 0)) {
3540 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3542 for (level = root; level >= leaf; level--) {
3543 if (!is_shadow_present_pte(sptes[level - 1]))
3546 * Use a bitwise-OR instead of a logical-OR to aggregate the
3547 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3548 * adding a Jcc in the loop.
3550 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level - 1]) ||
3551 __is_rsvd_bits_set(rsvd_check, sptes[level - 1],
3556 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3558 for (level = root; level >= leaf; level--)
3559 pr_err("------ spte 0x%llx level %d.\n",
3560 sptes[level - 1], level);
3563 *sptep = sptes[leaf - 1];
3568 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3573 if (mmio_info_in_cache(vcpu, addr, direct))
3574 return RET_PF_EMULATE;
3576 reserved = get_mmio_spte(vcpu, addr, &spte);
3577 if (WARN_ON(reserved))
3580 if (is_mmio_spte(spte)) {
3581 gfn_t gfn = get_mmio_spte_gfn(spte);
3582 unsigned int access = get_mmio_spte_access(spte);
3584 if (!check_mmio_spte(vcpu, spte))
3585 return RET_PF_INVALID;
3590 trace_handle_mmio_page_fault(addr, gfn, access);
3591 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3592 return RET_PF_EMULATE;
3596 * If the page table is zapped by other cpus, let CPU fault again on
3599 return RET_PF_RETRY;
3602 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3603 u32 error_code, gfn_t gfn)
3605 if (unlikely(error_code & PFERR_RSVD_MASK))
3608 if (!(error_code & PFERR_PRESENT_MASK) ||
3609 !(error_code & PFERR_WRITE_MASK))
3613 * guest is writing the page which is write tracked which can
3614 * not be fixed by page fault handler.
3616 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3622 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3624 struct kvm_shadow_walk_iterator iterator;
3627 walk_shadow_page_lockless_begin(vcpu);
3628 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3629 clear_sp_write_flooding_count(iterator.sptep);
3630 if (!is_shadow_present_pte(spte))
3633 walk_shadow_page_lockless_end(vcpu);
3636 static u32 alloc_apf_token(struct kvm_vcpu *vcpu)
3638 /* make sure the token value is not 0 */
3639 u32 id = vcpu->arch.apf.id;
3642 vcpu->arch.apf.id = 1;
3644 return (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3647 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3650 struct kvm_arch_async_pf arch;
3652 arch.token = alloc_apf_token(vcpu);
3654 arch.direct_map = vcpu->arch.mmu->direct_map;
3655 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3657 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3658 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3661 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3662 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
3665 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3669 * Retry the page fault if the gfn hit a memslot that is being deleted
3670 * or moved. This ensures any existing SPTEs for the old memslot will
3671 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3673 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3676 /* Don't expose private memslots to L2. */
3677 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3678 *pfn = KVM_PFN_NOSLOT;
3684 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3686 return false; /* *pfn has correct page already */
3688 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3689 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3690 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3691 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3692 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3694 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3698 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3702 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3703 bool prefault, int max_level, bool is_tdp)
3705 bool write = error_code & PFERR_WRITE_MASK;
3708 gfn_t gfn = gpa >> PAGE_SHIFT;
3709 unsigned long mmu_seq;
3713 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3714 return RET_PF_EMULATE;
3716 if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) {
3717 r = fast_page_fault(vcpu, gpa, error_code);
3718 if (r != RET_PF_INVALID)
3722 r = mmu_topup_memory_caches(vcpu, false);
3726 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3729 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3730 return RET_PF_RETRY;
3732 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3736 spin_lock(&vcpu->kvm->mmu_lock);
3737 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3739 r = make_mmu_pages_available(vcpu);
3743 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3744 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3747 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3751 spin_unlock(&vcpu->kvm->mmu_lock);
3752 kvm_release_pfn_clean(pfn);
3756 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3757 u32 error_code, bool prefault)
3759 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3761 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3762 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3763 PG_LEVEL_2M, false);
3766 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3767 u64 fault_address, char *insn, int insn_len)
3770 u32 flags = vcpu->arch.apf.host_apf_flags;
3772 #ifndef CONFIG_X86_64
3773 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3774 if (WARN_ON_ONCE(fault_address >> 32))
3778 vcpu->arch.l1tf_flush_l1d = true;
3780 trace_kvm_page_fault(fault_address, error_code);
3782 if (kvm_event_needs_reinjection(vcpu))
3783 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3784 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3786 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3787 vcpu->arch.apf.host_apf_flags = 0;
3788 local_irq_disable();
3789 kvm_async_pf_task_wait_schedule(fault_address);
3792 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3797 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3799 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3804 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3805 max_level > PG_LEVEL_4K;
3807 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3808 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3810 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3814 return direct_page_fault(vcpu, gpa, error_code, prefault,
3818 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3819 struct kvm_mmu *context)
3821 context->page_fault = nonpaging_page_fault;
3822 context->gva_to_gpa = nonpaging_gva_to_gpa;
3823 context->sync_page = nonpaging_sync_page;
3824 context->invlpg = NULL;
3825 context->root_level = 0;
3826 context->shadow_root_level = PT32E_ROOT_LEVEL;
3827 context->direct_map = true;
3828 context->nx = false;
3831 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3832 union kvm_mmu_page_role role)
3834 return (role.direct || pgd == root->pgd) &&
3835 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3836 role.word == to_shadow_page(root->hpa)->role.word;
3840 * Find out if a previously cached root matching the new pgd/role is available.
3841 * The current root is also inserted into the cache.
3842 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3844 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3845 * false is returned. This root should now be freed by the caller.
3847 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3848 union kvm_mmu_page_role new_role)
3851 struct kvm_mmu_root_info root;
3852 struct kvm_mmu *mmu = vcpu->arch.mmu;
3854 root.pgd = mmu->root_pgd;
3855 root.hpa = mmu->root_hpa;
3857 if (is_root_usable(&root, new_pgd, new_role))
3860 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3861 swap(root, mmu->prev_roots[i]);
3863 if (is_root_usable(&root, new_pgd, new_role))
3867 mmu->root_hpa = root.hpa;
3868 mmu->root_pgd = root.pgd;
3870 return i < KVM_MMU_NUM_PREV_ROOTS;
3873 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3874 union kvm_mmu_page_role new_role)
3876 struct kvm_mmu *mmu = vcpu->arch.mmu;
3879 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3880 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3881 * later if necessary.
3883 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3884 mmu->root_level >= PT64_ROOT_4LEVEL)
3885 return cached_root_available(vcpu, new_pgd, new_role);
3890 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3891 union kvm_mmu_page_role new_role,
3892 bool skip_tlb_flush, bool skip_mmu_sync)
3894 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3895 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3900 * It's possible that the cached previous root page is obsolete because
3901 * of a change in the MMU generation number. However, changing the
3902 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3903 * free the root set here and allocate a new one.
3905 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3907 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
3908 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3909 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
3910 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3913 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3914 * switching to a new CR3, that GVA->GPA mapping may no longer be
3915 * valid. So clear any cached MMIO info even when we don't need to sync
3916 * the shadow page tables.
3918 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3921 * If this is a direct root page, it doesn't have a write flooding
3922 * count. Otherwise, clear the write flooding count.
3924 if (!new_role.direct)
3925 __clear_sp_write_flooding_count(
3926 to_shadow_page(vcpu->arch.mmu->root_hpa));
3929 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
3932 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
3933 skip_tlb_flush, skip_mmu_sync);
3935 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
3937 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3939 return kvm_read_cr3(vcpu);
3942 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3943 unsigned int access, int *nr_present)
3945 if (unlikely(is_mmio_spte(*sptep))) {
3946 if (gfn != get_mmio_spte_gfn(*sptep)) {
3947 mmu_spte_clear_no_track(sptep);
3952 mark_mmio_spte(vcpu, sptep, gfn, access);
3959 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3960 unsigned level, unsigned gpte)
3963 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3964 * If it is clear, there are no large pages at this level, so clear
3965 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3967 gpte &= level - mmu->last_nonleaf_level;
3970 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
3971 * iff level <= PG_LEVEL_4K, which for our purpose means
3972 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
3974 gpte |= level - PG_LEVEL_4K - 1;
3976 return gpte & PT_PAGE_SIZE_MASK;
3979 #define PTTYPE_EPT 18 /* arbitrary */
3980 #define PTTYPE PTTYPE_EPT
3981 #include "paging_tmpl.h"
3985 #include "paging_tmpl.h"
3989 #include "paging_tmpl.h"
3993 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3994 struct rsvd_bits_validate *rsvd_check,
3995 int maxphyaddr, int level, bool nx, bool gbpages,
3998 u64 exb_bit_rsvd = 0;
3999 u64 gbpages_bit_rsvd = 0;
4000 u64 nonleaf_bit8_rsvd = 0;
4002 rsvd_check->bad_mt_xwr = 0;
4005 exb_bit_rsvd = rsvd_bits(63, 63);
4007 gbpages_bit_rsvd = rsvd_bits(7, 7);
4010 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4011 * leaf entries) on AMD CPUs only.
4014 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4017 case PT32_ROOT_LEVEL:
4018 /* no rsvd bits for 2 level 4K page table entries */
4019 rsvd_check->rsvd_bits_mask[0][1] = 0;
4020 rsvd_check->rsvd_bits_mask[0][0] = 0;
4021 rsvd_check->rsvd_bits_mask[1][0] =
4022 rsvd_check->rsvd_bits_mask[0][0];
4025 rsvd_check->rsvd_bits_mask[1][1] = 0;
4029 if (is_cpuid_PSE36())
4030 /* 36bits PSE 4MB page */
4031 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4033 /* 32 bits PSE 4MB page */
4034 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4036 case PT32E_ROOT_LEVEL:
4037 rsvd_check->rsvd_bits_mask[0][2] =
4038 rsvd_bits(maxphyaddr, 63) |
4039 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4040 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4041 rsvd_bits(maxphyaddr, 62); /* PDE */
4042 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4043 rsvd_bits(maxphyaddr, 62); /* PTE */
4044 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4045 rsvd_bits(maxphyaddr, 62) |
4046 rsvd_bits(13, 20); /* large page */
4047 rsvd_check->rsvd_bits_mask[1][0] =
4048 rsvd_check->rsvd_bits_mask[0][0];
4050 case PT64_ROOT_5LEVEL:
4051 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4052 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4053 rsvd_bits(maxphyaddr, 51);
4054 rsvd_check->rsvd_bits_mask[1][4] =
4055 rsvd_check->rsvd_bits_mask[0][4];
4057 case PT64_ROOT_4LEVEL:
4058 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4059 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4060 rsvd_bits(maxphyaddr, 51);
4061 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4063 rsvd_bits(maxphyaddr, 51);
4064 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4065 rsvd_bits(maxphyaddr, 51);
4066 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4067 rsvd_bits(maxphyaddr, 51);
4068 rsvd_check->rsvd_bits_mask[1][3] =
4069 rsvd_check->rsvd_bits_mask[0][3];
4070 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4071 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4073 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4074 rsvd_bits(maxphyaddr, 51) |
4075 rsvd_bits(13, 20); /* large page */
4076 rsvd_check->rsvd_bits_mask[1][0] =
4077 rsvd_check->rsvd_bits_mask[0][0];
4082 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4083 struct kvm_mmu *context)
4085 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4086 cpuid_maxphyaddr(vcpu), context->root_level,
4088 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4090 guest_cpuid_is_amd_or_hygon(vcpu));
4094 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4095 int maxphyaddr, bool execonly)
4099 rsvd_check->rsvd_bits_mask[0][4] =
4100 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4101 rsvd_check->rsvd_bits_mask[0][3] =
4102 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4103 rsvd_check->rsvd_bits_mask[0][2] =
4104 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4105 rsvd_check->rsvd_bits_mask[0][1] =
4106 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4107 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4110 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4111 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4112 rsvd_check->rsvd_bits_mask[1][2] =
4113 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4114 rsvd_check->rsvd_bits_mask[1][1] =
4115 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4116 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4118 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4119 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4120 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4121 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4122 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4124 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4125 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4127 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4130 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4131 struct kvm_mmu *context, bool execonly)
4133 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4134 cpuid_maxphyaddr(vcpu), execonly);
4138 * the page table on host is the shadow page table for the page
4139 * table in guest or amd nested guest, its mmu features completely
4140 * follow the features in guest.
4143 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4146 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4147 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4148 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4149 * The iTLB multi-hit workaround can be toggled at any time, so assume
4150 * NX can be used by any non-nested shadow MMU to avoid having to reset
4151 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4153 bool uses_nx = context->nx || !tdp_enabled ||
4154 context->mmu_role.base.smep_andnot_wp;
4155 struct rsvd_bits_validate *shadow_zero_check;
4159 * Passing "true" to the last argument is okay; it adds a check
4160 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4162 shadow_zero_check = &context->shadow_zero_check;
4163 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4165 context->shadow_root_level, uses_nx,
4166 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4167 is_pse(vcpu), true);
4169 if (!shadow_me_mask)
4172 for (i = context->shadow_root_level; --i >= 0;) {
4173 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4174 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4178 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4180 static inline bool boot_cpu_is_amd(void)
4182 WARN_ON_ONCE(!tdp_enabled);
4183 return shadow_x_mask == 0;
4187 * the direct page table on host, use as much mmu features as
4188 * possible, however, kvm currently does not do execution-protection.
4191 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4192 struct kvm_mmu *context)
4194 struct rsvd_bits_validate *shadow_zero_check;
4197 shadow_zero_check = &context->shadow_zero_check;
4199 if (boot_cpu_is_amd())
4200 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4202 context->shadow_root_level, false,
4203 boot_cpu_has(X86_FEATURE_GBPAGES),
4206 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4210 if (!shadow_me_mask)
4213 for (i = context->shadow_root_level; --i >= 0;) {
4214 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4215 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4220 * as the comments in reset_shadow_zero_bits_mask() except it
4221 * is the shadow page table for intel nested guest.
4224 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4225 struct kvm_mmu *context, bool execonly)
4227 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4228 shadow_phys_bits, execonly);
4231 #define BYTE_MASK(access) \
4232 ((1 & (access) ? 2 : 0) | \
4233 (2 & (access) ? 4 : 0) | \
4234 (3 & (access) ? 8 : 0) | \
4235 (4 & (access) ? 16 : 0) | \
4236 (5 & (access) ? 32 : 0) | \
4237 (6 & (access) ? 64 : 0) | \
4238 (7 & (access) ? 128 : 0))
4241 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4242 struct kvm_mmu *mmu, bool ept)
4246 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4247 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4248 const u8 u = BYTE_MASK(ACC_USER_MASK);
4250 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4251 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4252 bool cr0_wp = is_write_protection(vcpu);
4254 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4255 unsigned pfec = byte << 1;
4258 * Each "*f" variable has a 1 bit for each UWX value
4259 * that causes a fault with the given PFEC.
4262 /* Faults from writes to non-writable pages */
4263 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4264 /* Faults from user mode accesses to supervisor pages */
4265 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4266 /* Faults from fetches of non-executable pages*/
4267 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4268 /* Faults from kernel mode fetches of user pages */
4270 /* Faults from kernel mode accesses of user pages */
4274 /* Faults from kernel mode accesses to user pages */
4275 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4277 /* Not really needed: !nx will cause pte.nx to fault */
4281 /* Allow supervisor writes if !cr0.wp */
4283 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4285 /* Disallow supervisor fetches of user code if cr4.smep */
4287 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4290 * SMAP:kernel-mode data accesses from user-mode
4291 * mappings should fault. A fault is considered
4292 * as a SMAP violation if all of the following
4293 * conditions are true:
4294 * - X86_CR4_SMAP is set in CR4
4295 * - A user page is accessed
4296 * - The access is not a fetch
4297 * - Page fault in kernel mode
4298 * - if CPL = 3 or X86_EFLAGS_AC is clear
4300 * Here, we cover the first three conditions.
4301 * The fourth is computed dynamically in permission_fault();
4302 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4303 * *not* subject to SMAP restrictions.
4306 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4309 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4314 * PKU is an additional mechanism by which the paging controls access to
4315 * user-mode addresses based on the value in the PKRU register. Protection
4316 * key violations are reported through a bit in the page fault error code.
4317 * Unlike other bits of the error code, the PK bit is not known at the
4318 * call site of e.g. gva_to_gpa; it must be computed directly in
4319 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4320 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4322 * In particular the following conditions come from the error code, the
4323 * page tables and the machine state:
4324 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4325 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4326 * - PK is always zero if U=0 in the page tables
4327 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4329 * The PKRU bitmask caches the result of these four conditions. The error
4330 * code (minus the P bit) and the page table's U bit form an index into the
4331 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4332 * with the two bits of the PKRU register corresponding to the protection key.
4333 * For the first three conditions above the bits will be 00, thus masking
4334 * away both AD and WD. For all reads or if the last condition holds, WD
4335 * only will be masked away.
4337 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4348 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4349 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4354 wp = is_write_protection(vcpu);
4356 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4357 unsigned pfec, pkey_bits;
4358 bool check_pkey, check_write, ff, uf, wf, pte_user;
4361 ff = pfec & PFERR_FETCH_MASK;
4362 uf = pfec & PFERR_USER_MASK;
4363 wf = pfec & PFERR_WRITE_MASK;
4365 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4366 pte_user = pfec & PFERR_RSVD_MASK;
4369 * Only need to check the access which is not an
4370 * instruction fetch and is to a user page.
4372 check_pkey = (!ff && pte_user);
4374 * write access is controlled by PKRU if it is a
4375 * user access or CR0.WP = 1.
4377 check_write = check_pkey && wf && (uf || wp);
4379 /* PKRU.AD stops both read and write access. */
4380 pkey_bits = !!check_pkey;
4381 /* PKRU.WD stops write access. */
4382 pkey_bits |= (!!check_write) << 1;
4384 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4388 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4390 unsigned root_level = mmu->root_level;
4392 mmu->last_nonleaf_level = root_level;
4393 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4394 mmu->last_nonleaf_level++;
4397 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4398 struct kvm_mmu *context,
4401 context->nx = is_nx(vcpu);
4402 context->root_level = level;
4404 reset_rsvds_bits_mask(vcpu, context);
4405 update_permission_bitmask(vcpu, context, false);
4406 update_pkru_bitmask(vcpu, context, false);
4407 update_last_nonleaf_level(vcpu, context);
4409 MMU_WARN_ON(!is_pae(vcpu));
4410 context->page_fault = paging64_page_fault;
4411 context->gva_to_gpa = paging64_gva_to_gpa;
4412 context->sync_page = paging64_sync_page;
4413 context->invlpg = paging64_invlpg;
4414 context->shadow_root_level = level;
4415 context->direct_map = false;
4418 static void paging64_init_context(struct kvm_vcpu *vcpu,
4419 struct kvm_mmu *context)
4421 int root_level = is_la57_mode(vcpu) ?
4422 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4424 paging64_init_context_common(vcpu, context, root_level);
4427 static void paging32_init_context(struct kvm_vcpu *vcpu,
4428 struct kvm_mmu *context)
4430 context->nx = false;
4431 context->root_level = PT32_ROOT_LEVEL;
4433 reset_rsvds_bits_mask(vcpu, context);
4434 update_permission_bitmask(vcpu, context, false);
4435 update_pkru_bitmask(vcpu, context, false);
4436 update_last_nonleaf_level(vcpu, context);
4438 context->page_fault = paging32_page_fault;
4439 context->gva_to_gpa = paging32_gva_to_gpa;
4440 context->sync_page = paging32_sync_page;
4441 context->invlpg = paging32_invlpg;
4442 context->shadow_root_level = PT32E_ROOT_LEVEL;
4443 context->direct_map = false;
4446 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4447 struct kvm_mmu *context)
4449 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4452 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4454 union kvm_mmu_extended_role ext = {0};
4456 ext.cr0_pg = !!is_paging(vcpu);
4457 ext.cr4_pae = !!is_pae(vcpu);
4458 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4459 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4460 ext.cr4_pse = !!is_pse(vcpu);
4461 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4462 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4463 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4470 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4473 union kvm_mmu_role role = {0};
4475 role.base.access = ACC_ALL;
4476 role.base.nxe = !!is_nx(vcpu);
4477 role.base.cr0_wp = is_write_protection(vcpu);
4478 role.base.smm = is_smm(vcpu);
4479 role.base.guest_mode = is_guest_mode(vcpu);
4484 role.ext = kvm_calc_mmu_role_ext(vcpu);
4489 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4491 /* Use 5-level TDP if and only if it's useful/necessary. */
4492 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4495 return max_tdp_level;
4498 static union kvm_mmu_role
4499 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4501 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4503 role.base.ad_disabled = (shadow_accessed_mask == 0);
4504 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4505 role.base.direct = true;
4506 role.base.gpte_is_8_bytes = true;
4511 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4513 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4514 union kvm_mmu_role new_role =
4515 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4517 if (new_role.as_u64 == context->mmu_role.as_u64)
4520 context->mmu_role.as_u64 = new_role.as_u64;
4521 context->page_fault = kvm_tdp_page_fault;
4522 context->sync_page = nonpaging_sync_page;
4523 context->invlpg = NULL;
4524 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4525 context->direct_map = true;
4526 context->get_guest_pgd = get_cr3;
4527 context->get_pdptr = kvm_pdptr_read;
4528 context->inject_page_fault = kvm_inject_page_fault;
4530 if (!is_paging(vcpu)) {
4531 context->nx = false;
4532 context->gva_to_gpa = nonpaging_gva_to_gpa;
4533 context->root_level = 0;
4534 } else if (is_long_mode(vcpu)) {
4535 context->nx = is_nx(vcpu);
4536 context->root_level = is_la57_mode(vcpu) ?
4537 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4538 reset_rsvds_bits_mask(vcpu, context);
4539 context->gva_to_gpa = paging64_gva_to_gpa;
4540 } else if (is_pae(vcpu)) {
4541 context->nx = is_nx(vcpu);
4542 context->root_level = PT32E_ROOT_LEVEL;
4543 reset_rsvds_bits_mask(vcpu, context);
4544 context->gva_to_gpa = paging64_gva_to_gpa;
4546 context->nx = false;
4547 context->root_level = PT32_ROOT_LEVEL;
4548 reset_rsvds_bits_mask(vcpu, context);
4549 context->gva_to_gpa = paging32_gva_to_gpa;
4552 update_permission_bitmask(vcpu, context, false);
4553 update_pkru_bitmask(vcpu, context, false);
4554 update_last_nonleaf_level(vcpu, context);
4555 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4558 static union kvm_mmu_role
4559 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4561 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4563 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4564 !is_write_protection(vcpu);
4565 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4566 !is_write_protection(vcpu);
4567 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4572 static union kvm_mmu_role
4573 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4575 union kvm_mmu_role role =
4576 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4578 role.base.direct = !is_paging(vcpu);
4580 if (!is_long_mode(vcpu))
4581 role.base.level = PT32E_ROOT_LEVEL;
4582 else if (is_la57_mode(vcpu))
4583 role.base.level = PT64_ROOT_5LEVEL;
4585 role.base.level = PT64_ROOT_4LEVEL;
4590 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4591 u32 cr0, u32 cr4, u32 efer,
4592 union kvm_mmu_role new_role)
4594 if (!(cr0 & X86_CR0_PG))
4595 nonpaging_init_context(vcpu, context);
4596 else if (efer & EFER_LMA)
4597 paging64_init_context(vcpu, context);
4598 else if (cr4 & X86_CR4_PAE)
4599 paging32E_init_context(vcpu, context);
4601 paging32_init_context(vcpu, context);
4603 context->mmu_role.as_u64 = new_role.as_u64;
4604 reset_shadow_zero_bits_mask(vcpu, context);
4607 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4609 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4610 union kvm_mmu_role new_role =
4611 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4613 if (new_role.as_u64 != context->mmu_role.as_u64)
4614 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4617 static union kvm_mmu_role
4618 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4620 union kvm_mmu_role role =
4621 kvm_calc_shadow_root_page_role_common(vcpu, false);
4623 role.base.direct = false;
4624 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4629 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4632 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4633 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4635 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false);
4637 if (new_role.as_u64 != context->mmu_role.as_u64) {
4638 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4641 * Override the level set by the common init helper, nested TDP
4642 * always uses the host's TDP configuration.
4644 context->shadow_root_level = new_role.base.level;
4647 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4649 static union kvm_mmu_role
4650 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4651 bool execonly, u8 level)
4653 union kvm_mmu_role role = {0};
4655 /* SMM flag is inherited from root_mmu */
4656 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4658 role.base.level = level;
4659 role.base.gpte_is_8_bytes = true;
4660 role.base.direct = false;
4661 role.base.ad_disabled = !accessed_dirty;
4662 role.base.guest_mode = true;
4663 role.base.access = ACC_ALL;
4666 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4667 * SMAP variation to denote shadow EPT entries.
4669 role.base.cr0_wp = true;
4670 role.base.smap_andnot_wp = true;
4672 role.ext = kvm_calc_mmu_role_ext(vcpu);
4673 role.ext.execonly = execonly;
4678 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4679 bool accessed_dirty, gpa_t new_eptp)
4681 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4682 u8 level = vmx_eptp_page_walk_level(new_eptp);
4683 union kvm_mmu_role new_role =
4684 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4687 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
4689 if (new_role.as_u64 == context->mmu_role.as_u64)
4692 context->shadow_root_level = level;
4695 context->ept_ad = accessed_dirty;
4696 context->page_fault = ept_page_fault;
4697 context->gva_to_gpa = ept_gva_to_gpa;
4698 context->sync_page = ept_sync_page;
4699 context->invlpg = ept_invlpg;
4700 context->root_level = level;
4701 context->direct_map = false;
4702 context->mmu_role.as_u64 = new_role.as_u64;
4704 update_permission_bitmask(vcpu, context, true);
4705 update_pkru_bitmask(vcpu, context, true);
4706 update_last_nonleaf_level(vcpu, context);
4707 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4708 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4710 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4712 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4714 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4716 kvm_init_shadow_mmu(vcpu,
4717 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4718 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4721 context->get_guest_pgd = get_cr3;
4722 context->get_pdptr = kvm_pdptr_read;
4723 context->inject_page_fault = kvm_inject_page_fault;
4726 static union kvm_mmu_role kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu)
4728 union kvm_mmu_role role = kvm_calc_shadow_root_page_role_common(vcpu, false);
4731 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4732 * shadow pages of their own and so "direct" has no meaning. Set it
4733 * to "true" to try to detect bogus usage of the nested MMU.
4735 role.base.direct = true;
4737 if (!is_paging(vcpu))
4738 role.base.level = 0;
4739 else if (is_long_mode(vcpu))
4740 role.base.level = is_la57_mode(vcpu) ? PT64_ROOT_5LEVEL :
4742 else if (is_pae(vcpu))
4743 role.base.level = PT32E_ROOT_LEVEL;
4745 role.base.level = PT32_ROOT_LEVEL;
4750 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4752 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu);
4753 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4755 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4758 g_context->mmu_role.as_u64 = new_role.as_u64;
4759 g_context->get_guest_pgd = get_cr3;
4760 g_context->get_pdptr = kvm_pdptr_read;
4761 g_context->inject_page_fault = kvm_inject_page_fault;
4764 * L2 page tables are never shadowed, so there is no need to sync
4767 g_context->invlpg = NULL;
4770 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4771 * L1's nested page tables (e.g. EPT12). The nested translation
4772 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4773 * L2's page tables as the first level of translation and L1's
4774 * nested page tables as the second level of translation. Basically
4775 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4777 if (!is_paging(vcpu)) {
4778 g_context->nx = false;
4779 g_context->root_level = 0;
4780 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4781 } else if (is_long_mode(vcpu)) {
4782 g_context->nx = is_nx(vcpu);
4783 g_context->root_level = is_la57_mode(vcpu) ?
4784 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4785 reset_rsvds_bits_mask(vcpu, g_context);
4786 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4787 } else if (is_pae(vcpu)) {
4788 g_context->nx = is_nx(vcpu);
4789 g_context->root_level = PT32E_ROOT_LEVEL;
4790 reset_rsvds_bits_mask(vcpu, g_context);
4791 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4793 g_context->nx = false;
4794 g_context->root_level = PT32_ROOT_LEVEL;
4795 reset_rsvds_bits_mask(vcpu, g_context);
4796 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4799 update_permission_bitmask(vcpu, g_context, false);
4800 update_pkru_bitmask(vcpu, g_context, false);
4801 update_last_nonleaf_level(vcpu, g_context);
4804 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4809 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
4811 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4812 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4815 if (mmu_is_nested(vcpu))
4816 init_kvm_nested_mmu(vcpu);
4817 else if (tdp_enabled)
4818 init_kvm_tdp_mmu(vcpu);
4820 init_kvm_softmmu(vcpu);
4822 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4824 static union kvm_mmu_page_role
4825 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4827 union kvm_mmu_role role;
4830 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4832 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4837 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4839 kvm_mmu_unload(vcpu);
4840 kvm_init_mmu(vcpu, true);
4842 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4844 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4848 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4851 r = mmu_alloc_roots(vcpu);
4852 kvm_mmu_sync_roots(vcpu);
4855 kvm_mmu_load_pgd(vcpu);
4856 kvm_x86_ops.tlb_flush_current(vcpu);
4860 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4862 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4864 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4865 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4866 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4867 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4869 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4871 static bool need_remote_flush(u64 old, u64 new)
4873 if (!is_shadow_present_pte(old))
4875 if (!is_shadow_present_pte(new))
4877 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4879 old ^= shadow_nx_mask;
4880 new ^= shadow_nx_mask;
4881 return (old & ~new & PT64_PERM_MASK) != 0;
4884 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4891 * Assume that the pte write on a page table of the same type
4892 * as the current vcpu paging mode since we update the sptes only
4893 * when they have the same mode.
4895 if (is_pae(vcpu) && *bytes == 4) {
4896 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4901 if (*bytes == 4 || *bytes == 8) {
4902 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4911 * If we're seeing too many writes to a page, it may no longer be a page table,
4912 * or we may be forking, in which case it is better to unmap the page.
4914 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4917 * Skip write-flooding detected for the sp whose level is 1, because
4918 * it can become unsync, then the guest page is not write-protected.
4920 if (sp->role.level == PG_LEVEL_4K)
4923 atomic_inc(&sp->write_flooding_count);
4924 return atomic_read(&sp->write_flooding_count) >= 3;
4928 * Misaligned accesses are too much trouble to fix up; also, they usually
4929 * indicate a page is not used as a page table.
4931 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4934 unsigned offset, pte_size, misaligned;
4936 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4937 gpa, bytes, sp->role.word);
4939 offset = offset_in_page(gpa);
4940 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
4943 * Sometimes, the OS only writes the last one bytes to update status
4944 * bits, for example, in linux, andb instruction is used in clear_bit().
4946 if (!(offset & (pte_size - 1)) && bytes == 1)
4949 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4950 misaligned |= bytes < 4;
4955 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4957 unsigned page_offset, quadrant;
4961 page_offset = offset_in_page(gpa);
4962 level = sp->role.level;
4964 if (!sp->role.gpte_is_8_bytes) {
4965 page_offset <<= 1; /* 32->64 */
4967 * A 32-bit pde maps 4MB while the shadow pdes map
4968 * only 2MB. So we need to double the offset again
4969 * and zap two pdes instead of one.
4971 if (level == PT32_ROOT_LEVEL) {
4972 page_offset &= ~7; /* kill rounding error */
4976 quadrant = page_offset >> PAGE_SHIFT;
4977 page_offset &= ~PAGE_MASK;
4978 if (quadrant != sp->role.quadrant)
4982 spte = &sp->spt[page_offset / sizeof(*spte)];
4986 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4987 const u8 *new, int bytes,
4988 struct kvm_page_track_notifier_node *node)
4990 gfn_t gfn = gpa >> PAGE_SHIFT;
4991 struct kvm_mmu_page *sp;
4992 LIST_HEAD(invalid_list);
4993 u64 entry, gentry, *spte;
4995 bool remote_flush, local_flush;
4998 * If we don't have indirect shadow pages, it means no page is
4999 * write-protected, so we can exit simply.
5001 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5004 remote_flush = local_flush = false;
5006 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5009 * No need to care whether allocation memory is successful
5010 * or not since pte prefetch is skiped if it does not have
5011 * enough objects in the cache.
5013 mmu_topup_memory_caches(vcpu, true);
5015 spin_lock(&vcpu->kvm->mmu_lock);
5017 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5019 ++vcpu->kvm->stat.mmu_pte_write;
5020 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5022 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5023 if (detect_write_misaligned(sp, gpa, bytes) ||
5024 detect_write_flooding(sp)) {
5025 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5026 ++vcpu->kvm->stat.mmu_flooded;
5030 spte = get_written_sptes(sp, gpa, &npte);
5037 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5038 if (gentry && sp->role.level != PG_LEVEL_4K)
5039 ++vcpu->kvm->stat.mmu_pde_zapped;
5040 if (need_remote_flush(entry, *spte))
5041 remote_flush = true;
5045 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5046 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5047 spin_unlock(&vcpu->kvm->mmu_lock);
5050 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5055 if (vcpu->arch.mmu->direct_map)
5058 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5060 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5064 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5066 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5067 void *insn, int insn_len)
5069 int r, emulation_type = EMULTYPE_PF;
5070 bool direct = vcpu->arch.mmu->direct_map;
5072 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5073 return RET_PF_RETRY;
5076 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5077 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5078 if (r == RET_PF_EMULATE)
5082 if (r == RET_PF_INVALID) {
5083 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5084 lower_32_bits(error_code), false);
5085 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5091 if (r != RET_PF_EMULATE)
5095 * Before emulating the instruction, check if the error code
5096 * was due to a RO violation while translating the guest page.
5097 * This can occur when using nested virtualization with nested
5098 * paging in both guests. If true, we simply unprotect the page
5099 * and resume the guest.
5101 if (vcpu->arch.mmu->direct_map &&
5102 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5103 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5108 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5109 * optimistically try to just unprotect the page and let the processor
5110 * re-execute the instruction that caused the page fault. Do not allow
5111 * retrying MMIO emulation, as it's not only pointless but could also
5112 * cause us to enter an infinite loop because the processor will keep
5113 * faulting on the non-existent MMIO address. Retrying an instruction
5114 * from a nested guest is also pointless and dangerous as we are only
5115 * explicitly shadowing L1's page tables, i.e. unprotecting something
5116 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5118 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5119 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5121 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5124 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5126 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5127 gva_t gva, hpa_t root_hpa)
5131 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5132 if (mmu != &vcpu->arch.guest_mmu) {
5133 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5134 if (is_noncanonical_address(gva, vcpu))
5137 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5143 if (root_hpa == INVALID_PAGE) {
5144 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5147 * INVLPG is required to invalidate any global mappings for the VA,
5148 * irrespective of PCID. Since it would take us roughly similar amount
5149 * of work to determine whether any of the prev_root mappings of the VA
5150 * is marked global, or to just sync it blindly, so we might as well
5151 * just always sync it.
5153 * Mappings not reachable via the current cr3 or the prev_roots will be
5154 * synced when switching to that cr3, so nothing needs to be done here
5157 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5158 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5159 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5161 mmu->invlpg(vcpu, gva, root_hpa);
5164 EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva);
5166 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5168 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.walk_mmu, gva, INVALID_PAGE);
5169 ++vcpu->stat.invlpg;
5171 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5174 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5176 struct kvm_mmu *mmu = vcpu->arch.mmu;
5177 bool tlb_flush = false;
5180 if (pcid == kvm_get_active_pcid(vcpu)) {
5182 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5186 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5187 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5188 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5190 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5196 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5198 ++vcpu->stat.invlpg;
5201 * Mappings not reachable via the current cr3 or the prev_roots will be
5202 * synced when switching to that cr3, so nothing needs to be done here
5206 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5208 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5209 int tdp_huge_page_level)
5211 tdp_enabled = enable_tdp;
5212 max_tdp_level = tdp_max_root_level;
5215 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5216 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5217 * the kernel is not. But, KVM never creates a page size greater than
5218 * what is used by the kernel for any given HVA, i.e. the kernel's
5219 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5222 max_huge_page_level = tdp_huge_page_level;
5223 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5224 max_huge_page_level = PG_LEVEL_1G;
5226 max_huge_page_level = PG_LEVEL_2M;
5228 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5230 /* The return value indicates if tlb flush on all vcpus is needed. */
5231 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5233 /* The caller should hold mmu-lock before calling this function. */
5234 static __always_inline bool
5235 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5236 slot_level_handler fn, int start_level, int end_level,
5237 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5239 struct slot_rmap_walk_iterator iterator;
5242 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5243 end_gfn, &iterator) {
5245 flush |= fn(kvm, iterator.rmap);
5247 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5248 if (flush && lock_flush_tlb) {
5249 kvm_flush_remote_tlbs_with_address(kvm,
5251 iterator.gfn - start_gfn + 1);
5254 cond_resched_lock(&kvm->mmu_lock);
5258 if (flush && lock_flush_tlb) {
5259 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5260 end_gfn - start_gfn + 1);
5267 static __always_inline bool
5268 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5269 slot_level_handler fn, int start_level, int end_level,
5270 bool lock_flush_tlb)
5272 return slot_handle_level_range(kvm, memslot, fn, start_level,
5273 end_level, memslot->base_gfn,
5274 memslot->base_gfn + memslot->npages - 1,
5278 static __always_inline bool
5279 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5280 slot_level_handler fn, bool lock_flush_tlb)
5282 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5283 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5286 static __always_inline bool
5287 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5288 slot_level_handler fn, bool lock_flush_tlb)
5290 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1,
5291 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5294 static __always_inline bool
5295 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5296 slot_level_handler fn, bool lock_flush_tlb)
5298 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5299 PG_LEVEL_4K, lock_flush_tlb);
5302 static void free_mmu_pages(struct kvm_mmu *mmu)
5304 free_page((unsigned long)mmu->pae_root);
5305 free_page((unsigned long)mmu->lm_root);
5308 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5313 mmu->root_hpa = INVALID_PAGE;
5315 mmu->translate_gpa = translate_gpa;
5316 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5317 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5320 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5321 * while the PDP table is a per-vCPU construct that's allocated at MMU
5322 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5323 * x86_64. Therefore we need to allocate the PDP table in the first
5324 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5325 * generally doesn't use PAE paging and can skip allocating the PDP
5326 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5327 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5328 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5330 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5333 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5337 mmu->pae_root = page_address(page);
5338 for (i = 0; i < 4; ++i)
5339 mmu->pae_root[i] = INVALID_PAGE;
5344 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5348 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5349 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5351 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5352 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5354 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5356 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5357 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5359 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5361 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5365 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5367 goto fail_allocate_root;
5371 free_mmu_pages(&vcpu->arch.guest_mmu);
5375 #define BATCH_ZAP_PAGES 10
5376 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5378 struct kvm_mmu_page *sp, *node;
5379 int nr_zapped, batch = 0;
5383 list_for_each_entry_safe_reverse(sp, node,
5384 &kvm->arch.active_mmu_pages, link) {
5386 * No obsolete valid page exists before a newly created page
5387 * since active_mmu_pages is a FIFO list.
5389 if (!is_obsolete_sp(kvm, sp))
5393 * Invalid pages should never land back on the list of active
5394 * pages. Skip the bogus page, otherwise we'll get stuck in an
5395 * infinite loop if the page gets put back on the list (again).
5397 if (WARN_ON(sp->role.invalid))
5401 * No need to flush the TLB since we're only zapping shadow
5402 * pages with an obsolete generation number and all vCPUS have
5403 * loaded a new root, i.e. the shadow pages being zapped cannot
5404 * be in active use by the guest.
5406 if (batch >= BATCH_ZAP_PAGES &&
5407 cond_resched_lock(&kvm->mmu_lock)) {
5412 unstable = __kvm_mmu_prepare_zap_page(kvm, sp,
5413 &kvm->arch.zapped_obsolete_pages, &nr_zapped);
5421 * Trigger a remote TLB flush before freeing the page tables to ensure
5422 * KVM is not in the middle of a lockless shadow page table walk, which
5423 * may reference the pages.
5425 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5429 * Fast invalidate all shadow pages and use lock-break technique
5430 * to zap obsolete pages.
5432 * It's required when memslot is being deleted or VM is being
5433 * destroyed, in these cases, we should ensure that KVM MMU does
5434 * not use any resource of the being-deleted slot or all slots
5435 * after calling the function.
5437 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5439 lockdep_assert_held(&kvm->slots_lock);
5441 spin_lock(&kvm->mmu_lock);
5442 trace_kvm_mmu_zap_all_fast(kvm);
5445 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5446 * held for the entire duration of zapping obsolete pages, it's
5447 * impossible for there to be multiple invalid generations associated
5448 * with *valid* shadow pages at any given time, i.e. there is exactly
5449 * one valid generation and (at most) one invalid generation.
5451 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5454 * Notify all vcpus to reload its shadow page table and flush TLB.
5455 * Then all vcpus will switch to new shadow page table with the new
5458 * Note: we need to do this under the protection of mmu_lock,
5459 * otherwise, vcpu would purge shadow page but miss tlb flush.
5461 kvm_reload_remote_mmus(kvm);
5463 kvm_zap_obsolete_pages(kvm);
5465 if (kvm->arch.tdp_mmu_enabled)
5466 kvm_tdp_mmu_zap_all(kvm);
5468 spin_unlock(&kvm->mmu_lock);
5471 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5473 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5476 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5477 struct kvm_memory_slot *slot,
5478 struct kvm_page_track_notifier_node *node)
5480 kvm_mmu_zap_all_fast(kvm);
5483 void kvm_mmu_init_vm(struct kvm *kvm)
5485 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5487 kvm_mmu_init_tdp_mmu(kvm);
5489 node->track_write = kvm_mmu_pte_write;
5490 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5491 kvm_page_track_register_notifier(kvm, node);
5494 void kvm_mmu_uninit_vm(struct kvm *kvm)
5496 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5498 kvm_page_track_unregister_notifier(kvm, node);
5500 kvm_mmu_uninit_tdp_mmu(kvm);
5503 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5505 struct kvm_memslots *slots;
5506 struct kvm_memory_slot *memslot;
5510 spin_lock(&kvm->mmu_lock);
5511 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5512 slots = __kvm_memslots(kvm, i);
5513 kvm_for_each_memslot(memslot, slots) {
5516 start = max(gfn_start, memslot->base_gfn);
5517 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5521 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5523 KVM_MAX_HUGEPAGE_LEVEL,
5524 start, end - 1, true);
5528 if (kvm->arch.tdp_mmu_enabled) {
5529 flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end);
5531 kvm_flush_remote_tlbs(kvm);
5534 spin_unlock(&kvm->mmu_lock);
5537 static bool slot_rmap_write_protect(struct kvm *kvm,
5538 struct kvm_rmap_head *rmap_head)
5540 return __rmap_write_protect(kvm, rmap_head, false);
5543 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5544 struct kvm_memory_slot *memslot,
5549 spin_lock(&kvm->mmu_lock);
5550 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5551 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5552 if (kvm->arch.tdp_mmu_enabled)
5553 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_4K);
5554 spin_unlock(&kvm->mmu_lock);
5557 * We can flush all the TLBs out of the mmu lock without TLB
5558 * corruption since we just change the spte from writable to
5559 * readonly so that we only need to care the case of changing
5560 * spte from present to present (changing the spte from present
5561 * to nonpresent will flush all the TLBs immediately), in other
5562 * words, the only case we care is mmu_spte_update() where we
5563 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5564 * instead of PT_WRITABLE_MASK, that means it does not depend
5565 * on PT_WRITABLE_MASK anymore.
5568 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5571 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5572 struct kvm_rmap_head *rmap_head)
5575 struct rmap_iterator iter;
5576 int need_tlb_flush = 0;
5578 struct kvm_mmu_page *sp;
5581 for_each_rmap_spte(rmap_head, &iter, sptep) {
5582 sp = sptep_to_sp(sptep);
5583 pfn = spte_to_pfn(*sptep);
5586 * We cannot do huge page mapping for indirect shadow pages,
5587 * which are found on the last rmap (level = 1) when not using
5588 * tdp; such shadow pages are synced with the page table in
5589 * the guest, and the guest page table is using 4K page size
5590 * mapping if the indirect sp has level = 1.
5592 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5593 (kvm_is_zone_device_pfn(pfn) ||
5594 PageCompound(pfn_to_page(pfn)))) {
5595 pte_list_remove(rmap_head, sptep);
5597 if (kvm_available_flush_tlb_with_range())
5598 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5599 KVM_PAGES_PER_HPAGE(sp->role.level));
5607 return need_tlb_flush;
5610 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5611 const struct kvm_memory_slot *memslot)
5613 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5614 spin_lock(&kvm->mmu_lock);
5615 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5616 kvm_mmu_zap_collapsible_spte, true);
5618 if (kvm->arch.tdp_mmu_enabled)
5619 kvm_tdp_mmu_zap_collapsible_sptes(kvm, memslot);
5620 spin_unlock(&kvm->mmu_lock);
5623 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5624 struct kvm_memory_slot *memslot)
5627 * All current use cases for flushing the TLBs for a specific memslot
5628 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5629 * The interaction between the various operations on memslot must be
5630 * serialized by slots_locks to ensure the TLB flush from one operation
5631 * is observed by any other operation on the same memslot.
5633 lockdep_assert_held(&kvm->slots_lock);
5634 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5638 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5639 struct kvm_memory_slot *memslot)
5643 spin_lock(&kvm->mmu_lock);
5644 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5645 if (kvm->arch.tdp_mmu_enabled)
5646 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5647 spin_unlock(&kvm->mmu_lock);
5650 * It's also safe to flush TLBs out of mmu lock here as currently this
5651 * function is only used for dirty logging, in which case flushing TLB
5652 * out of mmu lock also guarantees no dirty pages will be lost in
5656 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5658 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5660 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5661 struct kvm_memory_slot *memslot)
5665 spin_lock(&kvm->mmu_lock);
5666 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5668 if (kvm->arch.tdp_mmu_enabled)
5669 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_2M);
5670 spin_unlock(&kvm->mmu_lock);
5673 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5675 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5677 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5678 struct kvm_memory_slot *memslot)
5682 spin_lock(&kvm->mmu_lock);
5683 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5684 if (kvm->arch.tdp_mmu_enabled)
5685 flush |= kvm_tdp_mmu_slot_set_dirty(kvm, memslot);
5686 spin_unlock(&kvm->mmu_lock);
5689 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5691 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5693 void kvm_mmu_zap_all(struct kvm *kvm)
5695 struct kvm_mmu_page *sp, *node;
5696 LIST_HEAD(invalid_list);
5699 spin_lock(&kvm->mmu_lock);
5701 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5702 if (WARN_ON(sp->role.invalid))
5704 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5706 if (cond_resched_lock(&kvm->mmu_lock))
5710 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5712 if (kvm->arch.tdp_mmu_enabled)
5713 kvm_tdp_mmu_zap_all(kvm);
5715 spin_unlock(&kvm->mmu_lock);
5718 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5720 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5722 gen &= MMIO_SPTE_GEN_MASK;
5725 * Generation numbers are incremented in multiples of the number of
5726 * address spaces in order to provide unique generations across all
5727 * address spaces. Strip what is effectively the address space
5728 * modifier prior to checking for a wrap of the MMIO generation so
5729 * that a wrap in any address space is detected.
5731 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5734 * The very rare case: if the MMIO generation number has wrapped,
5735 * zap all shadow pages.
5737 if (unlikely(gen == 0)) {
5738 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5739 kvm_mmu_zap_all_fast(kvm);
5743 static unsigned long
5744 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5747 int nr_to_scan = sc->nr_to_scan;
5748 unsigned long freed = 0;
5750 mutex_lock(&kvm_lock);
5752 list_for_each_entry(kvm, &vm_list, vm_list) {
5754 LIST_HEAD(invalid_list);
5757 * Never scan more than sc->nr_to_scan VM instances.
5758 * Will not hit this condition practically since we do not try
5759 * to shrink more than one VM and it is very unlikely to see
5760 * !n_used_mmu_pages so many times.
5765 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5766 * here. We may skip a VM instance errorneosly, but we do not
5767 * want to shrink a VM that only started to populate its MMU
5770 if (!kvm->arch.n_used_mmu_pages &&
5771 !kvm_has_zapped_obsolete_pages(kvm))
5774 idx = srcu_read_lock(&kvm->srcu);
5775 spin_lock(&kvm->mmu_lock);
5777 if (kvm_has_zapped_obsolete_pages(kvm)) {
5778 kvm_mmu_commit_zap_page(kvm,
5779 &kvm->arch.zapped_obsolete_pages);
5783 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5786 spin_unlock(&kvm->mmu_lock);
5787 srcu_read_unlock(&kvm->srcu, idx);
5790 * unfair on small ones
5791 * per-vm shrinkers cry out
5792 * sadness comes quickly
5794 list_move_tail(&kvm->vm_list, &vm_list);
5798 mutex_unlock(&kvm_lock);
5802 static unsigned long
5803 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5805 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5808 static struct shrinker mmu_shrinker = {
5809 .count_objects = mmu_shrink_count,
5810 .scan_objects = mmu_shrink_scan,
5811 .seeks = DEFAULT_SEEKS * 10,
5814 static void mmu_destroy_caches(void)
5816 kmem_cache_destroy(pte_list_desc_cache);
5817 kmem_cache_destroy(mmu_page_header_cache);
5820 static void kvm_set_mmio_spte_mask(void)
5825 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
5826 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
5827 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
5828 * 52-bit physical addresses then there are no reserved PA bits in the
5829 * PTEs and so the reserved PA approach must be disabled.
5831 if (shadow_phys_bits < 52)
5832 mask = BIT_ULL(51) | PT_PRESENT_MASK;
5836 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
5839 static bool get_nx_auto_mode(void)
5841 /* Return true when CPU has the bug, and mitigations are ON */
5842 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5845 static void __set_nx_huge_pages(bool val)
5847 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5850 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5852 bool old_val = nx_huge_pages;
5855 /* In "auto" mode deploy workaround only if CPU has the bug. */
5856 if (sysfs_streq(val, "off"))
5858 else if (sysfs_streq(val, "force"))
5860 else if (sysfs_streq(val, "auto"))
5861 new_val = get_nx_auto_mode();
5862 else if (strtobool(val, &new_val) < 0)
5865 __set_nx_huge_pages(new_val);
5867 if (new_val != old_val) {
5870 mutex_lock(&kvm_lock);
5872 list_for_each_entry(kvm, &vm_list, vm_list) {
5873 mutex_lock(&kvm->slots_lock);
5874 kvm_mmu_zap_all_fast(kvm);
5875 mutex_unlock(&kvm->slots_lock);
5877 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5879 mutex_unlock(&kvm_lock);
5886 * nx_huge_pages needs to be resolved to true/false when kvm.ko is loaded, as
5887 * its default value of -1 is technically undefined behavior for a boolean.
5889 void __init kvm_mmu_x86_module_init(void)
5891 if (nx_huge_pages == -1)
5892 __set_nx_huge_pages(get_nx_auto_mode());
5896 * The bulk of the MMU initialization is deferred until the vendor module is
5897 * loaded as many of the masks/values may be modified by VMX or SVM, i.e. need
5898 * to be reset when a potentially different vendor module is loaded.
5900 int kvm_mmu_vendor_module_init(void)
5905 * MMU roles use union aliasing which is, generally speaking, an
5906 * undefined behavior. However, we supposedly know how compilers behave
5907 * and the current status quo is unlikely to change. Guardians below are
5908 * supposed to let us know if the assumption becomes false.
5910 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5911 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5912 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5914 kvm_mmu_reset_all_pte_masks();
5916 kvm_set_mmio_spte_mask();
5918 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5919 sizeof(struct pte_list_desc),
5920 0, SLAB_ACCOUNT, NULL);
5921 if (!pte_list_desc_cache)
5924 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5925 sizeof(struct kvm_mmu_page),
5926 0, SLAB_ACCOUNT, NULL);
5927 if (!mmu_page_header_cache)
5930 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5933 ret = register_shrinker(&mmu_shrinker);
5940 mmu_destroy_caches();
5945 * Calculate mmu pages needed for kvm.
5947 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5949 unsigned long nr_mmu_pages;
5950 unsigned long nr_pages = 0;
5951 struct kvm_memslots *slots;
5952 struct kvm_memory_slot *memslot;
5955 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5956 slots = __kvm_memslots(kvm, i);
5958 kvm_for_each_memslot(memslot, slots)
5959 nr_pages += memslot->npages;
5962 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5963 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5965 return nr_mmu_pages;
5968 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5970 kvm_mmu_unload(vcpu);
5971 free_mmu_pages(&vcpu->arch.root_mmu);
5972 free_mmu_pages(&vcpu->arch.guest_mmu);
5973 mmu_free_memory_caches(vcpu);
5976 void kvm_mmu_vendor_module_exit(void)
5978 mmu_destroy_caches();
5979 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5980 unregister_shrinker(&mmu_shrinker);
5981 mmu_audit_disable();
5984 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
5986 unsigned int old_val;
5989 old_val = nx_huge_pages_recovery_ratio;
5990 err = param_set_uint(val, kp);
5994 if (READ_ONCE(nx_huge_pages) &&
5995 !old_val && nx_huge_pages_recovery_ratio) {
5998 mutex_lock(&kvm_lock);
6000 list_for_each_entry(kvm, &vm_list, vm_list)
6001 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6003 mutex_unlock(&kvm_lock);
6009 static void kvm_recover_nx_lpages(struct kvm *kvm)
6012 struct kvm_mmu_page *sp;
6014 LIST_HEAD(invalid_list);
6018 rcu_idx = srcu_read_lock(&kvm->srcu);
6019 spin_lock(&kvm->mmu_lock);
6021 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6022 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
6023 for ( ; to_zap; --to_zap) {
6024 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6028 * We use a separate list instead of just using active_mmu_pages
6029 * because the number of lpage_disallowed pages is expected to
6030 * be relatively small compared to the total.
6032 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6033 struct kvm_mmu_page,
6034 lpage_disallowed_link);
6035 WARN_ON_ONCE(!sp->lpage_disallowed);
6036 if (sp->tdp_mmu_page) {
6037 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6039 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6040 WARN_ON_ONCE(sp->lpage_disallowed);
6043 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
6044 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6045 cond_resched_lock(&kvm->mmu_lock);
6049 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6051 spin_unlock(&kvm->mmu_lock);
6052 srcu_read_unlock(&kvm->srcu, rcu_idx);
6055 static long get_nx_lpage_recovery_timeout(u64 start_time)
6057 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6058 ? start_time + 60 * HZ - get_jiffies_64()
6059 : MAX_SCHEDULE_TIMEOUT;
6062 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6065 long remaining_time;
6068 start_time = get_jiffies_64();
6069 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6071 set_current_state(TASK_INTERRUPTIBLE);
6072 while (!kthread_should_stop() && remaining_time > 0) {
6073 schedule_timeout(remaining_time);
6074 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6075 set_current_state(TASK_INTERRUPTIBLE);
6078 set_current_state(TASK_RUNNING);
6080 if (kthread_should_stop())
6083 kvm_recover_nx_lpages(kvm);
6087 int kvm_mmu_post_init_vm(struct kvm *kvm)
6091 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6092 "kvm-nx-lpage-recovery",
6093 &kvm->arch.nx_lpage_recovery_thread);
6095 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6100 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6102 if (kvm->arch.nx_lpage_recovery_thread)
6103 kthread_stop(kvm->arch.nx_lpage_recovery_thread);