1 // SPDX-License-Identifier: GPL-2.0
3 * check TSC synchronization.
5 * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
7 * We check whether all boot CPUs have their TSC's synchronized,
8 * print a warning if not and turn off the TSC clock-source.
10 * The warp-check is point-to-point between two CPUs, the CPU
11 * initiating the bootup is the 'source CPU', the freshly booting
12 * CPU is the 'target CPU'.
14 * Only two CPUs may participate - they can enter in any order.
15 * ( The serial nature of the boot logic and the CPU hotplug lock
16 * protects against more than 2 CPUs entering this code. )
18 #include <linux/workqueue.h>
19 #include <linux/topology.h>
20 #include <linux/spinlock.h>
21 #include <linux/kernel.h>
22 #include <linux/smp.h>
23 #include <linux/nmi.h>
29 unsigned long nextcheck;
33 static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
34 static struct timer_list tsc_sync_check_timer;
37 * TSC's on different sockets may be reset asynchronously.
38 * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
40 bool __read_mostly tsc_async_resets;
42 void mark_tsc_async_resets(char *reason)
46 tsc_async_resets = true;
47 pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
50 void tsc_verify_tsc_adjust(bool resume)
52 struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
55 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
58 /* Skip unnecessary error messages if TSC already unstable */
59 if (check_tsc_unstable())
62 /* Rate limit the MSR check */
63 if (!resume && time_before(jiffies, adj->nextcheck))
66 adj->nextcheck = jiffies + HZ;
68 rdmsrl(MSR_IA32_TSC_ADJUST, curval);
69 if (adj->adjusted == curval)
72 /* Restore the original value */
73 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);
75 if (!adj->warned || resume) {
76 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
77 smp_processor_id(), adj->adjusted, curval);
83 * Normally the tsc_sync will be checked every time system enters idle
84 * state, but there is still caveat that a system won't enter idle,
85 * either because it's too busy or configured purposely to not enter
88 * So setup a periodic timer (every 10 minutes) to make sure the check
92 #define SYNC_CHECK_INTERVAL (HZ * 600)
94 static void tsc_sync_check_timer_fn(struct timer_list *unused)
98 tsc_verify_tsc_adjust(false);
100 /* Run the check for all onlined CPUs in turn */
101 next_cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask);
102 if (next_cpu >= nr_cpu_ids)
103 next_cpu = cpumask_first(cpu_online_mask);
105 tsc_sync_check_timer.expires += SYNC_CHECK_INTERVAL;
106 add_timer_on(&tsc_sync_check_timer, next_cpu);
109 static int __init start_sync_check_timer(void)
111 if (!cpu_feature_enabled(X86_FEATURE_TSC_ADJUST) || tsc_clocksource_reliable)
114 timer_setup(&tsc_sync_check_timer, tsc_sync_check_timer_fn, 0);
115 tsc_sync_check_timer.expires = jiffies + SYNC_CHECK_INTERVAL;
116 add_timer(&tsc_sync_check_timer);
120 late_initcall(start_sync_check_timer);
122 static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
123 unsigned int cpu, bool bootcpu)
126 * First online CPU in a package stores the boot value in the
127 * adjustment value. This value might change later via the sync
128 * mechanism. If that fails we still can yell about boot values not
131 * On the boot cpu we just force set the ADJUST value to 0 if it's
132 * non zero. We don't do that on non boot cpus because physical
133 * hotplug should have set the ADJUST register to a value > 0 so
134 * the TSC is in sync with the already running cpus.
136 * Also don't force the ADJUST value to zero if that is a valid value
137 * for socket 0 as determined by the system arch. This is required
138 * when multiple sockets are reset asynchronously with each other
139 * and socket 0 may not have an TSC ADJUST value of 0.
141 if (bootcpu && bootval != 0) {
142 if (likely(!tsc_async_resets)) {
143 pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
145 wrmsrl(MSR_IA32_TSC_ADJUST, 0);
148 pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
152 cur->adjusted = bootval;
156 bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
158 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
161 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
164 /* Skip unnecessary error messages if TSC already unstable */
165 if (check_tsc_unstable())
168 rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
169 cur->bootval = bootval;
170 cur->nextcheck = jiffies + HZ;
171 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
175 #else /* !CONFIG_SMP */
178 * Store and check the TSC ADJUST MSR if available
180 bool tsc_store_and_check_tsc_adjust(bool bootcpu)
182 struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust);
183 unsigned int refcpu, cpu = smp_processor_id();
184 struct cpumask *mask;
187 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
190 rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
191 cur->bootval = bootval;
192 cur->nextcheck = jiffies + HZ;
196 * If a non-zero TSC value for socket 0 may be valid then the default
197 * adjusted value cannot assumed to be zero either.
199 if (tsc_async_resets)
200 cur->adjusted = bootval;
203 * Check whether this CPU is the first in a package to come up. In
204 * this case do not check the boot value against another package
205 * because the new package might have been physically hotplugged,
206 * where TSC_ADJUST is expected to be different. When called on the
207 * boot CPU topology_core_cpumask() might not be available yet.
209 mask = topology_core_cpumask(cpu);
210 refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
212 if (refcpu >= nr_cpu_ids) {
213 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
218 ref = per_cpu_ptr(&tsc_adjust, refcpu);
220 * Compare the boot value and complain if it differs in the
223 if (bootval != ref->bootval)
224 printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
227 * The TSC_ADJUST values in a package must be the same. If the boot
228 * value on this newly upcoming CPU differs from the adjustment
229 * value of the already online CPU in this package, set it to that
232 if (bootval != ref->adjusted) {
233 cur->adjusted = ref->adjusted;
234 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
237 * We have the TSCs forced to be in sync on this package. Skip sync
244 * Entry/exit counters that make sure that both CPUs
245 * run the measurement code at once:
247 static atomic_t start_count;
248 static atomic_t stop_count;
249 static atomic_t test_runs;
252 * We use a raw spinlock in this exceptional case, because
253 * we want to have the fastest, inlined, non-debug version
254 * of a critical section, to be able to prove TSC time-warps:
256 static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
258 static cycles_t last_tsc;
259 static cycles_t max_warp;
261 static int random_warps;
264 * TSC-warp measurement loop running on both CPUs. This is not called
265 * if there is no TSC.
267 static cycles_t check_tsc_warp(unsigned int timeout)
269 cycles_t start, now, prev, end, cur_max_warp = 0;
270 int i, cur_warps = 0;
272 start = rdtsc_ordered();
274 * The measurement runs for 'timeout' msecs:
276 end = start + (cycles_t) tsc_khz * timeout;
280 * We take the global lock, measure TSC, save the
281 * previous TSC that was measured (possibly on
282 * another CPU) and update the previous TSC timestamp.
284 arch_spin_lock(&sync_lock);
286 now = rdtsc_ordered();
288 arch_spin_unlock(&sync_lock);
291 * Be nice every now and then (and also check whether
292 * measurement is done [we also insert a 10 million
293 * loops safety exit, so we dont lock up in case the
294 * TSC readout is totally broken]):
296 if (unlikely(!(i & 7))) {
297 if (now > end || i > 10000000)
300 touch_nmi_watchdog();
303 * Outside the critical section we can now see whether
304 * we saw a time-warp of the TSC going backwards:
306 if (unlikely(prev > now)) {
307 arch_spin_lock(&sync_lock);
308 max_warp = max(max_warp, prev - now);
309 cur_max_warp = max_warp;
311 * Check whether this bounces back and forth. Only
312 * one CPU should observe time going backwards.
314 if (cur_warps != nr_warps)
317 cur_warps = nr_warps;
318 arch_spin_unlock(&sync_lock);
322 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
323 now-start, end-start);
328 * If the target CPU coming online doesn't have any of its core-siblings
329 * online, a timeout of 20msec will be used for the TSC-warp measurement
330 * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
331 * information about this socket already (and this information grows as we
332 * have more and more logical-siblings in that socket).
334 * Ideally we should be able to skip the TSC sync check on the other
335 * core-siblings, if the first logical CPU in a socket passed the sync test.
336 * But as the TSC is per-logical CPU and can potentially be modified wrongly
337 * by the bios, TSC sync test for smaller duration should be able
338 * to catch such errors. Also this will catch the condition where all the
339 * cores in the socket don't get reset at the same time.
341 static inline unsigned int loop_timeout(int cpu)
343 return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
346 static void tsc_sync_mark_tsc_unstable(struct work_struct *work)
348 mark_tsc_unstable("check_tsc_sync_source failed");
351 static DECLARE_WORK(tsc_sync_work, tsc_sync_mark_tsc_unstable);
354 * The freshly booted CPU initiates this via an async SMP function call.
356 static void check_tsc_sync_source(void *__cpu)
358 unsigned int cpu = (unsigned long)__cpu;
362 * Set the maximum number of test runs to
363 * 1 if the CPU does not provide the TSC_ADJUST MSR
364 * 3 if the MSR is available, so the target can try to adjust
366 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
367 atomic_set(&test_runs, 1);
369 atomic_set(&test_runs, 3);
371 /* Wait for the target to start. */
372 while (atomic_read(&start_count) != cpus - 1)
376 * Trigger the target to continue into the measurement too:
378 atomic_inc(&start_count);
380 check_tsc_warp(loop_timeout(cpu));
382 while (atomic_read(&stop_count) != cpus-1)
386 * If the test was successful set the number of runs to zero and
387 * stop. If not, decrement the number of runs an check if we can
388 * retry. In case of random warps no retry is attempted.
391 atomic_set(&test_runs, 0);
393 pr_debug("TSC synchronization [CPU#%d -> CPU#%u]: passed\n",
394 smp_processor_id(), cpu);
396 } else if (atomic_dec_and_test(&test_runs) || random_warps) {
397 /* Force it to 0 if random warps brought us here */
398 atomic_set(&test_runs, 0);
400 pr_warn("TSC synchronization [CPU#%d -> CPU#%u]:\n",
401 smp_processor_id(), cpu);
402 pr_warn("Measured %Ld cycles TSC warp between CPUs, "
403 "turning off TSC clock.\n", max_warp);
405 pr_warn("TSC warped randomly between CPUs\n");
406 schedule_work(&tsc_sync_work);
410 * Reset it - just in case we boot another CPU later:
412 atomic_set(&start_count, 0);
419 * Let the target continue with the bootup:
421 atomic_inc(&stop_count);
424 * Retry, if there is a chance to do so.
426 if (atomic_read(&test_runs) > 0)
431 * Freshly booted CPUs call into this:
433 void check_tsc_sync_target(void)
435 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
436 unsigned int cpu = smp_processor_id();
437 cycles_t cur_max_warp, gbl_max_warp;
440 /* Also aborts if there is no TSC. */
441 if (unsynchronized_tsc())
445 * Store, verify and sanitize the TSC adjust register. If
446 * successful skip the test.
448 * The test is also skipped when the TSC is marked reliable. This
449 * is true for SoCs which have no fallback clocksource. On these
450 * SoCs the TSC is frequency synchronized, but still the TSC ADJUST
451 * register might have been wreckaged by the BIOS..
453 if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable)
456 /* Kick the control CPU into the TSC synchronization function */
457 smp_call_function_single(cpumask_first(cpu_online_mask), check_tsc_sync_source,
458 (unsigned long *)(unsigned long)cpu, 0);
461 * Register this CPU's participation and wait for the
462 * source CPU to start the measurement:
464 atomic_inc(&start_count);
465 while (atomic_read(&start_count) != cpus)
468 cur_max_warp = check_tsc_warp(loop_timeout(cpu));
471 * Store the maximum observed warp value for a potential retry:
473 gbl_max_warp = max_warp;
478 atomic_inc(&stop_count);
481 * Wait for the source CPU to print stuff:
483 while (atomic_read(&stop_count) != cpus)
487 * Reset it for the next sync test:
489 atomic_set(&stop_count, 0);
492 * Check the number of remaining test runs. If not zero, the test
493 * failed and a retry with adjusted TSC is possible. If zero the
494 * test was either successful or failed terminally.
496 if (!atomic_read(&test_runs))
500 * If the warp value of this CPU is 0, then the other CPU
501 * observed time going backwards so this TSC was ahead and
502 * needs to move backwards.
505 cur_max_warp = -gbl_max_warp;
508 * Add the result to the previous adjustment value.
510 * The adjustment value is slightly off by the overhead of the
511 * sync mechanism (observed values are ~200 TSC cycles), but this
512 * really depends on CPU, node distance and frequency. So
513 * compensating for this is hard to get right. Experiments show
514 * that the warp is not longer detectable when the observed warp
515 * value is used. In the worst case the adjustment needs to go
516 * through a 3rd run for fine tuning.
518 cur->adjusted += cur_max_warp;
520 pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
521 cpu, cur_max_warp, cur->adjusted);
523 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);
528 #endif /* CONFIG_SMP */