2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * Handle hardware traps and faults.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/context_tracking.h>
16 #include <linux/interrupt.h>
17 #include <linux/kallsyms.h>
18 #include <linux/kmsan.h>
19 #include <linux/spinlock.h>
20 #include <linux/kprobes.h>
21 #include <linux/uaccess.h>
22 #include <linux/kdebug.h>
23 #include <linux/kgdb.h>
24 #include <linux/kernel.h>
25 #include <linux/export.h>
26 #include <linux/ptrace.h>
27 #include <linux/uprobes.h>
28 #include <linux/string.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/kexec.h>
32 #include <linux/sched.h>
33 #include <linux/sched/task_stack.h>
34 #include <linux/timer.h>
35 #include <linux/init.h>
36 #include <linux/bug.h>
37 #include <linux/nmi.h>
39 #include <linux/smp.h>
40 #include <linux/cpu.h>
42 #include <linux/hardirq.h>
43 #include <linux/atomic.h>
44 #include <linux/iommu.h>
46 #include <asm/stacktrace.h>
47 #include <asm/processor.h>
48 #include <asm/debugreg.h>
49 #include <asm/realmode.h>
50 #include <asm/text-patching.h>
51 #include <asm/ftrace.h>
52 #include <asm/traps.h>
54 #include <asm/fpu/api.h>
56 #include <asm/cpu_entry_area.h>
58 #include <asm/fixmap.h>
59 #include <asm/mach_traps.h>
60 #include <asm/alternative.h>
61 #include <asm/fpu/xstate.h>
65 #include <asm/insn-eval.h>
71 #include <asm/x86_init.h>
73 #include <asm/processor-flags.h>
74 #include <asm/setup.h>
77 #include <asm/proto.h>
79 DECLARE_BITMAP(system_vectors, NR_VECTORS);
81 __always_inline int is_valid_bugaddr(unsigned long addr)
83 if (addr < TASK_SIZE_MAX)
87 * We got #UD, if the text isn't readable we'd have gotten
88 * a different exception.
90 return *(unsigned short *)addr == INSN_UD2;
93 static nokprobe_inline int
94 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
95 struct pt_regs *regs, long error_code)
97 if (v8086_mode(regs)) {
99 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
100 * On nmi (interrupt 2), do_trap should not be called.
102 if (trapnr < X86_TRAP_UD) {
103 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
107 } else if (!user_mode(regs)) {
108 if (fixup_exception(regs, trapnr, error_code, 0))
111 tsk->thread.error_code = error_code;
112 tsk->thread.trap_nr = trapnr;
113 die(str, regs, error_code);
115 if (fixup_vdso_exception(regs, trapnr, error_code, 0))
120 * We want error_code and trap_nr set for userspace faults and
121 * kernelspace faults which result in die(), but not
122 * kernelspace faults which are fixed up. die() gives the
123 * process no chance to handle the signal and notice the
124 * kernel fault information, so that won't result in polluting
125 * the information about previously queued, but not yet
126 * delivered, faults. See also exc_general_protection below.
128 tsk->thread.error_code = error_code;
129 tsk->thread.trap_nr = trapnr;
134 static void show_signal(struct task_struct *tsk, int signr,
135 const char *type, const char *desc,
136 struct pt_regs *regs, long error_code)
138 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
139 printk_ratelimit()) {
140 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
141 tsk->comm, task_pid_nr(tsk), type, desc,
142 regs->ip, regs->sp, error_code);
143 print_vma_addr(KERN_CONT " in ", regs->ip);
149 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
150 long error_code, int sicode, void __user *addr)
152 struct task_struct *tsk = current;
154 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
157 show_signal(tsk, signr, "trap ", str, regs, error_code);
162 force_sig_fault(signr, sicode, addr);
164 NOKPROBE_SYMBOL(do_trap);
166 static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
167 unsigned long trapnr, int signr, int sicode, void __user *addr)
169 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
171 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
173 cond_local_irq_enable(regs);
174 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
175 cond_local_irq_disable(regs);
180 * Posix requires to provide the address of the faulting instruction for
181 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
183 * This address is usually regs->ip, but when an uprobe moved the code out
184 * of line then regs->ip points to the XOL code which would confuse
185 * anything which analyzes the fault address vs. the unmodified binary. If
186 * a trap happened in XOL code then uprobe maps regs->ip back to the
187 * original instruction address.
189 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
191 return (void __user *)uprobe_get_trap_addr(regs);
194 DEFINE_IDTENTRY(exc_divide_error)
196 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE,
197 FPE_INTDIV, error_get_trap_addr(regs));
200 DEFINE_IDTENTRY(exc_overflow)
202 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
205 #ifdef CONFIG_X86_F00F_BUG
206 void handle_invalid_op(struct pt_regs *regs)
208 static inline void handle_invalid_op(struct pt_regs *regs)
211 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
212 ILL_ILLOPN, error_get_trap_addr(regs));
215 static noinstr bool handle_bug(struct pt_regs *regs)
217 bool handled = false;
220 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug()
221 * is a rare case that uses @regs without passing them to
224 kmsan_unpoison_entry_regs(regs);
225 if (!is_valid_bugaddr(regs->ip))
229 * All lies, just get the WARN/BUG out.
231 instrumentation_begin();
233 * Since we're emulating a CALL with exceptions, restore the interrupt
234 * state to what it was at the exception site.
236 if (regs->flags & X86_EFLAGS_IF)
237 raw_local_irq_enable();
238 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN ||
239 handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) {
243 if (regs->flags & X86_EFLAGS_IF)
244 raw_local_irq_disable();
245 instrumentation_end();
250 DEFINE_IDTENTRY_RAW(exc_invalid_op)
252 irqentry_state_t state;
255 * We use UD2 as a short encoding for 'CALL __WARN', as such
256 * handle it before exception entry to avoid recursive WARN
257 * in case exception entry is the one triggering WARNs.
259 if (!user_mode(regs) && handle_bug(regs))
262 state = irqentry_enter(regs);
263 instrumentation_begin();
264 handle_invalid_op(regs);
265 instrumentation_end();
266 irqentry_exit(regs, state);
269 DEFINE_IDTENTRY(exc_coproc_segment_overrun)
271 do_error_trap(regs, 0, "coprocessor segment overrun",
272 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
275 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
277 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
281 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
283 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
287 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
289 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
293 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
295 char *str = "alignment check";
297 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
300 if (!user_mode(regs))
301 die("Split lock detected\n", regs, error_code);
305 if (handle_user_split_lock(regs, error_code))
308 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
309 error_code, BUS_ADRALN, NULL);
315 #ifdef CONFIG_VMAP_STACK
316 __visible void __noreturn handle_stack_overflow(struct pt_regs *regs,
317 unsigned long fault_address,
318 struct stack_info *info)
320 const char *name = stack_type_name(info->type);
322 printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n",
323 name, (void *)fault_address, info->begin, info->end);
325 die("stack guard page", regs, 0);
327 /* Be absolutely certain we don't return. */
328 panic("%s stack guard hit", name);
333 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
335 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
336 * SDM's warnings about double faults being unrecoverable, returning works as
337 * expected. Presumably what the SDM actually means is that the CPU may get
338 * the register state wrong on entry, so returning could be a bad idea.
340 * Various CPU engineers have promised that double faults due to an IRET fault
341 * while the stack is read-only are, in fact, recoverable.
343 * On x86_32, this is entered through a task gate, and regs are synthesized
344 * from the TSS. Returning is, in principle, okay, but changes to regs will
345 * be lost. If, for some reason, we need to return to a context with modified
346 * regs, the shim code could be adjusted to synchronize the registers.
348 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
349 * to be read before doing anything else.
351 DEFINE_IDTENTRY_DF(exc_double_fault)
353 static const char str[] = "double fault";
354 struct task_struct *tsk = current;
356 #ifdef CONFIG_VMAP_STACK
357 unsigned long address = read_cr2();
358 struct stack_info info;
361 #ifdef CONFIG_X86_ESPFIX64
362 extern unsigned char native_irq_return_iret[];
365 * If IRET takes a non-IST fault on the espfix64 stack, then we
366 * end up promoting it to a doublefault. In that case, take
367 * advantage of the fact that we're not using the normal (TSS.sp0)
368 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
369 * and then modify our own IRET frame so that, when we return,
370 * we land directly at the #GP(0) vector with the stack already
371 * set up according to its expectations.
373 * The net result is that our #GP handler will think that we
374 * entered from usermode with the bad user context.
376 * No need for nmi_enter() here because we don't use RCU.
378 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
379 regs->cs == __KERNEL_CS &&
380 regs->ip == (unsigned long)native_irq_return_iret)
382 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
383 unsigned long *p = (unsigned long *)regs->sp;
386 * regs->sp points to the failing IRET frame on the
387 * ESPFIX64 stack. Copy it to the entry stack. This fills
388 * in gpregs->ss through gpregs->ip.
393 gpregs->flags = p[2];
396 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
399 * Adjust our frame so that we return straight to the #GP
400 * vector with the expected RSP value. This is safe because
401 * we won't enable interrupts or schedule before we invoke
402 * general_protection, so nothing will clobber the stack
403 * frame we just set up.
405 * We will enter general_protection with kernel GSBASE,
406 * which is what the stub expects, given that the faulting
407 * RIP will be the IRET instruction.
409 regs->ip = (unsigned long)asm_exc_general_protection;
410 regs->sp = (unsigned long)&gpregs->orig_ax;
416 irqentry_nmi_enter(regs);
417 instrumentation_begin();
418 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
420 tsk->thread.error_code = error_code;
421 tsk->thread.trap_nr = X86_TRAP_DF;
423 #ifdef CONFIG_VMAP_STACK
425 * If we overflow the stack into a guard page, the CPU will fail
426 * to deliver #PF and will send #DF instead. Similarly, if we
427 * take any non-IST exception while too close to the bottom of
428 * the stack, the processor will get a page fault while
429 * delivering the exception and will generate a double fault.
431 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
432 * Page-Fault Exception (#PF):
434 * Processors update CR2 whenever a page fault is detected. If a
435 * second page fault occurs while an earlier page fault is being
436 * delivered, the faulting linear address of the second fault will
437 * overwrite the contents of CR2 (replacing the previous
438 * address). These updates to CR2 occur even if the page fault
439 * results in a double fault or occurs during the delivery of a
442 * The logic below has a small possibility of incorrectly diagnosing
443 * some errors as stack overflows. For example, if the IDT or GDT
444 * gets corrupted such that #GP delivery fails due to a bad descriptor
445 * causing #GP and we hit this condition while CR2 coincidentally
446 * points to the stack guard page, we'll think we overflowed the
447 * stack. Given that we're going to panic one way or another
448 * if this happens, this isn't necessarily worth fixing.
450 * If necessary, we could improve the test by only diagnosing
451 * a stack overflow if the saved RSP points within 47 bytes of
452 * the bottom of the stack: if RSP == tsk_stack + 48 and we
453 * take an exception, the stack is already aligned and there
454 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
455 * possible error code, so a stack overflow would *not* double
456 * fault. With any less space left, exception delivery could
457 * fail, and, as a practical matter, we've overflowed the
458 * stack even if the actual trigger for the double fault was
461 if (get_stack_guard_info((void *)address, &info))
462 handle_stack_overflow(regs, address, &info);
465 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
466 die("double fault", regs, error_code);
467 panic("Machine halted.");
468 instrumentation_end();
471 DEFINE_IDTENTRY(exc_bounds)
473 if (notify_die(DIE_TRAP, "bounds", regs, 0,
474 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
476 cond_local_irq_enable(regs);
478 if (!user_mode(regs))
479 die("bounds", regs, 0);
481 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
483 cond_local_irq_disable(regs);
486 enum kernel_gp_hint {
493 * When an uncaught #GP occurs, try to determine the memory address accessed by
494 * the instruction and return that address to the caller. Also, try to figure
495 * out whether any part of the access to that address was non-canonical.
497 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
500 u8 insn_buf[MAX_INSN_SIZE];
504 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
508 ret = insn_decode_kernel(&insn, insn_buf);
512 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
519 * - the operand is not in the kernel half
520 * - the last byte of the operand is not in the user canonical half
522 if (*addr < ~__VIRTUAL_MASK &&
523 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
524 return GP_NON_CANONICAL;
530 #define GPFSTR "general protection fault"
532 static bool fixup_iopl_exception(struct pt_regs *regs)
534 struct thread_struct *t = ¤t->thread;
538 if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3)
541 if (insn_get_effective_ip(regs, &ip))
544 if (get_user(byte, (const char __user *)ip))
547 if (byte != 0xfa && byte != 0xfb)
550 if (!t->iopl_warn && printk_ratelimit()) {
551 pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx",
552 current->comm, task_pid_nr(current), ip);
553 print_vma_addr(KERN_CONT " in ", ip);
563 * The unprivileged ENQCMD instruction generates #GPs if the
564 * IA32_PASID MSR has not been populated. If possible, populate
565 * the MSR from a PASID previously allocated to the mm.
567 static bool try_fixup_enqcmd_gp(void)
569 #ifdef CONFIG_ARCH_HAS_CPU_PASID
573 * MSR_IA32_PASID is managed using XSAVE. Directly
574 * writing to the MSR is only possible when fpregs
575 * are valid and the fpstate is not. This is
576 * guaranteed when handling a userspace exception
577 * in *before* interrupts are re-enabled.
579 lockdep_assert_irqs_disabled();
582 * Hardware without ENQCMD will not generate
583 * #GPs that can be fixed up here.
585 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
589 * If the mm has not been allocated a
590 * PASID, the #GP can not be fixed up.
592 if (!mm_valid_pasid(current->mm))
595 pasid = mm_get_enqcmd_pasid(current->mm);
598 * Did this thread already have its PASID activated?
599 * If so, the #GP must be from something else.
601 if (current->pasid_activated)
604 wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID);
605 current->pasid_activated = 1;
613 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr,
614 unsigned long error_code, const char *str,
615 unsigned long address)
617 if (fixup_exception(regs, trapnr, error_code, address))
620 current->thread.error_code = error_code;
621 current->thread.trap_nr = trapnr;
624 * To be potentially processing a kprobe fault and to trust the result
625 * from kprobe_running(), we have to be non-preemptible.
627 if (!preemptible() && kprobe_running() &&
628 kprobe_fault_handler(regs, trapnr))
631 return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP;
634 static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr,
635 unsigned long error_code, const char *str)
637 current->thread.error_code = error_code;
638 current->thread.trap_nr = trapnr;
639 show_signal(current, SIGSEGV, "", str, regs, error_code);
643 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
645 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
646 enum kernel_gp_hint hint = GP_NO_HINT;
647 unsigned long gp_addr;
649 if (user_mode(regs) && try_fixup_enqcmd_gp())
652 cond_local_irq_enable(regs);
654 if (static_cpu_has(X86_FEATURE_UMIP)) {
655 if (user_mode(regs) && fixup_umip_exception(regs))
659 if (v8086_mode(regs)) {
661 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
666 if (user_mode(regs)) {
667 if (fixup_iopl_exception(regs))
670 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0))
673 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc);
677 if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc, 0))
681 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
683 hint = get_kernel_gp_address(regs, &gp_addr);
685 if (hint != GP_NO_HINT)
686 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
687 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
688 : "maybe for address",
692 * KASAN is interested only in the non-canonical case, clear it
695 if (hint != GP_NON_CANONICAL)
698 die_addr(desc, regs, error_code, gp_addr);
701 cond_local_irq_disable(regs);
704 static bool do_int3(struct pt_regs *regs)
708 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
709 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
710 SIGTRAP) == NOTIFY_STOP)
712 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
714 #ifdef CONFIG_KPROBES
715 if (kprobe_int3_handler(regs))
718 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
720 return res == NOTIFY_STOP;
722 NOKPROBE_SYMBOL(do_int3);
724 static void do_int3_user(struct pt_regs *regs)
729 cond_local_irq_enable(regs);
730 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
731 cond_local_irq_disable(regs);
734 DEFINE_IDTENTRY_RAW(exc_int3)
737 * poke_int3_handler() is completely self contained code; it does (and
738 * must) *NOT* call out to anything, lest it hits upon yet another
741 if (poke_int3_handler(regs))
745 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
746 * and therefore can trigger INT3, hence poke_int3_handler() must
747 * be done before. If the entry came from kernel mode, then use
748 * nmi_enter() because the INT3 could have been hit in any context
751 if (user_mode(regs)) {
752 irqentry_enter_from_user_mode(regs);
753 instrumentation_begin();
755 instrumentation_end();
756 irqentry_exit_to_user_mode(regs);
758 irqentry_state_t irq_state = irqentry_nmi_enter(regs);
760 instrumentation_begin();
762 die("int3", regs, 0);
763 instrumentation_end();
764 irqentry_nmi_exit(regs, irq_state);
770 * Help handler running on a per-cpu (IST or entry trampoline) stack
771 * to switch to the normal thread stack if the interrupted code was in
772 * user mode. The actual stack switch is done in entry_64.S
774 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
776 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(pcpu_hot.top_of_stack) - 1;
782 #ifdef CONFIG_AMD_MEM_ENCRYPT
783 asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs)
785 unsigned long sp, *stack;
786 struct stack_info info;
787 struct pt_regs *regs_ret;
790 * In the SYSCALL entry path the RSP value comes from user-space - don't
791 * trust it and switch to the current kernel stack
793 if (ip_within_syscall_gap(regs)) {
794 sp = this_cpu_read(pcpu_hot.top_of_stack);
799 * From here on the RSP value is trusted. Now check whether entry
800 * happened from a safe stack. Not safe are the entry or unknown stacks,
801 * use the fall-back stack instead in this case.
804 stack = (unsigned long *)sp;
806 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY ||
807 info.type > STACK_TYPE_EXCEPTION_LAST)
808 sp = __this_cpu_ist_top_va(VC2);
812 * Found a safe stack - switch to it as if the entry didn't happen via
813 * IST stack. The code below only copies pt_regs, the real switch happens
816 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret);
818 regs_ret = (struct pt_regs *)sp;
825 asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs)
827 struct pt_regs tmp, *new_stack;
830 * This is called from entry_64.S early in handling a fault
831 * caused by a bad iret to user mode. To handle the fault
832 * correctly, we want to move our stack frame to where it would
833 * be had we entered directly on the entry stack (rather than
834 * just below the IRET frame) and we want to pretend that the
835 * exception came from the IRET target.
837 new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
839 /* Copy the IRET target to the temporary storage. */
840 __memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8);
842 /* Copy the remainder of the stack from the current stack. */
843 __memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip));
845 /* Update the entry stack */
846 __memcpy(new_stack, &tmp, sizeof(tmp));
848 BUG_ON(!user_mode(new_stack));
853 static bool is_sysenter_singlestep(struct pt_regs *regs)
856 * We don't try for precision here. If we're anywhere in the region of
857 * code that can be single-stepped in the SYSENTER entry path, then
858 * assume that this is a useless single-step trap due to SYSENTER
859 * being invoked with TF set. (We don't know in advance exactly
860 * which instructions will be hit because BTF could plausibly
864 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
865 (unsigned long)__end_SYSENTER_singlestep_region -
866 (unsigned long)__begin_SYSENTER_singlestep_region;
867 #elif defined(CONFIG_IA32_EMULATION)
868 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
869 (unsigned long)__end_entry_SYSENTER_compat -
870 (unsigned long)entry_SYSENTER_compat;
876 static __always_inline unsigned long debug_read_clear_dr6(void)
881 * The Intel SDM says:
883 * Certain debug exceptions may clear bits 0-3. The remaining
884 * contents of the DR6 register are never cleared by the
885 * processor. To avoid confusion in identifying debug
886 * exceptions, debug handlers should clear the register before
887 * returning to the interrupted task.
889 * Keep it simple: clear DR6 immediately.
891 get_debugreg(dr6, 6);
892 set_debugreg(DR6_RESERVED, 6);
893 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */
899 * Our handling of the processor debug registers is non-trivial.
900 * We do not clear them on entry and exit from the kernel. Therefore
901 * it is possible to get a watchpoint trap here from inside the kernel.
902 * However, the code in ./ptrace.c has ensured that the user can
903 * only set watchpoints on userspace addresses. Therefore the in-kernel
904 * watchpoint trap can only occur in code which is reading/writing
905 * from user space. Such code must not hold kernel locks (since it
906 * can equally take a page fault), therefore it is safe to call
907 * force_sig_info even though that claims and releases locks.
909 * Code in ./signal.c ensures that the debug control register
910 * is restored before we deliver any signal, and therefore that
911 * user code runs with the correct debug control register even though
914 * Being careful here means that we don't have to be as careful in a
915 * lot of more complicated places (task switching can be a bit lazy
916 * about restoring all the debug state, and ptrace doesn't have to
917 * find every occurrence of the TF bit that could be saved away even
920 * May run on IST stack.
923 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6)
926 * Notifiers will clear bits in @dr6 to indicate the event has been
927 * consumed - hw_breakpoint_handler(), single_stop_cont().
929 * Notifiers will set bits in @virtual_dr6 to indicate the desire
930 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler().
932 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP)
938 static __always_inline void exc_debug_kernel(struct pt_regs *regs,
942 * Disable breakpoints during exception handling; recursive exceptions
943 * are exceedingly 'fun'.
945 * Since this function is NOKPROBE, and that also applies to
946 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
947 * HW_BREAKPOINT_W on our stack)
949 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
950 * includes the entry stack is excluded for everything.
952 unsigned long dr7 = local_db_save();
953 irqentry_state_t irq_state = irqentry_nmi_enter(regs);
954 instrumentation_begin();
957 * If something gets miswired and we end up here for a user mode
958 * #DB, we will malfunction.
960 WARN_ON_ONCE(user_mode(regs));
962 if (test_thread_flag(TIF_BLOCKSTEP)) {
964 * The SDM says "The processor clears the BTF flag when it
965 * generates a debug exception." but PTRACE_BLOCKSTEP requested
966 * it for userspace, but we just took a kernel #DB, so re-set
969 unsigned long debugctl;
971 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
972 debugctl |= DEBUGCTLMSR_BTF;
973 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
977 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
978 * watchpoint at the same time then that will still be handled.
980 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs))
984 * The kernel doesn't use INT1
989 if (notify_debug(regs, &dr6))
993 * The kernel doesn't use TF single-step outside of:
995 * - Kprobes, consumed through kprobe_debug_handler()
996 * - KGDB, consumed through notify_debug()
998 * So if we get here with DR_STEP set, something is wonky.
1000 * A known way to trigger this is through QEMU's GDB stub,
1001 * which leaks #DB into the guest and causes IST recursion.
1003 if (WARN_ON_ONCE(dr6 & DR_STEP))
1004 regs->flags &= ~X86_EFLAGS_TF;
1006 instrumentation_end();
1007 irqentry_nmi_exit(regs, irq_state);
1009 local_db_restore(dr7);
1012 static __always_inline void exc_debug_user(struct pt_regs *regs,
1018 * If something gets miswired and we end up here for a kernel mode
1019 * #DB, we will malfunction.
1021 WARN_ON_ONCE(!user_mode(regs));
1024 * NB: We can't easily clear DR7 here because
1025 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access
1026 * user memory, etc. This means that a recursive #DB is possible. If
1027 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
1028 * Since we're not on the IST stack right now, everything will be
1032 irqentry_enter_from_user_mode(regs);
1033 instrumentation_begin();
1036 * Start the virtual/ptrace DR6 value with just the DR_STEP mask
1037 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits.
1039 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6)
1040 * even if it is not the result of PTRACE_SINGLESTEP.
1042 current->thread.virtual_dr6 = (dr6 & DR_STEP);
1045 * The SDM says "The processor clears the BTF flag when it
1046 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
1047 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
1049 clear_thread_flag(TIF_BLOCKSTEP);
1052 * If dr6 has no reason to give us about the origin of this trap,
1053 * then it's very likely the result of an icebp/int01 trap.
1054 * User wants a sigtrap for that.
1058 if (notify_debug(regs, &dr6))
1061 /* It's safe to allow irq's after DR6 has been saved */
1064 if (v8086_mode(regs)) {
1065 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB);
1069 /* #DB for bus lock can only be triggered from userspace. */
1070 if (dr6 & DR_BUS_LOCK)
1071 handle_bus_lock(regs);
1073 /* Add the virtual_dr6 bits for signals. */
1074 dr6 |= current->thread.virtual_dr6;
1075 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp)
1076 send_sigtrap(regs, 0, get_si_code(dr6));
1079 local_irq_disable();
1081 instrumentation_end();
1082 irqentry_exit_to_user_mode(regs);
1085 #ifdef CONFIG_X86_64
1086 /* IST stack entry */
1087 DEFINE_IDTENTRY_DEBUG(exc_debug)
1089 exc_debug_kernel(regs, debug_read_clear_dr6());
1092 /* User entry, runs on regular task stack */
1093 DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
1095 exc_debug_user(regs, debug_read_clear_dr6());
1098 /* 32 bit does not have separate entry points. */
1099 DEFINE_IDTENTRY_RAW(exc_debug)
1101 unsigned long dr6 = debug_read_clear_dr6();
1103 if (user_mode(regs))
1104 exc_debug_user(regs, dr6);
1106 exc_debug_kernel(regs, dr6);
1111 * Note that we play around with the 'TS' bit in an attempt to get
1112 * the correct behaviour even in the presence of the asynchronous
1115 static void math_error(struct pt_regs *regs, int trapnr)
1117 struct task_struct *task = current;
1118 struct fpu *fpu = &task->thread.fpu;
1120 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
1123 cond_local_irq_enable(regs);
1125 if (!user_mode(regs)) {
1126 if (fixup_exception(regs, trapnr, 0, 0))
1129 task->thread.error_code = 0;
1130 task->thread.trap_nr = trapnr;
1132 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
1133 SIGFPE) != NOTIFY_STOP)
1139 * Synchronize the FPU register state to the memory register state
1140 * if necessary. This allows the exception handler to inspect it.
1142 fpu_sync_fpstate(fpu);
1144 task->thread.trap_nr = trapnr;
1145 task->thread.error_code = 0;
1147 si_code = fpu__exception_code(fpu, trapnr);
1148 /* Retry when we get spurious exceptions: */
1152 if (fixup_vdso_exception(regs, trapnr, 0, 0))
1155 force_sig_fault(SIGFPE, si_code,
1156 (void __user *)uprobe_get_trap_addr(regs));
1158 cond_local_irq_disable(regs);
1161 DEFINE_IDTENTRY(exc_coprocessor_error)
1163 math_error(regs, X86_TRAP_MF);
1166 DEFINE_IDTENTRY(exc_simd_coprocessor_error)
1168 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
1169 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
1170 if (!static_cpu_has(X86_FEATURE_XMM)) {
1171 __exc_general_protection(regs, 0);
1175 math_error(regs, X86_TRAP_XF);
1178 DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1181 * This addresses a Pentium Pro Erratum:
1183 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1184 * Virtual Wire mode implemented through the local APIC, an
1185 * interrupt vector of 0Fh (Intel reserved encoding) may be
1186 * generated by the local APIC (Int 15). This vector may be
1187 * generated upon receipt of a spurious interrupt (an interrupt
1188 * which is removed before the system receives the INTA sequence)
1189 * instead of the programmed 8259 spurious interrupt vector.
1191 * IMPLICATION: The spurious interrupt vector programmed in the
1192 * 8259 is normally handled by an operating system's spurious
1193 * interrupt handler. However, a vector of 0Fh is unknown to some
1194 * operating systems, which would crash if this erratum occurred.
1196 * In theory this could be limited to 32bit, but the handler is not
1197 * hurting and who knows which other CPUs suffer from this.
1201 static bool handle_xfd_event(struct pt_regs *regs)
1206 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD))
1209 rdmsrl(MSR_IA32_XFD_ERR, xfd_err);
1213 wrmsrl(MSR_IA32_XFD_ERR, 0);
1215 /* Die if that happens in kernel space */
1216 if (WARN_ON(!user_mode(regs)))
1221 err = xfd_enable_feature(xfd_err);
1225 force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs));
1232 local_irq_disable();
1236 DEFINE_IDTENTRY(exc_device_not_available)
1238 unsigned long cr0 = read_cr0();
1240 if (handle_xfd_event(regs))
1243 #ifdef CONFIG_MATH_EMULATION
1244 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1245 struct math_emu_info info = { };
1247 cond_local_irq_enable(regs);
1250 math_emulate(&info);
1252 cond_local_irq_disable(regs);
1257 /* This should not happen. */
1258 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1259 /* Try to fix it up and carry on. */
1260 write_cr0(cr0 & ~X86_CR0_TS);
1263 * Something terrible happened, and we're better off trying
1264 * to kill the task than getting stuck in a never-ending
1265 * loop of #NM faults.
1267 die("unexpected #NM exception", regs, 0);
1271 #ifdef CONFIG_INTEL_TDX_GUEST
1273 #define VE_FAULT_STR "VE fault"
1275 static void ve_raise_fault(struct pt_regs *regs, long error_code,
1276 unsigned long address)
1278 if (user_mode(regs)) {
1279 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR);
1283 if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code,
1284 VE_FAULT_STR, address)) {
1288 die_addr(VE_FAULT_STR, regs, error_code, address);
1292 * Virtualization Exceptions (#VE) are delivered to TDX guests due to
1293 * specific guest actions which may happen in either user space or the
1296 * * Specific instructions (WBINVD, for example)
1297 * * Specific MSR accesses
1298 * * Specific CPUID leaf accesses
1299 * * Access to specific guest physical addresses
1301 * In the settings that Linux will run in, virtualization exceptions are
1302 * never generated on accesses to normal, TD-private memory that has been
1303 * accepted (by BIOS or with tdx_enc_status_changed()).
1305 * Syscall entry code has a critical window where the kernel stack is not
1306 * yet set up. Any exception in this window leads to hard to debug issues
1307 * and can be exploited for privilege escalation. Exceptions in the NMI
1308 * entry code also cause issues. Returning from the exception handler with
1309 * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack.
1311 * For these reasons, the kernel avoids #VEs during the syscall gap and
1312 * the NMI entry code. Entry code paths do not access TD-shared memory,
1313 * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves
1314 * that might generate #VE. VMM can remove memory from TD at any point,
1315 * but access to unaccepted (or missing) private memory leads to VM
1316 * termination, not to #VE.
1318 * Similarly to page faults and breakpoints, #VEs are allowed in NMI
1319 * handlers once the kernel is ready to deal with nested NMIs.
1321 * During #VE delivery, all interrupts, including NMIs, are blocked until
1322 * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads
1325 * If a guest kernel action which would normally cause a #VE occurs in
1326 * the interrupt-disabled region before TDGETVEINFO, a #DF (fault
1327 * exception) is delivered to the guest which will result in an oops.
1329 * The entry code has been audited carefully for following these expectations.
1330 * Changes in the entry code have to be audited for correctness vs. this
1331 * aspect. Similarly to #PF, #VE in these places will expose kernel to
1332 * privilege escalation or may lead to random crashes.
1334 DEFINE_IDTENTRY(exc_virtualization_exception)
1339 * NMIs/Machine-checks/Interrupts will be in a disabled state
1340 * till TDGETVEINFO TDCALL is executed. This ensures that VE
1341 * info cannot be overwritten by a nested #VE.
1343 tdx_get_ve_info(&ve);
1345 cond_local_irq_enable(regs);
1348 * If tdx_handle_virt_exception() could not process
1349 * it successfully, treat it as #GP(0) and handle it.
1351 if (!tdx_handle_virt_exception(regs, &ve))
1352 ve_raise_fault(regs, 0, ve.gla);
1354 cond_local_irq_disable(regs);
1359 #ifdef CONFIG_X86_32
1360 DEFINE_IDTENTRY_SW(iret_error)
1363 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1364 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1365 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1366 ILL_BADSTK, (void __user *)NULL);
1368 local_irq_disable();
1372 void __init trap_init(void)
1374 /* Init cpu_entry_area before IST entries are set up */
1375 setup_cpu_entry_areas();
1377 /* Init GHCB memory pages when running as an SEV-ES guest */
1378 sev_es_init_vc_handling();
1380 /* Initialize TSS before setting up traps so ISTs work */
1381 cpu_init_exception_handling();
1382 /* Setup traps as cpu_init() might #GP */