1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/stackprotector.h>
55 #include <linux/gfp.h>
56 #include <linux/cpuidle.h>
57 #include <linux/numa.h>
63 #include <asm/realmode.h>
66 #include <asm/pgtable.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
84 /* representing HT siblings of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
88 /* representing HT and core siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
92 /* representing HT, core, and die siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
94 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
100 EXPORT_PER_CPU_SYMBOL(cpu_info);
102 struct mwait_cpu_dead {
103 unsigned int control;
108 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
109 * that it's unlikely to be touched by other CPUs.
111 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
113 /* Logical package management. We might want to allocate that dynamically */
114 unsigned int __max_logical_packages __read_mostly;
115 EXPORT_SYMBOL(__max_logical_packages);
116 static unsigned int logical_packages __read_mostly;
117 static unsigned int logical_die __read_mostly;
119 /* Maximum number of SMT threads on any online core */
120 int __read_mostly __max_smt_threads = 1;
122 /* Flag to indicate if a complete sched domain rebuild is required */
123 bool x86_topology_update;
125 int arch_update_cpu_topology(void)
127 int retval = x86_topology_update;
129 x86_topology_update = false;
133 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
137 spin_lock_irqsave(&rtc_lock, flags);
138 CMOS_WRITE(0xa, 0xf);
139 spin_unlock_irqrestore(&rtc_lock, flags);
140 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
142 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
146 static inline void smpboot_restore_warm_reset_vector(void)
151 * Paranoid: Set warm reset code and vector here back
154 spin_lock_irqsave(&rtc_lock, flags);
156 spin_unlock_irqrestore(&rtc_lock, flags);
158 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
162 * Report back to the Boot Processor during boot time or to the caller processor
165 static void smp_callin(void)
170 * If waken up by an INIT in an 82489DX configuration
171 * cpu_callout_mask guarantees we don't get here before
172 * an INIT_deassert IPI reaches our local APIC, so it is
173 * now safe to touch our local APIC.
175 cpuid = smp_processor_id();
178 * the boot CPU has finished the init stage and is spinning
179 * on callin_map until we finish. We are free to set up this
180 * CPU, first the APIC. (this is probably redundant on most
186 * Save our processor parameters. Note: this information
187 * is needed for clock calibration.
189 smp_store_cpu_info(cpuid);
192 * The topology information must be up to date before
193 * calibrate_delay() and notify_cpu_starting().
195 set_cpu_sibling_map(raw_smp_processor_id());
199 * Update loops_per_jiffy in cpu_data. Previous call to
200 * smp_store_cpu_info() stored a value that is close but not as
201 * accurate as the value just calculated.
204 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
205 pr_debug("Stack at about %p\n", &cpuid);
209 notify_cpu_starting(cpuid);
212 * Allow the master to continue.
214 cpumask_set_cpu(cpuid, cpu_callin_mask);
217 static int cpu0_logical_apicid;
218 static int enable_start_cpu0;
220 * Activate a secondary processor.
222 static void notrace start_secondary(void *unused)
225 * Don't put *anything* except direct CPU state initialization
226 * before cpu_init(), SMP booting is too fragile that we want to
227 * limit the things done here to the most necessary things.
232 /* switch away from the initial page table */
233 load_cr3(swapper_pg_dir);
239 rcu_cpu_starting(raw_smp_processor_id());
240 x86_cpuinit.early_percpu_clock_init();
244 enable_start_cpu0 = 0;
246 /* otherwise gcc will move up smp_processor_id before the cpu_init */
249 * Check TSC synchronization with the boot CPU:
251 check_tsc_sync_target();
253 speculative_store_bypass_ht_init();
256 * Lock vector_lock, set CPU online and bring the vector
257 * allocator online. Online must be set with vector_lock held
258 * to prevent a concurrent irq setup/teardown from seeing a
259 * half valid vector space.
262 set_cpu_online(smp_processor_id(), true);
264 unlock_vector_lock();
265 cpu_set_state_online(smp_processor_id());
266 x86_platform.nmi_init();
268 /* enable local interrupts */
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
274 x86_cpuinit.setup_percpu_clockev();
277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
280 * Prevent tail call to cpu_startup_entry() because the stack protector
281 * guard has been changed a couple of function calls up, in
282 * boot_init_stack_canary() and must not be checked before tail calling
285 prevent_tail_call_optimization();
289 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
292 bool topology_is_primary_thread(unsigned int cpu)
294 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
298 * topology_smt_supported - Check whether SMT is supported by the CPUs
300 bool topology_smt_supported(void)
302 return smp_num_siblings > 1;
306 * topology_phys_to_logical_pkg - Map a physical package id to a logical
308 * Returns logical package id or -1 if not found
310 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
314 for_each_possible_cpu(cpu) {
315 struct cpuinfo_x86 *c = &cpu_data(cpu);
317 if (c->initialized && c->phys_proc_id == phys_pkg)
318 return c->logical_proc_id;
322 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
324 * topology_phys_to_logical_die - Map a physical die id to logical
326 * Returns logical die id or -1 if not found
328 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
331 int proc_id = cpu_data(cur_cpu).phys_proc_id;
333 for_each_possible_cpu(cpu) {
334 struct cpuinfo_x86 *c = &cpu_data(cpu);
336 if (c->initialized && c->cpu_die_id == die_id &&
337 c->phys_proc_id == proc_id)
338 return c->logical_die_id;
342 EXPORT_SYMBOL(topology_phys_to_logical_die);
345 * topology_update_package_map - Update the physical to logical package map
346 * @pkg: The physical package id as retrieved via CPUID
347 * @cpu: The cpu for which this is updated
349 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
353 /* Already available somewhere? */
354 new = topology_phys_to_logical_pkg(pkg);
358 new = logical_packages++;
360 pr_info("CPU %u Converting physical %u to logical package %u\n",
364 cpu_data(cpu).logical_proc_id = new;
368 * topology_update_die_map - Update the physical to logical die map
369 * @die: The die id as retrieved via CPUID
370 * @cpu: The cpu for which this is updated
372 int topology_update_die_map(unsigned int die, unsigned int cpu)
376 /* Already available somewhere? */
377 new = topology_phys_to_logical_die(die, cpu);
383 pr_info("CPU %u Converting physical %u to logical die %u\n",
387 cpu_data(cpu).logical_die_id = new;
391 void __init smp_store_boot_cpu_info(void)
393 int id = 0; /* CPU 0 */
394 struct cpuinfo_x86 *c = &cpu_data(id);
398 topology_update_package_map(c->phys_proc_id, id);
399 topology_update_die_map(c->cpu_die_id, id);
400 c->initialized = true;
404 * The bootstrap kernel entry code has set these up. Save them for
407 void smp_store_cpu_info(int id)
409 struct cpuinfo_x86 *c = &cpu_data(id);
411 /* Copy boot_cpu_data only on the first bringup */
416 * During boot time, CPU0 has this setup already. Save the info when
417 * bringing up AP or offlined CPU0.
419 identify_secondary_cpu(c);
420 c->initialized = true;
424 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
426 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
428 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
432 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
434 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
436 return !WARN_ONCE(!topology_same_node(c, o),
437 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
438 "[node: %d != %d]. Ignoring dependency.\n",
439 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
442 #define link_mask(mfunc, c1, c2) \
444 cpumask_set_cpu((c1), mfunc(c2)); \
445 cpumask_set_cpu((c2), mfunc(c1)); \
448 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
450 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
451 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
453 if (c->phys_proc_id == o->phys_proc_id &&
454 c->cpu_die_id == o->cpu_die_id &&
455 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
456 if (c->cpu_core_id == o->cpu_core_id)
457 return topology_sane(c, o, "smt");
459 if ((c->cu_id != 0xff) &&
460 (o->cu_id != 0xff) &&
461 (c->cu_id == o->cu_id))
462 return topology_sane(c, o, "smt");
465 } else if (c->phys_proc_id == o->phys_proc_id &&
466 c->cpu_die_id == o->cpu_die_id &&
467 c->cpu_core_id == o->cpu_core_id) {
468 return topology_sane(c, o, "smt");
475 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
477 * These are Intel CPUs that enumerate an LLC that is shared by
478 * multiple NUMA nodes. The LLC on these systems is shared for
479 * off-package data access but private to the NUMA node (half
480 * of the package) for on-package access.
482 * CPUID (the source of the information about the LLC) can only
483 * enumerate the cache as being shared *or* unshared, but not
484 * this particular configuration. The CPU in this case enumerates
485 * the cache to be shared across the entire package (spanning both
489 static const struct x86_cpu_id snc_cpu[] = {
490 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
494 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
496 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
498 /* Do not match if we do not have a valid APICID for cpu: */
499 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
502 /* Do not match if LLC id does not match: */
503 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
507 * Allow the SNC topology without warning. Return of false
508 * means 'c' does not share the LLC of 'o'. This will be
509 * reflected to userspace.
511 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
514 return topology_sane(c, o, "llc");
518 * Unlike the other levels, we do not enforce keeping a
519 * multicore group inside a NUMA node. If this happens, we will
520 * discard the MC level of the topology later.
522 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
524 if (c->phys_proc_id == o->phys_proc_id)
529 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
531 if ((c->phys_proc_id == o->phys_proc_id) &&
532 (c->cpu_die_id == o->cpu_die_id))
538 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
539 static inline int x86_sched_itmt_flags(void)
541 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
544 #ifdef CONFIG_SCHED_MC
545 static int x86_core_flags(void)
547 return cpu_core_flags() | x86_sched_itmt_flags();
550 #ifdef CONFIG_SCHED_SMT
551 static int x86_smt_flags(void)
553 return cpu_smt_flags() | x86_sched_itmt_flags();
558 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
559 #ifdef CONFIG_SCHED_SMT
560 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
562 #ifdef CONFIG_SCHED_MC
563 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
568 static struct sched_domain_topology_level x86_topology[] = {
569 #ifdef CONFIG_SCHED_SMT
570 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
572 #ifdef CONFIG_SCHED_MC
573 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
575 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
580 * Set if a package/die has multiple NUMA nodes inside.
581 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
582 * Sub-NUMA Clustering have this.
584 static bool x86_has_numa_in_package;
586 void set_cpu_sibling_map(int cpu)
588 bool has_smt = smp_num_siblings > 1;
589 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
590 struct cpuinfo_x86 *c = &cpu_data(cpu);
591 struct cpuinfo_x86 *o;
594 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
597 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
598 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
599 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
600 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
605 for_each_cpu(i, cpu_sibling_setup_mask) {
608 if ((i == cpu) || (has_smt && match_smt(c, o)))
609 link_mask(topology_sibling_cpumask, cpu, i);
611 if ((i == cpu) || (has_mp && match_llc(c, o)))
612 link_mask(cpu_llc_shared_mask, cpu, i);
617 * This needs a separate iteration over the cpus because we rely on all
618 * topology_sibling_cpumask links to be set-up.
620 for_each_cpu(i, cpu_sibling_setup_mask) {
623 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
624 link_mask(topology_core_cpumask, cpu, i);
627 * Does this new cpu bringup a new core?
630 topology_sibling_cpumask(cpu)) == 1) {
632 * for each core in package, increment
633 * the booted_cores for this new cpu
636 topology_sibling_cpumask(i)) == i)
639 * increment the core count for all
640 * the other cpus in this package
643 cpu_data(i).booted_cores++;
644 } else if (i != cpu && !c->booted_cores)
645 c->booted_cores = cpu_data(i).booted_cores;
647 if (match_pkg(c, o) && !topology_same_node(c, o))
648 x86_has_numa_in_package = true;
650 if ((i == cpu) || (has_mp && match_die(c, o)))
651 link_mask(topology_die_cpumask, cpu, i);
654 threads = cpumask_weight(topology_sibling_cpumask(cpu));
655 if (threads > __max_smt_threads)
656 __max_smt_threads = threads;
659 /* maps the cpu to the sched domain representing multi-core */
660 const struct cpumask *cpu_coregroup_mask(int cpu)
662 return cpu_llc_shared_mask(cpu);
665 static void impress_friends(void)
668 unsigned long bogosum = 0;
670 * Allow the user to impress friends.
672 pr_debug("Before bogomips\n");
673 for_each_possible_cpu(cpu)
674 if (cpumask_test_cpu(cpu, cpu_callout_mask))
675 bogosum += cpu_data(cpu).loops_per_jiffy;
676 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
679 (bogosum/(5000/HZ))%100);
681 pr_debug("Before bogocount - setting activated=1\n");
684 void __inquire_remote_apic(int apicid)
686 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
687 const char * const names[] = { "ID", "VERSION", "SPIV" };
691 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
693 for (i = 0; i < ARRAY_SIZE(regs); i++) {
694 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
699 status = safe_apic_wait_icr_idle();
701 pr_cont("a previous APIC delivery may have failed\n");
703 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
708 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
709 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
712 case APIC_ICR_RR_VALID:
713 status = apic_read(APIC_RRR);
714 pr_cont("%08x\n", status);
723 * The Multiprocessor Specification 1.4 (1997) example code suggests
724 * that there should be a 10ms delay between the BSP asserting INIT
725 * and de-asserting INIT, when starting a remote processor.
726 * But that slows boot and resume on modern processors, which include
727 * many cores and don't require that delay.
729 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
730 * Modern processor families are quirked to remove the delay entirely.
732 #define UDELAY_10MS_DEFAULT 10000
734 static unsigned int init_udelay = UINT_MAX;
736 static int __init cpu_init_udelay(char *str)
738 get_option(&str, &init_udelay);
742 early_param("cpu_init_udelay", cpu_init_udelay);
744 static void __init smp_quirk_init_udelay(void)
746 /* if cmdline changed it from default, leave it alone */
747 if (init_udelay != UINT_MAX)
750 /* if modern processor, use no delay */
751 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
752 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
753 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
757 /* else, use legacy delay */
758 init_udelay = UDELAY_10MS_DEFAULT;
762 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
763 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
764 * won't ... remember to clear down the APIC, etc later.
767 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
769 unsigned long send_status, accept_status = 0;
773 /* Boot on the stack */
774 /* Kick the second */
775 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
777 pr_debug("Waiting for send to finish...\n");
778 send_status = safe_apic_wait_icr_idle();
781 * Give the other CPU some time to accept the IPI.
784 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
785 maxlvt = lapic_get_maxlvt();
786 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
787 apic_write(APIC_ESR, 0);
788 accept_status = (apic_read(APIC_ESR) & 0xEF);
790 pr_debug("NMI sent\n");
793 pr_err("APIC never delivered???\n");
795 pr_err("APIC delivery error (%lx)\n", accept_status);
797 return (send_status | accept_status);
801 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
803 unsigned long send_status = 0, accept_status = 0;
804 int maxlvt, num_starts, j;
806 maxlvt = lapic_get_maxlvt();
809 * Be paranoid about clearing APIC errors.
811 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
812 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
813 apic_write(APIC_ESR, 0);
817 pr_debug("Asserting INIT\n");
820 * Turn INIT on target chip
825 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
828 pr_debug("Waiting for send to finish...\n");
829 send_status = safe_apic_wait_icr_idle();
833 pr_debug("Deasserting INIT\n");
837 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
839 pr_debug("Waiting for send to finish...\n");
840 send_status = safe_apic_wait_icr_idle();
845 * Should we send STARTUP IPIs ?
847 * Determine this based on the APIC version.
848 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
850 if (APIC_INTEGRATED(boot_cpu_apic_version))
856 * Run STARTUP IPI loop.
858 pr_debug("#startup loops: %d\n", num_starts);
860 for (j = 1; j <= num_starts; j++) {
861 pr_debug("Sending STARTUP #%d\n", j);
862 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
863 apic_write(APIC_ESR, 0);
865 pr_debug("After apic_write\n");
872 /* Boot on the stack */
873 /* Kick the second */
874 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
878 * Give the other CPU some time to accept the IPI.
880 if (init_udelay == 0)
885 pr_debug("Startup point 1\n");
887 pr_debug("Waiting for send to finish...\n");
888 send_status = safe_apic_wait_icr_idle();
891 * Give the other CPU some time to accept the IPI.
893 if (init_udelay == 0)
898 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
899 apic_write(APIC_ESR, 0);
900 accept_status = (apic_read(APIC_ESR) & 0xEF);
901 if (send_status || accept_status)
904 pr_debug("After Startup\n");
907 pr_err("APIC never delivered???\n");
909 pr_err("APIC delivery error (%lx)\n", accept_status);
911 return (send_status | accept_status);
914 /* reduce the number of lines printed when booting a large cpu count system */
915 static void announce_cpu(int cpu, int apicid)
917 static int current_node = NUMA_NO_NODE;
918 int node = early_cpu_to_node(cpu);
919 static int width, node_width;
922 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
925 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
928 printk(KERN_INFO "x86: Booting SMP configuration:\n");
930 if (system_state < SYSTEM_RUNNING) {
931 if (node != current_node) {
932 if (current_node > (-1))
936 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
937 node_width - num_digits(node), " ", node);
940 /* Add padding for the BSP */
942 pr_cont("%*s", width + 1, " ");
944 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
947 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
951 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
955 cpu = smp_processor_id();
956 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
963 * Wake up AP by INIT, INIT, STARTUP sequence.
965 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
966 * boot-strap code which is not a desired behavior for waking up BSP. To
967 * void the boot-strap code, wake up CPU0 by NMI instead.
969 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
970 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
971 * We'll change this code in the future to wake up hard offlined CPU0 if
972 * real platform and request are available.
975 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
976 int *cpu0_nmi_registered)
984 * Wake up AP by INIT, INIT, STARTUP sequence.
987 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
992 * Wake up BSP by nmi.
994 * Register a NMI handler to help wake up CPU0.
996 boot_error = register_nmi_handler(NMI_LOCAL,
997 wakeup_cpu0_nmi, 0, "wake_cpu0");
1000 enable_start_cpu0 = 1;
1001 *cpu0_nmi_registered = 1;
1002 if (apic->dest_logical == APIC_DEST_LOGICAL)
1003 id = cpu0_logical_apicid;
1006 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1015 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1019 /* Just in case we booted with a single CPU. */
1020 alternatives_enable_smp();
1022 per_cpu(current_task, cpu) = idle;
1024 /* Initialize the interrupt stack(s) */
1025 ret = irq_init_percpu_irqstack(cpu);
1029 #ifdef CONFIG_X86_32
1030 /* Stack for startup_32 can be just as for start_secondary onwards */
1031 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1033 initial_gs = per_cpu_offset(cpu);
1039 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1040 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1041 * Returns zero if CPU booted OK, else error code from
1042 * ->wakeup_secondary_cpu.
1044 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1045 int *cpu0_nmi_registered)
1047 /* start_ip had better be page-aligned! */
1048 unsigned long start_ip = real_mode_header->trampoline_start;
1050 unsigned long boot_error = 0;
1051 unsigned long timeout;
1053 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1054 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1055 initial_code = (unsigned long)start_secondary;
1056 initial_stack = idle->thread.sp;
1058 /* Enable the espfix hack for this CPU */
1059 init_espfix_ap(cpu);
1061 /* So we see what's up */
1062 announce_cpu(cpu, apicid);
1065 * This grunge runs the startup process for
1066 * the targeted processor.
1069 if (x86_platform.legacy.warm_reset) {
1071 pr_debug("Setting warm reset code and vector.\n");
1073 smpboot_setup_warm_reset_vector(start_ip);
1075 * Be paranoid about clearing APIC errors.
1077 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1078 apic_write(APIC_ESR, 0);
1079 apic_read(APIC_ESR);
1084 * AP might wait on cpu_callout_mask in cpu_init() with
1085 * cpu_initialized_mask set if previous attempt to online
1086 * it timed-out. Clear cpu_initialized_mask so that after
1087 * INIT/SIPI it could start with a clean state.
1089 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1093 * Wake up a CPU in difference cases:
1094 * - Use the method in the APIC driver if it's defined
1096 * - Use an INIT boot APIC message for APs or NMI for BSP.
1098 if (apic->wakeup_secondary_cpu)
1099 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1101 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1102 cpu0_nmi_registered);
1106 * Wait 10s total for first sign of life from AP
1109 timeout = jiffies + 10*HZ;
1110 while (time_before(jiffies, timeout)) {
1111 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1113 * Tell AP to proceed with initialization
1115 cpumask_set_cpu(cpu, cpu_callout_mask);
1125 * Wait till AP completes initial initialization
1127 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1129 * Allow other tasks to run while we wait for the
1130 * AP to come online. This also gives a chance
1131 * for the MTRR work(triggered by the AP coming online)
1132 * to be completed in the stop machine context.
1138 if (x86_platform.legacy.warm_reset) {
1140 * Cleanup possible dangling ends...
1142 smpboot_restore_warm_reset_vector();
1148 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1150 int apicid = apic->cpu_present_to_apicid(cpu);
1151 int cpu0_nmi_registered = 0;
1152 unsigned long flags;
1155 lockdep_assert_irqs_enabled();
1157 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1159 if (apicid == BAD_APICID ||
1160 !physid_isset(apicid, phys_cpu_present_map) ||
1161 !apic->apic_id_valid(apicid)) {
1162 pr_err("%s: bad cpu %d\n", __func__, cpu);
1167 * Already booted CPU?
1169 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1170 pr_debug("do_boot_cpu %d Already started\n", cpu);
1175 * Save current MTRR state in case it was changed since early boot
1176 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1180 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1181 err = cpu_check_up_prepare(cpu);
1182 if (err && err != -EBUSY)
1185 /* the FPU context is blank, nobody can own it */
1186 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1188 err = common_cpu_up(cpu, tidle);
1192 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1194 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1200 * Check TSC synchronization with the AP (keep irqs disabled
1203 local_irq_save(flags);
1204 check_tsc_sync_source(cpu);
1205 local_irq_restore(flags);
1207 while (!cpu_online(cpu)) {
1209 touch_nmi_watchdog();
1214 * Clean up the nmi handler. Do this after the callin and callout sync
1215 * to avoid impact of possible long unregister time.
1217 if (cpu0_nmi_registered)
1218 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1224 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1226 void arch_disable_smp_support(void)
1228 disable_ioapic_support();
1232 * Fall back to non SMP mode after errors.
1234 * RED-PEN audit/test this more. I bet there is more state messed up here.
1236 static __init void disable_smp(void)
1238 pr_info("SMP disabled\n");
1240 disable_ioapic_support();
1242 init_cpu_present(cpumask_of(0));
1243 init_cpu_possible(cpumask_of(0));
1245 if (smp_found_config)
1246 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1248 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1249 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1250 cpumask_set_cpu(0, topology_core_cpumask(0));
1251 cpumask_set_cpu(0, topology_die_cpumask(0));
1255 * Various sanity checks.
1257 static void __init smp_sanity_check(void)
1261 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1262 if (def_to_bigsmp && nr_cpu_ids > 8) {
1266 pr_warn("More than 8 CPUs detected - skipping them\n"
1267 "Use CONFIG_X86_BIGSMP\n");
1270 for_each_present_cpu(cpu) {
1272 set_cpu_present(cpu, false);
1277 for_each_possible_cpu(cpu) {
1279 set_cpu_possible(cpu, false);
1287 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1288 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1289 hard_smp_processor_id());
1291 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1295 * Should not be necessary because the MP table should list the boot
1296 * CPU too, but we do it for the sake of robustness anyway.
1298 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1299 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1300 boot_cpu_physical_apicid);
1301 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1306 static void __init smp_cpu_index_default(void)
1309 struct cpuinfo_x86 *c;
1311 for_each_possible_cpu(i) {
1313 /* mark all to hotplug */
1314 c->cpu_index = nr_cpu_ids;
1318 static void __init smp_get_logical_apicid(void)
1321 cpu0_logical_apicid = apic_read(APIC_LDR);
1323 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1327 * Prepare for SMP bootup.
1328 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1329 * for common interface support.
1331 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1335 smp_cpu_index_default();
1338 * Setup boot CPU information
1340 smp_store_boot_cpu_info(); /* Final full version of the data */
1341 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1344 for_each_possible_cpu(i) {
1345 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1346 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1347 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1348 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1352 * Set 'default' x86 topology, this matches default_topology() in that
1353 * it has NUMA nodes as a topology level. See also
1354 * native_smp_cpus_done().
1356 * Must be done before set_cpus_sibling_map() is ran.
1358 set_sched_topology(x86_topology);
1360 set_cpu_sibling_map(0);
1364 switch (apic_intr_mode) {
1366 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1369 case APIC_SYMMETRIC_IO_NO_ROUTING:
1371 /* Setup local timer */
1372 x86_init.timers.setup_percpu_clockev();
1374 case APIC_VIRTUAL_WIRE:
1375 case APIC_SYMMETRIC_IO:
1379 /* Setup local timer */
1380 x86_init.timers.setup_percpu_clockev();
1382 smp_get_logical_apicid();
1385 print_cpu_info(&cpu_data(0));
1389 set_mtrr_aps_delayed_init();
1391 smp_quirk_init_udelay();
1393 speculative_store_bypass_ht_init();
1396 void arch_enable_nonboot_cpus_begin(void)
1398 set_mtrr_aps_delayed_init();
1401 void arch_enable_nonboot_cpus_end(void)
1407 * Early setup to make printk work.
1409 void __init native_smp_prepare_boot_cpu(void)
1411 int me = smp_processor_id();
1412 switch_to_new_gdt(me);
1413 /* already set me in cpu_online_mask in boot_cpu_init() */
1414 cpumask_set_cpu(me, cpu_callout_mask);
1415 cpu_set_state_online(me);
1416 native_pv_lock_init();
1419 void __init calculate_max_logical_packages(void)
1424 * Today neither Intel nor AMD support heterogenous systems so
1425 * extrapolate the boot cpu's data to all packages.
1427 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1428 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1429 pr_info("Max logical packages: %u\n", __max_logical_packages);
1432 void __init native_smp_cpus_done(unsigned int max_cpus)
1434 pr_debug("Boot done\n");
1436 calculate_max_logical_packages();
1438 if (x86_has_numa_in_package)
1439 set_sched_topology(x86_numa_in_package_topology);
1446 static int __initdata setup_possible_cpus = -1;
1447 static int __init _setup_possible_cpus(char *str)
1449 get_option(&str, &setup_possible_cpus);
1452 early_param("possible_cpus", _setup_possible_cpus);
1456 * cpu_possible_mask should be static, it cannot change as cpu's
1457 * are onlined, or offlined. The reason is per-cpu data-structures
1458 * are allocated by some modules at init time, and dont expect to
1459 * do this dynamically on cpu arrival/departure.
1460 * cpu_present_mask on the other hand can change dynamically.
1461 * In case when cpu_hotplug is not compiled, then we resort to current
1462 * behaviour, which is cpu_possible == cpu_present.
1465 * Three ways to find out the number of additional hotplug CPUs:
1466 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1467 * - The user can overwrite it with possible_cpus=NUM
1468 * - Otherwise don't reserve additional CPUs.
1469 * We do this because additional CPUs waste a lot of memory.
1472 __init void prefill_possible_map(void)
1476 /* No boot processor was found in mptable or ACPI MADT */
1477 if (!num_processors) {
1478 if (boot_cpu_has(X86_FEATURE_APIC)) {
1479 int apicid = boot_cpu_physical_apicid;
1480 int cpu = hard_smp_processor_id();
1482 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1484 /* Make sure boot cpu is enumerated */
1485 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1486 apic->apic_id_valid(apicid))
1487 generic_processor_info(apicid, boot_cpu_apic_version);
1490 if (!num_processors)
1494 i = setup_max_cpus ?: 1;
1495 if (setup_possible_cpus == -1) {
1496 possible = num_processors;
1497 #ifdef CONFIG_HOTPLUG_CPU
1499 possible += disabled_cpus;
1505 possible = setup_possible_cpus;
1507 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1509 /* nr_cpu_ids could be reduced via nr_cpus= */
1510 if (possible > nr_cpu_ids) {
1511 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1512 possible, nr_cpu_ids);
1513 possible = nr_cpu_ids;
1516 #ifdef CONFIG_HOTPLUG_CPU
1517 if (!setup_max_cpus)
1520 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1521 possible, setup_max_cpus);
1525 nr_cpu_ids = possible;
1527 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1528 possible, max_t(int, possible - num_processors, 0));
1530 reset_cpu_possible_mask();
1532 for (i = 0; i < possible; i++)
1533 set_cpu_possible(i, true);
1536 #ifdef CONFIG_HOTPLUG_CPU
1538 /* Recompute SMT state for all CPUs on offline */
1539 static void recompute_smt_state(void)
1541 int max_threads, cpu;
1544 for_each_online_cpu (cpu) {
1545 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1547 if (threads > max_threads)
1548 max_threads = threads;
1550 __max_smt_threads = max_threads;
1553 static void remove_siblinginfo(int cpu)
1556 struct cpuinfo_x86 *c = &cpu_data(cpu);
1558 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1559 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1561 * last thread sibling in this cpu core going down
1563 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1564 cpu_data(sibling).booted_cores--;
1567 for_each_cpu(sibling, topology_die_cpumask(cpu))
1568 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1569 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1570 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1571 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1572 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1573 cpumask_clear(cpu_llc_shared_mask(cpu));
1574 cpumask_clear(topology_sibling_cpumask(cpu));
1575 cpumask_clear(topology_core_cpumask(cpu));
1576 cpumask_clear(topology_die_cpumask(cpu));
1578 c->booted_cores = 0;
1579 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1580 recompute_smt_state();
1583 static void remove_cpu_from_maps(int cpu)
1585 set_cpu_online(cpu, false);
1586 cpumask_clear_cpu(cpu, cpu_callout_mask);
1587 cpumask_clear_cpu(cpu, cpu_callin_mask);
1588 /* was set by cpu_init() */
1589 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1590 numa_remove_cpu(cpu);
1593 void cpu_disable_common(void)
1595 int cpu = smp_processor_id();
1597 remove_siblinginfo(cpu);
1599 /* It's now safe to remove this processor from the online map */
1601 remove_cpu_from_maps(cpu);
1602 unlock_vector_lock();
1607 int native_cpu_disable(void)
1611 ret = lapic_can_unplug_cpu();
1615 cpu_disable_common();
1618 * Disable the local APIC. Otherwise IPI broadcasts will reach
1619 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1622 * Disabling the APIC must happen after cpu_disable_common()
1623 * which invokes fixup_irqs().
1625 * Disabling the APIC preserves already set bits in IRR, but
1626 * an interrupt arriving after disabling the local APIC does not
1627 * set the corresponding IRR bit.
1629 * fixup_irqs() scans IRR for set bits so it can raise a not
1630 * yet handled interrupt on the new destination CPU via an IPI
1631 * but obviously it can't do so for IRR bits which are not set.
1632 * IOW, interrupts arriving after disabling the local APIC will
1635 apic_soft_disable();
1640 int common_cpu_die(unsigned int cpu)
1644 /* We don't do anything here: idle task is faking death itself. */
1646 /* They ack this in play_dead() by setting CPU_DEAD */
1647 if (cpu_wait_death(cpu, 5)) {
1648 if (system_state == SYSTEM_RUNNING)
1649 pr_info("CPU %u is now offline\n", cpu);
1651 pr_err("CPU %u didn't die...\n", cpu);
1658 void native_cpu_die(unsigned int cpu)
1660 common_cpu_die(cpu);
1663 void play_dead_common(void)
1668 (void)cpu_report_death();
1671 * With physical CPU hotplug, we should halt the cpu
1673 local_irq_disable();
1676 static bool wakeup_cpu0(void)
1678 if (smp_processor_id() == 0 && enable_start_cpu0)
1685 * We need to flush the caches before going to sleep, lest we have
1686 * dirty data in our caches when we come back up.
1688 static inline void mwait_play_dead(void)
1690 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1691 unsigned int eax, ebx, ecx, edx;
1692 unsigned int highest_cstate = 0;
1693 unsigned int highest_subcstate = 0;
1696 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1697 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1699 if (!this_cpu_has(X86_FEATURE_MWAIT))
1701 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1703 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1706 eax = CPUID_MWAIT_LEAF;
1708 native_cpuid(&eax, &ebx, &ecx, &edx);
1711 * eax will be 0 if EDX enumeration is not valid.
1712 * Initialized below to cstate, sub_cstate value when EDX is valid.
1714 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1717 edx >>= MWAIT_SUBSTATE_SIZE;
1718 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1719 if (edx & MWAIT_SUBSTATE_MASK) {
1721 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1724 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1725 (highest_subcstate - 1);
1732 * The CLFLUSH is a workaround for erratum AAI65 for
1733 * the Xeon 7400 series. It's not clear it is actually
1734 * needed, but it should be harmless in either case.
1735 * The WBINVD is insufficient due to the spurious-wakeup
1736 * case where we return around the loop.
1741 __monitor(md, 0, 0);
1745 * If NMI wants to wake up CPU0, start CPU0.
1752 void hlt_play_dead(void)
1754 if (__this_cpu_read(cpu_info.x86) >= 4)
1760 * If NMI wants to wake up CPU0, start CPU0.
1767 void native_play_dead(void)
1770 tboot_shutdown(TB_SHUTDOWN_WFS);
1772 mwait_play_dead(); /* Only returns on failure */
1773 if (cpuidle_play_dead())
1777 #else /* ... !CONFIG_HOTPLUG_CPU */
1778 int native_cpu_disable(void)
1783 void native_cpu_die(unsigned int cpu)
1785 /* We said "no" in __cpu_disable */
1789 void native_play_dead(void)