1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
64 #include <asm/realmode.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
83 #include <asm/stackprotector.h>
85 /* representing HT siblings of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 /* representing HT and core siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93 /* representing HT, core, and die siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
95 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
101 EXPORT_PER_CPU_SYMBOL(cpu_info);
103 struct mwait_cpu_dead {
104 unsigned int control;
109 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
110 * that it's unlikely to be touched by other CPUs.
112 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
114 /* Logical package management. We might want to allocate that dynamically */
115 unsigned int __max_logical_packages __read_mostly;
116 EXPORT_SYMBOL(__max_logical_packages);
117 static unsigned int logical_packages __read_mostly;
118 static unsigned int logical_die __read_mostly;
120 /* Maximum number of SMT threads on any online core */
121 int __read_mostly __max_smt_threads = 1;
123 /* Flag to indicate if a complete sched domain rebuild is required */
124 bool x86_topology_update;
126 int arch_update_cpu_topology(void)
128 int retval = x86_topology_update;
130 x86_topology_update = false;
134 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
138 spin_lock_irqsave(&rtc_lock, flags);
139 CMOS_WRITE(0xa, 0xf);
140 spin_unlock_irqrestore(&rtc_lock, flags);
141 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
143 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
147 static inline void smpboot_restore_warm_reset_vector(void)
152 * Paranoid: Set warm reset code and vector here back
155 spin_lock_irqsave(&rtc_lock, flags);
157 spin_unlock_irqrestore(&rtc_lock, flags);
159 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
162 static void init_freq_invariance(bool secondary);
165 * Report back to the Boot Processor during boot time or to the caller processor
168 static void smp_callin(void)
173 * If waken up by an INIT in an 82489DX configuration
174 * cpu_callout_mask guarantees we don't get here before
175 * an INIT_deassert IPI reaches our local APIC, so it is
176 * now safe to touch our local APIC.
178 cpuid = smp_processor_id();
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
189 * Save our processor parameters. Note: this information
190 * is needed for clock calibration.
192 smp_store_cpu_info(cpuid);
195 * The topology information must be up to date before
196 * calibrate_delay() and notify_cpu_starting().
198 set_cpu_sibling_map(raw_smp_processor_id());
200 init_freq_invariance(true);
204 * Update loops_per_jiffy in cpu_data. Previous call to
205 * smp_store_cpu_info() stored a value that is close but not as
206 * accurate as the value just calculated.
209 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
210 pr_debug("Stack at about %p\n", &cpuid);
214 notify_cpu_starting(cpuid);
217 * Allow the master to continue.
219 cpumask_set_cpu(cpuid, cpu_callin_mask);
222 static int cpu0_logical_apicid;
223 static int enable_start_cpu0;
225 * Activate a secondary processor.
227 static void notrace start_secondary(void *unused)
230 * Don't put *anything* except direct CPU state initialization
231 * before cpu_init(), SMP booting is too fragile that we want to
232 * limit the things done here to the most necessary things.
237 /* switch away from the initial page table */
238 load_cr3(swapper_pg_dir);
241 cpu_init_secondary();
242 rcu_cpu_starting(raw_smp_processor_id());
243 x86_cpuinit.early_percpu_clock_init();
246 enable_start_cpu0 = 0;
248 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 * Check TSC synchronization with the boot CPU:
253 check_tsc_sync_target();
255 speculative_store_bypass_ht_init();
258 * Lock vector_lock, set CPU online and bring the vector
259 * allocator online. Online must be set with vector_lock held
260 * to prevent a concurrent irq setup/teardown from seeing a
261 * half valid vector space.
264 set_cpu_online(smp_processor_id(), true);
266 unlock_vector_lock();
267 cpu_set_state_online(smp_processor_id());
268 x86_platform.nmi_init();
270 /* enable local interrupts */
273 x86_cpuinit.setup_percpu_clockev();
276 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
280 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
283 bool topology_is_primary_thread(unsigned int cpu)
285 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
289 * topology_smt_supported - Check whether SMT is supported by the CPUs
291 bool topology_smt_supported(void)
293 return smp_num_siblings > 1;
297 * topology_phys_to_logical_pkg - Map a physical package id to a logical
299 * Returns logical package id or -1 if not found
301 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
305 for_each_possible_cpu(cpu) {
306 struct cpuinfo_x86 *c = &cpu_data(cpu);
308 if (c->initialized && c->phys_proc_id == phys_pkg)
309 return c->logical_proc_id;
313 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
315 * topology_phys_to_logical_die - Map a physical die id to logical
317 * Returns logical die id or -1 if not found
319 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
322 int proc_id = cpu_data(cur_cpu).phys_proc_id;
324 for_each_possible_cpu(cpu) {
325 struct cpuinfo_x86 *c = &cpu_data(cpu);
327 if (c->initialized && c->cpu_die_id == die_id &&
328 c->phys_proc_id == proc_id)
329 return c->logical_die_id;
333 EXPORT_SYMBOL(topology_phys_to_logical_die);
336 * topology_update_package_map - Update the physical to logical package map
337 * @pkg: The physical package id as retrieved via CPUID
338 * @cpu: The cpu for which this is updated
340 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
344 /* Already available somewhere? */
345 new = topology_phys_to_logical_pkg(pkg);
349 new = logical_packages++;
351 pr_info("CPU %u Converting physical %u to logical package %u\n",
355 cpu_data(cpu).logical_proc_id = new;
359 * topology_update_die_map - Update the physical to logical die map
360 * @die: The die id as retrieved via CPUID
361 * @cpu: The cpu for which this is updated
363 int topology_update_die_map(unsigned int die, unsigned int cpu)
367 /* Already available somewhere? */
368 new = topology_phys_to_logical_die(die, cpu);
374 pr_info("CPU %u Converting physical %u to logical die %u\n",
378 cpu_data(cpu).logical_die_id = new;
382 void __init smp_store_boot_cpu_info(void)
384 int id = 0; /* CPU 0 */
385 struct cpuinfo_x86 *c = &cpu_data(id);
389 topology_update_package_map(c->phys_proc_id, id);
390 topology_update_die_map(c->cpu_die_id, id);
391 c->initialized = true;
395 * The bootstrap kernel entry code has set these up. Save them for
398 void smp_store_cpu_info(int id)
400 struct cpuinfo_x86 *c = &cpu_data(id);
402 /* Copy boot_cpu_data only on the first bringup */
407 * During boot time, CPU0 has this setup already. Save the info when
408 * bringing up AP or offlined CPU0.
410 identify_secondary_cpu(c);
411 c->initialized = true;
415 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
417 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
419 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
423 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
425 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
427 return !WARN_ONCE(!topology_same_node(c, o),
428 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
429 "[node: %d != %d]. Ignoring dependency.\n",
430 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
433 #define link_mask(mfunc, c1, c2) \
435 cpumask_set_cpu((c1), mfunc(c2)); \
436 cpumask_set_cpu((c2), mfunc(c1)); \
439 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
441 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
442 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
444 if (c->phys_proc_id == o->phys_proc_id &&
445 c->cpu_die_id == o->cpu_die_id &&
446 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
447 if (c->cpu_core_id == o->cpu_core_id)
448 return topology_sane(c, o, "smt");
450 if ((c->cu_id != 0xff) &&
451 (o->cu_id != 0xff) &&
452 (c->cu_id == o->cu_id))
453 return topology_sane(c, o, "smt");
456 } else if (c->phys_proc_id == o->phys_proc_id &&
457 c->cpu_die_id == o->cpu_die_id &&
458 c->cpu_core_id == o->cpu_core_id) {
459 return topology_sane(c, o, "smt");
465 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
467 if (c->phys_proc_id == o->phys_proc_id &&
468 c->cpu_die_id == o->cpu_die_id)
474 * Unlike the other levels, we do not enforce keeping a
475 * multicore group inside a NUMA node. If this happens, we will
476 * discard the MC level of the topology later.
478 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
480 if (c->phys_proc_id == o->phys_proc_id)
486 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
488 * Any Intel CPU that has multiple nodes per package and does not
489 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
491 * When in SNC mode, these CPUs enumerate an LLC that is shared
492 * by multiple NUMA nodes. The LLC is shared for off-package data
493 * access but private to the NUMA node (half of the package) for
494 * on-package access. CPUID (the source of the information about
495 * the LLC) can only enumerate the cache as shared or unshared,
496 * but not this particular configuration.
499 static const struct x86_cpu_id intel_cod_cpu[] = {
500 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
501 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
502 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
506 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
508 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
509 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
510 bool intel_snc = id && id->driver_data;
512 /* Do not match if we do not have a valid APICID for cpu: */
513 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
516 /* Do not match if LLC id does not match: */
517 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
521 * Allow the SNC topology without warning. Return of false
522 * means 'c' does not share the LLC of 'o'. This will be
523 * reflected to userspace.
525 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
528 return topology_sane(c, o, "llc");
532 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
533 static inline int x86_sched_itmt_flags(void)
535 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
538 #ifdef CONFIG_SCHED_MC
539 static int x86_core_flags(void)
541 return cpu_core_flags() | x86_sched_itmt_flags();
544 #ifdef CONFIG_SCHED_SMT
545 static int x86_smt_flags(void)
547 return cpu_smt_flags() | x86_sched_itmt_flags();
552 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
553 #ifdef CONFIG_SCHED_SMT
554 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
556 #ifdef CONFIG_SCHED_MC
557 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
562 static struct sched_domain_topology_level x86_topology[] = {
563 #ifdef CONFIG_SCHED_SMT
564 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
566 #ifdef CONFIG_SCHED_MC
567 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
569 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
574 * Set if a package/die has multiple NUMA nodes inside.
575 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
576 * Sub-NUMA Clustering have this.
578 static bool x86_has_numa_in_package;
580 void set_cpu_sibling_map(int cpu)
582 bool has_smt = smp_num_siblings > 1;
583 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
584 struct cpuinfo_x86 *c = &cpu_data(cpu);
585 struct cpuinfo_x86 *o;
588 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
591 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
592 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
593 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
594 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
599 for_each_cpu(i, cpu_sibling_setup_mask) {
602 if (match_pkg(c, o) && !topology_same_node(c, o))
603 x86_has_numa_in_package = true;
605 if ((i == cpu) || (has_smt && match_smt(c, o)))
606 link_mask(topology_sibling_cpumask, cpu, i);
608 if ((i == cpu) || (has_mp && match_llc(c, o)))
609 link_mask(cpu_llc_shared_mask, cpu, i);
611 if ((i == cpu) || (has_mp && match_die(c, o)))
612 link_mask(topology_die_cpumask, cpu, i);
615 threads = cpumask_weight(topology_sibling_cpumask(cpu));
616 if (threads > __max_smt_threads)
617 __max_smt_threads = threads;
620 * This needs a separate iteration over the cpus because we rely on all
621 * topology_sibling_cpumask links to be set-up.
623 for_each_cpu(i, cpu_sibling_setup_mask) {
626 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
627 link_mask(topology_core_cpumask, cpu, i);
630 * Does this new cpu bringup a new core?
634 * for each core in package, increment
635 * the booted_cores for this new cpu
638 topology_sibling_cpumask(i)) == i)
641 * increment the core count for all
642 * the other cpus in this package
645 cpu_data(i).booted_cores++;
646 } else if (i != cpu && !c->booted_cores)
647 c->booted_cores = cpu_data(i).booted_cores;
652 /* maps the cpu to the sched domain representing multi-core */
653 const struct cpumask *cpu_coregroup_mask(int cpu)
655 return cpu_llc_shared_mask(cpu);
658 static void impress_friends(void)
661 unsigned long bogosum = 0;
663 * Allow the user to impress friends.
665 pr_debug("Before bogomips\n");
666 for_each_possible_cpu(cpu)
667 if (cpumask_test_cpu(cpu, cpu_callout_mask))
668 bogosum += cpu_data(cpu).loops_per_jiffy;
669 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
672 (bogosum/(5000/HZ))%100);
674 pr_debug("Before bogocount - setting activated=1\n");
677 void __inquire_remote_apic(int apicid)
679 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
680 const char * const names[] = { "ID", "VERSION", "SPIV" };
684 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
686 for (i = 0; i < ARRAY_SIZE(regs); i++) {
687 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
692 status = safe_apic_wait_icr_idle();
694 pr_cont("a previous APIC delivery may have failed\n");
696 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
701 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
702 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
705 case APIC_ICR_RR_VALID:
706 status = apic_read(APIC_RRR);
707 pr_cont("%08x\n", status);
716 * The Multiprocessor Specification 1.4 (1997) example code suggests
717 * that there should be a 10ms delay between the BSP asserting INIT
718 * and de-asserting INIT, when starting a remote processor.
719 * But that slows boot and resume on modern processors, which include
720 * many cores and don't require that delay.
722 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
723 * Modern processor families are quirked to remove the delay entirely.
725 #define UDELAY_10MS_DEFAULT 10000
727 static unsigned int init_udelay = UINT_MAX;
729 static int __init cpu_init_udelay(char *str)
731 get_option(&str, &init_udelay);
735 early_param("cpu_init_udelay", cpu_init_udelay);
737 static void __init smp_quirk_init_udelay(void)
739 /* if cmdline changed it from default, leave it alone */
740 if (init_udelay != UINT_MAX)
743 /* if modern processor, use no delay */
744 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
745 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
746 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
750 /* else, use legacy delay */
751 init_udelay = UDELAY_10MS_DEFAULT;
755 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
756 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
757 * won't ... remember to clear down the APIC, etc later.
760 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
762 unsigned long send_status, accept_status = 0;
766 /* Boot on the stack */
767 /* Kick the second */
768 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
770 pr_debug("Waiting for send to finish...\n");
771 send_status = safe_apic_wait_icr_idle();
774 * Give the other CPU some time to accept the IPI.
777 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
778 maxlvt = lapic_get_maxlvt();
779 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
780 apic_write(APIC_ESR, 0);
781 accept_status = (apic_read(APIC_ESR) & 0xEF);
783 pr_debug("NMI sent\n");
786 pr_err("APIC never delivered???\n");
788 pr_err("APIC delivery error (%lx)\n", accept_status);
790 return (send_status | accept_status);
794 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
796 unsigned long send_status = 0, accept_status = 0;
797 int maxlvt, num_starts, j;
799 maxlvt = lapic_get_maxlvt();
802 * Be paranoid about clearing APIC errors.
804 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
805 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
806 apic_write(APIC_ESR, 0);
810 pr_debug("Asserting INIT\n");
813 * Turn INIT on target chip
818 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
821 pr_debug("Waiting for send to finish...\n");
822 send_status = safe_apic_wait_icr_idle();
826 pr_debug("Deasserting INIT\n");
830 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
832 pr_debug("Waiting for send to finish...\n");
833 send_status = safe_apic_wait_icr_idle();
838 * Should we send STARTUP IPIs ?
840 * Determine this based on the APIC version.
841 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
843 if (APIC_INTEGRATED(boot_cpu_apic_version))
849 * Run STARTUP IPI loop.
851 pr_debug("#startup loops: %d\n", num_starts);
853 for (j = 1; j <= num_starts; j++) {
854 pr_debug("Sending STARTUP #%d\n", j);
855 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
856 apic_write(APIC_ESR, 0);
858 pr_debug("After apic_write\n");
865 /* Boot on the stack */
866 /* Kick the second */
867 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
871 * Give the other CPU some time to accept the IPI.
873 if (init_udelay == 0)
878 pr_debug("Startup point 1\n");
880 pr_debug("Waiting for send to finish...\n");
881 send_status = safe_apic_wait_icr_idle();
884 * Give the other CPU some time to accept the IPI.
886 if (init_udelay == 0)
891 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
892 apic_write(APIC_ESR, 0);
893 accept_status = (apic_read(APIC_ESR) & 0xEF);
894 if (send_status || accept_status)
897 pr_debug("After Startup\n");
900 pr_err("APIC never delivered???\n");
902 pr_err("APIC delivery error (%lx)\n", accept_status);
904 return (send_status | accept_status);
907 /* reduce the number of lines printed when booting a large cpu count system */
908 static void announce_cpu(int cpu, int apicid)
910 static int current_node = NUMA_NO_NODE;
911 int node = early_cpu_to_node(cpu);
912 static int width, node_width;
915 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
918 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
921 printk(KERN_INFO "x86: Booting SMP configuration:\n");
923 if (system_state < SYSTEM_RUNNING) {
924 if (node != current_node) {
925 if (current_node > (-1))
929 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
930 node_width - num_digits(node), " ", node);
933 /* Add padding for the BSP */
935 pr_cont("%*s", width + 1, " ");
937 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
940 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
944 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
948 cpu = smp_processor_id();
949 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
956 * Wake up AP by INIT, INIT, STARTUP sequence.
958 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
959 * boot-strap code which is not a desired behavior for waking up BSP. To
960 * void the boot-strap code, wake up CPU0 by NMI instead.
962 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
963 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
964 * We'll change this code in the future to wake up hard offlined CPU0 if
965 * real platform and request are available.
968 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
969 int *cpu0_nmi_registered)
977 * Wake up AP by INIT, INIT, STARTUP sequence.
980 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
985 * Wake up BSP by nmi.
987 * Register a NMI handler to help wake up CPU0.
989 boot_error = register_nmi_handler(NMI_LOCAL,
990 wakeup_cpu0_nmi, 0, "wake_cpu0");
993 enable_start_cpu0 = 1;
994 *cpu0_nmi_registered = 1;
995 if (apic->dest_logical == APIC_DEST_LOGICAL)
996 id = cpu0_logical_apicid;
999 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1008 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1012 /* Just in case we booted with a single CPU. */
1013 alternatives_enable_smp();
1015 per_cpu(current_task, cpu) = idle;
1016 cpu_init_stack_canary(cpu, idle);
1018 /* Initialize the interrupt stack(s) */
1019 ret = irq_init_percpu_irqstack(cpu);
1023 #ifdef CONFIG_X86_32
1024 /* Stack for startup_32 can be just as for start_secondary onwards */
1025 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1027 initial_gs = per_cpu_offset(cpu);
1033 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1034 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1035 * Returns zero if CPU booted OK, else error code from
1036 * ->wakeup_secondary_cpu.
1038 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1039 int *cpu0_nmi_registered)
1041 /* start_ip had better be page-aligned! */
1042 unsigned long start_ip = real_mode_header->trampoline_start;
1044 unsigned long boot_error = 0;
1045 unsigned long timeout;
1047 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1048 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1049 initial_code = (unsigned long)start_secondary;
1050 initial_stack = idle->thread.sp;
1052 /* Enable the espfix hack for this CPU */
1053 init_espfix_ap(cpu);
1055 /* So we see what's up */
1056 announce_cpu(cpu, apicid);
1059 * This grunge runs the startup process for
1060 * the targeted processor.
1063 if (x86_platform.legacy.warm_reset) {
1065 pr_debug("Setting warm reset code and vector.\n");
1067 smpboot_setup_warm_reset_vector(start_ip);
1069 * Be paranoid about clearing APIC errors.
1071 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1072 apic_write(APIC_ESR, 0);
1073 apic_read(APIC_ESR);
1078 * AP might wait on cpu_callout_mask in cpu_init() with
1079 * cpu_initialized_mask set if previous attempt to online
1080 * it timed-out. Clear cpu_initialized_mask so that after
1081 * INIT/SIPI it could start with a clean state.
1083 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1087 * Wake up a CPU in difference cases:
1088 * - Use the method in the APIC driver if it's defined
1090 * - Use an INIT boot APIC message for APs or NMI for BSP.
1092 if (apic->wakeup_secondary_cpu)
1093 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1095 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1096 cpu0_nmi_registered);
1100 * Wait 10s total for first sign of life from AP
1103 timeout = jiffies + 10*HZ;
1104 while (time_before(jiffies, timeout)) {
1105 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1107 * Tell AP to proceed with initialization
1109 cpumask_set_cpu(cpu, cpu_callout_mask);
1119 * Wait till AP completes initial initialization
1121 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1123 * Allow other tasks to run while we wait for the
1124 * AP to come online. This also gives a chance
1125 * for the MTRR work(triggered by the AP coming online)
1126 * to be completed in the stop machine context.
1132 if (x86_platform.legacy.warm_reset) {
1134 * Cleanup possible dangling ends...
1136 smpboot_restore_warm_reset_vector();
1142 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1144 int apicid = apic->cpu_present_to_apicid(cpu);
1145 int cpu0_nmi_registered = 0;
1146 unsigned long flags;
1149 lockdep_assert_irqs_enabled();
1151 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1153 if (apicid == BAD_APICID ||
1154 !physid_isset(apicid, phys_cpu_present_map) ||
1155 !apic->apic_id_valid(apicid)) {
1156 pr_err("%s: bad cpu %d\n", __func__, cpu);
1161 * Already booted CPU?
1163 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1164 pr_debug("do_boot_cpu %d Already started\n", cpu);
1169 * Save current MTRR state in case it was changed since early boot
1170 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1174 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1175 err = cpu_check_up_prepare(cpu);
1176 if (err && err != -EBUSY)
1179 /* the FPU context is blank, nobody can own it */
1180 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1182 err = common_cpu_up(cpu, tidle);
1186 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1188 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1194 * Check TSC synchronization with the AP (keep irqs disabled
1197 local_irq_save(flags);
1198 check_tsc_sync_source(cpu);
1199 local_irq_restore(flags);
1201 while (!cpu_online(cpu)) {
1203 touch_nmi_watchdog();
1208 * Clean up the nmi handler. Do this after the callin and callout sync
1209 * to avoid impact of possible long unregister time.
1211 if (cpu0_nmi_registered)
1212 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1218 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1220 void arch_disable_smp_support(void)
1222 disable_ioapic_support();
1226 * Fall back to non SMP mode after errors.
1228 * RED-PEN audit/test this more. I bet there is more state messed up here.
1230 static __init void disable_smp(void)
1232 pr_info("SMP disabled\n");
1234 disable_ioapic_support();
1236 init_cpu_present(cpumask_of(0));
1237 init_cpu_possible(cpumask_of(0));
1239 if (smp_found_config)
1240 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1242 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1243 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1244 cpumask_set_cpu(0, topology_core_cpumask(0));
1245 cpumask_set_cpu(0, topology_die_cpumask(0));
1249 * Various sanity checks.
1251 static void __init smp_sanity_check(void)
1255 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1256 if (def_to_bigsmp && nr_cpu_ids > 8) {
1260 pr_warn("More than 8 CPUs detected - skipping them\n"
1261 "Use CONFIG_X86_BIGSMP\n");
1264 for_each_present_cpu(cpu) {
1266 set_cpu_present(cpu, false);
1271 for_each_possible_cpu(cpu) {
1273 set_cpu_possible(cpu, false);
1281 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1282 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1283 hard_smp_processor_id());
1285 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1289 * Should not be necessary because the MP table should list the boot
1290 * CPU too, but we do it for the sake of robustness anyway.
1292 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1293 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1294 boot_cpu_physical_apicid);
1295 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1300 static void __init smp_cpu_index_default(void)
1303 struct cpuinfo_x86 *c;
1305 for_each_possible_cpu(i) {
1307 /* mark all to hotplug */
1308 c->cpu_index = nr_cpu_ids;
1312 static void __init smp_get_logical_apicid(void)
1315 cpu0_logical_apicid = apic_read(APIC_LDR);
1317 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1321 * Prepare for SMP bootup.
1322 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1323 * for common interface support.
1325 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1329 smp_cpu_index_default();
1332 * Setup boot CPU information
1334 smp_store_boot_cpu_info(); /* Final full version of the data */
1335 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1338 for_each_possible_cpu(i) {
1339 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1340 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1341 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1342 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1346 * Set 'default' x86 topology, this matches default_topology() in that
1347 * it has NUMA nodes as a topology level. See also
1348 * native_smp_cpus_done().
1350 * Must be done before set_cpus_sibling_map() is ran.
1352 set_sched_topology(x86_topology);
1354 set_cpu_sibling_map(0);
1355 init_freq_invariance(false);
1358 switch (apic_intr_mode) {
1360 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1363 case APIC_SYMMETRIC_IO_NO_ROUTING:
1365 /* Setup local timer */
1366 x86_init.timers.setup_percpu_clockev();
1368 case APIC_VIRTUAL_WIRE:
1369 case APIC_SYMMETRIC_IO:
1373 /* Setup local timer */
1374 x86_init.timers.setup_percpu_clockev();
1376 smp_get_logical_apicid();
1379 print_cpu_info(&cpu_data(0));
1383 set_mtrr_aps_delayed_init();
1385 smp_quirk_init_udelay();
1387 speculative_store_bypass_ht_init();
1390 void arch_thaw_secondary_cpus_begin(void)
1392 set_mtrr_aps_delayed_init();
1395 void arch_thaw_secondary_cpus_end(void)
1401 * Early setup to make printk work.
1403 void __init native_smp_prepare_boot_cpu(void)
1405 int me = smp_processor_id();
1406 switch_to_new_gdt(me);
1407 /* already set me in cpu_online_mask in boot_cpu_init() */
1408 cpumask_set_cpu(me, cpu_callout_mask);
1409 cpu_set_state_online(me);
1410 native_pv_lock_init();
1413 void __init calculate_max_logical_packages(void)
1418 * Today neither Intel nor AMD support heterogenous systems so
1419 * extrapolate the boot cpu's data to all packages.
1421 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1422 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1423 pr_info("Max logical packages: %u\n", __max_logical_packages);
1426 void __init native_smp_cpus_done(unsigned int max_cpus)
1428 pr_debug("Boot done\n");
1430 calculate_max_logical_packages();
1432 if (x86_has_numa_in_package)
1433 set_sched_topology(x86_numa_in_package_topology);
1440 static int __initdata setup_possible_cpus = -1;
1441 static int __init _setup_possible_cpus(char *str)
1443 get_option(&str, &setup_possible_cpus);
1446 early_param("possible_cpus", _setup_possible_cpus);
1450 * cpu_possible_mask should be static, it cannot change as cpu's
1451 * are onlined, or offlined. The reason is per-cpu data-structures
1452 * are allocated by some modules at init time, and don't expect to
1453 * do this dynamically on cpu arrival/departure.
1454 * cpu_present_mask on the other hand can change dynamically.
1455 * In case when cpu_hotplug is not compiled, then we resort to current
1456 * behaviour, which is cpu_possible == cpu_present.
1459 * Three ways to find out the number of additional hotplug CPUs:
1460 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1461 * - The user can overwrite it with possible_cpus=NUM
1462 * - Otherwise don't reserve additional CPUs.
1463 * We do this because additional CPUs waste a lot of memory.
1466 __init void prefill_possible_map(void)
1470 /* No boot processor was found in mptable or ACPI MADT */
1471 if (!num_processors) {
1472 if (boot_cpu_has(X86_FEATURE_APIC)) {
1473 int apicid = boot_cpu_physical_apicid;
1474 int cpu = hard_smp_processor_id();
1476 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1478 /* Make sure boot cpu is enumerated */
1479 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1480 apic->apic_id_valid(apicid))
1481 generic_processor_info(apicid, boot_cpu_apic_version);
1484 if (!num_processors)
1488 i = setup_max_cpus ?: 1;
1489 if (setup_possible_cpus == -1) {
1490 possible = num_processors;
1491 #ifdef CONFIG_HOTPLUG_CPU
1493 possible += disabled_cpus;
1499 possible = setup_possible_cpus;
1501 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1503 /* nr_cpu_ids could be reduced via nr_cpus= */
1504 if (possible > nr_cpu_ids) {
1505 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1506 possible, nr_cpu_ids);
1507 possible = nr_cpu_ids;
1510 #ifdef CONFIG_HOTPLUG_CPU
1511 if (!setup_max_cpus)
1514 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1515 possible, setup_max_cpus);
1519 nr_cpu_ids = possible;
1521 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1522 possible, max_t(int, possible - num_processors, 0));
1524 reset_cpu_possible_mask();
1526 for (i = 0; i < possible; i++)
1527 set_cpu_possible(i, true);
1530 #ifdef CONFIG_HOTPLUG_CPU
1532 /* Recompute SMT state for all CPUs on offline */
1533 static void recompute_smt_state(void)
1535 int max_threads, cpu;
1538 for_each_online_cpu (cpu) {
1539 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1541 if (threads > max_threads)
1542 max_threads = threads;
1544 __max_smt_threads = max_threads;
1547 static void remove_siblinginfo(int cpu)
1550 struct cpuinfo_x86 *c = &cpu_data(cpu);
1552 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1553 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1555 * last thread sibling in this cpu core going down
1557 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1558 cpu_data(sibling).booted_cores--;
1561 for_each_cpu(sibling, topology_die_cpumask(cpu))
1562 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1563 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1564 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1565 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1566 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1567 cpumask_clear(cpu_llc_shared_mask(cpu));
1568 cpumask_clear(topology_sibling_cpumask(cpu));
1569 cpumask_clear(topology_core_cpumask(cpu));
1570 cpumask_clear(topology_die_cpumask(cpu));
1572 c->booted_cores = 0;
1573 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1574 recompute_smt_state();
1577 static void remove_cpu_from_maps(int cpu)
1579 set_cpu_online(cpu, false);
1580 cpumask_clear_cpu(cpu, cpu_callout_mask);
1581 cpumask_clear_cpu(cpu, cpu_callin_mask);
1582 /* was set by cpu_init() */
1583 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1584 numa_remove_cpu(cpu);
1587 void cpu_disable_common(void)
1589 int cpu = smp_processor_id();
1591 remove_siblinginfo(cpu);
1593 /* It's now safe to remove this processor from the online map */
1595 remove_cpu_from_maps(cpu);
1596 unlock_vector_lock();
1601 int native_cpu_disable(void)
1605 ret = lapic_can_unplug_cpu();
1609 cpu_disable_common();
1612 * Disable the local APIC. Otherwise IPI broadcasts will reach
1613 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1616 * Disabling the APIC must happen after cpu_disable_common()
1617 * which invokes fixup_irqs().
1619 * Disabling the APIC preserves already set bits in IRR, but
1620 * an interrupt arriving after disabling the local APIC does not
1621 * set the corresponding IRR bit.
1623 * fixup_irqs() scans IRR for set bits so it can raise a not
1624 * yet handled interrupt on the new destination CPU via an IPI
1625 * but obviously it can't do so for IRR bits which are not set.
1626 * IOW, interrupts arriving after disabling the local APIC will
1629 apic_soft_disable();
1634 int common_cpu_die(unsigned int cpu)
1638 /* We don't do anything here: idle task is faking death itself. */
1640 /* They ack this in play_dead() by setting CPU_DEAD */
1641 if (cpu_wait_death(cpu, 5)) {
1642 if (system_state == SYSTEM_RUNNING)
1643 pr_info("CPU %u is now offline\n", cpu);
1645 pr_err("CPU %u didn't die...\n", cpu);
1652 void native_cpu_die(unsigned int cpu)
1654 common_cpu_die(cpu);
1657 void play_dead_common(void)
1662 (void)cpu_report_death();
1665 * With physical CPU hotplug, we should halt the cpu
1667 local_irq_disable();
1671 * cond_wakeup_cpu0 - Wake up CPU0 if needed.
1673 * If NMI wants to wake up CPU0, start CPU0.
1675 void cond_wakeup_cpu0(void)
1677 if (smp_processor_id() == 0 && enable_start_cpu0)
1680 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
1683 * We need to flush the caches before going to sleep, lest we have
1684 * dirty data in our caches when we come back up.
1686 static inline void mwait_play_dead(void)
1688 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1689 unsigned int eax, ebx, ecx, edx;
1690 unsigned int highest_cstate = 0;
1691 unsigned int highest_subcstate = 0;
1694 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1695 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1697 if (!this_cpu_has(X86_FEATURE_MWAIT))
1699 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1701 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1704 eax = CPUID_MWAIT_LEAF;
1706 native_cpuid(&eax, &ebx, &ecx, &edx);
1709 * eax will be 0 if EDX enumeration is not valid.
1710 * Initialized below to cstate, sub_cstate value when EDX is valid.
1712 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1715 edx >>= MWAIT_SUBSTATE_SIZE;
1716 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1717 if (edx & MWAIT_SUBSTATE_MASK) {
1719 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1722 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1723 (highest_subcstate - 1);
1730 * The CLFLUSH is a workaround for erratum AAI65 for
1731 * the Xeon 7400 series. It's not clear it is actually
1732 * needed, but it should be harmless in either case.
1733 * The WBINVD is insufficient due to the spurious-wakeup
1734 * case where we return around the loop.
1739 __monitor(md, 0, 0);
1747 void hlt_play_dead(void)
1749 if (__this_cpu_read(cpu_info.x86) >= 4)
1759 void native_play_dead(void)
1762 tboot_shutdown(TB_SHUTDOWN_WFS);
1764 mwait_play_dead(); /* Only returns on failure */
1765 if (cpuidle_play_dead())
1769 #else /* ... !CONFIG_HOTPLUG_CPU */
1770 int native_cpu_disable(void)
1775 void native_cpu_die(unsigned int cpu)
1777 /* We said "no" in __cpu_disable */
1781 void native_play_dead(void)
1788 #ifdef CONFIG_X86_64
1790 * APERF/MPERF frequency ratio computation.
1792 * The scheduler wants to do frequency invariant accounting and needs a <1
1793 * ratio to account for the 'current' frequency, corresponding to
1794 * freq_curr / freq_max.
1796 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1797 * our P-state setting is little more than a request/hint, we need to observe
1798 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1799 * interval after discarding idle time. This is given by:
1801 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1803 * where freq_base is the max non-turbo P-state.
1805 * The freq_max term has to be set to a somewhat arbitrary value, because we
1806 * can't know which turbo states will be available at a given point in time:
1807 * it all depends on the thermal headroom of the entire package. We set it to
1808 * the turbo level with 4 cores active.
1810 * Benchmarks show that's a good compromise between the 1C turbo ratio
1811 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1812 * which would ignore the entire turbo range (a conspicuous part, making
1813 * freq_curr/freq_max always maxed out).
1815 * An exception to the heuristic above is the Atom uarch, where we choose the
1816 * highest turbo level for freq_max since Atom's are generally oriented towards
1819 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1820 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1823 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1825 static DEFINE_PER_CPU(u64, arch_prev_aperf);
1826 static DEFINE_PER_CPU(u64, arch_prev_mperf);
1827 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1828 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1830 void arch_set_max_freq_ratio(bool turbo_disabled)
1832 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1833 arch_turbo_freq_ratio;
1835 EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio);
1837 static bool turbo_disabled(void)
1842 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1846 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1849 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1853 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1857 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1861 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1862 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1867 #include <asm/cpu_device_id.h>
1868 #include <asm/intel-family.h>
1870 #define X86_MATCH(model) \
1871 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
1872 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL)
1874 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1875 X86_MATCH(XEON_PHI_KNL),
1876 X86_MATCH(XEON_PHI_KNM),
1880 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1881 X86_MATCH(SKYLAKE_X),
1885 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1886 X86_MATCH(ATOM_GOLDMONT),
1887 X86_MATCH(ATOM_GOLDMONT_D),
1888 X86_MATCH(ATOM_GOLDMONT_PLUS),
1892 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1893 int num_delta_fratio)
1895 int fratio, delta_fratio, found;
1899 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1903 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1905 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1909 fratio = (msr >> 8) & 0xFF;
1913 if (found >= num_delta_fratio) {
1914 *turbo_freq = fratio;
1918 delta_fratio = (msr >> (i + 5)) & 0x7;
1922 fratio -= delta_fratio;
1931 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1937 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1941 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1943 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
1947 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
1951 for (i = 0; i < 64; i += 8) {
1952 group_size = (counts >> i) & 0xFF;
1953 if (group_size >= size) {
1954 *turbo_freq = (ratios >> i) & 0xFF;
1962 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1967 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1971 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1975 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1976 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
1978 /* The CPU may have less than 4 cores */
1980 *turbo_freq = msr & 0xFF; /* 1C turbo */
1985 static bool intel_set_max_freq_ratio(void)
1987 u64 base_freq, turbo_freq;
1990 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
1993 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
1994 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1997 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
1998 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
2001 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
2002 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
2005 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
2012 * Some hypervisors advertise X86_FEATURE_APERFMPERF
2013 * but then fill all MSR's with zeroes.
2014 * Some CPUs have turbo boost but don't declare any turbo ratio
2015 * in MSR_TURBO_RATIO_LIMIT.
2017 if (!base_freq || !turbo_freq) {
2018 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n");
2022 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq);
2024 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n");
2028 arch_turbo_freq_ratio = turbo_ratio;
2029 arch_set_max_freq_ratio(turbo_disabled());
2034 static void init_counter_refs(void)
2038 rdmsrl(MSR_IA32_APERF, aperf);
2039 rdmsrl(MSR_IA32_MPERF, mperf);
2041 this_cpu_write(arch_prev_aperf, aperf);
2042 this_cpu_write(arch_prev_mperf, mperf);
2045 static void init_freq_invariance(bool secondary)
2049 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2053 if (static_branch_likely(&arch_scale_freq_key)) {
2054 init_counter_refs();
2059 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2060 ret = intel_set_max_freq_ratio();
2063 init_counter_refs();
2064 static_branch_enable(&arch_scale_freq_key);
2066 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2070 static void disable_freq_invariance_workfn(struct work_struct *work)
2072 static_branch_disable(&arch_scale_freq_key);
2075 static DECLARE_WORK(disable_freq_invariance_work,
2076 disable_freq_invariance_workfn);
2078 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2080 void arch_scale_freq_tick(void)
2082 u64 freq_scale = SCHED_CAPACITY_SCALE;
2086 if (!arch_scale_freq_invariant())
2089 rdmsrl(MSR_IA32_APERF, aperf);
2090 rdmsrl(MSR_IA32_MPERF, mperf);
2092 acnt = aperf - this_cpu_read(arch_prev_aperf);
2093 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2095 this_cpu_write(arch_prev_aperf, aperf);
2096 this_cpu_write(arch_prev_mperf, mperf);
2098 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
2101 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt)
2104 freq_scale = div64_u64(acnt, mcnt);
2108 if (freq_scale > SCHED_CAPACITY_SCALE)
2109 freq_scale = SCHED_CAPACITY_SCALE;
2111 this_cpu_write(arch_freq_scale, freq_scale);
2115 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n");
2116 schedule_work(&disable_freq_invariance_work);
2119 static inline void init_freq_invariance(bool secondary)
2122 #endif /* CONFIG_X86_64 */