2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
83 #include <asm/hw_irq.h>
85 /* representing HT siblings of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 /* representing HT and core siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95 /* Per CPU bogomips and other parameters */
96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
97 EXPORT_PER_CPU_SYMBOL(cpu_info);
99 struct mwait_cpu_dead {
100 unsigned int control;
105 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
106 * that it's unlikely to be touched by other CPUs.
108 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
110 /* Logical package management. We might want to allocate that dynamically */
111 unsigned int __max_logical_packages __read_mostly;
112 EXPORT_SYMBOL(__max_logical_packages);
113 static unsigned int logical_packages __read_mostly;
115 /* Maximum number of SMT threads on any online core */
116 int __read_mostly __max_smt_threads = 1;
118 /* Flag to indicate if a complete sched domain rebuild is required */
119 bool x86_topology_update;
121 int arch_update_cpu_topology(void)
123 int retval = x86_topology_update;
125 x86_topology_update = false;
129 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
133 spin_lock_irqsave(&rtc_lock, flags);
134 CMOS_WRITE(0xa, 0xf);
135 spin_unlock_irqrestore(&rtc_lock, flags);
136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
138 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
142 static inline void smpboot_restore_warm_reset_vector(void)
147 * Paranoid: Set warm reset code and vector here back
150 spin_lock_irqsave(&rtc_lock, flags);
152 spin_unlock_irqrestore(&rtc_lock, flags);
154 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
158 * Report back to the Boot Processor during boot time or to the caller processor
161 static void smp_callin(void)
166 * If waken up by an INIT in an 82489DX configuration
167 * cpu_callout_mask guarantees we don't get here before
168 * an INIT_deassert IPI reaches our local APIC, so it is
169 * now safe to touch our local APIC.
171 cpuid = smp_processor_id();
174 * (This works even if the APIC is not enabled.)
176 phys_id = read_apic_id();
179 * the boot CPU has finished the init stage and is spinning
180 * on callin_map until we finish. We are free to set up this
181 * CPU, first the APIC. (this is probably redundant on most
187 * Save our processor parameters. Note: this information
188 * is needed for clock calibration.
190 smp_store_cpu_info(cpuid);
193 * The topology information must be up to date before
194 * calibrate_delay() and notify_cpu_starting().
196 set_cpu_sibling_map(raw_smp_processor_id());
200 * Update loops_per_jiffy in cpu_data. Previous call to
201 * smp_store_cpu_info() stored a value that is close but not as
202 * accurate as the value just calculated.
205 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
206 pr_debug("Stack at about %p\n", &cpuid);
210 notify_cpu_starting(cpuid);
213 * Allow the master to continue.
215 cpumask_set_cpu(cpuid, cpu_callin_mask);
218 static int cpu0_logical_apicid;
219 static int enable_start_cpu0;
221 * Activate a secondary processor.
223 static void notrace start_secondary(void *unused)
226 * Don't put *anything* except direct CPU state initialization
227 * before cpu_init(), SMP booting is too fragile that we want to
228 * limit the things done here to the most necessary things.
230 if (boot_cpu_has(X86_FEATURE_PCID))
231 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
234 /* switch away from the initial page table */
235 load_cr3(swapper_pg_dir);
237 * Initialize the CR4 shadow before doing anything that could
246 x86_cpuinit.early_percpu_clock_init();
250 enable_start_cpu0 = 0;
252 /* otherwise gcc will move up smp_processor_id before the cpu_init */
255 * Check TSC synchronization with the boot CPU:
257 check_tsc_sync_target();
259 speculative_store_bypass_ht_init();
262 * Lock vector_lock, set CPU online and bring the vector
263 * allocator online. Online must be set with vector_lock held
264 * to prevent a concurrent irq setup/teardown from seeing a
265 * half valid vector space.
268 set_cpu_online(smp_processor_id(), true);
270 unlock_vector_lock();
271 cpu_set_state_online(smp_processor_id());
272 x86_platform.nmi_init();
274 /* enable local interrupts */
277 /* to prevent fake stack check failure in clock setup */
278 boot_init_stack_canary();
280 x86_cpuinit.setup_percpu_clockev();
283 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
286 * Prevent tail call to cpu_startup_entry() because the stack protector
287 * guard has been changed a couple of function calls up, in
288 * boot_init_stack_canary() and must not be checked before tail calling
291 prevent_tail_call_optimization();
295 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
298 bool topology_is_primary_thread(unsigned int cpu)
300 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
304 * topology_smt_supported - Check whether SMT is supported by the CPUs
306 bool topology_smt_supported(void)
308 return smp_num_siblings > 1;
312 * topology_phys_to_logical_pkg - Map a physical package id to a logical
314 * Returns logical package id or -1 if not found
316 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
320 for_each_possible_cpu(cpu) {
321 struct cpuinfo_x86 *c = &cpu_data(cpu);
323 if (c->initialized && c->phys_proc_id == phys_pkg)
324 return c->logical_proc_id;
328 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
331 * topology_update_package_map - Update the physical to logical package map
332 * @pkg: The physical package id as retrieved via CPUID
333 * @cpu: The cpu for which this is updated
335 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
339 /* Already available somewhere? */
340 new = topology_phys_to_logical_pkg(pkg);
344 new = logical_packages++;
346 pr_info("CPU %u Converting physical %u to logical package %u\n",
350 cpu_data(cpu).logical_proc_id = new;
354 void __init smp_store_boot_cpu_info(void)
356 int id = 0; /* CPU 0 */
357 struct cpuinfo_x86 *c = &cpu_data(id);
361 topology_update_package_map(c->phys_proc_id, id);
362 c->initialized = true;
366 * The bootstrap kernel entry code has set these up. Save them for
369 void smp_store_cpu_info(int id)
371 struct cpuinfo_x86 *c = &cpu_data(id);
373 /* Copy boot_cpu_data only on the first bringup */
378 * During boot time, CPU0 has this setup already. Save the info when
379 * bringing up AP or offlined CPU0.
381 identify_secondary_cpu(c);
382 c->initialized = true;
386 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
388 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
390 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
394 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
396 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
398 return !WARN_ONCE(!topology_same_node(c, o),
399 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
400 "[node: %d != %d]. Ignoring dependency.\n",
401 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
404 #define link_mask(mfunc, c1, c2) \
406 cpumask_set_cpu((c1), mfunc(c2)); \
407 cpumask_set_cpu((c2), mfunc(c1)); \
410 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
412 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
415 if (c->phys_proc_id == o->phys_proc_id &&
416 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
417 if (c->cpu_core_id == o->cpu_core_id)
418 return topology_sane(c, o, "smt");
420 if ((c->cu_id != 0xff) &&
421 (o->cu_id != 0xff) &&
422 (c->cu_id == o->cu_id))
423 return topology_sane(c, o, "smt");
426 } else if (c->phys_proc_id == o->phys_proc_id &&
427 c->cpu_core_id == o->cpu_core_id) {
428 return topology_sane(c, o, "smt");
435 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
437 * These are Intel CPUs that enumerate an LLC that is shared by
438 * multiple NUMA nodes. The LLC on these systems is shared for
439 * off-package data access but private to the NUMA node (half
440 * of the package) for on-package access.
442 * CPUID (the source of the information about the LLC) can only
443 * enumerate the cache as being shared *or* unshared, but not
444 * this particular configuration. The CPU in this case enumerates
445 * the cache to be shared across the entire package (spanning both
449 static const struct x86_cpu_id snc_cpu[] = {
450 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
454 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
456 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
458 /* Do not match if we do not have a valid APICID for cpu: */
459 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
462 /* Do not match if LLC id does not match: */
463 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
467 * Allow the SNC topology without warning. Return of false
468 * means 'c' does not share the LLC of 'o'. This will be
469 * reflected to userspace.
471 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
474 return topology_sane(c, o, "llc");
478 * Unlike the other levels, we do not enforce keeping a
479 * multicore group inside a NUMA node. If this happens, we will
480 * discard the MC level of the topology later.
482 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
484 if (c->phys_proc_id == o->phys_proc_id)
489 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
490 static inline int x86_sched_itmt_flags(void)
492 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
495 #ifdef CONFIG_SCHED_MC
496 static int x86_core_flags(void)
498 return cpu_core_flags() | x86_sched_itmt_flags();
501 #ifdef CONFIG_SCHED_SMT
502 static int x86_smt_flags(void)
504 return cpu_smt_flags() | x86_sched_itmt_flags();
509 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
510 #ifdef CONFIG_SCHED_SMT
511 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
513 #ifdef CONFIG_SCHED_MC
514 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
519 static struct sched_domain_topology_level x86_topology[] = {
520 #ifdef CONFIG_SCHED_SMT
521 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
523 #ifdef CONFIG_SCHED_MC
524 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
526 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
531 * Set if a package/die has multiple NUMA nodes inside.
532 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
533 * Sub-NUMA Clustering have this.
535 static bool x86_has_numa_in_package;
537 void set_cpu_sibling_map(int cpu)
539 bool has_smt = smp_num_siblings > 1;
540 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
541 struct cpuinfo_x86 *c = &cpu_data(cpu);
542 struct cpuinfo_x86 *o;
545 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
548 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
549 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
550 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
555 for_each_cpu(i, cpu_sibling_setup_mask) {
558 if ((i == cpu) || (has_smt && match_smt(c, o)))
559 link_mask(topology_sibling_cpumask, cpu, i);
561 if ((i == cpu) || (has_mp && match_llc(c, o)))
562 link_mask(cpu_llc_shared_mask, cpu, i);
567 * This needs a separate iteration over the cpus because we rely on all
568 * topology_sibling_cpumask links to be set-up.
570 for_each_cpu(i, cpu_sibling_setup_mask) {
573 if ((i == cpu) || (has_mp && match_die(c, o))) {
574 link_mask(topology_core_cpumask, cpu, i);
577 * Does this new cpu bringup a new core?
580 topology_sibling_cpumask(cpu)) == 1) {
582 * for each core in package, increment
583 * the booted_cores for this new cpu
586 topology_sibling_cpumask(i)) == i)
589 * increment the core count for all
590 * the other cpus in this package
593 cpu_data(i).booted_cores++;
594 } else if (i != cpu && !c->booted_cores)
595 c->booted_cores = cpu_data(i).booted_cores;
597 if (match_die(c, o) && !topology_same_node(c, o))
598 x86_has_numa_in_package = true;
601 threads = cpumask_weight(topology_sibling_cpumask(cpu));
602 if (threads > __max_smt_threads)
603 __max_smt_threads = threads;
606 /* maps the cpu to the sched domain representing multi-core */
607 const struct cpumask *cpu_coregroup_mask(int cpu)
609 return cpu_llc_shared_mask(cpu);
612 static void impress_friends(void)
615 unsigned long bogosum = 0;
617 * Allow the user to impress friends.
619 pr_debug("Before bogomips\n");
620 for_each_possible_cpu(cpu)
621 if (cpumask_test_cpu(cpu, cpu_callout_mask))
622 bogosum += cpu_data(cpu).loops_per_jiffy;
623 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
626 (bogosum/(5000/HZ))%100);
628 pr_debug("Before bogocount - setting activated=1\n");
631 void __inquire_remote_apic(int apicid)
633 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
634 const char * const names[] = { "ID", "VERSION", "SPIV" };
638 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
640 for (i = 0; i < ARRAY_SIZE(regs); i++) {
641 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
646 status = safe_apic_wait_icr_idle();
648 pr_cont("a previous APIC delivery may have failed\n");
650 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
655 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
656 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
659 case APIC_ICR_RR_VALID:
660 status = apic_read(APIC_RRR);
661 pr_cont("%08x\n", status);
670 * The Multiprocessor Specification 1.4 (1997) example code suggests
671 * that there should be a 10ms delay between the BSP asserting INIT
672 * and de-asserting INIT, when starting a remote processor.
673 * But that slows boot and resume on modern processors, which include
674 * many cores and don't require that delay.
676 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
677 * Modern processor families are quirked to remove the delay entirely.
679 #define UDELAY_10MS_DEFAULT 10000
681 static unsigned int init_udelay = UINT_MAX;
683 static int __init cpu_init_udelay(char *str)
685 get_option(&str, &init_udelay);
689 early_param("cpu_init_udelay", cpu_init_udelay);
691 static void __init smp_quirk_init_udelay(void)
693 /* if cmdline changed it from default, leave it alone */
694 if (init_udelay != UINT_MAX)
697 /* if modern processor, use no delay */
698 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
699 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
703 /* else, use legacy delay */
704 init_udelay = UDELAY_10MS_DEFAULT;
708 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
709 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
710 * won't ... remember to clear down the APIC, etc later.
713 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
715 unsigned long send_status, accept_status = 0;
719 /* Boot on the stack */
720 /* Kick the second */
721 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
723 pr_debug("Waiting for send to finish...\n");
724 send_status = safe_apic_wait_icr_idle();
727 * Give the other CPU some time to accept the IPI.
730 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
731 maxlvt = lapic_get_maxlvt();
732 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
733 apic_write(APIC_ESR, 0);
734 accept_status = (apic_read(APIC_ESR) & 0xEF);
736 pr_debug("NMI sent\n");
739 pr_err("APIC never delivered???\n");
741 pr_err("APIC delivery error (%lx)\n", accept_status);
743 return (send_status | accept_status);
747 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
749 unsigned long send_status = 0, accept_status = 0;
750 int maxlvt, num_starts, j;
752 maxlvt = lapic_get_maxlvt();
755 * Be paranoid about clearing APIC errors.
757 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
758 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
759 apic_write(APIC_ESR, 0);
763 pr_debug("Asserting INIT\n");
766 * Turn INIT on target chip
771 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
774 pr_debug("Waiting for send to finish...\n");
775 send_status = safe_apic_wait_icr_idle();
779 pr_debug("Deasserting INIT\n");
783 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
785 pr_debug("Waiting for send to finish...\n");
786 send_status = safe_apic_wait_icr_idle();
791 * Should we send STARTUP IPIs ?
793 * Determine this based on the APIC version.
794 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
796 if (APIC_INTEGRATED(boot_cpu_apic_version))
802 * Run STARTUP IPI loop.
804 pr_debug("#startup loops: %d\n", num_starts);
806 for (j = 1; j <= num_starts; j++) {
807 pr_debug("Sending STARTUP #%d\n", j);
808 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
809 apic_write(APIC_ESR, 0);
811 pr_debug("After apic_write\n");
818 /* Boot on the stack */
819 /* Kick the second */
820 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
824 * Give the other CPU some time to accept the IPI.
826 if (init_udelay == 0)
831 pr_debug("Startup point 1\n");
833 pr_debug("Waiting for send to finish...\n");
834 send_status = safe_apic_wait_icr_idle();
837 * Give the other CPU some time to accept the IPI.
839 if (init_udelay == 0)
844 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
845 apic_write(APIC_ESR, 0);
846 accept_status = (apic_read(APIC_ESR) & 0xEF);
847 if (send_status || accept_status)
850 pr_debug("After Startup\n");
853 pr_err("APIC never delivered???\n");
855 pr_err("APIC delivery error (%lx)\n", accept_status);
857 return (send_status | accept_status);
860 /* reduce the number of lines printed when booting a large cpu count system */
861 static void announce_cpu(int cpu, int apicid)
863 static int current_node = -1;
864 int node = early_cpu_to_node(cpu);
865 static int width, node_width;
868 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
871 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
874 printk(KERN_INFO "x86: Booting SMP configuration:\n");
876 if (system_state < SYSTEM_RUNNING) {
877 if (node != current_node) {
878 if (current_node > (-1))
882 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
883 node_width - num_digits(node), " ", node);
886 /* Add padding for the BSP */
888 pr_cont("%*s", width + 1, " ");
890 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
893 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
897 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
901 cpu = smp_processor_id();
902 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
909 * Wake up AP by INIT, INIT, STARTUP sequence.
911 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
912 * boot-strap code which is not a desired behavior for waking up BSP. To
913 * void the boot-strap code, wake up CPU0 by NMI instead.
915 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
916 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
917 * We'll change this code in the future to wake up hard offlined CPU0 if
918 * real platform and request are available.
921 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
922 int *cpu0_nmi_registered)
930 * Wake up AP by INIT, INIT, STARTUP sequence.
933 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
938 * Wake up BSP by nmi.
940 * Register a NMI handler to help wake up CPU0.
942 boot_error = register_nmi_handler(NMI_LOCAL,
943 wakeup_cpu0_nmi, 0, "wake_cpu0");
946 enable_start_cpu0 = 1;
947 *cpu0_nmi_registered = 1;
948 if (apic->dest_logical == APIC_DEST_LOGICAL)
949 id = cpu0_logical_apicid;
952 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
961 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
963 /* Just in case we booted with a single CPU. */
964 alternatives_enable_smp();
966 per_cpu(current_task, cpu) = idle;
969 /* Stack for startup_32 can be just as for start_secondary onwards */
971 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
973 initial_gs = per_cpu_offset(cpu);
978 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
979 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
980 * Returns zero if CPU booted OK, else error code from
981 * ->wakeup_secondary_cpu.
983 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
984 int *cpu0_nmi_registered)
986 volatile u32 *trampoline_status =
987 (volatile u32 *) __va(real_mode_header->trampoline_status);
988 /* start_ip had better be page-aligned! */
989 unsigned long start_ip = real_mode_header->trampoline_start;
991 unsigned long boot_error = 0;
992 unsigned long timeout;
994 idle->thread.sp = (unsigned long)task_pt_regs(idle);
995 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
996 initial_code = (unsigned long)start_secondary;
997 initial_stack = idle->thread.sp;
999 /* Enable the espfix hack for this CPU */
1000 init_espfix_ap(cpu);
1002 /* So we see what's up */
1003 announce_cpu(cpu, apicid);
1006 * This grunge runs the startup process for
1007 * the targeted processor.
1010 if (x86_platform.legacy.warm_reset) {
1012 pr_debug("Setting warm reset code and vector.\n");
1014 smpboot_setup_warm_reset_vector(start_ip);
1016 * Be paranoid about clearing APIC errors.
1018 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1019 apic_write(APIC_ESR, 0);
1020 apic_read(APIC_ESR);
1025 * AP might wait on cpu_callout_mask in cpu_init() with
1026 * cpu_initialized_mask set if previous attempt to online
1027 * it timed-out. Clear cpu_initialized_mask so that after
1028 * INIT/SIPI it could start with a clean state.
1030 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1034 * Wake up a CPU in difference cases:
1035 * - Use the method in the APIC driver if it's defined
1037 * - Use an INIT boot APIC message for APs or NMI for BSP.
1039 if (apic->wakeup_secondary_cpu)
1040 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1042 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1043 cpu0_nmi_registered);
1047 * Wait 10s total for first sign of life from AP
1050 timeout = jiffies + 10*HZ;
1051 while (time_before(jiffies, timeout)) {
1052 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1054 * Tell AP to proceed with initialization
1056 cpumask_set_cpu(cpu, cpu_callout_mask);
1066 * Wait till AP completes initial initialization
1068 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1070 * Allow other tasks to run while we wait for the
1071 * AP to come online. This also gives a chance
1072 * for the MTRR work(triggered by the AP coming online)
1073 * to be completed in the stop machine context.
1079 /* mark "stuck" area as not stuck */
1080 *trampoline_status = 0;
1082 if (x86_platform.legacy.warm_reset) {
1084 * Cleanup possible dangling ends...
1086 smpboot_restore_warm_reset_vector();
1092 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1094 int apicid = apic->cpu_present_to_apicid(cpu);
1095 int cpu0_nmi_registered = 0;
1096 unsigned long flags;
1099 lockdep_assert_irqs_enabled();
1101 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1103 if (apicid == BAD_APICID ||
1104 !physid_isset(apicid, phys_cpu_present_map) ||
1105 !apic->apic_id_valid(apicid)) {
1106 pr_err("%s: bad cpu %d\n", __func__, cpu);
1111 * Already booted CPU?
1113 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1114 pr_debug("do_boot_cpu %d Already started\n", cpu);
1119 * Save current MTRR state in case it was changed since early boot
1120 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1124 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1125 err = cpu_check_up_prepare(cpu);
1126 if (err && err != -EBUSY)
1129 /* the FPU context is blank, nobody can own it */
1130 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1132 common_cpu_up(cpu, tidle);
1134 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1136 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1142 * Check TSC synchronization with the AP (keep irqs disabled
1145 local_irq_save(flags);
1146 check_tsc_sync_source(cpu);
1147 local_irq_restore(flags);
1149 while (!cpu_online(cpu)) {
1151 touch_nmi_watchdog();
1156 * Clean up the nmi handler. Do this after the callin and callout sync
1157 * to avoid impact of possible long unregister time.
1159 if (cpu0_nmi_registered)
1160 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1166 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1168 void arch_disable_smp_support(void)
1170 disable_ioapic_support();
1174 * Fall back to non SMP mode after errors.
1176 * RED-PEN audit/test this more. I bet there is more state messed up here.
1178 static __init void disable_smp(void)
1180 pr_info("SMP disabled\n");
1182 disable_ioapic_support();
1184 init_cpu_present(cpumask_of(0));
1185 init_cpu_possible(cpumask_of(0));
1187 if (smp_found_config)
1188 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1190 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1191 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1192 cpumask_set_cpu(0, topology_core_cpumask(0));
1196 * Various sanity checks.
1198 static void __init smp_sanity_check(void)
1202 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1203 if (def_to_bigsmp && nr_cpu_ids > 8) {
1207 pr_warn("More than 8 CPUs detected - skipping them\n"
1208 "Use CONFIG_X86_BIGSMP\n");
1211 for_each_present_cpu(cpu) {
1213 set_cpu_present(cpu, false);
1218 for_each_possible_cpu(cpu) {
1220 set_cpu_possible(cpu, false);
1228 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1229 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1230 hard_smp_processor_id());
1232 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1236 * Should not be necessary because the MP table should list the boot
1237 * CPU too, but we do it for the sake of robustness anyway.
1239 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1240 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1241 boot_cpu_physical_apicid);
1242 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1247 static void __init smp_cpu_index_default(void)
1250 struct cpuinfo_x86 *c;
1252 for_each_possible_cpu(i) {
1254 /* mark all to hotplug */
1255 c->cpu_index = nr_cpu_ids;
1259 static void __init smp_get_logical_apicid(void)
1262 cpu0_logical_apicid = apic_read(APIC_LDR);
1264 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1268 * Prepare for SMP bootup.
1269 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1270 * for common interface support.
1272 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1276 smp_cpu_index_default();
1279 * Setup boot CPU information
1281 smp_store_boot_cpu_info(); /* Final full version of the data */
1282 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1285 for_each_possible_cpu(i) {
1286 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1287 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1288 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1292 * Set 'default' x86 topology, this matches default_topology() in that
1293 * it has NUMA nodes as a topology level. See also
1294 * native_smp_cpus_done().
1296 * Must be done before set_cpus_sibling_map() is ran.
1298 set_sched_topology(x86_topology);
1300 set_cpu_sibling_map(0);
1304 switch (apic_intr_mode) {
1306 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1309 case APIC_SYMMETRIC_IO_NO_ROUTING:
1311 /* Setup local timer */
1312 x86_init.timers.setup_percpu_clockev();
1314 case APIC_VIRTUAL_WIRE:
1315 case APIC_SYMMETRIC_IO:
1319 /* Setup local timer */
1320 x86_init.timers.setup_percpu_clockev();
1322 smp_get_logical_apicid();
1325 print_cpu_info(&cpu_data(0));
1327 native_pv_lock_init();
1331 set_mtrr_aps_delayed_init();
1333 smp_quirk_init_udelay();
1335 speculative_store_bypass_ht_init();
1338 void arch_enable_nonboot_cpus_begin(void)
1340 set_mtrr_aps_delayed_init();
1343 void arch_enable_nonboot_cpus_end(void)
1349 * Early setup to make printk work.
1351 void __init native_smp_prepare_boot_cpu(void)
1353 int me = smp_processor_id();
1354 switch_to_new_gdt(me);
1355 /* already set me in cpu_online_mask in boot_cpu_init() */
1356 cpumask_set_cpu(me, cpu_callout_mask);
1357 cpu_set_state_online(me);
1360 void __init calculate_max_logical_packages(void)
1365 * Today neither Intel nor AMD support heterogenous systems so
1366 * extrapolate the boot cpu's data to all packages.
1368 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1369 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1370 pr_info("Max logical packages: %u\n", __max_logical_packages);
1373 void __init native_smp_cpus_done(unsigned int max_cpus)
1375 pr_debug("Boot done\n");
1377 calculate_max_logical_packages();
1379 if (x86_has_numa_in_package)
1380 set_sched_topology(x86_numa_in_package_topology);
1387 static int __initdata setup_possible_cpus = -1;
1388 static int __init _setup_possible_cpus(char *str)
1390 get_option(&str, &setup_possible_cpus);
1393 early_param("possible_cpus", _setup_possible_cpus);
1397 * cpu_possible_mask should be static, it cannot change as cpu's
1398 * are onlined, or offlined. The reason is per-cpu data-structures
1399 * are allocated by some modules at init time, and dont expect to
1400 * do this dynamically on cpu arrival/departure.
1401 * cpu_present_mask on the other hand can change dynamically.
1402 * In case when cpu_hotplug is not compiled, then we resort to current
1403 * behaviour, which is cpu_possible == cpu_present.
1406 * Three ways to find out the number of additional hotplug CPUs:
1407 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1408 * - The user can overwrite it with possible_cpus=NUM
1409 * - Otherwise don't reserve additional CPUs.
1410 * We do this because additional CPUs waste a lot of memory.
1413 __init void prefill_possible_map(void)
1417 /* No boot processor was found in mptable or ACPI MADT */
1418 if (!num_processors) {
1419 if (boot_cpu_has(X86_FEATURE_APIC)) {
1420 int apicid = boot_cpu_physical_apicid;
1421 int cpu = hard_smp_processor_id();
1423 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1425 /* Make sure boot cpu is enumerated */
1426 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1427 apic->apic_id_valid(apicid))
1428 generic_processor_info(apicid, boot_cpu_apic_version);
1431 if (!num_processors)
1435 i = setup_max_cpus ?: 1;
1436 if (setup_possible_cpus == -1) {
1437 possible = num_processors;
1438 #ifdef CONFIG_HOTPLUG_CPU
1440 possible += disabled_cpus;
1446 possible = setup_possible_cpus;
1448 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1450 /* nr_cpu_ids could be reduced via nr_cpus= */
1451 if (possible > nr_cpu_ids) {
1452 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1453 possible, nr_cpu_ids);
1454 possible = nr_cpu_ids;
1457 #ifdef CONFIG_HOTPLUG_CPU
1458 if (!setup_max_cpus)
1461 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1462 possible, setup_max_cpus);
1466 nr_cpu_ids = possible;
1468 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1469 possible, max_t(int, possible - num_processors, 0));
1471 reset_cpu_possible_mask();
1473 for (i = 0; i < possible; i++)
1474 set_cpu_possible(i, true);
1477 #ifdef CONFIG_HOTPLUG_CPU
1479 /* Recompute SMT state for all CPUs on offline */
1480 static void recompute_smt_state(void)
1482 int max_threads, cpu;
1485 for_each_online_cpu (cpu) {
1486 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1488 if (threads > max_threads)
1489 max_threads = threads;
1491 __max_smt_threads = max_threads;
1494 static void remove_siblinginfo(int cpu)
1497 struct cpuinfo_x86 *c = &cpu_data(cpu);
1499 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1500 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1502 * last thread sibling in this cpu core going down
1504 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1505 cpu_data(sibling).booted_cores--;
1508 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1509 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1510 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1511 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1512 cpumask_clear(cpu_llc_shared_mask(cpu));
1513 cpumask_clear(topology_sibling_cpumask(cpu));
1514 cpumask_clear(topology_core_cpumask(cpu));
1516 c->booted_cores = 0;
1517 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1518 recompute_smt_state();
1521 static void remove_cpu_from_maps(int cpu)
1523 set_cpu_online(cpu, false);
1524 cpumask_clear_cpu(cpu, cpu_callout_mask);
1525 cpumask_clear_cpu(cpu, cpu_callin_mask);
1526 /* was set by cpu_init() */
1527 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1528 numa_remove_cpu(cpu);
1531 void cpu_disable_common(void)
1533 int cpu = smp_processor_id();
1535 remove_siblinginfo(cpu);
1537 /* It's now safe to remove this processor from the online map */
1539 remove_cpu_from_maps(cpu);
1540 unlock_vector_lock();
1545 int native_cpu_disable(void)
1549 ret = lapic_can_unplug_cpu();
1554 cpu_disable_common();
1559 int common_cpu_die(unsigned int cpu)
1563 /* We don't do anything here: idle task is faking death itself. */
1565 /* They ack this in play_dead() by setting CPU_DEAD */
1566 if (cpu_wait_death(cpu, 5)) {
1567 if (system_state == SYSTEM_RUNNING)
1568 pr_info("CPU %u is now offline\n", cpu);
1570 pr_err("CPU %u didn't die...\n", cpu);
1577 void native_cpu_die(unsigned int cpu)
1579 common_cpu_die(cpu);
1582 void play_dead_common(void)
1587 (void)cpu_report_death();
1590 * With physical CPU hotplug, we should halt the cpu
1592 local_irq_disable();
1595 static bool wakeup_cpu0(void)
1597 if (smp_processor_id() == 0 && enable_start_cpu0)
1604 * We need to flush the caches before going to sleep, lest we have
1605 * dirty data in our caches when we come back up.
1607 static inline void mwait_play_dead(void)
1609 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1610 unsigned int eax, ebx, ecx, edx;
1611 unsigned int highest_cstate = 0;
1612 unsigned int highest_subcstate = 0;
1615 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1617 if (!this_cpu_has(X86_FEATURE_MWAIT))
1619 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1621 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1624 eax = CPUID_MWAIT_LEAF;
1626 native_cpuid(&eax, &ebx, &ecx, &edx);
1629 * eax will be 0 if EDX enumeration is not valid.
1630 * Initialized below to cstate, sub_cstate value when EDX is valid.
1632 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1635 edx >>= MWAIT_SUBSTATE_SIZE;
1636 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1637 if (edx & MWAIT_SUBSTATE_MASK) {
1639 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1642 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1643 (highest_subcstate - 1);
1650 * The CLFLUSH is a workaround for erratum AAI65 for
1651 * the Xeon 7400 series. It's not clear it is actually
1652 * needed, but it should be harmless in either case.
1653 * The WBINVD is insufficient due to the spurious-wakeup
1654 * case where we return around the loop.
1659 __monitor(md, 0, 0);
1663 * If NMI wants to wake up CPU0, start CPU0.
1670 void hlt_play_dead(void)
1672 if (__this_cpu_read(cpu_info.x86) >= 4)
1678 * If NMI wants to wake up CPU0, start CPU0.
1685 void native_play_dead(void)
1688 tboot_shutdown(TB_SHUTDOWN_WFS);
1690 mwait_play_dead(); /* Only returns on failure */
1691 if (cpuidle_play_dead())
1695 #else /* ... !CONFIG_HOTPLUG_CPU */
1696 int native_cpu_disable(void)
1701 void native_cpu_die(unsigned int cpu)
1703 /* We said "no" in __cpu_disable */
1707 void native_play_dead(void)