2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/spec-ctrl.h>
81 #include <asm/hw_irq.h>
83 /* representing HT siblings of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
85 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
87 /* representing HT and core siblings of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
93 /* Per CPU bogomips and other parameters */
94 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
95 EXPORT_PER_CPU_SYMBOL(cpu_info);
97 struct mwait_cpu_dead {
103 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
104 * that it's unlikely to be touched by other CPUs.
106 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
108 /* Logical package management. We might want to allocate that dynamically */
109 static int *physical_to_logical_pkg __read_mostly;
110 static unsigned long *physical_package_map __read_mostly;;
111 static unsigned int max_physical_pkg_id __read_mostly;
112 unsigned int __max_logical_packages __read_mostly;
113 EXPORT_SYMBOL(__max_logical_packages);
114 static unsigned int logical_packages __read_mostly;
116 /* Maximum number of SMT threads on any online core */
117 int __max_smt_threads __read_mostly;
119 /* Flag to indicate if a complete sched domain rebuild is required */
120 bool x86_topology_update;
122 int arch_update_cpu_topology(void)
124 int retval = x86_topology_update;
126 x86_topology_update = false;
130 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
134 spin_lock_irqsave(&rtc_lock, flags);
135 CMOS_WRITE(0xa, 0xf);
136 spin_unlock_irqrestore(&rtc_lock, flags);
137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
139 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
143 static inline void smpboot_restore_warm_reset_vector(void)
148 * Paranoid: Set warm reset code and vector here back
151 spin_lock_irqsave(&rtc_lock, flags);
153 spin_unlock_irqrestore(&rtc_lock, flags);
155 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
159 * Report back to the Boot Processor during boot time or to the caller processor
162 static void smp_callin(void)
167 * If waken up by an INIT in an 82489DX configuration
168 * cpu_callout_mask guarantees we don't get here before
169 * an INIT_deassert IPI reaches our local APIC, so it is
170 * now safe to touch our local APIC.
172 cpuid = smp_processor_id();
175 * (This works even if the APIC is not enabled.)
177 phys_id = read_apic_id();
180 * the boot CPU has finished the init stage and is spinning
181 * on callin_map until we finish. We are free to set up this
182 * CPU, first the APIC. (this is probably redundant on most
188 * Save our processor parameters. Note: this information
189 * is needed for clock calibration.
191 smp_store_cpu_info(cpuid);
194 * The topology information must be up to date before
195 * calibrate_delay() and notify_cpu_starting().
197 set_cpu_sibling_map(raw_smp_processor_id());
201 * Update loops_per_jiffy in cpu_data. Previous call to
202 * smp_store_cpu_info() stored a value that is close but not as
203 * accurate as the value just calculated.
206 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
207 pr_debug("Stack at about %p\n", &cpuid);
211 notify_cpu_starting(cpuid);
214 * Allow the master to continue.
216 cpumask_set_cpu(cpuid, cpu_callin_mask);
219 static int cpu0_logical_apicid;
220 static int enable_start_cpu0;
222 * Activate a secondary processor.
224 static void notrace start_secondary(void *unused)
227 * Don't put *anything* except direct CPU state initialization
228 * before cpu_init(), SMP booting is too fragile that we want to
229 * limit the things done here to the most necessary things.
231 if (boot_cpu_has(X86_FEATURE_PCID))
232 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
235 /* switch away from the initial page table */
236 load_cr3(swapper_pg_dir);
238 * Initialize the CR4 shadow before doing anything that could
247 x86_cpuinit.early_percpu_clock_init();
251 enable_start_cpu0 = 0;
253 /* otherwise gcc will move up smp_processor_id before the cpu_init */
256 * Check TSC synchronization with the BP:
258 check_tsc_sync_target();
260 speculative_store_bypass_ht_init();
263 * Lock vector_lock and initialize the vectors on this cpu
264 * before setting the cpu online. We must set it online with
265 * vector_lock held to prevent a concurrent setup/teardown
266 * from seeing a half valid vector space.
269 setup_vector_irq(smp_processor_id());
270 set_cpu_online(smp_processor_id(), true);
271 unlock_vector_lock();
272 cpu_set_state_online(smp_processor_id());
273 x86_platform.nmi_init();
275 /* enable local interrupts */
278 /* to prevent fake stack check failure in clock setup */
279 boot_init_stack_canary();
281 x86_cpuinit.setup_percpu_clockev();
284 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
287 * Prevent tail call to cpu_startup_entry() because the stack protector
288 * guard has been changed a couple of function calls up, in
289 * boot_init_stack_canary() and must not be checked before tail calling
292 prevent_tail_call_optimization();
296 * topology_update_package_map - Update the physical to logical package map
297 * @pkg: The physical package id as retrieved via CPUID
298 * @cpu: The cpu for which this is updated
300 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
304 /* Called from early boot ? */
305 if (!physical_package_map)
308 if (pkg >= max_physical_pkg_id)
311 /* Set the logical package id */
312 if (test_and_set_bit(pkg, physical_package_map))
315 if (logical_packages >= __max_logical_packages) {
316 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
317 logical_packages, cpu, __max_logical_packages);
321 new = logical_packages++;
323 pr_info("CPU %u Converting physical %u to logical package %u\n",
326 physical_to_logical_pkg[pkg] = new;
329 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
334 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
337 bool topology_is_primary_thread(unsigned int cpu)
339 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
343 * topology_smt_supported - Check whether SMT is supported by the CPUs
345 bool topology_smt_supported(void)
347 return smp_num_siblings > 1;
351 * topology_phys_to_logical_pkg - Map a physical package id to a logical
353 * Returns logical package id or -1 if not found
355 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
357 if (phys_pkg >= max_physical_pkg_id)
359 return physical_to_logical_pkg[phys_pkg];
361 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
363 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu)
369 * Today neither Intel nor AMD support heterogenous systems. That
370 * might change in the future....
372 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
373 * computation, this won't actually work since some Intel BIOSes
374 * report inconsistent HT data when they disable HT.
376 * In particular, they reduce the APIC-IDs to only include the cores,
377 * but leave the CPUID topology to say there are (2) siblings.
378 * This means we don't know how many threads there will be until
379 * after the APIC enumeration.
381 * By not including this we'll sometimes over-estimate the number of
382 * logical packages by the amount of !present siblings, but this is
383 * still better than MAX_LOCAL_APIC.
385 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
386 * on the command line leading to a similar issue as the HT disable
387 * problem because the hyperthreads are usually enumerated after the
390 ncpus = boot_cpu_data.x86_max_cores;
392 pr_warn("x86_max_cores == zero !?!?");
396 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
397 logical_packages = 0;
400 * Possibly larger than what we need as the number of apic ids per
401 * package can be smaller than the actual used apic ids.
403 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
404 size = max_physical_pkg_id * sizeof(unsigned int);
405 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
406 memset(physical_to_logical_pkg, 0xff, size);
407 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
408 physical_package_map = kzalloc(size, GFP_KERNEL);
410 pr_info("Max logical packages: %u\n", __max_logical_packages);
412 topology_update_package_map(c->phys_proc_id, cpu);
415 void __init smp_store_boot_cpu_info(void)
417 int id = 0; /* CPU 0 */
418 struct cpuinfo_x86 *c = &cpu_data(id);
422 smp_init_package_map(c, id);
426 * The bootstrap kernel entry code has set these up. Save them for
429 void smp_store_cpu_info(int id)
431 struct cpuinfo_x86 *c = &cpu_data(id);
436 * During boot time, CPU0 has this setup already. Save the info when
437 * bringing up AP or offlined CPU0.
439 identify_secondary_cpu(c);
443 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
445 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
447 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
451 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
453 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
455 return !WARN_ONCE(!topology_same_node(c, o),
456 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
457 "[node: %d != %d]. Ignoring dependency.\n",
458 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
461 #define link_mask(mfunc, c1, c2) \
463 cpumask_set_cpu((c1), mfunc(c2)); \
464 cpumask_set_cpu((c2), mfunc(c1)); \
467 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
469 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
470 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
472 if (c->phys_proc_id == o->phys_proc_id &&
473 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
474 if (c->cpu_core_id == o->cpu_core_id)
475 return topology_sane(c, o, "smt");
477 if ((c->cu_id != 0xff) &&
478 (o->cu_id != 0xff) &&
479 (c->cu_id == o->cu_id))
480 return topology_sane(c, o, "smt");
483 } else if (c->phys_proc_id == o->phys_proc_id &&
484 c->cpu_core_id == o->cpu_core_id) {
485 return topology_sane(c, o, "smt");
491 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
493 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
495 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
496 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
497 return topology_sane(c, o, "llc");
503 * Unlike the other levels, we do not enforce keeping a
504 * multicore group inside a NUMA node. If this happens, we will
505 * discard the MC level of the topology later.
507 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
509 if (c->phys_proc_id == o->phys_proc_id)
514 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
515 static inline int x86_sched_itmt_flags(void)
517 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
520 #ifdef CONFIG_SCHED_MC
521 static int x86_core_flags(void)
523 return cpu_core_flags() | x86_sched_itmt_flags();
526 #ifdef CONFIG_SCHED_SMT
527 static int x86_smt_flags(void)
529 return cpu_smt_flags() | x86_sched_itmt_flags();
534 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
535 #ifdef CONFIG_SCHED_SMT
536 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
538 #ifdef CONFIG_SCHED_MC
539 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
544 static struct sched_domain_topology_level x86_topology[] = {
545 #ifdef CONFIG_SCHED_SMT
546 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
548 #ifdef CONFIG_SCHED_MC
549 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
551 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
556 * Set if a package/die has multiple NUMA nodes inside.
557 * AMD Magny-Cours and Intel Cluster-on-Die have this.
559 static bool x86_has_numa_in_package;
561 void set_cpu_sibling_map(int cpu)
563 bool has_smt = smp_num_siblings > 1;
564 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
565 struct cpuinfo_x86 *c = &cpu_data(cpu);
566 struct cpuinfo_x86 *o;
569 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
572 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
573 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
574 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
579 for_each_cpu(i, cpu_sibling_setup_mask) {
582 if ((i == cpu) || (has_smt && match_smt(c, o)))
583 link_mask(topology_sibling_cpumask, cpu, i);
585 if ((i == cpu) || (has_mp && match_llc(c, o)))
586 link_mask(cpu_llc_shared_mask, cpu, i);
591 * This needs a separate iteration over the cpus because we rely on all
592 * topology_sibling_cpumask links to be set-up.
594 for_each_cpu(i, cpu_sibling_setup_mask) {
597 if ((i == cpu) || (has_mp && match_die(c, o))) {
598 link_mask(topology_core_cpumask, cpu, i);
601 * Does this new cpu bringup a new core?
604 topology_sibling_cpumask(cpu)) == 1) {
606 * for each core in package, increment
607 * the booted_cores for this new cpu
610 topology_sibling_cpumask(i)) == i)
613 * increment the core count for all
614 * the other cpus in this package
617 cpu_data(i).booted_cores++;
618 } else if (i != cpu && !c->booted_cores)
619 c->booted_cores = cpu_data(i).booted_cores;
621 if (match_die(c, o) && !topology_same_node(c, o))
622 x86_has_numa_in_package = true;
625 threads = cpumask_weight(topology_sibling_cpumask(cpu));
626 if (threads > __max_smt_threads)
627 __max_smt_threads = threads;
630 /* maps the cpu to the sched domain representing multi-core */
631 const struct cpumask *cpu_coregroup_mask(int cpu)
633 return cpu_llc_shared_mask(cpu);
636 static void impress_friends(void)
639 unsigned long bogosum = 0;
641 * Allow the user to impress friends.
643 pr_debug("Before bogomips\n");
644 for_each_possible_cpu(cpu)
645 if (cpumask_test_cpu(cpu, cpu_callout_mask))
646 bogosum += cpu_data(cpu).loops_per_jiffy;
647 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
650 (bogosum/(5000/HZ))%100);
652 pr_debug("Before bogocount - setting activated=1\n");
655 void __inquire_remote_apic(int apicid)
657 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
658 const char * const names[] = { "ID", "VERSION", "SPIV" };
662 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
664 for (i = 0; i < ARRAY_SIZE(regs); i++) {
665 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
670 status = safe_apic_wait_icr_idle();
672 pr_cont("a previous APIC delivery may have failed\n");
674 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
679 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
680 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
683 case APIC_ICR_RR_VALID:
684 status = apic_read(APIC_RRR);
685 pr_cont("%08x\n", status);
694 * The Multiprocessor Specification 1.4 (1997) example code suggests
695 * that there should be a 10ms delay between the BSP asserting INIT
696 * and de-asserting INIT, when starting a remote processor.
697 * But that slows boot and resume on modern processors, which include
698 * many cores and don't require that delay.
700 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
701 * Modern processor families are quirked to remove the delay entirely.
703 #define UDELAY_10MS_DEFAULT 10000
705 static unsigned int init_udelay = UINT_MAX;
707 static int __init cpu_init_udelay(char *str)
709 get_option(&str, &init_udelay);
713 early_param("cpu_init_udelay", cpu_init_udelay);
715 static void __init smp_quirk_init_udelay(void)
717 /* if cmdline changed it from default, leave it alone */
718 if (init_udelay != UINT_MAX)
721 /* if modern processor, use no delay */
722 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
723 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
727 /* else, use legacy delay */
728 init_udelay = UDELAY_10MS_DEFAULT;
732 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
733 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
734 * won't ... remember to clear down the APIC, etc later.
737 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
739 unsigned long send_status, accept_status = 0;
743 /* Boot on the stack */
744 /* Kick the second */
745 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
747 pr_debug("Waiting for send to finish...\n");
748 send_status = safe_apic_wait_icr_idle();
751 * Give the other CPU some time to accept the IPI.
754 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
755 maxlvt = lapic_get_maxlvt();
756 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
757 apic_write(APIC_ESR, 0);
758 accept_status = (apic_read(APIC_ESR) & 0xEF);
760 pr_debug("NMI sent\n");
763 pr_err("APIC never delivered???\n");
765 pr_err("APIC delivery error (%lx)\n", accept_status);
767 return (send_status | accept_status);
771 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
773 unsigned long send_status = 0, accept_status = 0;
774 int maxlvt, num_starts, j;
776 maxlvt = lapic_get_maxlvt();
779 * Be paranoid about clearing APIC errors.
781 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
782 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
783 apic_write(APIC_ESR, 0);
787 pr_debug("Asserting INIT\n");
790 * Turn INIT on target chip
795 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
798 pr_debug("Waiting for send to finish...\n");
799 send_status = safe_apic_wait_icr_idle();
803 pr_debug("Deasserting INIT\n");
807 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
809 pr_debug("Waiting for send to finish...\n");
810 send_status = safe_apic_wait_icr_idle();
815 * Should we send STARTUP IPIs ?
817 * Determine this based on the APIC version.
818 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
820 if (APIC_INTEGRATED(boot_cpu_apic_version))
826 * Run STARTUP IPI loop.
828 pr_debug("#startup loops: %d\n", num_starts);
830 for (j = 1; j <= num_starts; j++) {
831 pr_debug("Sending STARTUP #%d\n", j);
832 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
833 apic_write(APIC_ESR, 0);
835 pr_debug("After apic_write\n");
842 /* Boot on the stack */
843 /* Kick the second */
844 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
848 * Give the other CPU some time to accept the IPI.
850 if (init_udelay == 0)
855 pr_debug("Startup point 1\n");
857 pr_debug("Waiting for send to finish...\n");
858 send_status = safe_apic_wait_icr_idle();
861 * Give the other CPU some time to accept the IPI.
863 if (init_udelay == 0)
868 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
869 apic_write(APIC_ESR, 0);
870 accept_status = (apic_read(APIC_ESR) & 0xEF);
871 if (send_status || accept_status)
874 pr_debug("After Startup\n");
877 pr_err("APIC never delivered???\n");
879 pr_err("APIC delivery error (%lx)\n", accept_status);
881 return (send_status | accept_status);
884 /* reduce the number of lines printed when booting a large cpu count system */
885 static void announce_cpu(int cpu, int apicid)
887 static int current_node = -1;
888 int node = early_cpu_to_node(cpu);
889 static int width, node_width;
892 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
895 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
898 printk(KERN_INFO "x86: Booting SMP configuration:\n");
900 if (system_state < SYSTEM_RUNNING) {
901 if (node != current_node) {
902 if (current_node > (-1))
906 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
907 node_width - num_digits(node), " ", node);
910 /* Add padding for the BSP */
912 pr_cont("%*s", width + 1, " ");
914 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
917 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
921 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
925 cpu = smp_processor_id();
926 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
933 * Wake up AP by INIT, INIT, STARTUP sequence.
935 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
936 * boot-strap code which is not a desired behavior for waking up BSP. To
937 * void the boot-strap code, wake up CPU0 by NMI instead.
939 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
940 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
941 * We'll change this code in the future to wake up hard offlined CPU0 if
942 * real platform and request are available.
945 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
946 int *cpu0_nmi_registered)
954 * Wake up AP by INIT, INIT, STARTUP sequence.
957 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
962 * Wake up BSP by nmi.
964 * Register a NMI handler to help wake up CPU0.
966 boot_error = register_nmi_handler(NMI_LOCAL,
967 wakeup_cpu0_nmi, 0, "wake_cpu0");
970 enable_start_cpu0 = 1;
971 *cpu0_nmi_registered = 1;
972 if (apic->dest_logical == APIC_DEST_LOGICAL)
973 id = cpu0_logical_apicid;
976 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
985 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
987 /* Just in case we booted with a single CPU. */
988 alternatives_enable_smp();
990 per_cpu(current_task, cpu) = idle;
993 /* Stack for startup_32 can be just as for start_secondary onwards */
995 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
997 initial_gs = per_cpu_offset(cpu);
1002 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1003 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1004 * Returns zero if CPU booted OK, else error code from
1005 * ->wakeup_secondary_cpu.
1007 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1008 int *cpu0_nmi_registered)
1010 volatile u32 *trampoline_status =
1011 (volatile u32 *) __va(real_mode_header->trampoline_status);
1012 /* start_ip had better be page-aligned! */
1013 unsigned long start_ip = real_mode_header->trampoline_start;
1015 unsigned long boot_error = 0;
1016 unsigned long timeout;
1018 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1019 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1020 initial_code = (unsigned long)start_secondary;
1021 initial_stack = idle->thread.sp;
1023 /* Enable the espfix hack for this CPU */
1024 init_espfix_ap(cpu);
1026 /* So we see what's up */
1027 announce_cpu(cpu, apicid);
1030 * This grunge runs the startup process for
1031 * the targeted processor.
1034 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1036 pr_debug("Setting warm reset code and vector.\n");
1038 smpboot_setup_warm_reset_vector(start_ip);
1040 * Be paranoid about clearing APIC errors.
1042 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1043 apic_write(APIC_ESR, 0);
1044 apic_read(APIC_ESR);
1049 * AP might wait on cpu_callout_mask in cpu_init() with
1050 * cpu_initialized_mask set if previous attempt to online
1051 * it timed-out. Clear cpu_initialized_mask so that after
1052 * INIT/SIPI it could start with a clean state.
1054 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1058 * Wake up a CPU in difference cases:
1059 * - Use the method in the APIC driver if it's defined
1061 * - Use an INIT boot APIC message for APs or NMI for BSP.
1063 if (apic->wakeup_secondary_cpu)
1064 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1066 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1067 cpu0_nmi_registered);
1071 * Wait 10s total for first sign of life from AP
1074 timeout = jiffies + 10*HZ;
1075 while (time_before(jiffies, timeout)) {
1076 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1078 * Tell AP to proceed with initialization
1080 cpumask_set_cpu(cpu, cpu_callout_mask);
1090 * Wait till AP completes initial initialization
1092 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1094 * Allow other tasks to run while we wait for the
1095 * AP to come online. This also gives a chance
1096 * for the MTRR work(triggered by the AP coming online)
1097 * to be completed in the stop machine context.
1103 /* mark "stuck" area as not stuck */
1104 *trampoline_status = 0;
1106 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1108 * Cleanup possible dangling ends...
1110 smpboot_restore_warm_reset_vector();
1116 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1118 int apicid = apic->cpu_present_to_apicid(cpu);
1119 int cpu0_nmi_registered = 0;
1120 unsigned long flags;
1123 WARN_ON(irqs_disabled());
1125 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1127 if (apicid == BAD_APICID ||
1128 !physid_isset(apicid, phys_cpu_present_map) ||
1129 !apic->apic_id_valid(apicid)) {
1130 pr_err("%s: bad cpu %d\n", __func__, cpu);
1135 * Already booted CPU?
1137 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1138 pr_debug("do_boot_cpu %d Already started\n", cpu);
1143 * Save current MTRR state in case it was changed since early boot
1144 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1148 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1149 err = cpu_check_up_prepare(cpu);
1150 if (err && err != -EBUSY)
1153 /* the FPU context is blank, nobody can own it */
1154 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1156 common_cpu_up(cpu, tidle);
1158 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1160 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1166 * Check TSC synchronization with the AP (keep irqs disabled
1169 local_irq_save(flags);
1170 check_tsc_sync_source(cpu);
1171 local_irq_restore(flags);
1173 while (!cpu_online(cpu)) {
1175 touch_nmi_watchdog();
1180 * Clean up the nmi handler. Do this after the callin and callout sync
1181 * to avoid impact of possible long unregister time.
1183 if (cpu0_nmi_registered)
1184 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1190 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1192 void arch_disable_smp_support(void)
1194 disable_ioapic_support();
1198 * Fall back to non SMP mode after errors.
1200 * RED-PEN audit/test this more. I bet there is more state messed up here.
1202 static __init void disable_smp(void)
1204 pr_info("SMP disabled\n");
1206 disable_ioapic_support();
1208 init_cpu_present(cpumask_of(0));
1209 init_cpu_possible(cpumask_of(0));
1211 if (smp_found_config)
1212 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1214 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1215 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1216 cpumask_set_cpu(0, topology_core_cpumask(0));
1227 * Various sanity checks.
1229 static int __init smp_sanity_check(unsigned max_cpus)
1233 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1234 if (def_to_bigsmp && nr_cpu_ids > 8) {
1238 pr_warn("More than 8 CPUs detected - skipping them\n"
1239 "Use CONFIG_X86_BIGSMP\n");
1242 for_each_present_cpu(cpu) {
1244 set_cpu_present(cpu, false);
1249 for_each_possible_cpu(cpu) {
1251 set_cpu_possible(cpu, false);
1259 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1260 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1261 hard_smp_processor_id());
1263 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1267 * If we couldn't find an SMP configuration at boot time,
1268 * get out of here now!
1270 if (!smp_found_config && !acpi_lapic) {
1272 pr_notice("SMP motherboard not detected\n");
1273 return SMP_NO_CONFIG;
1277 * Should not be necessary because the MP table should list the boot
1278 * CPU too, but we do it for the sake of robustness anyway.
1280 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1281 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1282 boot_cpu_physical_apicid);
1283 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1288 * If we couldn't find a local APIC, then get out of here now!
1290 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
1291 !boot_cpu_has(X86_FEATURE_APIC)) {
1292 if (!disable_apic) {
1293 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1294 boot_cpu_physical_apicid);
1295 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1301 * If SMP should be disabled, then really disable it!
1304 pr_info("SMP mode deactivated\n");
1305 return SMP_FORCE_UP;
1311 static void __init smp_cpu_index_default(void)
1314 struct cpuinfo_x86 *c;
1316 for_each_possible_cpu(i) {
1318 /* mark all to hotplug */
1319 c->cpu_index = nr_cpu_ids;
1324 * Prepare for SMP bootup. The MP table or ACPI has been read
1325 * earlier. Just do some sanity checking here and enable APIC mode.
1327 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1331 smp_cpu_index_default();
1334 * Setup boot CPU information
1336 smp_store_boot_cpu_info(); /* Final full version of the data */
1337 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1340 for_each_possible_cpu(i) {
1341 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1342 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1343 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1347 * Set 'default' x86 topology, this matches default_topology() in that
1348 * it has NUMA nodes as a topology level. See also
1349 * native_smp_cpus_done().
1351 * Must be done before set_cpus_sibling_map() is ran.
1353 set_sched_topology(x86_topology);
1355 set_cpu_sibling_map(0);
1357 switch (smp_sanity_check(max_cpus)) {
1360 if (APIC_init_uniprocessor())
1361 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1368 apic_bsp_setup(false);
1374 if (read_apic_id() != boot_cpu_physical_apicid) {
1375 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1376 read_apic_id(), boot_cpu_physical_apicid);
1377 /* Or can we switch back to PIC here? */
1380 default_setup_apic_routing();
1381 cpu0_logical_apicid = apic_bsp_setup(false);
1384 print_cpu_info(&cpu_data(0));
1388 set_mtrr_aps_delayed_init();
1390 smp_quirk_init_udelay();
1392 speculative_store_bypass_ht_init();
1395 void arch_enable_nonboot_cpus_begin(void)
1397 set_mtrr_aps_delayed_init();
1400 void arch_enable_nonboot_cpus_end(void)
1406 * Early setup to make printk work.
1408 void __init native_smp_prepare_boot_cpu(void)
1410 int me = smp_processor_id();
1411 switch_to_new_gdt(me);
1412 /* already set me in cpu_online_mask in boot_cpu_init() */
1413 cpumask_set_cpu(me, cpu_callout_mask);
1414 cpu_set_state_online(me);
1417 void __init native_smp_cpus_done(unsigned int max_cpus)
1419 pr_debug("Boot done\n");
1421 if (x86_has_numa_in_package)
1422 set_sched_topology(x86_numa_in_package_topology);
1426 setup_ioapic_dest();
1430 static int __initdata setup_possible_cpus = -1;
1431 static int __init _setup_possible_cpus(char *str)
1433 get_option(&str, &setup_possible_cpus);
1436 early_param("possible_cpus", _setup_possible_cpus);
1440 * cpu_possible_mask should be static, it cannot change as cpu's
1441 * are onlined, or offlined. The reason is per-cpu data-structures
1442 * are allocated by some modules at init time, and dont expect to
1443 * do this dynamically on cpu arrival/departure.
1444 * cpu_present_mask on the other hand can change dynamically.
1445 * In case when cpu_hotplug is not compiled, then we resort to current
1446 * behaviour, which is cpu_possible == cpu_present.
1449 * Three ways to find out the number of additional hotplug CPUs:
1450 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1451 * - The user can overwrite it with possible_cpus=NUM
1452 * - Otherwise don't reserve additional CPUs.
1453 * We do this because additional CPUs waste a lot of memory.
1456 __init void prefill_possible_map(void)
1460 /* No boot processor was found in mptable or ACPI MADT */
1461 if (!num_processors) {
1462 if (boot_cpu_has(X86_FEATURE_APIC)) {
1463 int apicid = boot_cpu_physical_apicid;
1464 int cpu = hard_smp_processor_id();
1466 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1468 /* Make sure boot cpu is enumerated */
1469 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1470 apic->apic_id_valid(apicid))
1471 generic_processor_info(apicid, boot_cpu_apic_version);
1474 if (!num_processors)
1478 i = setup_max_cpus ?: 1;
1479 if (setup_possible_cpus == -1) {
1480 possible = num_processors;
1481 #ifdef CONFIG_HOTPLUG_CPU
1483 possible += disabled_cpus;
1489 possible = setup_possible_cpus;
1491 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1493 /* nr_cpu_ids could be reduced via nr_cpus= */
1494 if (possible > nr_cpu_ids) {
1495 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1496 possible, nr_cpu_ids);
1497 possible = nr_cpu_ids;
1500 #ifdef CONFIG_HOTPLUG_CPU
1501 if (!setup_max_cpus)
1504 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1505 possible, setup_max_cpus);
1509 nr_cpu_ids = possible;
1511 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1512 possible, max_t(int, possible - num_processors, 0));
1514 reset_cpu_possible_mask();
1516 for (i = 0; i < possible; i++)
1517 set_cpu_possible(i, true);
1520 #ifdef CONFIG_HOTPLUG_CPU
1522 /* Recompute SMT state for all CPUs on offline */
1523 static void recompute_smt_state(void)
1525 int max_threads, cpu;
1528 for_each_online_cpu (cpu) {
1529 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1531 if (threads > max_threads)
1532 max_threads = threads;
1534 __max_smt_threads = max_threads;
1537 static void remove_siblinginfo(int cpu)
1540 struct cpuinfo_x86 *c = &cpu_data(cpu);
1542 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1543 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1545 * last thread sibling in this cpu core going down
1547 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1548 cpu_data(sibling).booted_cores--;
1551 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1552 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1553 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1554 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1555 cpumask_clear(cpu_llc_shared_mask(cpu));
1556 cpumask_clear(topology_sibling_cpumask(cpu));
1557 cpumask_clear(topology_core_cpumask(cpu));
1558 c->phys_proc_id = 0;
1560 c->booted_cores = 0;
1561 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1562 recompute_smt_state();
1565 static void remove_cpu_from_maps(int cpu)
1567 set_cpu_online(cpu, false);
1568 cpumask_clear_cpu(cpu, cpu_callout_mask);
1569 cpumask_clear_cpu(cpu, cpu_callin_mask);
1570 /* was set by cpu_init() */
1571 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1572 numa_remove_cpu(cpu);
1575 void cpu_disable_common(void)
1577 int cpu = smp_processor_id();
1579 remove_siblinginfo(cpu);
1581 /* It's now safe to remove this processor from the online map */
1583 remove_cpu_from_maps(cpu);
1584 unlock_vector_lock();
1588 int native_cpu_disable(void)
1592 ret = check_irq_vectors_for_cpu_disable();
1597 cpu_disable_common();
1602 int common_cpu_die(unsigned int cpu)
1606 /* We don't do anything here: idle task is faking death itself. */
1608 /* They ack this in play_dead() by setting CPU_DEAD */
1609 if (cpu_wait_death(cpu, 5)) {
1610 if (system_state == SYSTEM_RUNNING)
1611 pr_info("CPU %u is now offline\n", cpu);
1613 pr_err("CPU %u didn't die...\n", cpu);
1620 void native_cpu_die(unsigned int cpu)
1622 common_cpu_die(cpu);
1625 void play_dead_common(void)
1630 (void)cpu_report_death();
1633 * With physical CPU hotplug, we should halt the cpu
1635 local_irq_disable();
1638 static bool wakeup_cpu0(void)
1640 if (smp_processor_id() == 0 && enable_start_cpu0)
1647 * We need to flush the caches before going to sleep, lest we have
1648 * dirty data in our caches when we come back up.
1650 static inline void mwait_play_dead(void)
1652 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1653 unsigned int eax, ebx, ecx, edx;
1654 unsigned int highest_cstate = 0;
1655 unsigned int highest_subcstate = 0;
1658 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1660 if (!this_cpu_has(X86_FEATURE_MWAIT))
1662 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1664 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1667 eax = CPUID_MWAIT_LEAF;
1669 native_cpuid(&eax, &ebx, &ecx, &edx);
1672 * eax will be 0 if EDX enumeration is not valid.
1673 * Initialized below to cstate, sub_cstate value when EDX is valid.
1675 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1678 edx >>= MWAIT_SUBSTATE_SIZE;
1679 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1680 if (edx & MWAIT_SUBSTATE_MASK) {
1682 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1685 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1686 (highest_subcstate - 1);
1693 * The CLFLUSH is a workaround for erratum AAI65 for
1694 * the Xeon 7400 series. It's not clear it is actually
1695 * needed, but it should be harmless in either case.
1696 * The WBINVD is insufficient due to the spurious-wakeup
1697 * case where we return around the loop.
1702 __monitor(md, 0, 0);
1706 * If NMI wants to wake up CPU0, start CPU0.
1713 void hlt_play_dead(void)
1715 if (__this_cpu_read(cpu_info.x86) >= 4)
1721 * If NMI wants to wake up CPU0, start CPU0.
1728 void native_play_dead(void)
1731 tboot_shutdown(TB_SHUTDOWN_WFS);
1733 mwait_play_dead(); /* Only returns on failure */
1734 if (cpuidle_play_dead())
1738 #else /* ... !CONFIG_HOTPLUG_CPU */
1739 int native_cpu_disable(void)
1744 void native_cpu_die(unsigned int cpu)
1746 /* We said "no" in __cpu_disable */
1750 void native_play_dead(void)