2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
78 #include <asm/spec-ctrl.h>
80 /* Number of siblings per CPU package */
81 int smp_num_siblings = 1;
82 EXPORT_SYMBOL(smp_num_siblings);
84 /* Last level cache ID of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
87 /* representing HT siblings of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
91 /* representing HT and core siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
97 /* Per CPU bogomips and other parameters */
98 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
99 EXPORT_PER_CPU_SYMBOL(cpu_info);
101 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
105 spin_lock_irqsave(&rtc_lock, flags);
106 CMOS_WRITE(0xa, 0xf);
107 spin_unlock_irqrestore(&rtc_lock, flags);
108 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
110 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
114 static inline void smpboot_restore_warm_reset_vector(void)
119 * Paranoid: Set warm reset code and vector here back
122 spin_lock_irqsave(&rtc_lock, flags);
124 spin_unlock_irqrestore(&rtc_lock, flags);
126 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
130 * Report back to the Boot Processor during boot time or to the caller processor
133 static void smp_callin(void)
138 * If waken up by an INIT in an 82489DX configuration
139 * cpu_callout_mask guarantees we don't get here before
140 * an INIT_deassert IPI reaches our local APIC, so it is
141 * now safe to touch our local APIC.
143 cpuid = smp_processor_id();
146 * (This works even if the APIC is not enabled.)
148 phys_id = read_apic_id();
151 * the boot CPU has finished the init stage and is spinning
152 * on callin_map until we finish. We are free to set up this
153 * CPU, first the APIC. (this is probably redundant on most
159 * Save our processor parameters. Note: this information
160 * is needed for clock calibration.
162 smp_store_cpu_info(cpuid);
166 * Update loops_per_jiffy in cpu_data. Previous call to
167 * smp_store_cpu_info() stored a value that is close but not as
168 * accurate as the value just calculated.
171 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
172 pr_debug("Stack at about %p\n", &cpuid);
175 * This must be done before setting cpu_online_mask
176 * or calling notify_cpu_starting.
178 set_cpu_sibling_map(raw_smp_processor_id());
181 notify_cpu_starting(cpuid);
184 * Allow the master to continue.
186 cpumask_set_cpu(cpuid, cpu_callin_mask);
189 static int cpu0_logical_apicid;
190 static int enable_start_cpu0;
192 * Activate a secondary processor.
194 static void notrace start_secondary(void *unused)
197 * Don't put *anything* before cpu_init(), SMP booting is too
198 * fragile that we want to limit the things done here to the
199 * most necessary things.
202 x86_cpuinit.early_percpu_clock_init();
206 enable_start_cpu0 = 0;
209 /* switch away from the initial page table */
210 load_cr3(swapper_pg_dir);
214 /* otherwise gcc will move up smp_processor_id before the cpu_init */
217 * Check TSC synchronization with the BP:
219 check_tsc_sync_target();
221 speculative_store_bypass_ht_init();
224 * Lock vector_lock and initialize the vectors on this cpu
225 * before setting the cpu online. We must set it online with
226 * vector_lock held to prevent a concurrent setup/teardown
227 * from seeing a half valid vector space.
230 setup_vector_irq(smp_processor_id());
231 set_cpu_online(smp_processor_id(), true);
232 unlock_vector_lock();
233 cpu_set_state_online(smp_processor_id());
234 x86_platform.nmi_init();
236 /* enable local interrupts */
239 /* to prevent fake stack check failure in clock setup */
240 boot_init_stack_canary();
242 x86_cpuinit.setup_percpu_clockev();
245 cpu_startup_entry(CPUHP_ONLINE);
248 * Prevent tail call to cpu_startup_entry() because the stack protector
249 * guard has been changed a couple of function calls up, in
250 * boot_init_stack_canary() and must not be checked before tail calling
253 prevent_tail_call_optimization();
256 void __init smp_store_boot_cpu_info(void)
258 int id = 0; /* CPU 0 */
259 struct cpuinfo_x86 *c = &cpu_data(id);
266 * The bootstrap kernel entry code has set these up. Save them for
269 void smp_store_cpu_info(int id)
271 struct cpuinfo_x86 *c = &cpu_data(id);
276 * During boot time, CPU0 has this setup already. Save the info when
277 * bringing up AP or offlined CPU0.
279 identify_secondary_cpu(c);
283 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
285 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
287 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
291 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
293 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
295 return !WARN_ONCE(!topology_same_node(c, o),
296 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
297 "[node: %d != %d]. Ignoring dependency.\n",
298 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
301 #define link_mask(mfunc, c1, c2) \
303 cpumask_set_cpu((c1), mfunc(c2)); \
304 cpumask_set_cpu((c2), mfunc(c1)); \
307 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
309 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
310 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
312 if (c->phys_proc_id == o->phys_proc_id &&
313 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
314 c->compute_unit_id == o->compute_unit_id)
315 return topology_sane(c, o, "smt");
317 } else if (c->phys_proc_id == o->phys_proc_id &&
318 c->cpu_core_id == o->cpu_core_id) {
319 return topology_sane(c, o, "smt");
325 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
327 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
329 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
330 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
331 return topology_sane(c, o, "llc");
337 * Unlike the other levels, we do not enforce keeping a
338 * multicore group inside a NUMA node. If this happens, we will
339 * discard the MC level of the topology later.
341 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
343 if (c->phys_proc_id == o->phys_proc_id)
348 static struct sched_domain_topology_level numa_inside_package_topology[] = {
349 #ifdef CONFIG_SCHED_SMT
350 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
352 #ifdef CONFIG_SCHED_MC
353 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
358 * set_sched_topology() sets the topology internal to a CPU. The
359 * NUMA topologies are layered on top of it to build the full
362 * If NUMA nodes are observed to occur within a CPU package, this
363 * function should be called. It forces the sched domain code to
364 * only use the SMT level for the CPU portion of the topology.
365 * This essentially falls back to relying on NUMA information
366 * from the SRAT table to describe the entire system topology
367 * (except for hyperthreads).
369 static void primarily_use_numa_for_topology(void)
371 set_sched_topology(numa_inside_package_topology);
374 void set_cpu_sibling_map(int cpu)
376 bool has_smt = smp_num_siblings > 1;
377 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
378 struct cpuinfo_x86 *c = &cpu_data(cpu);
379 struct cpuinfo_x86 *o;
382 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
385 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
386 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
387 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
392 for_each_cpu(i, cpu_sibling_setup_mask) {
395 if ((i == cpu) || (has_smt && match_smt(c, o)))
396 link_mask(topology_sibling_cpumask, cpu, i);
398 if ((i == cpu) || (has_mp && match_llc(c, o)))
399 link_mask(cpu_llc_shared_mask, cpu, i);
404 * This needs a separate iteration over the cpus because we rely on all
405 * topology_sibling_cpumask links to be set-up.
407 for_each_cpu(i, cpu_sibling_setup_mask) {
410 if ((i == cpu) || (has_mp && match_die(c, o))) {
411 link_mask(topology_core_cpumask, cpu, i);
414 * Does this new cpu bringup a new core?
417 topology_sibling_cpumask(cpu)) == 1) {
419 * for each core in package, increment
420 * the booted_cores for this new cpu
423 topology_sibling_cpumask(i)) == i)
426 * increment the core count for all
427 * the other cpus in this package
430 cpu_data(i).booted_cores++;
431 } else if (i != cpu && !c->booted_cores)
432 c->booted_cores = cpu_data(i).booted_cores;
434 if (match_die(c, o) && !topology_same_node(c, o))
435 primarily_use_numa_for_topology();
439 /* maps the cpu to the sched domain representing multi-core */
440 const struct cpumask *cpu_coregroup_mask(int cpu)
442 return cpu_llc_shared_mask(cpu);
445 static void impress_friends(void)
448 unsigned long bogosum = 0;
450 * Allow the user to impress friends.
452 pr_debug("Before bogomips\n");
453 for_each_possible_cpu(cpu)
454 if (cpumask_test_cpu(cpu, cpu_callout_mask))
455 bogosum += cpu_data(cpu).loops_per_jiffy;
456 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
459 (bogosum/(5000/HZ))%100);
461 pr_debug("Before bogocount - setting activated=1\n");
464 void __inquire_remote_apic(int apicid)
466 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
467 const char * const names[] = { "ID", "VERSION", "SPIV" };
471 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
473 for (i = 0; i < ARRAY_SIZE(regs); i++) {
474 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
479 status = safe_apic_wait_icr_idle();
481 pr_cont("a previous APIC delivery may have failed\n");
483 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
488 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
489 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
492 case APIC_ICR_RR_VALID:
493 status = apic_read(APIC_RRR);
494 pr_cont("%08x\n", status);
503 * The Multiprocessor Specification 1.4 (1997) example code suggests
504 * that there should be a 10ms delay between the BSP asserting INIT
505 * and de-asserting INIT, when starting a remote processor.
506 * But that slows boot and resume on modern processors, which include
507 * many cores and don't require that delay.
509 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
510 * Modern processor families are quirked to remove the delay entirely.
512 #define UDELAY_10MS_DEFAULT 10000
514 static unsigned int init_udelay = UINT_MAX;
516 static int __init cpu_init_udelay(char *str)
518 get_option(&str, &init_udelay);
522 early_param("cpu_init_udelay", cpu_init_udelay);
524 static void __init smp_quirk_init_udelay(void)
526 /* if cmdline changed it from default, leave it alone */
527 if (init_udelay != UINT_MAX)
530 /* if modern processor, use no delay */
531 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
532 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
536 /* else, use legacy delay */
537 init_udelay = UDELAY_10MS_DEFAULT;
541 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
542 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
543 * won't ... remember to clear down the APIC, etc later.
546 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
548 unsigned long send_status, accept_status = 0;
552 /* Boot on the stack */
553 /* Kick the second */
554 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
556 pr_debug("Waiting for send to finish...\n");
557 send_status = safe_apic_wait_icr_idle();
560 * Give the other CPU some time to accept the IPI.
563 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
564 maxlvt = lapic_get_maxlvt();
565 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
566 apic_write(APIC_ESR, 0);
567 accept_status = (apic_read(APIC_ESR) & 0xEF);
569 pr_debug("NMI sent\n");
572 pr_err("APIC never delivered???\n");
574 pr_err("APIC delivery error (%lx)\n", accept_status);
576 return (send_status | accept_status);
580 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
582 unsigned long send_status = 0, accept_status = 0;
583 int maxlvt, num_starts, j;
585 maxlvt = lapic_get_maxlvt();
588 * Be paranoid about clearing APIC errors.
590 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
591 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
592 apic_write(APIC_ESR, 0);
596 pr_debug("Asserting INIT\n");
599 * Turn INIT on target chip
604 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
607 pr_debug("Waiting for send to finish...\n");
608 send_status = safe_apic_wait_icr_idle();
612 pr_debug("Deasserting INIT\n");
616 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
618 pr_debug("Waiting for send to finish...\n");
619 send_status = safe_apic_wait_icr_idle();
624 * Should we send STARTUP IPIs ?
626 * Determine this based on the APIC version.
627 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
629 if (APIC_INTEGRATED(apic_version[phys_apicid]))
635 * Paravirt / VMI wants a startup IPI hook here to set up the
636 * target processor state.
638 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
642 * Run STARTUP IPI loop.
644 pr_debug("#startup loops: %d\n", num_starts);
646 for (j = 1; j <= num_starts; j++) {
647 pr_debug("Sending STARTUP #%d\n", j);
648 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
649 apic_write(APIC_ESR, 0);
651 pr_debug("After apic_write\n");
658 /* Boot on the stack */
659 /* Kick the second */
660 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
664 * Give the other CPU some time to accept the IPI.
666 if (init_udelay == 0)
671 pr_debug("Startup point 1\n");
673 pr_debug("Waiting for send to finish...\n");
674 send_status = safe_apic_wait_icr_idle();
677 * Give the other CPU some time to accept the IPI.
679 if (init_udelay == 0)
684 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
685 apic_write(APIC_ESR, 0);
686 accept_status = (apic_read(APIC_ESR) & 0xEF);
687 if (send_status || accept_status)
690 pr_debug("After Startup\n");
693 pr_err("APIC never delivered???\n");
695 pr_err("APIC delivery error (%lx)\n", accept_status);
697 return (send_status | accept_status);
700 void smp_announce(void)
702 int num_nodes = num_online_nodes();
704 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
705 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
708 /* reduce the number of lines printed when booting a large cpu count system */
709 static void announce_cpu(int cpu, int apicid)
711 static int current_node = -1;
712 int node = early_cpu_to_node(cpu);
713 static int width, node_width;
716 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
719 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
722 printk(KERN_INFO "x86: Booting SMP configuration:\n");
724 if (system_state == SYSTEM_BOOTING) {
725 if (node != current_node) {
726 if (current_node > (-1))
730 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
731 node_width - num_digits(node), " ", node);
734 /* Add padding for the BSP */
736 pr_cont("%*s", width + 1, " ");
738 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
741 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
745 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
749 cpu = smp_processor_id();
750 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
757 * Wake up AP by INIT, INIT, STARTUP sequence.
759 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
760 * boot-strap code which is not a desired behavior for waking up BSP. To
761 * void the boot-strap code, wake up CPU0 by NMI instead.
763 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
764 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
765 * We'll change this code in the future to wake up hard offlined CPU0 if
766 * real platform and request are available.
769 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
770 int *cpu0_nmi_registered)
778 * Wake up AP by INIT, INIT, STARTUP sequence.
781 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
786 * Wake up BSP by nmi.
788 * Register a NMI handler to help wake up CPU0.
790 boot_error = register_nmi_handler(NMI_LOCAL,
791 wakeup_cpu0_nmi, 0, "wake_cpu0");
794 enable_start_cpu0 = 1;
795 *cpu0_nmi_registered = 1;
796 if (apic->dest_logical == APIC_DEST_LOGICAL)
797 id = cpu0_logical_apicid;
800 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
809 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
811 /* Just in case we booted with a single CPU. */
812 alternatives_enable_smp();
814 per_cpu(current_task, cpu) = idle;
817 /* Stack for startup_32 can be just as for start_secondary onwards */
819 per_cpu(cpu_current_top_of_stack, cpu) =
820 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
822 clear_tsk_thread_flag(idle, TIF_FORK);
823 initial_gs = per_cpu_offset(cpu);
828 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
829 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
830 * Returns zero if CPU booted OK, else error code from
831 * ->wakeup_secondary_cpu.
833 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
835 volatile u32 *trampoline_status =
836 (volatile u32 *) __va(real_mode_header->trampoline_status);
837 /* start_ip had better be page-aligned! */
838 unsigned long start_ip = real_mode_header->trampoline_start;
840 unsigned long boot_error = 0;
841 int cpu0_nmi_registered = 0;
842 unsigned long timeout;
844 idle->thread.sp = (unsigned long) (((struct pt_regs *)
845 (THREAD_SIZE + task_stack_page(idle))) - 1);
847 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
848 initial_code = (unsigned long)start_secondary;
849 stack_start = idle->thread.sp;
852 * Enable the espfix hack for this CPU
854 #ifdef CONFIG_X86_ESPFIX64
858 /* So we see what's up */
859 announce_cpu(cpu, apicid);
862 * This grunge runs the startup process for
863 * the targeted processor.
866 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
868 pr_debug("Setting warm reset code and vector.\n");
870 smpboot_setup_warm_reset_vector(start_ip);
872 * Be paranoid about clearing APIC errors.
874 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
875 apic_write(APIC_ESR, 0);
881 * AP might wait on cpu_callout_mask in cpu_init() with
882 * cpu_initialized_mask set if previous attempt to online
883 * it timed-out. Clear cpu_initialized_mask so that after
884 * INIT/SIPI it could start with a clean state.
886 cpumask_clear_cpu(cpu, cpu_initialized_mask);
890 * Wake up a CPU in difference cases:
891 * - Use the method in the APIC driver if it's defined
893 * - Use an INIT boot APIC message for APs or NMI for BSP.
895 if (apic->wakeup_secondary_cpu)
896 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
898 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
899 &cpu0_nmi_registered);
903 * Wait 10s total for first sign of life from AP
906 timeout = jiffies + 10*HZ;
907 while (time_before(jiffies, timeout)) {
908 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
910 * Tell AP to proceed with initialization
912 cpumask_set_cpu(cpu, cpu_callout_mask);
922 * Wait till AP completes initial initialization
924 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
926 * Allow other tasks to run while we wait for the
927 * AP to come online. This also gives a chance
928 * for the MTRR work(triggered by the AP coming online)
929 * to be completed in the stop machine context.
935 /* mark "stuck" area as not stuck */
936 *trampoline_status = 0;
938 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
940 * Cleanup possible dangling ends...
942 smpboot_restore_warm_reset_vector();
945 * Clean up the nmi handler. Do this after the callin and callout sync
946 * to avoid impact of possible long unregister time.
948 if (cpu0_nmi_registered)
949 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
954 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
956 int apicid = apic->cpu_present_to_apicid(cpu);
960 WARN_ON(irqs_disabled());
962 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
964 if (apicid == BAD_APICID ||
965 !physid_isset(apicid, phys_cpu_present_map) ||
966 !apic->apic_id_valid(apicid)) {
967 pr_err("%s: bad cpu %d\n", __func__, cpu);
972 * Already booted CPU?
974 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
975 pr_debug("do_boot_cpu %d Already started\n", cpu);
980 * Save current MTRR state in case it was changed since early boot
981 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
985 /* x86 CPUs take themselves offline, so delayed offline is OK. */
986 err = cpu_check_up_prepare(cpu);
987 if (err && err != -EBUSY)
990 /* the FPU context is blank, nobody can own it */
991 __cpu_disable_lazy_restore(cpu);
993 common_cpu_up(cpu, tidle);
996 * We have to walk the irq descriptors to setup the vector
997 * space for the cpu which comes online. Prevent irq
998 * alloc/free across the bringup.
1002 err = do_boot_cpu(apicid, cpu, tidle);
1005 irq_unlock_sparse();
1006 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1011 * Check TSC synchronization with the AP (keep irqs disabled
1014 local_irq_save(flags);
1015 check_tsc_sync_source(cpu);
1016 local_irq_restore(flags);
1018 while (!cpu_online(cpu)) {
1020 touch_nmi_watchdog();
1023 irq_unlock_sparse();
1029 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1031 void arch_disable_smp_support(void)
1033 disable_ioapic_support();
1037 * Fall back to non SMP mode after errors.
1039 * RED-PEN audit/test this more. I bet there is more state messed up here.
1041 static __init void disable_smp(void)
1043 pr_info("SMP disabled\n");
1045 disable_ioapic_support();
1047 init_cpu_present(cpumask_of(0));
1048 init_cpu_possible(cpumask_of(0));
1050 if (smp_found_config)
1051 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1053 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1054 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1055 cpumask_set_cpu(0, topology_core_cpumask(0));
1066 * Various sanity checks.
1068 static int __init smp_sanity_check(unsigned max_cpus)
1072 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1073 if (def_to_bigsmp && nr_cpu_ids > 8) {
1077 pr_warn("More than 8 CPUs detected - skipping them\n"
1078 "Use CONFIG_X86_BIGSMP\n");
1081 for_each_present_cpu(cpu) {
1083 set_cpu_present(cpu, false);
1088 for_each_possible_cpu(cpu) {
1090 set_cpu_possible(cpu, false);
1098 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1099 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1100 hard_smp_processor_id());
1102 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1106 * If we couldn't find an SMP configuration at boot time,
1107 * get out of here now!
1109 if (!smp_found_config && !acpi_lapic) {
1111 pr_notice("SMP motherboard not detected\n");
1112 return SMP_NO_CONFIG;
1116 * Should not be necessary because the MP table should list the boot
1117 * CPU too, but we do it for the sake of robustness anyway.
1119 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1120 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1121 boot_cpu_physical_apicid);
1122 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1127 * If we couldn't find a local APIC, then get out of here now!
1129 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1131 if (!disable_apic) {
1132 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1133 boot_cpu_physical_apicid);
1134 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1140 * If SMP should be disabled, then really disable it!
1143 pr_info("SMP mode deactivated\n");
1144 return SMP_FORCE_UP;
1150 static void __init smp_cpu_index_default(void)
1153 struct cpuinfo_x86 *c;
1155 for_each_possible_cpu(i) {
1157 /* mark all to hotplug */
1158 c->cpu_index = nr_cpu_ids;
1163 * Prepare for SMP bootup. The MP table or ACPI has been read
1164 * earlier. Just do some sanity checking here and enable APIC mode.
1166 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1170 smp_cpu_index_default();
1173 * Setup boot CPU information
1175 smp_store_boot_cpu_info(); /* Final full version of the data */
1176 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1179 current_thread_info()->cpu = 0; /* needed? */
1180 for_each_possible_cpu(i) {
1181 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1182 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1183 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1185 set_cpu_sibling_map(0);
1187 switch (smp_sanity_check(max_cpus)) {
1190 if (APIC_init_uniprocessor())
1191 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1198 apic_bsp_setup(false);
1204 default_setup_apic_routing();
1206 if (read_apic_id() != boot_cpu_physical_apicid) {
1207 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1208 read_apic_id(), boot_cpu_physical_apicid);
1209 /* Or can we switch back to PIC here? */
1212 cpu0_logical_apicid = apic_bsp_setup(false);
1214 pr_info("CPU%d: ", 0);
1215 print_cpu_info(&cpu_data(0));
1220 set_mtrr_aps_delayed_init();
1222 smp_quirk_init_udelay();
1224 speculative_store_bypass_ht_init();
1227 void arch_enable_nonboot_cpus_begin(void)
1229 set_mtrr_aps_delayed_init();
1232 void arch_enable_nonboot_cpus_end(void)
1238 * Early setup to make printk work.
1240 void __init native_smp_prepare_boot_cpu(void)
1242 int me = smp_processor_id();
1243 switch_to_new_gdt(me);
1244 /* already set me in cpu_online_mask in boot_cpu_init() */
1245 cpumask_set_cpu(me, cpu_callout_mask);
1246 cpu_set_state_online(me);
1249 void __init native_smp_cpus_done(unsigned int max_cpus)
1251 pr_debug("Boot done\n");
1255 setup_ioapic_dest();
1259 static int __initdata setup_possible_cpus = -1;
1260 static int __init _setup_possible_cpus(char *str)
1262 get_option(&str, &setup_possible_cpus);
1265 early_param("possible_cpus", _setup_possible_cpus);
1269 * cpu_possible_mask should be static, it cannot change as cpu's
1270 * are onlined, or offlined. The reason is per-cpu data-structures
1271 * are allocated by some modules at init time, and dont expect to
1272 * do this dynamically on cpu arrival/departure.
1273 * cpu_present_mask on the other hand can change dynamically.
1274 * In case when cpu_hotplug is not compiled, then we resort to current
1275 * behaviour, which is cpu_possible == cpu_present.
1278 * Three ways to find out the number of additional hotplug CPUs:
1279 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1280 * - The user can overwrite it with possible_cpus=NUM
1281 * - Otherwise don't reserve additional CPUs.
1282 * We do this because additional CPUs waste a lot of memory.
1285 __init void prefill_possible_map(void)
1289 /* no processor from mptable or madt */
1290 if (!num_processors)
1293 i = setup_max_cpus ?: 1;
1294 if (setup_possible_cpus == -1) {
1295 possible = num_processors;
1296 #ifdef CONFIG_HOTPLUG_CPU
1298 possible += disabled_cpus;
1304 possible = setup_possible_cpus;
1306 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1308 /* nr_cpu_ids could be reduced via nr_cpus= */
1309 if (possible > nr_cpu_ids) {
1310 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1311 possible, nr_cpu_ids);
1312 possible = nr_cpu_ids;
1315 #ifdef CONFIG_HOTPLUG_CPU
1316 if (!setup_max_cpus)
1319 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1320 possible, setup_max_cpus);
1324 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1325 possible, max_t(int, possible - num_processors, 0));
1327 for (i = 0; i < possible; i++)
1328 set_cpu_possible(i, true);
1329 for (; i < NR_CPUS; i++)
1330 set_cpu_possible(i, false);
1332 nr_cpu_ids = possible;
1335 #ifdef CONFIG_HOTPLUG_CPU
1337 static void remove_siblinginfo(int cpu)
1340 struct cpuinfo_x86 *c = &cpu_data(cpu);
1342 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1343 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1345 * last thread sibling in this cpu core going down
1347 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1348 cpu_data(sibling).booted_cores--;
1351 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1352 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1353 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1354 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1355 cpumask_clear(cpu_llc_shared_mask(cpu));
1356 cpumask_clear(topology_sibling_cpumask(cpu));
1357 cpumask_clear(topology_core_cpumask(cpu));
1358 c->phys_proc_id = 0;
1360 c->booted_cores = 0;
1361 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1364 static void remove_cpu_from_maps(int cpu)
1366 set_cpu_online(cpu, false);
1367 cpumask_clear_cpu(cpu, cpu_callout_mask);
1368 cpumask_clear_cpu(cpu, cpu_callin_mask);
1369 /* was set by cpu_init() */
1370 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1371 numa_remove_cpu(cpu);
1374 void cpu_disable_common(void)
1376 int cpu = smp_processor_id();
1378 remove_siblinginfo(cpu);
1380 /* It's now safe to remove this processor from the online map */
1382 remove_cpu_from_maps(cpu);
1383 unlock_vector_lock();
1387 int native_cpu_disable(void)
1391 ret = check_irq_vectors_for_cpu_disable();
1396 cpu_disable_common();
1401 int common_cpu_die(unsigned int cpu)
1405 /* We don't do anything here: idle task is faking death itself. */
1407 /* They ack this in play_dead() by setting CPU_DEAD */
1408 if (cpu_wait_death(cpu, 5)) {
1409 if (system_state == SYSTEM_RUNNING)
1410 pr_info("CPU %u is now offline\n", cpu);
1412 pr_err("CPU %u didn't die...\n", cpu);
1419 void native_cpu_die(unsigned int cpu)
1421 common_cpu_die(cpu);
1424 void play_dead_common(void)
1427 reset_lazy_tlbstate();
1428 amd_e400_remove_cpu(raw_smp_processor_id());
1431 (void)cpu_report_death();
1434 * With physical CPU hotplug, we should halt the cpu
1436 local_irq_disable();
1439 static bool wakeup_cpu0(void)
1441 if (smp_processor_id() == 0 && enable_start_cpu0)
1448 * We need to flush the caches before going to sleep, lest we have
1449 * dirty data in our caches when we come back up.
1451 static inline void mwait_play_dead(void)
1453 unsigned int eax, ebx, ecx, edx;
1454 unsigned int highest_cstate = 0;
1455 unsigned int highest_subcstate = 0;
1459 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1461 if (!this_cpu_has(X86_FEATURE_MWAIT))
1463 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1465 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1468 eax = CPUID_MWAIT_LEAF;
1470 native_cpuid(&eax, &ebx, &ecx, &edx);
1473 * eax will be 0 if EDX enumeration is not valid.
1474 * Initialized below to cstate, sub_cstate value when EDX is valid.
1476 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1479 edx >>= MWAIT_SUBSTATE_SIZE;
1480 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1481 if (edx & MWAIT_SUBSTATE_MASK) {
1483 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1486 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1487 (highest_subcstate - 1);
1491 * This should be a memory location in a cache line which is
1492 * unlikely to be touched by other processors. The actual
1493 * content is immaterial as it is not actually modified in any way.
1495 mwait_ptr = ¤t_thread_info()->flags;
1501 * The CLFLUSH is a workaround for erratum AAI65 for
1502 * the Xeon 7400 series. It's not clear it is actually
1503 * needed, but it should be harmless in either case.
1504 * The WBINVD is insufficient due to the spurious-wakeup
1505 * case where we return around the loop.
1510 __monitor(mwait_ptr, 0, 0);
1514 * If NMI wants to wake up CPU0, start CPU0.
1521 static inline void hlt_play_dead(void)
1523 if (__this_cpu_read(cpu_info.x86) >= 4)
1529 * If NMI wants to wake up CPU0, start CPU0.
1536 void native_play_dead(void)
1539 tboot_shutdown(TB_SHUTDOWN_WFS);
1541 mwait_play_dead(); /* Only returns on failure */
1542 if (cpuidle_play_dead())
1546 #else /* ... !CONFIG_HOTPLUG_CPU */
1547 int native_cpu_disable(void)
1552 void native_cpu_die(unsigned int cpu)
1554 /* We said "no" in __cpu_disable */
1558 void native_play_dead(void)