2 * Intel SMP support routines.
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
10 * This code is released under the GNU General Public License version 2 or
14 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/spinlock.h>
19 #include <linux/export.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/cache.h>
23 #include <linux/interrupt.h>
24 #include <linux/cpu.h>
25 #include <linux/gfp.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/proto.h>
34 #include <asm/trace/irq_vectors.h>
36 * Some notes on x86 processor bugs affecting SMP operation:
38 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
39 * The Linux implications for SMP are handled as follows:
41 * Pentium III / [Xeon]
42 * None of the E1AP-E3AP errata are visible to the user.
49 * None of the A1AP-A3AP errata are visible to the user.
56 * None of 1AP-9AP errata are visible to the normal user,
57 * except occasional delivery of 'spurious interrupt' as trap #15.
58 * This is very rare and a non-problem.
60 * 1AP. Linux maps APIC as non-cacheable
61 * 2AP. worked around in hardware
62 * 3AP. fixed in C0 and above steppings microcode update.
63 * Linux does not use excessive STARTUP_IPIs.
64 * 4AP. worked around in hardware
65 * 5AP. symmetric IO mode (normal Linux operation) not affected.
66 * 'noapic' mode has vector 0xf filled out properly.
67 * 6AP. 'noapic' mode might be affected - fixed in later steppings
68 * 7AP. We do not assume writes to the LVT deassering IRQs
69 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
70 * 9AP. We do not use mixed mode
73 * There is a marginal case where REP MOVS on 100MHz SMP
74 * machines with B stepping processors can fail. XXX should provide
75 * an L1cache=Writethrough or L1cache=off option.
77 * B stepping CPUs may hang. There are hardware work arounds
78 * for this. We warn about it in case your board doesn't have the work
79 * arounds. Basically that's so I can tell anyone with a B stepping
80 * CPU and SMP problems "tough".
82 * Specific items [From Pentium Processor Specification Update]
84 * 1AP. Linux doesn't use remote read
85 * 2AP. Linux doesn't trust APIC errors
86 * 3AP. We work around this
87 * 4AP. Linux never generated 3 interrupts of the same priority
88 * to cause a lost local interrupt.
89 * 5AP. Remote read is never used
90 * 6AP. not affected - worked around in hardware
91 * 7AP. not affected - worked around in hardware
92 * 8AP. worked around in hardware - we get explicit CS errors if not
93 * 9AP. only 'noapic' mode affected. Might generate spurious
94 * interrupts, we log only the first one and count the
96 * 10AP. not affected - worked around in hardware
97 * 11AP. Linux reads the APIC between writes to avoid this, as per
98 * the documentation. Make sure you preserve this as it affects
99 * the C stepping chips too.
100 * 12AP. not affected - worked around in hardware
101 * 13AP. not affected - worked around in hardware
102 * 14AP. we always deassert INIT during bootup
103 * 15AP. not affected - worked around in hardware
104 * 16AP. not affected - worked around in hardware
105 * 17AP. not affected - worked around in hardware
106 * 18AP. not affected - worked around in hardware
107 * 19AP. not affected - worked around in BIOS
109 * If this sounds worrying believe me these bugs are either ___RARE___,
110 * or are signal timing bugs worked around in hardware and there's
111 * about nothing of note with C stepping upwards.
114 static atomic_t stopping_cpu = ATOMIC_INIT(-1);
115 static bool smp_no_nmi_ipi = false;
118 * this function sends a 'reschedule' IPI to another CPU.
119 * it goes straight through and wastes no time serializing
120 * anything. Worst case is that we lose a reschedule ...
122 static void native_smp_send_reschedule(int cpu)
124 if (unlikely(cpu_is_offline(cpu))) {
128 apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
131 void native_send_call_func_single_ipi(int cpu)
133 apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
136 void native_send_call_func_ipi(const struct cpumask *mask)
138 cpumask_var_t allbutself;
140 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
141 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
145 cpumask_copy(allbutself, cpu_online_mask);
146 cpumask_clear_cpu(smp_processor_id(), allbutself);
148 if (cpumask_equal(mask, allbutself) &&
149 cpumask_equal(cpu_online_mask, cpu_callout_mask))
150 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
152 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
154 free_cpumask_var(allbutself);
157 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
159 /* We are registered on stopping cpu too, avoid spurious NMI */
160 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
169 * this function calls the 'stop' function on all other CPUs in the system.
172 asmlinkage __visible void smp_reboot_interrupt(void)
174 ipi_entering_ack_irq();
179 static int register_stop_handler(void)
181 return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
182 NMI_FLAG_FIRST, "smp_stop");
185 static void native_stop_other_cpus(int wait)
188 unsigned long timeout;
194 * Use an own vector here because smp_call_function
195 * does lots of things not suitable in a panic situation.
199 * We start by using the REBOOT_VECTOR irq.
200 * The irq is treated as a sync point to allow critical
201 * regions of code on other cpus to release their spin locks
202 * and re-enable irqs. Jumping straight to an NMI might
203 * accidentally cause deadlocks with further shutdown/panic
204 * code. By syncing, we give the cpus up to one second to
205 * finish their work before we force them off with the NMI.
207 if (num_online_cpus() > 1) {
208 /* did someone beat us here? */
209 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
212 /* sync above data before sending IRQ */
215 apic->send_IPI_allbutself(REBOOT_VECTOR);
218 * Don't wait longer than a second for IPI completion. The
219 * wait request is not checked here because that would
220 * prevent an NMI shutdown attempt in case that not all
221 * CPUs reach shutdown state.
223 timeout = USEC_PER_SEC;
224 while (num_online_cpus() > 1 && timeout--)
228 /* if the REBOOT_VECTOR didn't work, try with the NMI */
229 if (num_online_cpus() > 1) {
231 * If NMI IPI is enabled, try to register the stop handler
232 * and send the IPI. In any case try to wait for the other
235 if (!smp_no_nmi_ipi && !register_stop_handler()) {
236 /* Sync above data before sending IRQ */
239 pr_emerg("Shutting down cpus with NMI\n");
241 apic->send_IPI_allbutself(NMI_VECTOR);
244 * Don't wait longer than 10 ms if the caller didn't
245 * reqeust it. If wait is true, the machine hangs here if
246 * one or more CPUs do not reach shutdown state.
248 timeout = USEC_PER_MSEC * 10;
249 while (num_online_cpus() > 1 && (wait || timeout--))
253 local_irq_save(flags);
254 disable_local_APIC();
255 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
256 local_irq_restore(flags);
260 * Reschedule call back.
262 static inline void __smp_reschedule_interrupt(void)
264 inc_irq_stat(irq_resched_count);
268 __visible void smp_reschedule_interrupt(struct pt_regs *regs)
271 __smp_reschedule_interrupt();
273 * KVM uses this interrupt to force a cpu out of guest mode
277 __visible void smp_trace_reschedule_interrupt(struct pt_regs *regs)
280 * Need to call irq_enter() before calling the trace point.
281 * __smp_reschedule_interrupt() calls irq_enter/exit() too (in
282 * scheduler_ipi(). This is OK, since those functions are allowed
285 ipi_entering_ack_irq();
286 trace_reschedule_entry(RESCHEDULE_VECTOR);
287 __smp_reschedule_interrupt();
288 trace_reschedule_exit(RESCHEDULE_VECTOR);
291 * KVM uses this interrupt to force a cpu out of guest mode
295 static inline void __smp_call_function_interrupt(void)
297 generic_smp_call_function_interrupt();
298 inc_irq_stat(irq_call_count);
301 __visible void smp_call_function_interrupt(struct pt_regs *regs)
303 ipi_entering_ack_irq();
304 __smp_call_function_interrupt();
308 __visible void smp_trace_call_function_interrupt(struct pt_regs *regs)
310 ipi_entering_ack_irq();
311 trace_call_function_entry(CALL_FUNCTION_VECTOR);
312 __smp_call_function_interrupt();
313 trace_call_function_exit(CALL_FUNCTION_VECTOR);
317 static inline void __smp_call_function_single_interrupt(void)
319 generic_smp_call_function_single_interrupt();
320 inc_irq_stat(irq_call_count);
323 __visible void smp_call_function_single_interrupt(struct pt_regs *regs)
325 ipi_entering_ack_irq();
326 __smp_call_function_single_interrupt();
330 __visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs)
332 ipi_entering_ack_irq();
333 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
334 __smp_call_function_single_interrupt();
335 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
339 static int __init nonmi_ipi_setup(char *str)
341 smp_no_nmi_ipi = true;
345 __setup("nonmi_ipi", nonmi_ipi_setup);
347 struct smp_ops smp_ops = {
348 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
349 .smp_prepare_cpus = native_smp_prepare_cpus,
350 .smp_cpus_done = native_smp_cpus_done,
352 .stop_other_cpus = native_stop_other_cpus,
353 .smp_send_reschedule = native_smp_send_reschedule,
355 .cpu_up = native_cpu_up,
356 .cpu_die = native_cpu_die,
357 .cpu_disable = native_cpu_disable,
358 .play_dead = native_play_dead,
360 .send_call_func_ipi = native_send_call_func_ipi,
361 .send_call_func_single_ipi = native_send_call_func_single_ipi,
363 EXPORT_SYMBOL_GPL(smp_ops);