1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/internal.h>
34 #include <asm/debugreg.h>
36 #include <asm/tlbflush.h>
39 #include <asm/switch_to.h>
41 #include <asm/prctl.h>
42 #include <asm/spec-ctrl.h>
43 #include <asm/io_bitmap.h>
44 #include <asm/proto.h>
45 #include <asm/frame.h>
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
67 .sp1 = TOP_OF_INIT_STACK,
72 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
75 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
77 DEFINE_PER_CPU(bool, __tss_limit_invalid);
78 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
81 * this gets called so that we can store lazy state into memory and copy the
82 * current task into the new thread.
84 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
86 memcpy(dst, src, arch_task_struct_size);
88 dst->thread.vm86 = NULL;
90 return fpu_clone(dst);
94 * Free thread data structures etc..
96 void exit_thread(struct task_struct *tsk)
98 struct thread_struct *t = &tsk->thread;
99 struct fpu *fpu = &t->fpu;
101 if (test_thread_flag(TIF_IO_BITMAP))
109 static int set_new_tls(struct task_struct *p, unsigned long tls)
111 struct user_desc __user *utls = (struct user_desc __user *)tls;
113 if (in_ia32_syscall())
114 return do_set_thread_area(p, -1, utls, 0);
116 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
119 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
120 struct task_struct *p, unsigned long tls)
122 struct inactive_task_frame *frame;
123 struct fork_frame *fork_frame;
124 struct pt_regs *childregs;
127 childregs = task_pt_regs(p);
128 fork_frame = container_of(childregs, struct fork_frame, regs);
129 frame = &fork_frame->frame;
131 frame->bp = encode_frame_pointer(childregs);
132 frame->ret_addr = (unsigned long) ret_from_fork;
133 p->thread.sp = (unsigned long) fork_frame;
134 p->thread.io_bitmap = NULL;
135 p->thread.iopl_warn = 0;
136 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
140 p->thread.fsindex = current->thread.fsindex;
141 p->thread.fsbase = current->thread.fsbase;
142 p->thread.gsindex = current->thread.gsindex;
143 p->thread.gsbase = current->thread.gsbase;
145 savesegment(es, p->thread.es);
146 savesegment(ds, p->thread.ds);
148 p->thread.sp0 = (unsigned long) (childregs + 1);
150 * Clear all status flags including IF and set fixed bit. 64bit
151 * does not have this initialization as the frame does not contain
152 * flags. The flags consistency (especially vs. AC) is there
153 * ensured via objtool, which lacks 32bit support.
155 frame->flags = X86_EFLAGS_FIXED;
158 /* Kernel thread ? */
159 if (unlikely(p->flags & PF_KTHREAD)) {
160 p->thread.pkru = pkru_get_init_value();
161 memset(childregs, 0, sizeof(struct pt_regs));
162 kthread_frame_init(frame, sp, arg);
167 * Clone current's PKRU value from hardware. tsk->thread.pkru
168 * is only valid when scheduled out.
170 p->thread.pkru = read_pkru();
173 *childregs = *current_pt_regs();
179 task_user_gs(p) = get_user_gs(current_pt_regs());
182 if (unlikely(p->flags & PF_IO_WORKER)) {
184 * An IO thread is a user space thread, but it doesn't
185 * return to ret_after_fork().
187 * In order to indicate that to tools like gdb,
188 * we reset the stack and instruction pointers.
190 * It does the same kernel frame setup to return to a kernel
191 * function that a kernel thread does.
195 kthread_frame_init(frame, sp, arg);
199 /* Set a new TLS for the child thread? */
200 if (clone_flags & CLONE_SETTLS)
201 ret = set_new_tls(p, tls);
203 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
209 static void pkru_flush_thread(void)
212 * If PKRU is enabled the default PKRU value has to be loaded into
213 * the hardware right here (similar to context switch).
215 pkru_write_default();
218 void flush_thread(void)
220 struct task_struct *tsk = current;
222 flush_ptrace_hw_breakpoint(tsk);
223 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
229 void disable_TSC(void)
232 if (!test_and_set_thread_flag(TIF_NOTSC))
234 * Must flip the CPU state synchronously with
235 * TIF_NOTSC in the current running context.
237 cr4_set_bits(X86_CR4_TSD);
241 static void enable_TSC(void)
244 if (test_and_clear_thread_flag(TIF_NOTSC))
246 * Must flip the CPU state synchronously with
247 * TIF_NOTSC in the current running context.
249 cr4_clear_bits(X86_CR4_TSD);
253 int get_tsc_mode(unsigned long adr)
257 if (test_thread_flag(TIF_NOTSC))
258 val = PR_TSC_SIGSEGV;
262 return put_user(val, (unsigned int __user *)adr);
265 int set_tsc_mode(unsigned int val)
267 if (val == PR_TSC_SIGSEGV)
269 else if (val == PR_TSC_ENABLE)
277 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
279 static void set_cpuid_faulting(bool on)
283 msrval = this_cpu_read(msr_misc_features_shadow);
284 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
285 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
286 this_cpu_write(msr_misc_features_shadow, msrval);
287 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
290 static void disable_cpuid(void)
293 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
295 * Must flip the CPU state synchronously with
296 * TIF_NOCPUID in the current running context.
298 set_cpuid_faulting(true);
303 static void enable_cpuid(void)
306 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
308 * Must flip the CPU state synchronously with
309 * TIF_NOCPUID in the current running context.
311 set_cpuid_faulting(false);
316 static int get_cpuid_mode(void)
318 return !test_thread_flag(TIF_NOCPUID);
321 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
323 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
335 * Called immediately after a successful exec.
337 void arch_setup_new_exec(void)
339 /* If cpuid was previously disabled for this task, re-enable it. */
340 if (test_thread_flag(TIF_NOCPUID))
344 * Don't inherit TIF_SSBD across exec boundary when
345 * PR_SPEC_DISABLE_NOEXEC is used.
347 if (test_thread_flag(TIF_SSBD) &&
348 task_spec_ssb_noexec(current)) {
349 clear_thread_flag(TIF_SSBD);
350 task_clear_spec_ssb_disable(current);
351 task_clear_spec_ssb_noexec(current);
352 speculation_ctrl_update(task_thread_info(current)->flags);
356 #ifdef CONFIG_X86_IOPL_IOPERM
357 static inline void switch_to_bitmap(unsigned long tifp)
360 * Invalidate I/O bitmap if the previous task used it. This prevents
361 * any possible leakage of an active I/O bitmap.
363 * If the next task has an I/O bitmap it will handle it on exit to
366 if (tifp & _TIF_IO_BITMAP)
367 tss_invalidate_io_bitmap();
370 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
373 * Copy at least the byte range of the incoming tasks bitmap which
374 * covers the permitted I/O ports.
376 * If the previous task which used an I/O bitmap had more bits
377 * permitted, then the copy needs to cover those as well so they
380 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
381 max(tss->io_bitmap.prev_max, iobm->max));
384 * Store the new max and the sequence number of this bitmap
385 * and a pointer to the bitmap itself.
387 tss->io_bitmap.prev_max = iobm->max;
388 tss->io_bitmap.prev_sequence = iobm->sequence;
392 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
394 void native_tss_update_io_bitmap(void)
396 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
397 struct thread_struct *t = ¤t->thread;
398 u16 *base = &tss->x86_tss.io_bitmap_base;
400 if (!test_thread_flag(TIF_IO_BITMAP)) {
401 native_tss_invalidate_io_bitmap();
405 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
406 *base = IO_BITMAP_OFFSET_VALID_ALL;
408 struct io_bitmap *iobm = t->io_bitmap;
411 * Only copy bitmap data when the sequence number differs. The
412 * update time is accounted to the incoming task.
414 if (tss->io_bitmap.prev_sequence != iobm->sequence)
415 tss_copy_io_bitmap(tss, iobm);
417 /* Enable the bitmap */
418 *base = IO_BITMAP_OFFSET_VALID_MAP;
422 * Make sure that the TSS limit is covering the IO bitmap. It might have
423 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
424 * access from user space to trigger a #GP because tbe bitmap is outside
429 #else /* CONFIG_X86_IOPL_IOPERM */
430 static inline void switch_to_bitmap(unsigned long tifp) { }
436 struct ssb_state *shared_state;
438 unsigned int disable_state;
439 unsigned long local_state;
444 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
446 void speculative_store_bypass_ht_init(void)
448 struct ssb_state *st = this_cpu_ptr(&ssb_state);
449 unsigned int this_cpu = smp_processor_id();
455 * Shared state setup happens once on the first bringup
456 * of the CPU. It's not destroyed on CPU hotunplug.
458 if (st->shared_state)
461 raw_spin_lock_init(&st->lock);
464 * Go over HT siblings and check whether one of them has set up the
465 * shared state pointer already.
467 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
471 if (!per_cpu(ssb_state, cpu).shared_state)
474 /* Link it to the state of the sibling: */
475 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
480 * First HT sibling to come up on the core. Link shared state of
481 * the first HT sibling to itself. The siblings on the same core
482 * which come up later will see the shared state pointer and link
483 * themselves to the state of this CPU.
485 st->shared_state = st;
489 * Logic is: First HT sibling enables SSBD for both siblings in the core
490 * and last sibling to disable it, disables it for the whole core. This how
491 * MSR_SPEC_CTRL works in "hardware":
493 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
495 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
497 struct ssb_state *st = this_cpu_ptr(&ssb_state);
498 u64 msr = x86_amd_ls_cfg_base;
500 if (!static_cpu_has(X86_FEATURE_ZEN)) {
501 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
502 wrmsrl(MSR_AMD64_LS_CFG, msr);
506 if (tifn & _TIF_SSBD) {
508 * Since this can race with prctl(), block reentry on the
511 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
514 msr |= x86_amd_ls_cfg_ssbd_mask;
516 raw_spin_lock(&st->shared_state->lock);
517 /* First sibling enables SSBD: */
518 if (!st->shared_state->disable_state)
519 wrmsrl(MSR_AMD64_LS_CFG, msr);
520 st->shared_state->disable_state++;
521 raw_spin_unlock(&st->shared_state->lock);
523 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
526 raw_spin_lock(&st->shared_state->lock);
527 st->shared_state->disable_state--;
528 if (!st->shared_state->disable_state)
529 wrmsrl(MSR_AMD64_LS_CFG, msr);
530 raw_spin_unlock(&st->shared_state->lock);
534 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
536 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
538 wrmsrl(MSR_AMD64_LS_CFG, msr);
542 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
545 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
546 * so ssbd_tif_to_spec_ctrl() just works.
548 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
552 * Update the MSRs managing speculation control, during context switch.
554 * tifp: Previous task's thread flags
555 * tifn: Next task's thread flags
557 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
560 unsigned long tif_diff = tifp ^ tifn;
561 u64 msr = x86_spec_ctrl_base;
564 lockdep_assert_irqs_disabled();
566 /* Handle change of TIF_SSBD depending on the mitigation method. */
567 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
568 if (tif_diff & _TIF_SSBD)
569 amd_set_ssb_virt_state(tifn);
570 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
571 if (tif_diff & _TIF_SSBD)
572 amd_set_core_ssb_state(tifn);
573 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
574 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
575 updmsr |= !!(tif_diff & _TIF_SSBD);
576 msr |= ssbd_tif_to_spec_ctrl(tifn);
579 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
580 if (IS_ENABLED(CONFIG_SMP) &&
581 static_branch_unlikely(&switch_to_cond_stibp)) {
582 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
583 msr |= stibp_tif_to_spec_ctrl(tifn);
587 update_spec_ctrl_cond(msr);
590 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
592 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
593 if (task_spec_ssb_disable(tsk))
594 set_tsk_thread_flag(tsk, TIF_SSBD);
596 clear_tsk_thread_flag(tsk, TIF_SSBD);
598 if (task_spec_ib_disable(tsk))
599 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
601 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
603 /* Return the updated threadinfo flags*/
604 return task_thread_info(tsk)->flags;
607 void speculation_ctrl_update(unsigned long tif)
611 /* Forced update. Make sure all relevant TIF flags are different */
612 local_irq_save(flags);
613 __speculation_ctrl_update(~tif, tif);
614 local_irq_restore(flags);
617 /* Called from seccomp/prctl update */
618 void speculation_ctrl_update_current(void)
621 speculation_ctrl_update(speculation_ctrl_update_tif(current));
625 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
627 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
631 this_cpu_write(cpu_tlbstate.cr4, newval);
636 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
638 unsigned long tifp, tifn;
640 tifn = READ_ONCE(task_thread_info(next_p)->flags);
641 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
643 switch_to_bitmap(tifp);
645 propagate_user_return_notify(prev_p, next_p);
647 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
648 arch_has_block_step()) {
649 unsigned long debugctl, msk;
651 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
652 debugctl &= ~DEBUGCTLMSR_BTF;
653 msk = tifn & _TIF_BLOCKSTEP;
654 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
655 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
658 if ((tifp ^ tifn) & _TIF_NOTSC)
659 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
661 if ((tifp ^ tifn) & _TIF_NOCPUID)
662 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
664 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
665 __speculation_ctrl_update(tifp, tifn);
667 speculation_ctrl_update_tif(prev_p);
668 tifn = speculation_ctrl_update_tif(next_p);
670 /* Enforce MSR update to ensure consistent state */
671 __speculation_ctrl_update(~tifn, tifn);
674 if ((tifp ^ tifn) & _TIF_SLD)
679 * Idle related variables and functions
681 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
682 EXPORT_SYMBOL(boot_option_idle_override);
684 static void (*x86_idle)(void);
687 static inline void play_dead(void)
693 void arch_cpu_idle_enter(void)
695 tsc_verify_tsc_adjust(false);
699 void arch_cpu_idle_dead(void)
705 * Called from the generic idle code.
707 void arch_cpu_idle(void)
713 * We use this if we don't have any better idle routine..
715 void __cpuidle default_idle(void)
719 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
720 EXPORT_SYMBOL(default_idle);
724 bool xen_set_default_idle(void)
726 bool ret = !!x86_idle;
728 x86_idle = default_idle;
734 void __noreturn stop_this_cpu(void *dummy)
740 set_cpu_online(smp_processor_id(), false);
741 disable_local_APIC();
742 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
745 * Use wbinvd on processors that support SME. This provides support
746 * for performing a successful kexec when going from SME inactive
747 * to SME active (or vice-versa). The cache must be cleared so that
748 * if there are entries with the same physical address, both with and
749 * without the encryption bit, they don't race each other when flushed
750 * and potentially end up with the wrong entry being committed to
753 if (boot_cpu_has(X86_FEATURE_SME))
757 * Use native_halt() so that memory contents don't change
758 * (stack usage and variables) after possibly issuing the
759 * native_wbinvd() above.
766 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
767 * states (local apic timer and TSC stop).
769 * XXX this function is completely buggered vs RCU and tracing.
771 static void amd_e400_idle(void)
774 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
775 * gets set after static_cpu_has() places have been converted via
778 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
783 tick_broadcast_enter();
788 * The switch back from broadcast mode needs to be called with
789 * interrupts disabled.
791 raw_local_irq_disable();
792 tick_broadcast_exit();
793 raw_local_irq_enable();
797 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
798 * We can't rely on cpuidle installing MWAIT, because it will not load
799 * on systems that support only C1 -- so the boot default must be MWAIT.
801 * Some AMD machines are the opposite, they depend on using HALT.
803 * So for default C1, which is used during boot until cpuidle loads,
804 * use MWAIT-C1 on Intel HW that has it, else use HALT.
806 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
808 /* User has disallowed the use of MWAIT. Fallback to HALT */
809 if (boot_option_idle_override == IDLE_NOMWAIT)
812 if (c->x86_vendor != X86_VENDOR_INTEL)
815 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
822 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
823 * with interrupts enabled and no flags, which is backwards compatible with the
824 * original MWAIT implementation.
826 static __cpuidle void mwait_idle(void)
828 if (!current_set_polling_and_test()) {
829 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
831 clflush((void *)¤t_thread_info()->flags);
835 __monitor((void *)¤t_thread_info()->flags, 0, 0);
839 raw_local_irq_enable();
841 raw_local_irq_enable();
843 __current_clr_polling();
846 void select_idle_routine(const struct cpuinfo_x86 *c)
849 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
850 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
852 if (x86_idle || boot_option_idle_override == IDLE_POLL)
855 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
856 pr_info("using AMD E400 aware idle routine\n");
857 x86_idle = amd_e400_idle;
858 } else if (prefer_mwait_c1_over_halt(c)) {
859 pr_info("using mwait in idle threads\n");
860 x86_idle = mwait_idle;
862 x86_idle = default_idle;
865 void amd_e400_c1e_apic_setup(void)
867 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
868 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
870 tick_broadcast_force();
875 void __init arch_post_acpi_subsys_init(void)
879 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
883 * AMD E400 detection needs to happen after ACPI has been enabled. If
884 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
885 * MSR_K8_INT_PENDING_MSG.
887 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
888 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
891 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
893 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
894 mark_tsc_unstable("TSC halt in AMD C1E");
895 pr_info("System has AMD C1E enabled\n");
898 static int __init idle_setup(char *str)
903 if (!strcmp(str, "poll")) {
904 pr_info("using polling idle threads\n");
905 boot_option_idle_override = IDLE_POLL;
906 cpu_idle_poll_ctrl(true);
907 } else if (!strcmp(str, "halt")) {
909 * When the boot option of idle=halt is added, halt is
910 * forced to be used for CPU idle. In such case CPU C2/C3
911 * won't be used again.
912 * To continue to load the CPU idle driver, don't touch
913 * the boot_option_idle_override.
915 x86_idle = default_idle;
916 boot_option_idle_override = IDLE_HALT;
917 } else if (!strcmp(str, "nomwait")) {
919 * If the boot option of "idle=nomwait" is added,
920 * it means that mwait will be disabled for CPU C1/C2/C3
923 boot_option_idle_override = IDLE_NOMWAIT;
929 early_param("idle", idle_setup);
931 unsigned long arch_align_stack(unsigned long sp)
933 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
934 sp -= get_random_int() % 8192;
938 unsigned long arch_randomize_brk(struct mm_struct *mm)
940 return randomize_page(mm->brk, 0x02000000);
944 * Called from fs/proc with a reference on @p to find the function
945 * which called into schedule(). This needs to be done carefully
946 * because the task might wake up and we might look at a stack
949 unsigned long get_wchan(struct task_struct *p)
951 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
954 if (p == current || task_is_running(p))
957 if (!try_get_task_stack(p))
960 start = (unsigned long)task_stack_page(p);
965 * Layout of the stack page:
967 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
969 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
971 * ----------- bottom = start
973 * The tasks stack pointer points at the location where the
974 * framepointer is stored. The data on the stack is:
975 * ... IP FP ... IP FP
977 * We need to read FP and IP, so we need to adjust the upper
978 * bound by another unsigned long.
980 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
981 top -= 2 * sizeof(unsigned long);
984 sp = READ_ONCE(p->thread.sp);
985 if (sp < bottom || sp > top)
988 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
990 if (fp < bottom || fp > top)
992 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
993 if (!in_sched_functions(ip)) {
997 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
998 } while (count++ < 16 && !task_is_running(p));
1005 long do_arch_prctl_common(struct task_struct *task, int option,
1006 unsigned long cpuid_enabled)
1009 case ARCH_GET_CPUID:
1010 return get_cpuid_mode();
1011 case ARCH_SET_CPUID:
1012 return set_cpuid_mode(task, cpuid_enabled);