1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/internal.h>
34 #include <asm/debugreg.h>
36 #include <asm/tlbflush.h>
39 #include <asm/switch_to.h>
41 #include <asm/prctl.h>
42 #include <asm/spec-ctrl.h>
43 #include <asm/io_bitmap.h>
44 #include <asm/proto.h>
45 #include <asm/frame.h>
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
67 * .sp1 is cpu_current_top_of_stack. The init task never
68 * runs user code, but cpu_current_top_of_stack should still
69 * be well defined before the first context switch.
71 .sp1 = TOP_OF_INIT_STACK,
77 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
80 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
82 DEFINE_PER_CPU(bool, __tss_limit_invalid);
83 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
86 * this gets called so that we can store lazy state into memory and copy the
87 * current task into the new thread.
89 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
91 memcpy(dst, src, arch_task_struct_size);
93 dst->thread.vm86 = NULL;
96 return fpu__copy(dst, src);
100 * Free thread data structures etc..
102 void exit_thread(struct task_struct *tsk)
104 struct thread_struct *t = &tsk->thread;
105 struct fpu *fpu = &t->fpu;
107 if (test_thread_flag(TIF_IO_BITMAP))
115 static int set_new_tls(struct task_struct *p, unsigned long tls)
117 struct user_desc __user *utls = (struct user_desc __user *)tls;
119 if (in_ia32_syscall())
120 return do_set_thread_area(p, -1, utls, 0);
122 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
125 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
126 struct task_struct *p, unsigned long tls)
128 struct inactive_task_frame *frame;
129 struct fork_frame *fork_frame;
130 struct pt_regs *childregs;
133 childregs = task_pt_regs(p);
134 fork_frame = container_of(childregs, struct fork_frame, regs);
135 frame = &fork_frame->frame;
137 frame->bp = encode_frame_pointer(childregs);
138 frame->ret_addr = (unsigned long) ret_from_fork;
139 p->thread.sp = (unsigned long) fork_frame;
140 p->thread.io_bitmap = NULL;
141 p->thread.iopl_warn = 0;
142 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
146 p->thread.fsindex = current->thread.fsindex;
147 p->thread.fsbase = current->thread.fsbase;
148 p->thread.gsindex = current->thread.gsindex;
149 p->thread.gsbase = current->thread.gsbase;
151 savesegment(es, p->thread.es);
152 savesegment(ds, p->thread.ds);
154 p->thread.sp0 = (unsigned long) (childregs + 1);
156 * Clear all status flags including IF and set fixed bit. 64bit
157 * does not have this initialization as the frame does not contain
158 * flags. The flags consistency (especially vs. AC) is there
159 * ensured via objtool, which lacks 32bit support.
161 frame->flags = X86_EFLAGS_FIXED;
164 /* Kernel thread ? */
165 if (unlikely(p->flags & PF_KTHREAD)) {
166 memset(childregs, 0, sizeof(struct pt_regs));
167 kthread_frame_init(frame, sp, arg);
172 *childregs = *current_pt_regs();
178 task_user_gs(p) = get_user_gs(current_pt_regs());
181 if (unlikely(p->flags & PF_IO_WORKER)) {
183 * An IO thread is a user space thread, but it doesn't
184 * return to ret_after_fork().
186 * In order to indicate that to tools like gdb,
187 * we reset the stack and instruction pointers.
189 * It does the same kernel frame setup to return to a kernel
190 * function that a kernel thread does.
194 kthread_frame_init(frame, sp, arg);
198 /* Set a new TLS for the child thread? */
199 if (clone_flags & CLONE_SETTLS)
200 ret = set_new_tls(p, tls);
202 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
208 void flush_thread(void)
210 struct task_struct *tsk = current;
212 flush_ptrace_hw_breakpoint(tsk);
213 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
215 fpu__clear_all(&tsk->thread.fpu);
218 void disable_TSC(void)
221 if (!test_and_set_thread_flag(TIF_NOTSC))
223 * Must flip the CPU state synchronously with
224 * TIF_NOTSC in the current running context.
226 cr4_set_bits(X86_CR4_TSD);
230 static void enable_TSC(void)
233 if (test_and_clear_thread_flag(TIF_NOTSC))
235 * Must flip the CPU state synchronously with
236 * TIF_NOTSC in the current running context.
238 cr4_clear_bits(X86_CR4_TSD);
242 int get_tsc_mode(unsigned long adr)
246 if (test_thread_flag(TIF_NOTSC))
247 val = PR_TSC_SIGSEGV;
251 return put_user(val, (unsigned int __user *)adr);
254 int set_tsc_mode(unsigned int val)
256 if (val == PR_TSC_SIGSEGV)
258 else if (val == PR_TSC_ENABLE)
266 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
268 static void set_cpuid_faulting(bool on)
272 msrval = this_cpu_read(msr_misc_features_shadow);
273 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
274 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
275 this_cpu_write(msr_misc_features_shadow, msrval);
276 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
279 static void disable_cpuid(void)
282 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
284 * Must flip the CPU state synchronously with
285 * TIF_NOCPUID in the current running context.
287 set_cpuid_faulting(true);
292 static void enable_cpuid(void)
295 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
297 * Must flip the CPU state synchronously with
298 * TIF_NOCPUID in the current running context.
300 set_cpuid_faulting(false);
305 static int get_cpuid_mode(void)
307 return !test_thread_flag(TIF_NOCPUID);
310 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
312 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
324 * Called immediately after a successful exec.
326 void arch_setup_new_exec(void)
328 /* If cpuid was previously disabled for this task, re-enable it. */
329 if (test_thread_flag(TIF_NOCPUID))
333 * Don't inherit TIF_SSBD across exec boundary when
334 * PR_SPEC_DISABLE_NOEXEC is used.
336 if (test_thread_flag(TIF_SSBD) &&
337 task_spec_ssb_noexec(current)) {
338 clear_thread_flag(TIF_SSBD);
339 task_clear_spec_ssb_disable(current);
340 task_clear_spec_ssb_noexec(current);
341 speculation_ctrl_update(task_thread_info(current)->flags);
345 #ifdef CONFIG_X86_IOPL_IOPERM
346 static inline void switch_to_bitmap(unsigned long tifp)
349 * Invalidate I/O bitmap if the previous task used it. This prevents
350 * any possible leakage of an active I/O bitmap.
352 * If the next task has an I/O bitmap it will handle it on exit to
355 if (tifp & _TIF_IO_BITMAP)
356 tss_invalidate_io_bitmap();
359 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
362 * Copy at least the byte range of the incoming tasks bitmap which
363 * covers the permitted I/O ports.
365 * If the previous task which used an I/O bitmap had more bits
366 * permitted, then the copy needs to cover those as well so they
369 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
370 max(tss->io_bitmap.prev_max, iobm->max));
373 * Store the new max and the sequence number of this bitmap
374 * and a pointer to the bitmap itself.
376 tss->io_bitmap.prev_max = iobm->max;
377 tss->io_bitmap.prev_sequence = iobm->sequence;
381 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
383 void native_tss_update_io_bitmap(void)
385 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
386 struct thread_struct *t = ¤t->thread;
387 u16 *base = &tss->x86_tss.io_bitmap_base;
389 if (!test_thread_flag(TIF_IO_BITMAP)) {
390 native_tss_invalidate_io_bitmap();
394 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
395 *base = IO_BITMAP_OFFSET_VALID_ALL;
397 struct io_bitmap *iobm = t->io_bitmap;
400 * Only copy bitmap data when the sequence number differs. The
401 * update time is accounted to the incoming task.
403 if (tss->io_bitmap.prev_sequence != iobm->sequence)
404 tss_copy_io_bitmap(tss, iobm);
406 /* Enable the bitmap */
407 *base = IO_BITMAP_OFFSET_VALID_MAP;
411 * Make sure that the TSS limit is covering the IO bitmap. It might have
412 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
413 * access from user space to trigger a #GP because tbe bitmap is outside
418 #else /* CONFIG_X86_IOPL_IOPERM */
419 static inline void switch_to_bitmap(unsigned long tifp) { }
425 struct ssb_state *shared_state;
427 unsigned int disable_state;
428 unsigned long local_state;
433 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
435 void speculative_store_bypass_ht_init(void)
437 struct ssb_state *st = this_cpu_ptr(&ssb_state);
438 unsigned int this_cpu = smp_processor_id();
444 * Shared state setup happens once on the first bringup
445 * of the CPU. It's not destroyed on CPU hotunplug.
447 if (st->shared_state)
450 raw_spin_lock_init(&st->lock);
453 * Go over HT siblings and check whether one of them has set up the
454 * shared state pointer already.
456 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
460 if (!per_cpu(ssb_state, cpu).shared_state)
463 /* Link it to the state of the sibling: */
464 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
469 * First HT sibling to come up on the core. Link shared state of
470 * the first HT sibling to itself. The siblings on the same core
471 * which come up later will see the shared state pointer and link
472 * themself to the state of this CPU.
474 st->shared_state = st;
478 * Logic is: First HT sibling enables SSBD for both siblings in the core
479 * and last sibling to disable it, disables it for the whole core. This how
480 * MSR_SPEC_CTRL works in "hardware":
482 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
484 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
486 struct ssb_state *st = this_cpu_ptr(&ssb_state);
487 u64 msr = x86_amd_ls_cfg_base;
489 if (!static_cpu_has(X86_FEATURE_ZEN)) {
490 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
491 wrmsrl(MSR_AMD64_LS_CFG, msr);
495 if (tifn & _TIF_SSBD) {
497 * Since this can race with prctl(), block reentry on the
500 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
503 msr |= x86_amd_ls_cfg_ssbd_mask;
505 raw_spin_lock(&st->shared_state->lock);
506 /* First sibling enables SSBD: */
507 if (!st->shared_state->disable_state)
508 wrmsrl(MSR_AMD64_LS_CFG, msr);
509 st->shared_state->disable_state++;
510 raw_spin_unlock(&st->shared_state->lock);
512 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
515 raw_spin_lock(&st->shared_state->lock);
516 st->shared_state->disable_state--;
517 if (!st->shared_state->disable_state)
518 wrmsrl(MSR_AMD64_LS_CFG, msr);
519 raw_spin_unlock(&st->shared_state->lock);
523 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
525 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
527 wrmsrl(MSR_AMD64_LS_CFG, msr);
531 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
534 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
535 * so ssbd_tif_to_spec_ctrl() just works.
537 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
541 * Update the MSRs managing speculation control, during context switch.
543 * tifp: Previous task's thread flags
544 * tifn: Next task's thread flags
546 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
549 unsigned long tif_diff = tifp ^ tifn;
550 u64 msr = x86_spec_ctrl_base;
553 lockdep_assert_irqs_disabled();
555 /* Handle change of TIF_SSBD depending on the mitigation method. */
556 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
557 if (tif_diff & _TIF_SSBD)
558 amd_set_ssb_virt_state(tifn);
559 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
560 if (tif_diff & _TIF_SSBD)
561 amd_set_core_ssb_state(tifn);
562 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
563 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
564 updmsr |= !!(tif_diff & _TIF_SSBD);
565 msr |= ssbd_tif_to_spec_ctrl(tifn);
568 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
569 if (IS_ENABLED(CONFIG_SMP) &&
570 static_branch_unlikely(&switch_to_cond_stibp)) {
571 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
572 msr |= stibp_tif_to_spec_ctrl(tifn);
576 update_spec_ctrl_cond(msr);
579 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
581 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
582 if (task_spec_ssb_disable(tsk))
583 set_tsk_thread_flag(tsk, TIF_SSBD);
585 clear_tsk_thread_flag(tsk, TIF_SSBD);
587 if (task_spec_ib_disable(tsk))
588 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
590 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
592 /* Return the updated threadinfo flags*/
593 return task_thread_info(tsk)->flags;
596 void speculation_ctrl_update(unsigned long tif)
600 /* Forced update. Make sure all relevant TIF flags are different */
601 local_irq_save(flags);
602 __speculation_ctrl_update(~tif, tif);
603 local_irq_restore(flags);
606 /* Called from seccomp/prctl update */
607 void speculation_ctrl_update_current(void)
610 speculation_ctrl_update(speculation_ctrl_update_tif(current));
614 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
616 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
620 this_cpu_write(cpu_tlbstate.cr4, newval);
625 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
627 unsigned long tifp, tifn;
629 tifn = READ_ONCE(task_thread_info(next_p)->flags);
630 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
632 switch_to_bitmap(tifp);
634 propagate_user_return_notify(prev_p, next_p);
636 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
637 arch_has_block_step()) {
638 unsigned long debugctl, msk;
640 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
641 debugctl &= ~DEBUGCTLMSR_BTF;
642 msk = tifn & _TIF_BLOCKSTEP;
643 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
644 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
647 if ((tifp ^ tifn) & _TIF_NOTSC)
648 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
650 if ((tifp ^ tifn) & _TIF_NOCPUID)
651 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
653 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
654 __speculation_ctrl_update(tifp, tifn);
656 speculation_ctrl_update_tif(prev_p);
657 tifn = speculation_ctrl_update_tif(next_p);
659 /* Enforce MSR update to ensure consistent state */
660 __speculation_ctrl_update(~tifn, tifn);
663 if ((tifp ^ tifn) & _TIF_SLD)
668 * Idle related variables and functions
670 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
671 EXPORT_SYMBOL(boot_option_idle_override);
673 static void (*x86_idle)(void);
676 static inline void play_dead(void)
682 void arch_cpu_idle_enter(void)
684 tsc_verify_tsc_adjust(false);
688 void arch_cpu_idle_dead(void)
694 * Called from the generic idle code.
696 void arch_cpu_idle(void)
702 * We use this if we don't have any better idle routine..
704 void __cpuidle default_idle(void)
708 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
709 EXPORT_SYMBOL(default_idle);
713 bool xen_set_default_idle(void)
715 bool ret = !!x86_idle;
717 x86_idle = default_idle;
723 void __noreturn stop_this_cpu(void *dummy)
729 set_cpu_online(smp_processor_id(), false);
730 disable_local_APIC();
731 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
734 * Use wbinvd on processors that support SME. This provides support
735 * for performing a successful kexec when going from SME inactive
736 * to SME active (or vice-versa). The cache must be cleared so that
737 * if there are entries with the same physical address, both with and
738 * without the encryption bit, they don't race each other when flushed
739 * and potentially end up with the wrong entry being committed to
742 if (boot_cpu_has(X86_FEATURE_SME))
746 * Use native_halt() so that memory contents don't change
747 * (stack usage and variables) after possibly issuing the
748 * native_wbinvd() above.
755 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
756 * states (local apic timer and TSC stop).
758 * XXX this function is completely buggered vs RCU and tracing.
760 static void amd_e400_idle(void)
763 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
764 * gets set after static_cpu_has() places have been converted via
767 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
772 tick_broadcast_enter();
777 * The switch back from broadcast mode needs to be called with
778 * interrupts disabled.
780 raw_local_irq_disable();
781 tick_broadcast_exit();
782 raw_local_irq_enable();
786 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
787 * We can't rely on cpuidle installing MWAIT, because it will not load
788 * on systems that support only C1 -- so the boot default must be MWAIT.
790 * Some AMD machines are the opposite, they depend on using HALT.
792 * So for default C1, which is used during boot until cpuidle loads,
793 * use MWAIT-C1 on Intel HW that has it, else use HALT.
795 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
797 /* User has disallowed the use of MWAIT. Fallback to HALT */
798 if (boot_option_idle_override == IDLE_NOMWAIT)
801 if (c->x86_vendor != X86_VENDOR_INTEL)
804 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
811 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
812 * with interrupts enabled and no flags, which is backwards compatible with the
813 * original MWAIT implementation.
815 static __cpuidle void mwait_idle(void)
817 if (!current_set_polling_and_test()) {
818 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
820 clflush((void *)¤t_thread_info()->flags);
824 __monitor((void *)¤t_thread_info()->flags, 0, 0);
828 raw_local_irq_enable();
830 raw_local_irq_enable();
832 __current_clr_polling();
835 void select_idle_routine(const struct cpuinfo_x86 *c)
838 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
839 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
841 if (x86_idle || boot_option_idle_override == IDLE_POLL)
844 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
845 pr_info("using AMD E400 aware idle routine\n");
846 x86_idle = amd_e400_idle;
847 } else if (prefer_mwait_c1_over_halt(c)) {
848 pr_info("using mwait in idle threads\n");
849 x86_idle = mwait_idle;
851 x86_idle = default_idle;
854 void amd_e400_c1e_apic_setup(void)
856 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
857 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
859 tick_broadcast_force();
864 void __init arch_post_acpi_subsys_init(void)
868 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
872 * AMD E400 detection needs to happen after ACPI has been enabled. If
873 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
874 * MSR_K8_INT_PENDING_MSG.
876 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
877 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
880 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
882 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
883 mark_tsc_unstable("TSC halt in AMD C1E");
884 pr_info("System has AMD C1E enabled\n");
887 static int __init idle_setup(char *str)
892 if (!strcmp(str, "poll")) {
893 pr_info("using polling idle threads\n");
894 boot_option_idle_override = IDLE_POLL;
895 cpu_idle_poll_ctrl(true);
896 } else if (!strcmp(str, "halt")) {
898 * When the boot option of idle=halt is added, halt is
899 * forced to be used for CPU idle. In such case CPU C2/C3
900 * won't be used again.
901 * To continue to load the CPU idle driver, don't touch
902 * the boot_option_idle_override.
904 x86_idle = default_idle;
905 boot_option_idle_override = IDLE_HALT;
906 } else if (!strcmp(str, "nomwait")) {
908 * If the boot option of "idle=nomwait" is added,
909 * it means that mwait will be disabled for CPU C1/C2/C3
912 boot_option_idle_override = IDLE_NOMWAIT;
918 early_param("idle", idle_setup);
920 unsigned long arch_align_stack(unsigned long sp)
922 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
923 sp -= get_random_int() % 8192;
927 unsigned long arch_randomize_brk(struct mm_struct *mm)
929 return randomize_page(mm->brk, 0x02000000);
933 * Called from fs/proc with a reference on @p to find the function
934 * which called into schedule(). This needs to be done carefully
935 * because the task might wake up and we might look at a stack
938 unsigned long get_wchan(struct task_struct *p)
940 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
943 if (p == current || p->state == TASK_RUNNING)
946 if (!try_get_task_stack(p))
949 start = (unsigned long)task_stack_page(p);
954 * Layout of the stack page:
956 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
958 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
960 * ----------- bottom = start
962 * The tasks stack pointer points at the location where the
963 * framepointer is stored. The data on the stack is:
964 * ... IP FP ... IP FP
966 * We need to read FP and IP, so we need to adjust the upper
967 * bound by another unsigned long.
969 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
970 top -= 2 * sizeof(unsigned long);
973 sp = READ_ONCE(p->thread.sp);
974 if (sp < bottom || sp > top)
977 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
979 if (fp < bottom || fp > top)
981 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
982 if (!in_sched_functions(ip)) {
986 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
987 } while (count++ < 16 && p->state != TASK_RUNNING);
994 long do_arch_prctl_common(struct task_struct *task, int option,
995 unsigned long cpuid_enabled)
999 return get_cpuid_mode();
1000 case ARCH_SET_CPUID:
1001 return set_cpuid_mode(task, cpuid_enabled);