arch/x86/kernel/pci-calgary_64.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Derived from arch/powerpc/kernel/iommu.c
   4  *
   5  * Copyright IBM Corporation, 2006-2007
   6  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   7  *
   8  * Author: Jon Mason <jdmason@kudzu.us>
   9  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
  10
  11  */
  12
  13 #define pr_fmt(fmt) "Calgary: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/slab.h>
  19 #include <linux/mm.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/string.h>
  22 #include <linux/crash_dump.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dma-direct.h>
  25 #include <linux/bitmap.h>
  26 #include <linux/pci_ids.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/iommu-helper.h>
  31
  32 #include <asm/iommu.h>
  33 #include <asm/calgary.h>
  34 #include <asm/tce.h>
  35 #include <asm/pci-direct.h>
  36 #include <asm/dma.h>
  37 #include <asm/rio.h>
  38 #include <asm/bios_ebda.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/iommu_table.h>
  41
  42 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  43 int use_calgary __read_mostly = 1;
  44 #else
  45 int use_calgary __read_mostly = 0;
  46 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  47
  48 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  49 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  50
  51 /* register offsets inside the host bridge space */
  52 #define CALGARY_CONFIG_REG      0x0108
  53 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  54 #define PHB_PLSSR_OFFSET        0x0120
  55 #define PHB_CONFIG_RW_OFFSET    0x0160
  56 #define PHB_IOBASE_BAR_LOW      0x0170
  57 #define PHB_IOBASE_BAR_HIGH     0x0180
  58 #define PHB_MEM_1_LOW           0x0190
  59 #define PHB_MEM_1_HIGH          0x01A0
  60 #define PHB_IO_ADDR_SIZE        0x01B0
  61 #define PHB_MEM_1_SIZE          0x01C0
  62 #define PHB_MEM_ST_OFFSET       0x01D0
  63 #define PHB_AER_OFFSET          0x0200
  64 #define PHB_CONFIG_0_HIGH       0x0220
  65 #define PHB_CONFIG_0_LOW        0x0230
  66 #define PHB_CONFIG_0_END        0x0240
  67 #define PHB_MEM_2_LOW           0x02B0
  68 #define PHB_MEM_2_HIGH          0x02C0
  69 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  70 #define PHB_MEM_2_SIZE_LOW      0x02E0
  71 #define PHB_DOSHOLE_OFFSET      0x08E0
  72
  73 /* CalIOC2 specific */
  74 #define PHB_SAVIOR_L2           0x0DB0
  75 #define PHB_PAGE_MIG_CTRL       0x0DA8
  76 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  77 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  78
  79 /* PHB_CONFIG_RW */
  80 #define PHB_TCE_ENABLE          0x20000000
  81 #define PHB_SLOT_DISABLE        0x1C000000
  82 #define PHB_DAC_DISABLE         0x01000000
  83 #define PHB_MEM2_ENABLE         0x00400000
  84 #define PHB_MCSR_ENABLE         0x00100000
  85 /* TAR (Table Address Register) */
  86 #define TAR_SW_BITS             0x0000ffffffff800fUL
  87 #define TAR_VALID               0x0000000000000008UL
  88 /* CSR (Channel/DMA Status Register) */
  89 #define CSR_AGENT_MASK          0xffe0ffff
  90 /* CCR (Calgary Configuration Register) */
  91 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  92 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  93 #define PMR_SOFTSTOP            0x80000000
  94 #define PMR_SOFTSTOPFAULT       0x40000000
  95 #define PMR_HARDSTOP            0x20000000
  96
  97 /*
  98  * The maximum PHB bus number.
  99  * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 100  * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
 101  * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
 102  * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
 103  */
 104 #define MAX_PHB_BUS_NUM         256
 105
 106 #define PHBS_PER_CALGARY          4
 107
 108 /* register offsets in Calgary's internal register space */
 109 static const unsigned long tar_offsets[] = {
 110         0x0580 /* TAR0 */,
 111         0x0588 /* TAR1 */,
 112         0x0590 /* TAR2 */,
 113         0x0598 /* TAR3 */
 114 };
 115
 116 static const unsigned long split_queue_offsets[] = {
 117         0x4870 /* SPLIT QUEUE 0 */,
 118         0x5870 /* SPLIT QUEUE 1 */,
 119         0x6870 /* SPLIT QUEUE 2 */,
 120         0x7870 /* SPLIT QUEUE 3 */
 121 };
 122
 123 static const unsigned long phb_offsets[] = {
 124         0x8000 /* PHB0 */,
 125         0x9000 /* PHB1 */,
 126         0xA000 /* PHB2 */,
 127         0xB000 /* PHB3 */
 128 };
 129
 130 /* PHB debug registers */
 131
 132 static const unsigned long phb_debug_offsets[] = {
 133         0x4000  /* PHB 0 DEBUG */,
 134         0x5000  /* PHB 1 DEBUG */,
 135         0x6000  /* PHB 2 DEBUG */,
 136         0x7000  /* PHB 3 DEBUG */
 137 };
 138
 139 /*
 140  * STUFF register for each debug PHB,
 141  * byte 1 = start bus number, byte 2 = end bus number
 142  */
 143
 144 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 145
 146 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 147 static int translate_empty_slots __read_mostly = 0;
 148 static int calgary_detected __read_mostly = 0;
 149
 150 static struct rio_table_hdr     *rio_table_hdr __initdata;
 151 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 152 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 153
 154 struct calgary_bus_info {
 155         void *tce_space;
 156         unsigned char translation_disabled;
 157         signed char phbid;
 158         void __iomem *bbar;
 159 };
 160
 161 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 162 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 163 static void calgary_dump_error_regs(struct iommu_table *tbl);
 164 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 165 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 166 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 167 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 168 static void get_tce_space_from_tar(void);
 169
 170 static const struct cal_chipset_ops calgary_chip_ops = {
 171         .handle_quirks = calgary_handle_quirks,
 172         .tce_cache_blast = calgary_tce_cache_blast,
 173         .dump_error_regs = calgary_dump_error_regs
 174 };
 175
 176 static const struct cal_chipset_ops calioc2_chip_ops = {
 177         .handle_quirks = calioc2_handle_quirks,
 178         .tce_cache_blast = calioc2_tce_cache_blast,
 179         .dump_error_regs = calioc2_dump_error_regs
 180 };
 181
 182 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 183
 184 static inline int translation_enabled(struct iommu_table *tbl)
 185 {
 186         /* only PHBs with translation enabled have an IOMMU table */
 187         return (tbl != NULL);
 188 }
 189
 190 static void iommu_range_reserve(struct iommu_table *tbl,
 191         unsigned long start_addr, unsigned int npages)
 192 {
 193         unsigned long index;
 194         unsigned long end;
 195         unsigned long flags;
 196
 197         index = start_addr >> PAGE_SHIFT;
 198
 199         /* bail out if we're asked to reserve a region we don't cover */
 200         if (index >= tbl->it_size)
 201                 return;
 202
 203         end = index + npages;
 204         if (end > tbl->it_size) /* don't go off the table */
 205                 end = tbl->it_size;
 206
 207         spin_lock_irqsave(&tbl->it_lock, flags);
 208
 209         bitmap_set(tbl->it_map, index, npages);
 210
 211         spin_unlock_irqrestore(&tbl->it_lock, flags);
 212 }
 213
 214 static unsigned long iommu_range_alloc(struct device *dev,
 215                                        struct iommu_table *tbl,
 216                                        unsigned int npages)
 217 {
 218         unsigned long flags;
 219         unsigned long offset;
 220         unsigned long boundary_size;
 221
 222         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 223                               PAGE_SIZE) >> PAGE_SHIFT;
 224
 225         BUG_ON(npages == 0);
 226
 227         spin_lock_irqsave(&tbl->it_lock, flags);
 228
 229         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 230                                   npages, 0, boundary_size, 0);
 231         if (offset == ~0UL) {
 232                 tbl->chip_ops->tce_cache_blast(tbl);
 233
 234                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 235                                           npages, 0, boundary_size, 0);
 236                 if (offset == ~0UL) {
 237                         pr_warn("IOMMU full\n");
 238                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 239                         if (panic_on_overflow)
 240                                 panic("Calgary: fix the allocator.\n");
 241                         else
 242                                 return DMA_MAPPING_ERROR;
 243                 }
 244         }
 245
 246         tbl->it_hint = offset + npages;
 247         BUG_ON(tbl->it_hint > tbl->it_size);
 248
 249         spin_unlock_irqrestore(&tbl->it_lock, flags);
 250
 251         return offset;
 252 }
 253
 254 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 255                               void *vaddr, unsigned int npages, int direction)
 256 {
 257         unsigned long entry;
 258         dma_addr_t ret;
 259
 260         entry = iommu_range_alloc(dev, tbl, npages);
 261         if (unlikely(entry == DMA_MAPPING_ERROR)) {
 262                 pr_warn("failed to allocate %u pages in iommu %p\n",
 263                         npages, tbl);
 264                 return DMA_MAPPING_ERROR;
 265         }
 266
 267         /* set the return dma address */
 268         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 269
 270         /* put the TCEs in the HW table */
 271         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 272                   direction);
 273         return ret;
 274 }
 275
 276 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 277         unsigned int npages)
 278 {
 279         unsigned long entry;
 280         unsigned long flags;
 281
 282         /* were we called with bad_dma_address? */
 283         if (unlikely(dma_addr == DMA_MAPPING_ERROR)) {
 284                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 285                        "address 0x%Lx\n", dma_addr);
 286                 return;
 287         }
 288
 289         entry = dma_addr >> PAGE_SHIFT;
 290
 291         BUG_ON(entry + npages > tbl->it_size);
 292
 293         tce_free(tbl, entry, npages);
 294
 295         spin_lock_irqsave(&tbl->it_lock, flags);
 296
 297         bitmap_clear(tbl->it_map, entry, npages);
 298
 299         spin_unlock_irqrestore(&tbl->it_lock, flags);
 300 }
 301
 302 static inline struct iommu_table *find_iommu_table(struct device *dev)
 303 {
 304         struct pci_dev *pdev;
 305         struct pci_bus *pbus;
 306         struct iommu_table *tbl;
 307
 308         pdev = to_pci_dev(dev);
 309
 310         /* search up the device tree for an iommu */
 311         pbus = pdev->bus;
 312         do {
 313                 tbl = pci_iommu(pbus);
 314                 if (tbl && tbl->it_busno == pbus->number)
 315                         break;
 316                 tbl = NULL;
 317                 pbus = pbus->parent;
 318         } while (pbus);
 319
 320         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 321
 322         return tbl;
 323 }
 324
 325 static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 326                              int nelems,enum dma_data_direction dir,
 327                              unsigned long attrs)
 328 {
 329         struct iommu_table *tbl = find_iommu_table(dev);
 330         struct scatterlist *s;
 331         int i;
 332
 333         if (!translation_enabled(tbl))
 334                 return;
 335
 336         for_each_sg(sglist, s, nelems, i) {
 337                 unsigned int npages;
 338                 dma_addr_t dma = s->dma_address;
 339                 unsigned int dmalen = s->dma_length;
 340
 341                 if (dmalen == 0)
 342                         break;
 343
 344                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 345                 iommu_free(tbl, dma, npages);
 346         }
 347 }
 348
 349 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 350                           int nelems, enum dma_data_direction dir,
 351                           unsigned long attrs)
 352 {
 353         struct iommu_table *tbl = find_iommu_table(dev);
 354         struct scatterlist *s;
 355         unsigned long vaddr;
 356         unsigned int npages;
 357         unsigned long entry;
 358         int i;
 359
 360         for_each_sg(sg, s, nelems, i) {
 361                 BUG_ON(!sg_page(s));
 362
 363                 vaddr = (unsigned long) sg_virt(s);
 364                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 365
 366                 entry = iommu_range_alloc(dev, tbl, npages);
 367                 if (entry == DMA_MAPPING_ERROR) {
 368                         /* makes sure unmap knows to stop */
 369                         s->dma_length = 0;
 370                         goto error;
 371                 }
 372
 373                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 374
 375                 /* insert into HW table */
 376                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
 377
 378                 s->dma_length = s->length;
 379         }
 380
 381         return nelems;
 382 error:
 383         calgary_unmap_sg(dev, sg, nelems, dir, 0);
 384         for_each_sg(sg, s, nelems, i) {
 385                 sg->dma_address = DMA_MAPPING_ERROR;
 386                 sg->dma_length = 0;
 387         }
 388         return 0;
 389 }
 390
 391 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 392                                    unsigned long offset, size_t size,
 393                                    enum dma_data_direction dir,
 394                                    unsigned long attrs)
 395 {
 396         void *vaddr = page_address(page) + offset;
 397         unsigned long uaddr;
 398         unsigned int npages;
 399         struct iommu_table *tbl = find_iommu_table(dev);
 400
 401         uaddr = (unsigned long)vaddr;
 402         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 403
 404         return iommu_alloc(dev, tbl, vaddr, npages, dir);
 405 }
 406
 407 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 408                                size_t size, enum dma_data_direction dir,
 409                                unsigned long attrs)
 410 {
 411         struct iommu_table *tbl = find_iommu_table(dev);
 412         unsigned int npages;
 413
 414         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 415         iommu_free(tbl, dma_addr, npages);
 416 }
 417
 418 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 419         dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
 420 {
 421         void *ret = NULL;
 422         dma_addr_t mapping;
 423         unsigned int npages, order;
 424         struct iommu_table *tbl = find_iommu_table(dev);
 425
 426         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 427         npages = size >> PAGE_SHIFT;
 428         order = get_order(size);
 429
 430         /* alloc enough pages (and possibly more) */
 431         ret = (void *)__get_free_pages(flag, order);
 432         if (!ret)
 433                 goto error;
 434         memset(ret, 0, size);
 435
 436         /* set up tces to cover the allocated range */
 437         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 438         if (mapping == DMA_MAPPING_ERROR)
 439                 goto free;
 440         *dma_handle = mapping;
 441         return ret;
 442 free:
 443         free_pages((unsigned long)ret, get_order(size));
 444         ret = NULL;
 445 error:
 446         return ret;
 447 }
 448
 449 static void calgary_free_coherent(struct device *dev, size_t size,
 450                                   void *vaddr, dma_addr_t dma_handle,
 451                                   unsigned long attrs)
 452 {
 453         unsigned int npages;
 454         struct iommu_table *tbl = find_iommu_table(dev);
 455
 456         size = PAGE_ALIGN(size);
 457         npages = size >> PAGE_SHIFT;
 458
 459         iommu_free(tbl, dma_handle, npages);
 460         free_pages((unsigned long)vaddr, get_order(size));
 461 }
 462
 463 static const struct dma_map_ops calgary_dma_ops = {
 464         .alloc = calgary_alloc_coherent,
 465         .free = calgary_free_coherent,
 466         .map_sg = calgary_map_sg,
 467         .unmap_sg = calgary_unmap_sg,
 468         .map_page = calgary_map_page,
 469         .unmap_page = calgary_unmap_page,
 470         .dma_supported = dma_direct_supported,
 471         .mmap = dma_common_mmap,
 472         .get_sgtable = dma_common_get_sgtable,
 473 };
 474
 475 static inline void __iomem * busno_to_bbar(unsigned char num)
 476 {
 477         return bus_info[num].bbar;
 478 }
 479
 480 static inline int busno_to_phbid(unsigned char num)
 481 {
 482         return bus_info[num].phbid;
 483 }
 484
 485 static inline unsigned long split_queue_offset(unsigned char num)
 486 {
 487         size_t idx = busno_to_phbid(num);
 488
 489         return split_queue_offsets[idx];
 490 }
 491
 492 static inline unsigned long tar_offset(unsigned char num)
 493 {
 494         size_t idx = busno_to_phbid(num);
 495
 496         return tar_offsets[idx];
 497 }
 498
 499 static inline unsigned long phb_offset(unsigned char num)
 500 {
 501         size_t idx = busno_to_phbid(num);
 502
 503         return phb_offsets[idx];
 504 }
 505
 506 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 507 {
 508         unsigned long target = ((unsigned long)bar) | offset;
 509         return (void __iomem*)target;
 510 }
 511
 512 static inline int is_calioc2(unsigned short device)
 513 {
 514         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 515 }
 516
 517 static inline int is_calgary(unsigned short device)
 518 {
 519         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 520 }
 521
 522 static inline int is_cal_pci_dev(unsigned short device)
 523 {
 524         return (is_calgary(device) || is_calioc2(device));
 525 }
 526
 527 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 528 {
 529         u64 val;
 530         u32 aer;
 531         int i = 0;
 532         void __iomem *bbar = tbl->bbar;
 533         void __iomem *target;
 534
 535         /* disable arbitration on the bus */
 536         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 537         aer = readl(target);
 538         writel(0, target);
 539
 540         /* read plssr to ensure it got there */
 541         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 542         val = readl(target);
 543
 544         /* poll split queues until all DMA activity is done */
 545         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 546         do {
 547                 val = readq(target);
 548                 i++;
 549         } while ((val & 0xff) != 0xff && i < 100);
 550         if (i == 100)
 551                 pr_warn("PCI bus not quiesced, continuing anyway\n");
 552
 553         /* invalidate TCE cache */
 554         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 555         writeq(tbl->tar_val, target);
 556
 557         /* enable arbitration */
 558         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 559         writel(aer, target);
 560         (void)readl(target); /* flush */
 561 }
 562
 563 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 564 {
 565         void __iomem *bbar = tbl->bbar;
 566         void __iomem *target;
 567         u64 val64;
 568         u32 val;
 569         int i = 0;
 570         int count = 1;
 571         unsigned char bus = tbl->it_busno;
 572
 573 begin:
 574         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 575                "sequence - count %d\n", bus, count);
 576
 577         /* 1. using the Page Migration Control reg set SoftStop */
 578         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 579         val = be32_to_cpu(readl(target));
 580         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 581         val |= PMR_SOFTSTOP;
 582         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 583         writel(cpu_to_be32(val), target);
 584
 585         /* 2. poll split queues until all DMA activity is done */
 586         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 587         target = calgary_reg(bbar, split_queue_offset(bus));
 588         do {
 589                 val64 = readq(target);
 590                 i++;
 591         } while ((val64 & 0xff) != 0xff && i < 100);
 592         if (i == 100)
 593                 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
 594
 595         /* 3. poll Page Migration DEBUG for SoftStopFault */
 596         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 597         val = be32_to_cpu(readl(target));
 598         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 599
 600         /* 4. if SoftStopFault - goto (1) */
 601         if (val & PMR_SOFTSTOPFAULT) {
 602                 if (++count < 100)
 603                         goto begin;
 604                 else {
 605                         pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
 606                         return; /* pray for the best */
 607                 }
 608         }
 609
 610         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 611         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 612         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 613         val = be32_to_cpu(readl(target));
 614         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 615         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 616         val = be32_to_cpu(readl(target));
 617         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 618
 619         /* 6. invalidate TCE cache */
 620         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 621         target = calgary_reg(bbar, tar_offset(bus));
 622         writeq(tbl->tar_val, target);
 623
 624         /* 7. Re-read PMCR */
 625         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 626         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 627         val = be32_to_cpu(readl(target));
 628         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 629
 630         /* 8. Remove HardStop */
 631         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 632         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 633         val = 0;
 634         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 635         writel(cpu_to_be32(val), target);
 636         val = be32_to_cpu(readl(target));
 637         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 638 }
 639
 640 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 641         u64 limit)
 642 {
 643         unsigned int numpages;
 644
 645         limit = limit | 0xfffff;
 646         limit++;
 647
 648         numpages = ((limit - start) >> PAGE_SHIFT);
 649         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 650 }
 651
 652 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 653 {
 654         void __iomem *target;
 655         u64 low, high, sizelow;
 656         u64 start, limit;
 657         struct iommu_table *tbl = pci_iommu(dev->bus);
 658         unsigned char busnum = dev->bus->number;
 659         void __iomem *bbar = tbl->bbar;
 660
 661         /* peripheral MEM_1 region */
 662         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 663         low = be32_to_cpu(readl(target));
 664         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 665         high = be32_to_cpu(readl(target));
 666         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 667         sizelow = be32_to_cpu(readl(target));
 668
 669         start = (high << 32) | low;
 670         limit = sizelow;
 671
 672         calgary_reserve_mem_region(dev, start, limit);
 673 }
 674
 675 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 676 {
 677         void __iomem *target;
 678         u32 val32;
 679         u64 low, high, sizelow, sizehigh;
 680         u64 start, limit;
 681         struct iommu_table *tbl = pci_iommu(dev->bus);
 682         unsigned char busnum = dev->bus->number;
 683         void __iomem *bbar = tbl->bbar;
 684
 685         /* is it enabled? */
 686         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 687         val32 = be32_to_cpu(readl(target));
 688         if (!(val32 & PHB_MEM2_ENABLE))
 689                 return;
 690
 691         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 692         low = be32_to_cpu(readl(target));
 693         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 694         high = be32_to_cpu(readl(target));
 695         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 696         sizelow = be32_to_cpu(readl(target));
 697         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 698         sizehigh = be32_to_cpu(readl(target));
 699
 700         start = (high << 32) | low;
 701         limit = (sizehigh << 32) | sizelow;
 702
 703         calgary_reserve_mem_region(dev, start, limit);
 704 }
 705
 706 /*
 707  * some regions of the IO address space do not get translated, so we
 708  * must not give devices IO addresses in those regions. The regions
 709  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 710  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 711  * later.
 712  */
 713 static void __init calgary_reserve_regions(struct pci_dev *dev)
 714 {
 715         unsigned int npages;
 716         u64 start;
 717         struct iommu_table *tbl = pci_iommu(dev->bus);
 718
 719         /* avoid the BIOS/VGA first 640KB-1MB region */
 720         /* for CalIOC2 - avoid the entire first MB */
 721         if (is_calgary(dev->device)) {
 722                 start = (640 * 1024);
 723                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 724         } else { /* calioc2 */
 725                 start = 0;
 726                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 727         }
 728         iommu_range_reserve(tbl, start, npages);
 729
 730         /* reserve the two PCI peripheral memory regions in IO space */
 731         calgary_reserve_peripheral_mem_1(dev);
 732         calgary_reserve_peripheral_mem_2(dev);
 733 }
 734
 735 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 736 {
 737         u64 val64;
 738         u64 table_phys;
 739         void __iomem *target;
 740         int ret;
 741         struct iommu_table *tbl;
 742
 743         /* build TCE tables for each PHB */
 744         ret = build_tce_table(dev, bbar);
 745         if (ret)
 746                 return ret;
 747
 748         tbl = pci_iommu(dev->bus);
 749         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 750
 751         if (is_kdump_kernel())
 752                 calgary_init_bitmap_from_tce_table(tbl);
 753         else
 754                 tce_free(tbl, 0, tbl->it_size);
 755
 756         if (is_calgary(dev->device))
 757                 tbl->chip_ops = &calgary_chip_ops;
 758         else if (is_calioc2(dev->device))
 759                 tbl->chip_ops = &calioc2_chip_ops;
 760         else
 761                 BUG();
 762
 763         calgary_reserve_regions(dev);
 764
 765         /* set TARs for each PHB */
 766         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 767         val64 = be64_to_cpu(readq(target));
 768
 769         /* zero out all TAR bits under sw control */
 770         val64 &= ~TAR_SW_BITS;
 771         table_phys = (u64)__pa(tbl->it_base);
 772
 773         val64 |= table_phys;
 774
 775         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 776         val64 |= (u64) specified_table_size;
 777
 778         tbl->tar_val = cpu_to_be64(val64);
 779
 780         writeq(tbl->tar_val, target);
 781         readq(target); /* flush */
 782
 783         return 0;
 784 }
 785
 786 static void __init calgary_free_bus(struct pci_dev *dev)
 787 {
 788         u64 val64;
 789         struct iommu_table *tbl = pci_iommu(dev->bus);
 790         void __iomem *target;
 791         unsigned int bitmapsz;
 792
 793         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 794         val64 = be64_to_cpu(readq(target));
 795         val64 &= ~TAR_SW_BITS;
 796         writeq(cpu_to_be64(val64), target);
 797         readq(target); /* flush */
 798
 799         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 800         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 801         tbl->it_map = NULL;
 802
 803         kfree(tbl);
 804
 805         set_pci_iommu(dev->bus, NULL);
 806
 807         /* Can't free bootmem allocated memory after system is up :-( */
 808         bus_info[dev->bus->number].tce_space = NULL;
 809 }
 810
 811 static void calgary_dump_error_regs(struct iommu_table *tbl)
 812 {
 813         void __iomem *bbar = tbl->bbar;
 814         void __iomem *target;
 815         u32 csr, plssr;
 816
 817         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 818         csr = be32_to_cpu(readl(target));
 819
 820         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 821         plssr = be32_to_cpu(readl(target));
 822
 823         /* If no error, the agent ID in the CSR is not valid */
 824         pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
 825                  tbl->it_busno, csr, plssr);
 826 }
 827
 828 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 829 {
 830         void __iomem *bbar = tbl->bbar;
 831         u32 csr, csmr, plssr, mck, rcstat;
 832         void __iomem *target;
 833         unsigned long phboff = phb_offset(tbl->it_busno);
 834         unsigned long erroff;
 835         u32 errregs[7];
 836         int i;
 837
 838         /* dump CSR */
 839         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 840         csr = be32_to_cpu(readl(target));
 841         /* dump PLSSR */
 842         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 843         plssr = be32_to_cpu(readl(target));
 844         /* dump CSMR */
 845         target = calgary_reg(bbar, phboff | 0x290);
 846         csmr = be32_to_cpu(readl(target));
 847         /* dump mck */
 848         target = calgary_reg(bbar, phboff | 0x800);
 849         mck = be32_to_cpu(readl(target));
 850
 851         pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
 852
 853         pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 854                  csr, plssr, csmr, mck);
 855
 856         /* dump rest of error regs */
 857         pr_emerg("");
 858         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 859                 /* err regs are at 0x810 - 0x870 */
 860                 erroff = (0x810 + (i * 0x10));
 861                 target = calgary_reg(bbar, phboff | erroff);
 862                 errregs[i] = be32_to_cpu(readl(target));
 863                 pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
 864         }
 865         pr_cont("\n");
 866
 867         /* root complex status */
 868         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 869         rcstat = be32_to_cpu(readl(target));
 870         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 871                PHB_ROOT_COMPLEX_STATUS);
 872 }
 873
 874 static void calgary_watchdog(struct timer_list *t)
 875 {
 876         struct iommu_table *tbl = from_timer(tbl, t, watchdog_timer);
 877         void __iomem *bbar = tbl->bbar;
 878         u32 val32;
 879         void __iomem *target;
 880
 881         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 882         val32 = be32_to_cpu(readl(target));
 883
 884         /* If no error, the agent ID in the CSR is not valid */
 885         if (val32 & CSR_AGENT_MASK) {
 886                 tbl->chip_ops->dump_error_regs(tbl);
 887
 888                 /* reset error */
 889                 writel(0, target);
 890
 891                 /* Disable bus that caused the error */
 892                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 893                                      PHB_CONFIG_RW_OFFSET);
 894                 val32 = be32_to_cpu(readl(target));
 895                 val32 |= PHB_SLOT_DISABLE;
 896                 writel(cpu_to_be32(val32), target);
 897                 readl(target); /* flush */
 898         } else {
 899                 /* Reset the timer */
 900                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 901         }
 902 }
 903
 904 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 905         unsigned char busnum, unsigned long timeout)
 906 {
 907         u64 val64;
 908         void __iomem *target;
 909         unsigned int phb_shift = ~0; /* silence gcc */
 910         u64 mask;
 911
 912         switch (busno_to_phbid(busnum)) {
 913         case 0: phb_shift = (63 - 19);
 914                 break;
 915         case 1: phb_shift = (63 - 23);
 916                 break;
 917         case 2: phb_shift = (63 - 27);
 918                 break;
 919         case 3: phb_shift = (63 - 35);
 920                 break;
 921         default:
 922                 BUG_ON(busno_to_phbid(busnum));
 923         }
 924
 925         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 926         val64 = be64_to_cpu(readq(target));
 927
 928         /* zero out this PHB's timer bits */
 929         mask = ~(0xFUL << phb_shift);
 930         val64 &= mask;
 931         val64 |= (timeout << phb_shift);
 932         writeq(cpu_to_be64(val64), target);
 933         readq(target); /* flush */
 934 }
 935
 936 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 937 {
 938         unsigned char busnum = dev->bus->number;
 939         void __iomem *bbar = tbl->bbar;
 940         void __iomem *target;
 941         u32 val;
 942
 943         /*
 944          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
 945          */
 946         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
 947         val = cpu_to_be32(readl(target));
 948         val |= 0x00800000;
 949         writel(cpu_to_be32(val), target);
 950 }
 951
 952 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 953 {
 954         unsigned char busnum = dev->bus->number;
 955
 956         /*
 957          * Give split completion a longer timeout on bus 1 for aic94xx
 958          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 959          */
 960         if (is_calgary(dev->device) && (busnum == 1))
 961                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
 962                                                      CCR_2SEC_TIMEOUT);
 963 }
 964
 965 static void __init calgary_enable_translation(struct pci_dev *dev)
 966 {
 967         u32 val32;
 968         unsigned char busnum;
 969         void __iomem *target;
 970         void __iomem *bbar;
 971         struct iommu_table *tbl;
 972
 973         busnum = dev->bus->number;
 974         tbl = pci_iommu(dev->bus);
 975         bbar = tbl->bbar;
 976
 977         /* enable TCE in PHB Config Register */
 978         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 979         val32 = be32_to_cpu(readl(target));
 980         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 981
 982         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
 983                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
 984                "Calgary" : "CalIOC2", busnum);
 985         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 986                "bus.\n");
 987
 988         writel(cpu_to_be32(val32), target);
 989         readl(target); /* flush */
 990
 991         timer_setup(&tbl->watchdog_timer, calgary_watchdog, 0);
 992         mod_timer(&tbl->watchdog_timer, jiffies);
 993 }
 994
 995 static void __init calgary_disable_translation(struct pci_dev *dev)
 996 {
 997         u32 val32;
 998         unsigned char busnum;
 999         void __iomem *target;
1000         void __iomem *bbar;
1001         struct iommu_table *tbl;
1002
1003         busnum = dev->bus->number;
1004         tbl = pci_iommu(dev->bus);
1005         bbar = tbl->bbar;
1006
1007         /* disable TCE in PHB Config Register */
1008         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1009         val32 = be32_to_cpu(readl(target));
1010         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1011
1012         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1013         writel(cpu_to_be32(val32), target);
1014         readl(target); /* flush */
1015
1016         del_timer_sync(&tbl->watchdog_timer);
1017 }
1018
1019 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1020 {
1021         pci_dev_get(dev);
1022         set_pci_iommu(dev->bus, NULL);
1023
1024         /* is the device behind a bridge? */
1025         if (dev->bus->parent)
1026                 dev->bus->parent->self = dev;
1027         else
1028                 dev->bus->self = dev;
1029 }
1030
1031 static int __init calgary_init_one(struct pci_dev *dev)
1032 {
1033         void __iomem *bbar;
1034         struct iommu_table *tbl;
1035         int ret;
1036
1037         bbar = busno_to_bbar(dev->bus->number);
1038         ret = calgary_setup_tar(dev, bbar);
1039         if (ret)
1040                 goto done;
1041
1042         pci_dev_get(dev);
1043
1044         if (dev->bus->parent) {
1045                 if (dev->bus->parent->self)
1046                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1047                                "bus->parent->self!\n", dev);
1048                 dev->bus->parent->self = dev;
1049         } else
1050                 dev->bus->self = dev;
1051
1052         tbl = pci_iommu(dev->bus);
1053         tbl->chip_ops->handle_quirks(tbl, dev);
1054
1055         calgary_enable_translation(dev);
1056
1057         return 0;
1058
1059 done:
1060         return ret;
1061 }
1062
1063 static int __init calgary_locate_bbars(void)
1064 {
1065         int ret;
1066         int rioidx, phb, bus;
1067         void __iomem *bbar;
1068         void __iomem *target;
1069         unsigned long offset;
1070         u8 start_bus, end_bus;
1071         u32 val;
1072
1073         ret = -ENODATA;
1074         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1075                 struct rio_detail *rio = rio_devs[rioidx];
1076
1077                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1078                         continue;
1079
1080                 /* map entire 1MB of Calgary config space */
1081                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1082                 if (!bbar)
1083                         goto error;
1084
1085                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1086                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1087                         target = calgary_reg(bbar, offset);
1088
1089                         val = be32_to_cpu(readl(target));
1090
1091                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1092                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1093
1094                         if (end_bus) {
1095                                 for (bus = start_bus; bus <= end_bus; bus++) {
1096                                         bus_info[bus].bbar = bbar;
1097                                         bus_info[bus].phbid = phb;
1098                                 }
1099                         } else {
1100                                 bus_info[start_bus].bbar = bbar;
1101                                 bus_info[start_bus].phbid = phb;
1102                         }
1103                 }
1104         }
1105
1106         return 0;
1107
1108 error:
1109         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1110         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1111                 if (bus_info[bus].bbar)
1112                         iounmap(bus_info[bus].bbar);
1113
1114         return ret;
1115 }
1116
1117 static int __init calgary_init(void)
1118 {
1119         int ret;
1120         struct pci_dev *dev = NULL;
1121         struct calgary_bus_info *info;
1122
1123         ret = calgary_locate_bbars();
1124         if (ret)
1125                 return ret;
1126
1127         /* Purely for kdump kernel case */
1128         if (is_kdump_kernel())
1129                 get_tce_space_from_tar();
1130
1131         do {
1132                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1133                 if (!dev)
1134                         break;
1135                 if (!is_cal_pci_dev(dev->device))
1136                         continue;
1137
1138                 info = &bus_info[dev->bus->number];
1139                 if (info->translation_disabled) {
1140                         calgary_init_one_nontraslated(dev);
1141                         continue;
1142                 }
1143
1144                 if (!info->tce_space && !translate_empty_slots)
1145                         continue;
1146
1147                 ret = calgary_init_one(dev);
1148                 if (ret)
1149                         goto error;
1150         } while (1);
1151
1152         dev = NULL;
1153         for_each_pci_dev(dev) {
1154                 struct iommu_table *tbl;
1155
1156                 tbl = find_iommu_table(&dev->dev);
1157
1158                 if (translation_enabled(tbl))
1159                         dev->dev.dma_ops = &calgary_dma_ops;
1160         }
1161
1162         return ret;
1163
1164 error:
1165         do {
1166                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1167                 if (!dev)
1168                         break;
1169                 if (!is_cal_pci_dev(dev->device))
1170                         continue;
1171
1172                 info = &bus_info[dev->bus->number];
1173                 if (info->translation_disabled) {
1174                         pci_dev_put(dev);
1175                         continue;
1176                 }
1177                 if (!info->tce_space && !translate_empty_slots)
1178                         continue;
1179
1180                 calgary_disable_translation(dev);
1181                 calgary_free_bus(dev);
1182                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1183                 dev->dev.dma_ops = NULL;
1184         } while (1);
1185
1186         return ret;
1187 }
1188
1189 static inline int __init determine_tce_table_size(void)
1190 {
1191         int ret;
1192
1193         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1194                 return specified_table_size;
1195
1196         if (is_kdump_kernel() && saved_max_pfn) {
1197                 /*
1198                  * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1199                  * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1200                  * larger table size has twice as many entries, so shift the
1201                  * max ram address by 13 to divide by 8K and then look at the
1202                  * order of the result to choose between 0-7.
1203                  */
1204                 ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
1205                 if (ret > TCE_TABLE_SIZE_8M)
1206                         ret = TCE_TABLE_SIZE_8M;
1207         } else {
1208                 /*
1209                  * Use 8M by default (suggested by Muli) if it's not
1210                  * kdump kernel and saved_max_pfn isn't set.
1211                  */
1212                 ret = TCE_TABLE_SIZE_8M;
1213         }
1214
1215         return ret;
1216 }
1217
1218 static int __init build_detail_arrays(void)
1219 {
1220         unsigned long ptr;
1221         unsigned numnodes, i;
1222         int scal_detail_size, rio_detail_size;
1223
1224         numnodes = rio_table_hdr->num_scal_dev;
1225         if (numnodes > MAX_NUMNODES){
1226                 printk(KERN_WARNING
1227                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1228                         "but system has %d nodes.\n",
1229                         MAX_NUMNODES, numnodes);
1230                 return -ENODEV;
1231         }
1232
1233         switch (rio_table_hdr->version){
1234         case 2:
1235                 scal_detail_size = 11;
1236                 rio_detail_size = 13;
1237                 break;
1238         case 3:
1239                 scal_detail_size = 12;
1240                 rio_detail_size = 15;
1241                 break;
1242         default:
1243                 printk(KERN_WARNING
1244                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1245                        rio_table_hdr->version);
1246                 return -EPROTO;
1247         }
1248
1249         ptr = ((unsigned long)rio_table_hdr) + 3;
1250         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1251                 scal_devs[i] = (struct scal_detail *)ptr;
1252
1253         for (i = 0; i < rio_table_hdr->num_rio_dev;
1254                     i++, ptr += rio_detail_size)
1255                 rio_devs[i] = (struct rio_detail *)ptr;
1256
1257         return 0;
1258 }
1259
1260 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1261 {
1262         int dev;
1263         u32 val;
1264
1265         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1266                 /*
1267                  * FIXME: properly scan for devices across the
1268                  * PCI-to-PCI bridge on every CalIOC2 port.
1269                  */
1270                 return 1;
1271         }
1272
1273         for (dev = 1; dev < 8; dev++) {
1274                 val = read_pci_config(bus, dev, 0, 0);
1275                 if (val != 0xffffffff)
1276                         break;
1277         }
1278         return (val != 0xffffffff);
1279 }
1280
1281 /*
1282  * calgary_init_bitmap_from_tce_table():
1283  * Function for kdump case. In the second/kdump kernel initialize
1284  * the bitmap based on the tce table entries obtained from first kernel
1285  */
1286 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1287 {
1288         u64 *tp;
1289         unsigned int index;
1290         tp = ((u64 *)tbl->it_base);
1291         for (index = 0 ; index < tbl->it_size; index++) {
1292                 if (*tp != 0x0)
1293                         set_bit(index, tbl->it_map);
1294                 tp++;
1295         }
1296 }
1297
1298 /*
1299  * get_tce_space_from_tar():
1300  * Function for kdump case. Get the tce tables from first kernel
1301  * by reading the contents of the base address register of calgary iommu
1302  */
1303 static void __init get_tce_space_from_tar(void)
1304 {
1305         int bus;
1306         void __iomem *target;
1307         unsigned long tce_space;
1308
1309         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1310                 struct calgary_bus_info *info = &bus_info[bus];
1311                 unsigned short pci_device;
1312                 u32 val;
1313
1314                 val = read_pci_config(bus, 0, 0, 0);
1315                 pci_device = (val & 0xFFFF0000) >> 16;
1316
1317                 if (!is_cal_pci_dev(pci_device))
1318                         continue;
1319                 if (info->translation_disabled)
1320                         continue;
1321
1322                 if (calgary_bus_has_devices(bus, pci_device) ||
1323                                                 translate_empty_slots) {
1324                         target = calgary_reg(bus_info[bus].bbar,
1325                                                 tar_offset(bus));
1326                         tce_space = be64_to_cpu(readq(target));
1327                         tce_space = tce_space & TAR_SW_BITS;
1328
1329                         tce_space = tce_space & (~specified_table_size);
1330                         info->tce_space = (u64 *)__va(tce_space);
1331                 }
1332         }
1333         return;
1334 }
1335
1336 static int __init calgary_iommu_init(void)
1337 {
1338         int ret;
1339
1340         /* ok, we're trying to use Calgary - let's roll */
1341         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1342
1343         ret = calgary_init();
1344         if (ret) {
1345                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1346                        "falling back to no_iommu\n", ret);
1347                 return ret;
1348         }
1349
1350         return 0;
1351 }
1352
1353 int __init detect_calgary(void)
1354 {
1355         int bus;
1356         void *tbl;
1357         int calgary_found = 0;
1358         unsigned long ptr;
1359         unsigned int offset, prev_offset;
1360         int ret;
1361
1362         /*
1363          * if the user specified iommu=off or iommu=soft or we found
1364          * another HW IOMMU already, bail out.
1365          */
1366         if (no_iommu || iommu_detected)
1367                 return -ENODEV;
1368
1369         if (!use_calgary)
1370                 return -ENODEV;
1371
1372         if (!early_pci_allowed())
1373                 return -ENODEV;
1374
1375         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1376
1377         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1378
1379         rio_table_hdr = NULL;
1380         prev_offset = 0;
1381         offset = 0x180;
1382         /*
1383          * The next offset is stored in the 1st word.
1384          * Only parse up until the offset increases:
1385          */
1386         while (offset > prev_offset) {
1387                 /* The block id is stored in the 2nd word */
1388                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1389                         /* set the pointer past the offset & block id */
1390                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1391                         break;
1392                 }
1393                 prev_offset = offset;
1394                 offset = *((unsigned short *)(ptr + offset));
1395         }
1396         if (!rio_table_hdr) {
1397                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1398                        "in EBDA - bailing!\n");
1399                 return -ENODEV;
1400         }
1401
1402         ret = build_detail_arrays();
1403         if (ret) {
1404                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1405                 return -ENOMEM;
1406         }
1407
1408         specified_table_size = determine_tce_table_size();
1409
1410         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1411                 struct calgary_bus_info *info = &bus_info[bus];
1412                 unsigned short pci_device;
1413                 u32 val;
1414
1415                 val = read_pci_config(bus, 0, 0, 0);
1416                 pci_device = (val & 0xFFFF0000) >> 16;
1417
1418                 if (!is_cal_pci_dev(pci_device))
1419                         continue;
1420
1421                 if (info->translation_disabled)
1422                         continue;
1423
1424                 if (calgary_bus_has_devices(bus, pci_device) ||
1425                     translate_empty_slots) {
1426                         /*
1427                          * If it is kdump kernel, find and use tce tables
1428                          * from first kernel, else allocate tce tables here
1429                          */
1430                         if (!is_kdump_kernel()) {
1431                                 tbl = alloc_tce_table();
1432                                 if (!tbl)
1433                                         goto cleanup;
1434                                 info->tce_space = tbl;
1435                         }
1436                         calgary_found = 1;
1437                 }
1438         }
1439
1440         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1441                calgary_found ? "found" : "not found");
1442
1443         if (calgary_found) {
1444                 iommu_detected = 1;
1445                 calgary_detected = 1;
1446                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1447                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1448                        specified_table_size);
1449
1450                 x86_init.iommu.iommu_init = calgary_iommu_init;
1451         }
1452         return calgary_found;
1453
1454 cleanup:
1455         for (--bus; bus >= 0; --bus) {
1456                 struct calgary_bus_info *info = &bus_info[bus];
1457
1458                 if (info->tce_space)
1459                         free_tce_table(info->tce_space);
1460         }
1461         return -ENOMEM;
1462 }
1463
1464 static int __init calgary_parse_options(char *p)
1465 {
1466         unsigned int bridge;
1467         unsigned long val;
1468         size_t len;
1469         ssize_t ret;
1470
1471         while (*p) {
1472                 if (!strncmp(p, "64k", 3))
1473                         specified_table_size = TCE_TABLE_SIZE_64K;
1474                 else if (!strncmp(p, "128k", 4))
1475                         specified_table_size = TCE_TABLE_SIZE_128K;
1476                 else if (!strncmp(p, "256k", 4))
1477                         specified_table_size = TCE_TABLE_SIZE_256K;
1478                 else if (!strncmp(p, "512k", 4))
1479                         specified_table_size = TCE_TABLE_SIZE_512K;
1480                 else if (!strncmp(p, "1M", 2))
1481                         specified_table_size = TCE_TABLE_SIZE_1M;
1482                 else if (!strncmp(p, "2M", 2))
1483                         specified_table_size = TCE_TABLE_SIZE_2M;
1484                 else if (!strncmp(p, "4M", 2))
1485                         specified_table_size = TCE_TABLE_SIZE_4M;
1486                 else if (!strncmp(p, "8M", 2))
1487                         specified_table_size = TCE_TABLE_SIZE_8M;
1488
1489                 len = strlen("translate_empty_slots");
1490                 if (!strncmp(p, "translate_empty_slots", len))
1491                         translate_empty_slots = 1;
1492
1493                 len = strlen("disable");
1494                 if (!strncmp(p, "disable", len)) {
1495                         p += len;
1496                         if (*p == '=')
1497                                 ++p;
1498                         if (*p == '\0')
1499                                 break;
1500                         ret = kstrtoul(p, 0, &val);
1501                         if (ret)
1502                                 break;
1503
1504                         bridge = val;
1505                         if (bridge < MAX_PHB_BUS_NUM) {
1506                                 printk(KERN_INFO "Calgary: disabling "
1507                                        "translation for PHB %#x\n", bridge);
1508                                 bus_info[bridge].translation_disabled = 1;
1509                         }
1510                 }
1511
1512                 p = strpbrk(p, ",");
1513                 if (!p)
1514                         break;
1515
1516                 p++; /* skip ',' */
1517         }
1518         return 1;
1519 }
1520 __setup("calgary=", calgary_parse_options);
1521
1522 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1523 {
1524         struct iommu_table *tbl;
1525         unsigned int npages;
1526         int i;
1527
1528         tbl = pci_iommu(dev->bus);
1529
1530         for (i = 0; i < 4; i++) {
1531                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1532
1533                 /* Don't give out TCEs that map MEM resources */
1534                 if (!(r->flags & IORESOURCE_MEM))
1535                         continue;
1536
1537                 /* 0-based? we reserve the whole 1st MB anyway */
1538                 if (!r->start)
1539                         continue;
1540
1541                 /* cover the whole region */
1542                 npages = resource_size(r) >> PAGE_SHIFT;
1543                 npages++;
1544
1545                 iommu_range_reserve(tbl, r->start, npages);
1546         }
1547 }
1548
1549 static int __init calgary_fixup_tce_spaces(void)
1550 {
1551         struct pci_dev *dev = NULL;
1552         struct calgary_bus_info *info;
1553
1554         if (no_iommu || swiotlb || !calgary_detected)
1555                 return -ENODEV;
1556
1557         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1558
1559         do {
1560                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1561                 if (!dev)
1562                         break;
1563                 if (!is_cal_pci_dev(dev->device))
1564                         continue;
1565
1566                 info = &bus_info[dev->bus->number];
1567                 if (info->translation_disabled)
1568                         continue;
1569
1570                 if (!info->tce_space)
1571                         continue;
1572
1573                 calgary_fixup_one_tce_space(dev);
1574
1575         } while (1);
1576
1577         return 0;
1578 }
1579
1580 /*
1581  * We need to be call after pcibios_assign_resources (fs_initcall level)
1582  * and before device_initcall.
1583  */
1584 rootfs_initcall(calgary_fixup_tce_spaces);
1585
1586 IOMMU_INIT_POST(detect_calgary);