2 * Common interrupt code for 32 and 64 bit
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
8 #include <linux/seq_file.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13 #include <linux/irq.h>
16 #include <asm/io_apic.h>
19 #include <asm/hw_irq.h>
22 #define CREATE_TRACE_POINTS
23 #include <asm/trace/irq_vectors.h>
25 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
26 EXPORT_PER_CPU_SYMBOL(irq_stat);
28 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
29 EXPORT_PER_CPU_SYMBOL(irq_regs);
31 atomic_t irq_err_count;
34 * 'what should we do if we get a hw irq event on an illegal vector'.
35 * each architecture has to answer this themselves.
37 void ack_bad_irq(unsigned int irq)
39 if (printk_ratelimit())
40 pr_err("unexpected IRQ trap at vector %02x\n", irq);
43 * Currently unexpected vectors happen only on SMP and APIC.
44 * We _must_ ack these because every local APIC has only N
45 * irq slots per priority level, and a 'hanging, unacked' IRQ
46 * holds up an irq slot - in excessive cases (when multiple
47 * unexpected vectors occur) that might lock up the APIC
49 * But only ack when the APIC is enabled -AK
54 #define irq_stats(x) (&per_cpu(irq_stat, x))
56 * /proc/interrupts printing for arch specific interrupts
58 int arch_show_interrupts(struct seq_file *p, int prec)
62 seq_printf(p, "%*s: ", prec, "NMI");
63 for_each_online_cpu(j)
64 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
65 seq_puts(p, " Non-maskable interrupts\n");
66 #ifdef CONFIG_X86_LOCAL_APIC
67 seq_printf(p, "%*s: ", prec, "LOC");
68 for_each_online_cpu(j)
69 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
70 seq_puts(p, " Local timer interrupts\n");
72 seq_printf(p, "%*s: ", prec, "SPU");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
75 seq_puts(p, " Spurious interrupts\n");
76 seq_printf(p, "%*s: ", prec, "PMI");
77 for_each_online_cpu(j)
78 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
79 seq_puts(p, " Performance monitoring interrupts\n");
80 seq_printf(p, "%*s: ", prec, "IWI");
81 for_each_online_cpu(j)
82 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
83 seq_puts(p, " IRQ work interrupts\n");
84 seq_printf(p, "%*s: ", prec, "RTR");
85 for_each_online_cpu(j)
86 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
87 seq_puts(p, " APIC ICR read retries\n");
88 if (x86_platform_ipi_callback) {
89 seq_printf(p, "%*s: ", prec, "PLT");
90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
92 seq_puts(p, " Platform interrupts\n");
96 seq_printf(p, "%*s: ", prec, "RES");
97 for_each_online_cpu(j)
98 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
99 seq_puts(p, " Rescheduling interrupts\n");
100 seq_printf(p, "%*s: ", prec, "CAL");
101 for_each_online_cpu(j)
102 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
103 seq_puts(p, " Function call interrupts\n");
104 seq_printf(p, "%*s: ", prec, "TLB");
105 for_each_online_cpu(j)
106 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
107 seq_puts(p, " TLB shootdowns\n");
109 #ifdef CONFIG_X86_THERMAL_VECTOR
110 seq_printf(p, "%*s: ", prec, "TRM");
111 for_each_online_cpu(j)
112 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
113 seq_puts(p, " Thermal event interrupts\n");
115 #ifdef CONFIG_X86_MCE_THRESHOLD
116 seq_printf(p, "%*s: ", prec, "THR");
117 for_each_online_cpu(j)
118 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
119 seq_puts(p, " Threshold APIC interrupts\n");
121 #ifdef CONFIG_X86_MCE_AMD
122 seq_printf(p, "%*s: ", prec, "DFR");
123 for_each_online_cpu(j)
124 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
125 seq_puts(p, " Deferred Error APIC interrupts\n");
127 #ifdef CONFIG_X86_MCE
128 seq_printf(p, "%*s: ", prec, "MCE");
129 for_each_online_cpu(j)
130 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
131 seq_puts(p, " Machine check exceptions\n");
132 seq_printf(p, "%*s: ", prec, "MCP");
133 for_each_online_cpu(j)
134 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
135 seq_puts(p, " Machine check polls\n");
137 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
138 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
139 seq_printf(p, "%*s: ", prec, "HYP");
140 for_each_online_cpu(j)
141 seq_printf(p, "%10u ",
142 irq_stats(j)->irq_hv_callback_count);
143 seq_puts(p, " Hypervisor callback interrupts\n");
146 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
147 #if defined(CONFIG_X86_IO_APIC)
148 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
150 #ifdef CONFIG_HAVE_KVM
151 seq_printf(p, "%*s: ", prec, "PIN");
152 for_each_online_cpu(j)
153 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
154 seq_puts(p, " Posted-interrupt notification event\n");
156 seq_printf(p, "%*s: ", prec, "NPI");
157 for_each_online_cpu(j)
158 seq_printf(p, "%10u ",
159 irq_stats(j)->kvm_posted_intr_nested_ipis);
160 seq_puts(p, " Nested posted-interrupt event\n");
162 seq_printf(p, "%*s: ", prec, "PIW");
163 for_each_online_cpu(j)
164 seq_printf(p, "%10u ",
165 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
166 seq_puts(p, " Posted-interrupt wakeup event\n");
174 u64 arch_irq_stat_cpu(unsigned int cpu)
176 u64 sum = irq_stats(cpu)->__nmi_count;
178 #ifdef CONFIG_X86_LOCAL_APIC
179 sum += irq_stats(cpu)->apic_timer_irqs;
180 sum += irq_stats(cpu)->irq_spurious_count;
181 sum += irq_stats(cpu)->apic_perf_irqs;
182 sum += irq_stats(cpu)->apic_irq_work_irqs;
183 sum += irq_stats(cpu)->icr_read_retry_count;
184 if (x86_platform_ipi_callback)
185 sum += irq_stats(cpu)->x86_platform_ipis;
188 sum += irq_stats(cpu)->irq_resched_count;
189 sum += irq_stats(cpu)->irq_call_count;
191 #ifdef CONFIG_X86_THERMAL_VECTOR
192 sum += irq_stats(cpu)->irq_thermal_count;
194 #ifdef CONFIG_X86_MCE_THRESHOLD
195 sum += irq_stats(cpu)->irq_threshold_count;
197 #ifdef CONFIG_X86_MCE
198 sum += per_cpu(mce_exception_count, cpu);
199 sum += per_cpu(mce_poll_count, cpu);
204 u64 arch_irq_stat(void)
206 u64 sum = atomic_read(&irq_err_count);
212 * do_IRQ handles all normal device IRQ's (the special
213 * SMP cross-CPU interrupts have their own specific
216 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
218 struct pt_regs *old_regs = set_irq_regs(regs);
219 struct irq_desc * desc;
220 /* high bit used in ret_from_ code */
221 unsigned vector = ~regs->orig_ax;
225 /* entering_irq() tells RCU that we're not quiescent. Check it. */
226 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
228 desc = __this_cpu_read(vector_irq[vector]);
230 if (!handle_irq(desc, regs)) {
233 if (desc != VECTOR_RETRIGGERED) {
234 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
235 __func__, smp_processor_id(),
238 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
244 set_irq_regs(old_regs);
248 #ifdef CONFIG_X86_LOCAL_APIC
249 /* Function pointer for generic interrupt vector handling */
250 void (*x86_platform_ipi_callback)(void) = NULL;
252 * Handler for X86_PLATFORM_IPI_VECTOR.
254 __visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
256 struct pt_regs *old_regs = set_irq_regs(regs);
259 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
260 inc_irq_stat(x86_platform_ipis);
261 if (x86_platform_ipi_callback)
262 x86_platform_ipi_callback();
263 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
265 set_irq_regs(old_regs);
269 #ifdef CONFIG_HAVE_KVM
270 static void dummy_handler(void) {}
271 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
273 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
276 kvm_posted_intr_wakeup_handler = handler;
278 kvm_posted_intr_wakeup_handler = dummy_handler;
282 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
285 * Handler for POSTED_INTERRUPT_VECTOR.
287 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
289 struct pt_regs *old_regs = set_irq_regs(regs);
292 inc_irq_stat(kvm_posted_intr_ipis);
294 set_irq_regs(old_regs);
298 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
300 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
302 struct pt_regs *old_regs = set_irq_regs(regs);
305 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
306 kvm_posted_intr_wakeup_handler();
308 set_irq_regs(old_regs);
312 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
314 __visible void smp_kvm_posted_intr_nested_ipi(struct pt_regs *regs)
316 struct pt_regs *old_regs = set_irq_regs(regs);
319 inc_irq_stat(kvm_posted_intr_nested_ipis);
321 set_irq_regs(old_regs);
326 #ifdef CONFIG_HOTPLUG_CPU
328 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
329 * below, which is protected by stop_machine(). Putting them on the stack
330 * results in a stack frame overflow. Dynamically allocating could result in a
331 * failure so declare these two cpumasks as global.
333 static struct cpumask affinity_new, online_new;
336 * This cpu is going to be removed and its vectors migrated to the remaining
337 * online cpus. Check to see if there are enough vectors in the remaining cpus.
338 * This function is protected by stop_machine().
340 int check_irq_vectors_for_cpu_disable(void)
342 unsigned int this_cpu, vector, this_count, count;
343 struct irq_desc *desc;
344 struct irq_data *data;
347 this_cpu = smp_processor_id();
348 cpumask_copy(&online_new, cpu_online_mask);
349 cpumask_clear_cpu(this_cpu, &online_new);
352 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
353 desc = __this_cpu_read(vector_irq[vector]);
354 if (IS_ERR_OR_NULL(desc))
357 * Protect against concurrent action removal, affinity
360 raw_spin_lock(&desc->lock);
361 data = irq_desc_get_irq_data(desc);
362 cpumask_copy(&affinity_new,
363 irq_data_get_affinity_mask(data));
364 cpumask_clear_cpu(this_cpu, &affinity_new);
366 /* Do not count inactive or per-cpu irqs. */
367 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
368 raw_spin_unlock(&desc->lock);
372 raw_spin_unlock(&desc->lock);
374 * A single irq may be mapped to multiple cpu's
375 * vector_irq[] (for example IOAPIC cluster mode). In
376 * this case we have two possibilities:
378 * 1) the resulting affinity mask is empty; that is
379 * this the down'd cpu is the last cpu in the irq's
382 * 2) the resulting affinity mask is no longer a
383 * subset of the online cpus but the affinity mask is
384 * not zero; that is the down'd cpu is the last online
385 * cpu in a user set affinity mask.
387 if (cpumask_empty(&affinity_new) ||
388 !cpumask_subset(&affinity_new, &online_new))
391 /* No need to check any further. */
396 for_each_online_cpu(cpu) {
400 * We scan from FIRST_EXTERNAL_VECTOR to first system
401 * vector. If the vector is marked in the used vectors
402 * bitmap or an irq is assigned to it, we don't count
405 * As this is an inaccurate snapshot anyway, we can do
406 * this w/o holding vector_lock.
408 for (vector = FIRST_EXTERNAL_VECTOR;
409 vector < FIRST_SYSTEM_VECTOR; vector++) {
410 if (!test_bit(vector, used_vectors) &&
411 IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector])) {
412 if (++count == this_count)
418 if (count < this_count) {
419 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
420 this_cpu, this_count, count);
426 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
427 void fixup_irqs(void)
429 unsigned int irr, vector;
430 struct irq_desc *desc;
431 struct irq_data *data;
432 struct irq_chip *chip;
434 irq_migrate_all_off_this_cpu();
437 * We can remove mdelay() and then send spuriuous interrupts to
438 * new cpu targets for all the irqs that were handled previously by
439 * this cpu. While it works, I have seen spurious interrupt messages
440 * (nothing wrong but still...).
442 * So for now, retain mdelay(1) and check the IRR and then send those
443 * interrupts to new targets as this cpu is already offlined...
448 * We can walk the vector array of this cpu without holding
449 * vector_lock because the cpu is already marked !online, so
450 * nothing else will touch it.
452 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
453 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
456 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
457 if (irr & (1 << (vector % 32))) {
458 desc = __this_cpu_read(vector_irq[vector]);
460 raw_spin_lock(&desc->lock);
461 data = irq_desc_get_irq_data(desc);
462 chip = irq_data_get_irq_chip(data);
463 if (chip->irq_retrigger) {
464 chip->irq_retrigger(data);
465 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
467 raw_spin_unlock(&desc->lock);
469 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
470 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);