1 // SPDX-License-Identifier: GPL-2.0-only
3 * Interrupt descriptor table related code
5 #include <linux/interrupt.h>
7 #include <asm/cpu_entry_area.h>
8 #include <asm/set_memory.h>
10 #include <asm/proto.h>
12 #include <asm/hw_irq.h>
13 #include <asm/idtentry.h>
18 #define DEFAULT_STACK 0
20 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \
28 .segment = _segment, \
32 #define INTG(_vector, _addr) \
33 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
35 /* System interrupt gate */
36 #define SYSG(_vector, _addr) \
37 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
41 * Interrupt gate with interrupt stack. The _ist index is the index in
42 * the tss.ist[] array, but for the descriptor it needs to start at 1.
44 #define ISTG(_vector, _addr, _ist) \
45 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
47 #define ISTG(_vector, _addr, _ist) INTG(_vector, _addr)
51 #define TSKG(_vector, _gdt) \
52 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
54 #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc))
56 static bool idt_setup_done __initdata;
59 * Early traps running on the DEFAULT_STACK because the other interrupt
60 * stacks work only after cpu_init().
62 static const __initconst struct idt_data early_idts[] = {
63 INTG(X86_TRAP_DB, asm_exc_debug),
64 SYSG(X86_TRAP_BP, asm_exc_int3),
68 * Not possible on 64-bit. See idt_setup_early_pf() for details.
70 INTG(X86_TRAP_PF, asm_exc_page_fault),
72 #ifdef CONFIG_INTEL_TDX_GUEST
73 INTG(X86_TRAP_VE, asm_exc_virtualization_exception),
78 * The default IDT entries which are set up in trap_init() before
79 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
80 * the traps which use them are reinitialized with IST after cpu_init() has
83 static const __initconst struct idt_data def_idts[] = {
84 INTG(X86_TRAP_DE, asm_exc_divide_error),
85 ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI),
86 INTG(X86_TRAP_BR, asm_exc_bounds),
87 INTG(X86_TRAP_UD, asm_exc_invalid_op),
88 INTG(X86_TRAP_NM, asm_exc_device_not_available),
89 INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun),
90 INTG(X86_TRAP_TS, asm_exc_invalid_tss),
91 INTG(X86_TRAP_NP, asm_exc_segment_not_present),
92 INTG(X86_TRAP_SS, asm_exc_stack_segment),
93 INTG(X86_TRAP_GP, asm_exc_general_protection),
94 INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug),
95 INTG(X86_TRAP_MF, asm_exc_coprocessor_error),
96 INTG(X86_TRAP_AC, asm_exc_alignment_check),
97 INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error),
100 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
102 ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF),
104 ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB),
106 #ifdef CONFIG_X86_MCE
107 ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE),
110 #ifdef CONFIG_X86_KERNEL_IBT
111 INTG(X86_TRAP_CP, asm_exc_control_protection),
114 #ifdef CONFIG_AMD_MEM_ENCRYPT
115 ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC),
118 SYSG(X86_TRAP_OF, asm_exc_overflow),
119 #if defined(CONFIG_IA32_EMULATION)
120 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
121 #elif defined(CONFIG_X86_32)
122 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
127 * The APIC and SMP idt entries
129 static const __initconst struct idt_data apic_idts[] = {
131 INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
132 INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
133 INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
134 INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
135 INTG(REBOOT_VECTOR, asm_sysvec_reboot),
138 #ifdef CONFIG_X86_THERMAL_VECTOR
139 INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal),
142 #ifdef CONFIG_X86_MCE_THRESHOLD
143 INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold),
146 #ifdef CONFIG_X86_MCE_AMD
147 INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error),
150 #ifdef CONFIG_X86_LOCAL_APIC
151 INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt),
152 INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi),
153 # ifdef CONFIG_HAVE_KVM
154 INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi),
155 INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi),
156 INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi),
158 # ifdef CONFIG_IRQ_WORK
159 INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work),
161 INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt),
162 INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt),
166 /* Must be page-aligned because the real IDT is used in the cpu entry area */
167 static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
169 static struct desc_ptr idt_descr __ro_after_init = {
170 .size = IDT_TABLE_SIZE - 1,
171 .address = (unsigned long) idt_table,
174 void load_current_idt(void)
176 lockdep_assert_irqs_disabled();
177 load_idt(&idt_descr);
180 #ifdef CONFIG_X86_F00F_BUG
181 bool idt_is_f00f_address(unsigned long address)
183 return ((address - idt_descr.address) >> 3) == 6;
188 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
192 for (; size > 0; t++, size--) {
193 idt_init_desc(&desc, t);
194 write_idt_entry(idt, t->vector, &desc);
196 set_bit(t->vector, system_vectors);
200 static __init void set_intr_gate(unsigned int n, const void *addr)
202 struct idt_data data;
204 init_idt_data(&data, n, addr);
206 idt_setup_from_table(idt_table, &data, 1, false);
210 * idt_setup_early_traps - Initialize the idt table with early traps
212 * On X8664 these traps do not use interrupt stacks as they can't work
213 * before cpu_init() is invoked and sets up TSS. The IST variants are
214 * installed after that.
216 void __init idt_setup_early_traps(void)
218 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
220 load_idt(&idt_descr);
224 * idt_setup_traps - Initialize the idt table with default traps
226 void __init idt_setup_traps(void)
228 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
233 * Early traps running on the DEFAULT_STACK because the other interrupt
234 * stacks work only after cpu_init().
236 static const __initconst struct idt_data early_pf_idts[] = {
237 INTG(X86_TRAP_PF, asm_exc_page_fault),
241 * idt_setup_early_pf - Initialize the idt table with early pagefault handler
243 * On X8664 this does not use interrupt stacks as they can't work before
244 * cpu_init() is invoked and sets up TSS. The IST variant is installed
247 * Note, that X86_64 cannot install the real #PF handler in
248 * idt_setup_early_traps() because the memory initialization needs the #PF
249 * handler from the early_idt_handler_array to initialize the early page
252 void __init idt_setup_early_pf(void)
254 idt_setup_from_table(idt_table, early_pf_idts,
255 ARRAY_SIZE(early_pf_idts), true);
259 static void __init idt_map_in_cea(void)
262 * Set the IDT descriptor to a fixed read-only location in the cpu
263 * entry area, so that the "sidt" instruction will not leak the
264 * location of the kernel, and to defend the IDT against arbitrary
265 * memory write vulnerabilities.
267 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
269 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
273 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
275 void __init idt_setup_apic_and_irq_gates(void)
277 int i = FIRST_EXTERNAL_VECTOR;
280 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
282 for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
283 entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR);
284 set_intr_gate(i, entry);
287 #ifdef CONFIG_X86_LOCAL_APIC
288 for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
290 * Don't set the non assigned system vectors in the
291 * system_vectors bitmap. Otherwise they show up in
294 entry = spurious_entries_start + IDT_ALIGN * (i - FIRST_SYSTEM_VECTOR);
295 set_intr_gate(i, entry);
298 /* Map IDT into CPU entry area and reload it. */
300 load_idt(&idt_descr);
302 /* Make the IDT table read only */
303 set_memory_ro((unsigned long)&idt_table, 1);
305 idt_setup_done = true;
309 * idt_setup_early_handler - Initializes the idt table with early handlers
311 void __init idt_setup_early_handler(void)
315 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
316 set_intr_gate(i, early_idt_handler_array[i]);
318 for ( ; i < NR_VECTORS; i++)
319 set_intr_gate(i, early_ignore_irq);
321 load_idt(&idt_descr);
325 * idt_invalidate - Invalidate interrupt descriptor table
327 void idt_invalidate(void)
329 static const struct desc_ptr idt = { .address = 0, .size = 0 };
334 void __init alloc_intr_gate(unsigned int n, const void *addr)
336 if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
339 if (WARN_ON(idt_setup_done))
342 if (!WARN_ON(test_and_set_bit(n, system_vectors)))
343 set_intr_gate(n, addr);