arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/i8253.h>
   8 #include <linux/slab.h>
   9 #include <linux/hpet.h>
  10 #include <linux/init.h>
  11 #include <linux/cpu.h>
  12 #include <linux/pm.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/cpufeature.h>
  16 #include <asm/irqdomain.h>
  17 #include <asm/fixmap.h>
  18 #include <asm/hpet.h>
  19 #include <asm/time.h>
  20
  21 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  22
  23 /* FSEC = 10^-15
  24    NSEC = 10^-9 */
  25 #define FSEC_PER_NSEC                   1000000L
  26
  27 #define HPET_DEV_USED_BIT               2
  28 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  29 #define HPET_DEV_VALID                  0x8
  30 #define HPET_DEV_FSB_CAP                0x1000
  31 #define HPET_DEV_PERI_CAP               0x2000
  32
  33 #define HPET_MIN_CYCLES                 128
  34 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  35
  36 /*
  37  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  38  */
  39 unsigned long                           hpet_address;
  40 u8                                      hpet_blockid; /* OS timer block num */
  41 bool                                    hpet_msi_disable;
  42
  43 #ifdef CONFIG_PCI_MSI
  44 static unsigned int                     hpet_num_timers;
  45 #endif
  46 static void __iomem                     *hpet_virt_address;
  47
  48 struct hpet_dev {
  49         struct clock_event_device       evt;
  50         unsigned int                    num;
  51         int                             cpu;
  52         unsigned int                    irq;
  53         unsigned int                    flags;
  54         char                            name[10];
  55 };
  56
  57 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
  58 {
  59         return container_of(evtdev, struct hpet_dev, evt);
  60 }
  61
  62 inline unsigned int hpet_readl(unsigned int a)
  63 {
  64         return readl(hpet_virt_address + a);
  65 }
  66
  67 static inline void hpet_writel(unsigned int d, unsigned int a)
  68 {
  69         writel(d, hpet_virt_address + a);
  70 }
  71
  72 #ifdef CONFIG_X86_64
  73 #include <asm/pgtable.h>
  74 #endif
  75
  76 static inline void hpet_set_mapping(void)
  77 {
  78         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  79 }
  80
  81 static inline void hpet_clear_mapping(void)
  82 {
  83         iounmap(hpet_virt_address);
  84         hpet_virt_address = NULL;
  85 }
  86
  87 /*
  88  * HPET command line enable / disable
  89  */
  90 bool boot_hpet_disable;
  91 bool hpet_force_user;
  92 static bool hpet_verbose;
  93
  94 static int __init hpet_setup(char *str)
  95 {
  96         while (str) {
  97                 char *next = strchr(str, ',');
  98
  99                 if (next)
 100                         *next++ = 0;
 101                 if (!strncmp("disable", str, 7))
 102                         boot_hpet_disable = true;
 103                 if (!strncmp("force", str, 5))
 104                         hpet_force_user = true;
 105                 if (!strncmp("verbose", str, 7))
 106                         hpet_verbose = true;
 107                 str = next;
 108         }
 109         return 1;
 110 }
 111 __setup("hpet=", hpet_setup);
 112
 113 static int __init disable_hpet(char *str)
 114 {
 115         boot_hpet_disable = true;
 116         return 1;
 117 }
 118 __setup("nohpet", disable_hpet);
 119
 120 static inline int is_hpet_capable(void)
 121 {
 122         return !boot_hpet_disable && hpet_address;
 123 }
 124
 125 /*
 126  * HPET timer interrupt enable / disable
 127  */
 128 static bool hpet_legacy_int_enabled;
 129
 130 /**
 131  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 132  */
 133 int is_hpet_enabled(void)
 134 {
 135         return is_hpet_capable() && hpet_legacy_int_enabled;
 136 }
 137 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 138
 139 static void _hpet_print_config(const char *function, int line)
 140 {
 141         u32 i, timers, l, h;
 142         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 143         l = hpet_readl(HPET_ID);
 144         h = hpet_readl(HPET_PERIOD);
 145         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 146         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 147         l = hpet_readl(HPET_CFG);
 148         h = hpet_readl(HPET_STATUS);
 149         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 150         l = hpet_readl(HPET_COUNTER);
 151         h = hpet_readl(HPET_COUNTER+4);
 152         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 153
 154         for (i = 0; i < timers; i++) {
 155                 l = hpet_readl(HPET_Tn_CFG(i));
 156                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 157                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 158                        i, l, h);
 159                 l = hpet_readl(HPET_Tn_CMP(i));
 160                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 161                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 162                        i, l, h);
 163                 l = hpet_readl(HPET_Tn_ROUTE(i));
 164                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 165                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 166                        i, l, h);
 167         }
 168 }
 169
 170 #define hpet_print_config()                                     \
 171 do {                                                            \
 172         if (hpet_verbose)                                       \
 173                 _hpet_print_config(__func__, __LINE__); \
 174 } while (0)
 175
 176 /*
 177  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 178  * timer 0 and timer 1 in case of RTC emulation.
 179  */
 180 #ifdef CONFIG_HPET
 181
 182 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 183
 184 static void hpet_reserve_platform_timers(unsigned int id)
 185 {
 186         struct hpet __iomem *hpet = hpet_virt_address;
 187         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 188         unsigned int nrtimers, i;
 189         struct hpet_data hd;
 190
 191         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 192
 193         memset(&hd, 0, sizeof(hd));
 194         hd.hd_phys_address      = hpet_address;
 195         hd.hd_address           = hpet;
 196         hd.hd_nirqs             = nrtimers;
 197         hpet_reserve_timer(&hd, 0);
 198
 199 #ifdef CONFIG_HPET_EMULATE_RTC
 200         hpet_reserve_timer(&hd, 1);
 201 #endif
 202
 203         /*
 204          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 205          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 206          * don't bother configuring *any* comparator interrupts.
 207          */
 208         hd.hd_irq[0] = HPET_LEGACY_8254;
 209         hd.hd_irq[1] = HPET_LEGACY_RTC;
 210
 211         for (i = 2; i < nrtimers; timer++, i++) {
 212                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 213                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 214         }
 215
 216         hpet_reserve_msi_timers(&hd);
 217
 218         hpet_alloc(&hd);
 219
 220 }
 221 #else
 222 static void hpet_reserve_platform_timers(unsigned int id) { }
 223 #endif
 224
 225 /*
 226  * Common hpet info
 227  */
 228 static unsigned long hpet_freq;
 229
 230 static struct clock_event_device hpet_clockevent;
 231
 232 static void hpet_stop_counter(void)
 233 {
 234         u32 cfg = hpet_readl(HPET_CFG);
 235         cfg &= ~HPET_CFG_ENABLE;
 236         hpet_writel(cfg, HPET_CFG);
 237 }
 238
 239 static void hpet_reset_counter(void)
 240 {
 241         hpet_writel(0, HPET_COUNTER);
 242         hpet_writel(0, HPET_COUNTER + 4);
 243 }
 244
 245 static void hpet_start_counter(void)
 246 {
 247         unsigned int cfg = hpet_readl(HPET_CFG);
 248         cfg |= HPET_CFG_ENABLE;
 249         hpet_writel(cfg, HPET_CFG);
 250 }
 251
 252 static void hpet_restart_counter(void)
 253 {
 254         hpet_stop_counter();
 255         hpet_reset_counter();
 256         hpet_start_counter();
 257 }
 258
 259 static void hpet_resume_device(void)
 260 {
 261         force_hpet_resume();
 262 }
 263
 264 static void hpet_resume_counter(struct clocksource *cs)
 265 {
 266         hpet_resume_device();
 267         hpet_restart_counter();
 268 }
 269
 270 static void hpet_enable_legacy_int(void)
 271 {
 272         unsigned int cfg = hpet_readl(HPET_CFG);
 273
 274         cfg |= HPET_CFG_LEGACY;
 275         hpet_writel(cfg, HPET_CFG);
 276         hpet_legacy_int_enabled = true;
 277 }
 278
 279 static void hpet_legacy_clockevent_register(void)
 280 {
 281         /* Start HPET legacy interrupts */
 282         hpet_enable_legacy_int();
 283
 284         /*
 285          * Start hpet with the boot cpu mask and make it
 286          * global after the IO_APIC has been initialized.
 287          */
 288         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 289         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 290                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 291         global_clock_event = &hpet_clockevent;
 292         printk(KERN_DEBUG "hpet clockevent registered\n");
 293 }
 294
 295 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
 296 {
 297         unsigned int cfg, cmp, now;
 298         uint64_t delta;
 299
 300         hpet_stop_counter();
 301         delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
 302         delta >>= evt->shift;
 303         now = hpet_readl(HPET_COUNTER);
 304         cmp = now + (unsigned int)delta;
 305         cfg = hpet_readl(HPET_Tn_CFG(timer));
 306         cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
 307                HPET_TN_32BIT;
 308         hpet_writel(cfg, HPET_Tn_CFG(timer));
 309         hpet_writel(cmp, HPET_Tn_CMP(timer));
 310         udelay(1);
 311         /*
 312          * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 313          * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 314          * bit is automatically cleared after the first write.
 315          * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 316          * Publication # 24674)
 317          */
 318         hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
 319         hpet_start_counter();
 320         hpet_print_config();
 321
 322         return 0;
 323 }
 324
 325 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
 326 {
 327         unsigned int cfg;
 328
 329         cfg = hpet_readl(HPET_Tn_CFG(timer));
 330         cfg &= ~HPET_TN_PERIODIC;
 331         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 332         hpet_writel(cfg, HPET_Tn_CFG(timer));
 333
 334         return 0;
 335 }
 336
 337 static int hpet_shutdown(struct clock_event_device *evt, int timer)
 338 {
 339         unsigned int cfg;
 340
 341         cfg = hpet_readl(HPET_Tn_CFG(timer));
 342         cfg &= ~HPET_TN_ENABLE;
 343         hpet_writel(cfg, HPET_Tn_CFG(timer));
 344
 345         return 0;
 346 }
 347
 348 static int hpet_resume(struct clock_event_device *evt, int timer)
 349 {
 350         if (!timer) {
 351                 hpet_enable_legacy_int();
 352         } else {
 353                 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 354
 355                 irq_domain_deactivate_irq(irq_get_irq_data(hdev->irq));
 356                 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
 357                 disable_hardirq(hdev->irq);
 358                 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 359                 enable_irq(hdev->irq);
 360         }
 361         hpet_print_config();
 362
 363         return 0;
 364 }
 365
 366 static int hpet_next_event(unsigned long delta,
 367                            struct clock_event_device *evt, int timer)
 368 {
 369         u32 cnt;
 370         s32 res;
 371
 372         cnt = hpet_readl(HPET_COUNTER);
 373         cnt += (u32) delta;
 374         hpet_writel(cnt, HPET_Tn_CMP(timer));
 375
 376         /*
 377          * HPETs are a complete disaster. The compare register is
 378          * based on a equal comparison and neither provides a less
 379          * than or equal functionality (which would require to take
 380          * the wraparound into account) nor a simple count down event
 381          * mode. Further the write to the comparator register is
 382          * delayed internally up to two HPET clock cycles in certain
 383          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 384          * longer delays. We worked around that by reading back the
 385          * compare register, but that required another workaround for
 386          * ICH9,10 chips where the first readout after write can
 387          * return the old stale value. We already had a minimum
 388          * programming delta of 5us enforced, but a NMI or SMI hitting
 389          * between the counter readout and the comparator write can
 390          * move us behind that point easily. Now instead of reading
 391          * the compare register back several times, we make the ETIME
 392          * decision based on the following: Return ETIME if the
 393          * counter value after the write is less than HPET_MIN_CYCLES
 394          * away from the event or if the counter is already ahead of
 395          * the event. The minimum programming delta for the generic
 396          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 397          */
 398         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 399
 400         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 401 }
 402
 403 static int hpet_legacy_shutdown(struct clock_event_device *evt)
 404 {
 405         return hpet_shutdown(evt, 0);
 406 }
 407
 408 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
 409 {
 410         return hpet_set_oneshot(evt, 0);
 411 }
 412
 413 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
 414 {
 415         return hpet_set_periodic(evt, 0);
 416 }
 417
 418 static int hpet_legacy_resume(struct clock_event_device *evt)
 419 {
 420         return hpet_resume(evt, 0);
 421 }
 422
 423 static int hpet_legacy_next_event(unsigned long delta,
 424                         struct clock_event_device *evt)
 425 {
 426         return hpet_next_event(delta, evt, 0);
 427 }
 428
 429 /*
 430  * The hpet clock event device
 431  */
 432 static struct clock_event_device hpet_clockevent = {
 433         .name                   = "hpet",
 434         .features               = CLOCK_EVT_FEAT_PERIODIC |
 435                                   CLOCK_EVT_FEAT_ONESHOT,
 436         .set_state_periodic     = hpet_legacy_set_periodic,
 437         .set_state_oneshot      = hpet_legacy_set_oneshot,
 438         .set_state_shutdown     = hpet_legacy_shutdown,
 439         .tick_resume            = hpet_legacy_resume,
 440         .set_next_event         = hpet_legacy_next_event,
 441         .irq                    = 0,
 442         .rating                 = 50,
 443 };
 444
 445 /*
 446  * HPET MSI Support
 447  */
 448 #ifdef CONFIG_PCI_MSI
 449
 450 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 451 static struct hpet_dev  *hpet_devs;
 452 static struct irq_domain *hpet_domain;
 453
 454 void hpet_msi_unmask(struct irq_data *data)
 455 {
 456         struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
 457         unsigned int cfg;
 458
 459         /* unmask it */
 460         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 461         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
 462         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 463 }
 464
 465 void hpet_msi_mask(struct irq_data *data)
 466 {
 467         struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
 468         unsigned int cfg;
 469
 470         /* mask it */
 471         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 472         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
 473         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 474 }
 475
 476 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 477 {
 478         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 479         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 480 }
 481
 482 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 483 {
 484         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 485         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 486         msg->address_hi = 0;
 487 }
 488
 489 static int hpet_msi_shutdown(struct clock_event_device *evt)
 490 {
 491         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 492
 493         return hpet_shutdown(evt, hdev->num);
 494 }
 495
 496 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
 497 {
 498         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 499
 500         return hpet_set_oneshot(evt, hdev->num);
 501 }
 502
 503 static int hpet_msi_set_periodic(struct clock_event_device *evt)
 504 {
 505         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 506
 507         return hpet_set_periodic(evt, hdev->num);
 508 }
 509
 510 static int hpet_msi_resume(struct clock_event_device *evt)
 511 {
 512         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 513
 514         return hpet_resume(evt, hdev->num);
 515 }
 516
 517 static int hpet_msi_next_event(unsigned long delta,
 518                                 struct clock_event_device *evt)
 519 {
 520         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 521         return hpet_next_event(delta, evt, hdev->num);
 522 }
 523
 524 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 525 {
 526         struct hpet_dev *dev = (struct hpet_dev *)data;
 527         struct clock_event_device *hevt = &dev->evt;
 528
 529         if (!hevt->event_handler) {
 530                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 531                                 dev->num);
 532                 return IRQ_HANDLED;
 533         }
 534
 535         hevt->event_handler(hevt);
 536         return IRQ_HANDLED;
 537 }
 538
 539 static int hpet_setup_irq(struct hpet_dev *dev)
 540 {
 541
 542         if (request_irq(dev->irq, hpet_interrupt_handler,
 543                         IRQF_TIMER | IRQF_NOBALANCING,
 544                         dev->name, dev))
 545                 return -1;
 546
 547         disable_irq(dev->irq);
 548         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 549         enable_irq(dev->irq);
 550
 551         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 552                          dev->name, dev->irq);
 553
 554         return 0;
 555 }
 556
 557 /* This should be called in specific @cpu */
 558 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 559 {
 560         struct clock_event_device *evt = &hdev->evt;
 561
 562         WARN_ON(cpu != smp_processor_id());
 563         if (!(hdev->flags & HPET_DEV_VALID))
 564                 return;
 565
 566         hdev->cpu = cpu;
 567         per_cpu(cpu_hpet_dev, cpu) = hdev;
 568         evt->name = hdev->name;
 569         hpet_setup_irq(hdev);
 570         evt->irq = hdev->irq;
 571
 572         evt->rating = 110;
 573         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 574         if (hdev->flags & HPET_DEV_PERI_CAP) {
 575                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 576                 evt->set_state_periodic = hpet_msi_set_periodic;
 577         }
 578
 579         evt->set_state_shutdown = hpet_msi_shutdown;
 580         evt->set_state_oneshot = hpet_msi_set_oneshot;
 581         evt->tick_resume = hpet_msi_resume;
 582         evt->set_next_event = hpet_msi_next_event;
 583         evt->cpumask = cpumask_of(hdev->cpu);
 584
 585         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 586                                         0x7FFFFFFF);
 587 }
 588
 589 #ifdef CONFIG_HPET
 590 /* Reserve at least one timer for userspace (/dev/hpet) */
 591 #define RESERVE_TIMERS 1
 592 #else
 593 #define RESERVE_TIMERS 0
 594 #endif
 595
 596 static void hpet_msi_capability_lookup(unsigned int start_timer)
 597 {
 598         unsigned int id;
 599         unsigned int num_timers;
 600         unsigned int num_timers_used = 0;
 601         int i, irq;
 602
 603         if (hpet_msi_disable)
 604                 return;
 605
 606         if (boot_cpu_has(X86_FEATURE_ARAT))
 607                 return;
 608         id = hpet_readl(HPET_ID);
 609
 610         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 611         num_timers++; /* Value read out starts from 0 */
 612         hpet_print_config();
 613
 614         hpet_domain = hpet_create_irq_domain(hpet_blockid);
 615         if (!hpet_domain)
 616                 return;
 617
 618         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 619         if (!hpet_devs)
 620                 return;
 621
 622         hpet_num_timers = num_timers;
 623
 624         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 625                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 626                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 627
 628                 /* Only consider HPET timer with MSI support */
 629                 if (!(cfg & HPET_TN_FSB_CAP))
 630                         continue;
 631
 632                 hdev->flags = 0;
 633                 if (cfg & HPET_TN_PERIODIC_CAP)
 634                         hdev->flags |= HPET_DEV_PERI_CAP;
 635                 sprintf(hdev->name, "hpet%d", i);
 636                 hdev->num = i;
 637
 638                 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
 639                 if (irq <= 0)
 640                         continue;
 641
 642                 hdev->irq = irq;
 643                 hdev->flags |= HPET_DEV_FSB_CAP;
 644                 hdev->flags |= HPET_DEV_VALID;
 645                 num_timers_used++;
 646                 if (num_timers_used == num_possible_cpus())
 647                         break;
 648         }
 649
 650         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 651                 num_timers, num_timers_used);
 652 }
 653
 654 #ifdef CONFIG_HPET
 655 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 656 {
 657         int i;
 658
 659         if (!hpet_devs)
 660                 return;
 661
 662         for (i = 0; i < hpet_num_timers; i++) {
 663                 struct hpet_dev *hdev = &hpet_devs[i];
 664
 665                 if (!(hdev->flags & HPET_DEV_VALID))
 666                         continue;
 667
 668                 hd->hd_irq[hdev->num] = hdev->irq;
 669                 hpet_reserve_timer(hd, hdev->num);
 670         }
 671 }
 672 #endif
 673
 674 static struct hpet_dev *hpet_get_unused_timer(void)
 675 {
 676         int i;
 677
 678         if (!hpet_devs)
 679                 return NULL;
 680
 681         for (i = 0; i < hpet_num_timers; i++) {
 682                 struct hpet_dev *hdev = &hpet_devs[i];
 683
 684                 if (!(hdev->flags & HPET_DEV_VALID))
 685                         continue;
 686                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 687                         (unsigned long *)&hdev->flags))
 688                         continue;
 689                 return hdev;
 690         }
 691         return NULL;
 692 }
 693
 694 struct hpet_work_struct {
 695         struct delayed_work work;
 696         struct completion complete;
 697 };
 698
 699 static void hpet_work(struct work_struct *w)
 700 {
 701         struct hpet_dev *hdev;
 702         int cpu = smp_processor_id();
 703         struct hpet_work_struct *hpet_work;
 704
 705         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 706
 707         hdev = hpet_get_unused_timer();
 708         if (hdev)
 709                 init_one_hpet_msi_clockevent(hdev, cpu);
 710
 711         complete(&hpet_work->complete);
 712 }
 713
 714 static int hpet_cpuhp_notify(struct notifier_block *n,
 715                 unsigned long action, void *hcpu)
 716 {
 717         unsigned long cpu = (unsigned long)hcpu;
 718         struct hpet_work_struct work;
 719         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 720
 721         switch (action & 0xf) {
 722         case CPU_ONLINE:
 723                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 724                 init_completion(&work.complete);
 725                 /* FIXME: add schedule_work_on() */
 726                 schedule_delayed_work_on(cpu, &work.work, 0);
 727                 wait_for_completion(&work.complete);
 728                 destroy_delayed_work_on_stack(&work.work);
 729                 break;
 730         case CPU_DEAD:
 731                 if (hdev) {
 732                         free_irq(hdev->irq, hdev);
 733                         hdev->flags &= ~HPET_DEV_USED;
 734                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 735                 }
 736                 break;
 737         }
 738         return NOTIFY_OK;
 739 }
 740 #else
 741
 742 static void hpet_msi_capability_lookup(unsigned int start_timer)
 743 {
 744         return;
 745 }
 746
 747 #ifdef CONFIG_HPET
 748 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 749 {
 750         return;
 751 }
 752 #endif
 753
 754 static int hpet_cpuhp_notify(struct notifier_block *n,
 755                 unsigned long action, void *hcpu)
 756 {
 757         return NOTIFY_OK;
 758 }
 759
 760 #endif
 761
 762 /*
 763  * Clock source related code
 764  */
 765 static cycle_t read_hpet(struct clocksource *cs)
 766 {
 767         return (cycle_t)hpet_readl(HPET_COUNTER);
 768 }
 769
 770 static struct clocksource clocksource_hpet = {
 771         .name           = "hpet",
 772         .rating         = 250,
 773         .read           = read_hpet,
 774         .mask           = HPET_MASK,
 775         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 776         .resume         = hpet_resume_counter,
 777 };
 778
 779 static int hpet_clocksource_register(void)
 780 {
 781         u64 start, now;
 782         cycle_t t1;
 783
 784         /* Start the counter */
 785         hpet_restart_counter();
 786
 787         /* Verify whether hpet counter works */
 788         t1 = hpet_readl(HPET_COUNTER);
 789         start = rdtsc();
 790
 791         /*
 792          * We don't know the TSC frequency yet, but waiting for
 793          * 200000 TSC cycles is safe:
 794          * 4 GHz == 50us
 795          * 1 GHz == 200us
 796          */
 797         do {
 798                 rep_nop();
 799                 now = rdtsc();
 800         } while ((now - start) < 200000UL);
 801
 802         if (t1 == hpet_readl(HPET_COUNTER)) {
 803                 printk(KERN_WARNING
 804                        "HPET counter not counting. HPET disabled\n");
 805                 return -ENODEV;
 806         }
 807
 808         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 809         return 0;
 810 }
 811
 812 static u32 *hpet_boot_cfg;
 813
 814 /**
 815  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 816  */
 817 int __init hpet_enable(void)
 818 {
 819         u32 hpet_period, cfg, id;
 820         u64 freq;
 821         unsigned int i, last;
 822
 823         if (!is_hpet_capable())
 824                 return 0;
 825
 826         hpet_set_mapping();
 827         if (!hpet_virt_address)
 828                 return 0;
 829
 830         /*
 831          * Read the period and check for a sane value:
 832          */
 833         hpet_period = hpet_readl(HPET_PERIOD);
 834
 835         /*
 836          * AMD SB700 based systems with spread spectrum enabled use a
 837          * SMM based HPET emulation to provide proper frequency
 838          * setting. The SMM code is initialized with the first HPET
 839          * register access and takes some time to complete. During
 840          * this time the config register reads 0xffffffff. We check
 841          * for max. 1000 loops whether the config register reads a non
 842          * 0xffffffff value to make sure that HPET is up and running
 843          * before we go further. A counting loop is safe, as the HPET
 844          * access takes thousands of CPU cycles. On non SB700 based
 845          * machines this check is only done once and has no side
 846          * effects.
 847          */
 848         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 849                 if (i == 1000) {
 850                         printk(KERN_WARNING
 851                                "HPET config register value = 0xFFFFFFFF. "
 852                                "Disabling HPET\n");
 853                         goto out_nohpet;
 854                 }
 855         }
 856
 857         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 858                 goto out_nohpet;
 859
 860         /*
 861          * The period is a femto seconds value. Convert it to a
 862          * frequency.
 863          */
 864         freq = FSEC_PER_SEC;
 865         do_div(freq, hpet_period);
 866         hpet_freq = freq;
 867
 868         /*
 869          * Read the HPET ID register to retrieve the IRQ routing
 870          * information and the number of channels
 871          */
 872         id = hpet_readl(HPET_ID);
 873         hpet_print_config();
 874
 875         last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
 876
 877 #ifdef CONFIG_HPET_EMULATE_RTC
 878         /*
 879          * The legacy routing mode needs at least two channels, tick timer
 880          * and the rtc emulation channel.
 881          */
 882         if (!last)
 883                 goto out_nohpet;
 884 #endif
 885
 886         cfg = hpet_readl(HPET_CFG);
 887         hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
 888                                 GFP_KERNEL);
 889         if (hpet_boot_cfg)
 890                 *hpet_boot_cfg = cfg;
 891         else
 892                 pr_warn("HPET initial state will not be saved\n");
 893         cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
 894         hpet_writel(cfg, HPET_CFG);
 895         if (cfg)
 896                 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
 897                         cfg);
 898
 899         for (i = 0; i <= last; ++i) {
 900                 cfg = hpet_readl(HPET_Tn_CFG(i));
 901                 if (hpet_boot_cfg)
 902                         hpet_boot_cfg[i + 1] = cfg;
 903                 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
 904                 hpet_writel(cfg, HPET_Tn_CFG(i));
 905                 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
 906                          | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
 907                          | HPET_TN_FSB | HPET_TN_FSB_CAP);
 908                 if (cfg)
 909                         pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
 910                                 cfg, i);
 911         }
 912         hpet_print_config();
 913
 914         if (hpet_clocksource_register())
 915                 goto out_nohpet;
 916
 917         if (id & HPET_ID_LEGSUP) {
 918                 hpet_legacy_clockevent_register();
 919                 return 1;
 920         }
 921         return 0;
 922
 923 out_nohpet:
 924         hpet_clear_mapping();
 925         hpet_address = 0;
 926         return 0;
 927 }
 928
 929 /*
 930  * Needs to be late, as the reserve_timer code calls kalloc !
 931  *
 932  * Not a problem on i386 as hpet_enable is called from late_time_init,
 933  * but on x86_64 it is necessary !
 934  */
 935 static __init int hpet_late_init(void)
 936 {
 937         int cpu;
 938
 939         if (boot_hpet_disable)
 940                 return -ENODEV;
 941
 942         if (!hpet_address) {
 943                 if (!force_hpet_address)
 944                         return -ENODEV;
 945
 946                 hpet_address = force_hpet_address;
 947                 hpet_enable();
 948         }
 949
 950         if (!hpet_virt_address)
 951                 return -ENODEV;
 952
 953         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 954                 hpet_msi_capability_lookup(2);
 955         else
 956                 hpet_msi_capability_lookup(0);
 957
 958         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 959         hpet_print_config();
 960
 961         if (hpet_msi_disable)
 962                 return 0;
 963
 964         if (boot_cpu_has(X86_FEATURE_ARAT))
 965                 return 0;
 966
 967         cpu_notifier_register_begin();
 968         for_each_online_cpu(cpu) {
 969                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 970         }
 971
 972         /* This notifier should be called after workqueue is ready */
 973         __hotcpu_notifier(hpet_cpuhp_notify, -20);
 974         cpu_notifier_register_done();
 975
 976         return 0;
 977 }
 978 fs_initcall(hpet_late_init);
 979
 980 void hpet_disable(void)
 981 {
 982         if (is_hpet_capable() && hpet_virt_address) {
 983                 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
 984
 985                 if (hpet_boot_cfg)
 986                         cfg = *hpet_boot_cfg;
 987                 else if (hpet_legacy_int_enabled) {
 988                         cfg &= ~HPET_CFG_LEGACY;
 989                         hpet_legacy_int_enabled = false;
 990                 }
 991                 cfg &= ~HPET_CFG_ENABLE;
 992                 hpet_writel(cfg, HPET_CFG);
 993
 994                 if (!hpet_boot_cfg)
 995                         return;
 996
 997                 id = hpet_readl(HPET_ID);
 998                 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 999
1000                 for (id = 0; id <= last; ++id)
1001                         hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1002
1003                 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1004                         hpet_writel(*hpet_boot_cfg, HPET_CFG);
1005         }
1006 }
1007
1008 #ifdef CONFIG_HPET_EMULATE_RTC
1009
1010 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1011  * is enabled, we support RTC interrupt functionality in software.
1012  * RTC has 3 kinds of interrupts:
1013  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1014  *    is updated
1015  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1016  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1017  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1018  * (1) and (2) above are implemented using polling at a frequency of
1019  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1020  * overhead. (DEFAULT_RTC_INT_FREQ)
1021  * For (3), we use interrupts at 64Hz or user specified periodic
1022  * frequency, whichever is higher.
1023  */
1024 #include <linux/mc146818rtc.h>
1025 #include <linux/rtc.h>
1026 #include <asm/rtc.h>
1027
1028 #define DEFAULT_RTC_INT_FREQ    64
1029 #define DEFAULT_RTC_SHIFT       6
1030 #define RTC_NUM_INTS            1
1031
1032 static unsigned long hpet_rtc_flags;
1033 static int hpet_prev_update_sec;
1034 static struct rtc_time hpet_alarm_time;
1035 static unsigned long hpet_pie_count;
1036 static u32 hpet_t1_cmp;
1037 static u32 hpet_default_delta;
1038 static u32 hpet_pie_delta;
1039 static unsigned long hpet_pie_limit;
1040
1041 static rtc_irq_handler irq_handler;
1042
1043 /*
1044  * Check that the hpet counter c1 is ahead of the c2
1045  */
1046 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1047 {
1048         return (s32)(c2 - c1) < 0;
1049 }
1050
1051 /*
1052  * Registers a IRQ handler.
1053  */
1054 int hpet_register_irq_handler(rtc_irq_handler handler)
1055 {
1056         if (!is_hpet_enabled())
1057                 return -ENODEV;
1058         if (irq_handler)
1059                 return -EBUSY;
1060
1061         irq_handler = handler;
1062
1063         return 0;
1064 }
1065 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1066
1067 /*
1068  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1069  * and does cleanup.
1070  */
1071 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1072 {
1073         if (!is_hpet_enabled())
1074                 return;
1075
1076         irq_handler = NULL;
1077         hpet_rtc_flags = 0;
1078 }
1079 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1080
1081 /*
1082  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1083  * is not supported by all HPET implementations for timer 1.
1084  *
1085  * hpet_rtc_timer_init() is called when the rtc is initialized.
1086  */
1087 int hpet_rtc_timer_init(void)
1088 {
1089         unsigned int cfg, cnt, delta;
1090         unsigned long flags;
1091
1092         if (!is_hpet_enabled())
1093                 return 0;
1094
1095         if (!hpet_default_delta) {
1096                 uint64_t clc;
1097
1098                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1099                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1100                 hpet_default_delta = clc;
1101         }
1102
1103         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1104                 delta = hpet_default_delta;
1105         else
1106                 delta = hpet_pie_delta;
1107
1108         local_irq_save(flags);
1109
1110         cnt = delta + hpet_readl(HPET_COUNTER);
1111         hpet_writel(cnt, HPET_T1_CMP);
1112         hpet_t1_cmp = cnt;
1113
1114         cfg = hpet_readl(HPET_T1_CFG);
1115         cfg &= ~HPET_TN_PERIODIC;
1116         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1117         hpet_writel(cfg, HPET_T1_CFG);
1118
1119         local_irq_restore(flags);
1120
1121         return 1;
1122 }
1123 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1124
1125 static void hpet_disable_rtc_channel(void)
1126 {
1127         u32 cfg = hpet_readl(HPET_T1_CFG);
1128         cfg &= ~HPET_TN_ENABLE;
1129         hpet_writel(cfg, HPET_T1_CFG);
1130 }
1131
1132 /*
1133  * The functions below are called from rtc driver.
1134  * Return 0 if HPET is not being used.
1135  * Otherwise do the necessary changes and return 1.
1136  */
1137 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1138 {
1139         if (!is_hpet_enabled())
1140                 return 0;
1141
1142         hpet_rtc_flags &= ~bit_mask;
1143         if (unlikely(!hpet_rtc_flags))
1144                 hpet_disable_rtc_channel();
1145
1146         return 1;
1147 }
1148 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1149
1150 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1151 {
1152         unsigned long oldbits = hpet_rtc_flags;
1153
1154         if (!is_hpet_enabled())
1155                 return 0;
1156
1157         hpet_rtc_flags |= bit_mask;
1158
1159         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1160                 hpet_prev_update_sec = -1;
1161
1162         if (!oldbits)
1163                 hpet_rtc_timer_init();
1164
1165         return 1;
1166 }
1167 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1168
1169 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1170                         unsigned char sec)
1171 {
1172         if (!is_hpet_enabled())
1173                 return 0;
1174
1175         hpet_alarm_time.tm_hour = hrs;
1176         hpet_alarm_time.tm_min = min;
1177         hpet_alarm_time.tm_sec = sec;
1178
1179         return 1;
1180 }
1181 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1182
1183 int hpet_set_periodic_freq(unsigned long freq)
1184 {
1185         uint64_t clc;
1186
1187         if (!is_hpet_enabled())
1188                 return 0;
1189
1190         if (freq <= DEFAULT_RTC_INT_FREQ)
1191                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1192         else {
1193                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1194                 do_div(clc, freq);
1195                 clc >>= hpet_clockevent.shift;
1196                 hpet_pie_delta = clc;
1197                 hpet_pie_limit = 0;
1198         }
1199         return 1;
1200 }
1201 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1202
1203 int hpet_rtc_dropped_irq(void)
1204 {
1205         return is_hpet_enabled();
1206 }
1207 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1208
1209 static void hpet_rtc_timer_reinit(void)
1210 {
1211         unsigned int delta;
1212         int lost_ints = -1;
1213
1214         if (unlikely(!hpet_rtc_flags))
1215                 hpet_disable_rtc_channel();
1216
1217         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1218                 delta = hpet_default_delta;
1219         else
1220                 delta = hpet_pie_delta;
1221
1222         /*
1223          * Increment the comparator value until we are ahead of the
1224          * current count.
1225          */
1226         do {
1227                 hpet_t1_cmp += delta;
1228                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1229                 lost_ints++;
1230         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1231
1232         if (lost_ints) {
1233                 if (hpet_rtc_flags & RTC_PIE)
1234                         hpet_pie_count += lost_ints;
1235                 if (printk_ratelimit())
1236                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1237                                 lost_ints);
1238         }
1239 }
1240
1241 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1242 {
1243         struct rtc_time curr_time;
1244         unsigned long rtc_int_flag = 0;
1245
1246         hpet_rtc_timer_reinit();
1247         memset(&curr_time, 0, sizeof(struct rtc_time));
1248
1249         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1250                 get_rtc_time(&curr_time);
1251
1252         if (hpet_rtc_flags & RTC_UIE &&
1253             curr_time.tm_sec != hpet_prev_update_sec) {
1254                 if (hpet_prev_update_sec >= 0)
1255                         rtc_int_flag = RTC_UF;
1256                 hpet_prev_update_sec = curr_time.tm_sec;
1257         }
1258
1259         if (hpet_rtc_flags & RTC_PIE &&
1260             ++hpet_pie_count >= hpet_pie_limit) {
1261                 rtc_int_flag |= RTC_PF;
1262                 hpet_pie_count = 0;
1263         }
1264
1265         if (hpet_rtc_flags & RTC_AIE &&
1266             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1267             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1268             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1269                         rtc_int_flag |= RTC_AF;
1270
1271         if (rtc_int_flag) {
1272                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1273                 if (irq_handler)
1274                         irq_handler(rtc_int_flag, dev_id);
1275         }
1276         return IRQ_HANDLED;
1277 }
1278 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1279 #endif