1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/delay.h>
6 #include <linux/hpet.h>
12 #include <asm/mwait.h>
15 #define pr_fmt(fmt) "hpet: " fmt
25 struct clock_event_device evt;
31 unsigned int boot_cfg;
36 unsigned int nr_channels;
37 unsigned int nr_clockevents;
38 unsigned int boot_cfg;
39 struct hpet_channel *channels;
42 #define HPET_MASK CLOCKSOURCE_MASK(32)
44 #define HPET_MIN_CYCLES 128
45 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
48 * HPET address is set in acpi/boot.c, when an ACPI entry exists
50 unsigned long hpet_address;
51 u8 hpet_blockid; /* OS timer block num */
52 bool hpet_msi_disable;
55 static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel);
56 static struct irq_domain *hpet_domain;
59 static void __iomem *hpet_virt_address;
61 static struct hpet_base hpet_base;
63 static bool hpet_legacy_int_enabled;
64 static unsigned long hpet_freq;
66 bool boot_hpet_disable;
68 static bool hpet_verbose;
71 struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt)
73 return container_of(evt, struct hpet_channel, evt);
76 inline unsigned int hpet_readl(unsigned int a)
78 return readl(hpet_virt_address + a);
81 static inline void hpet_writel(unsigned int d, unsigned int a)
83 writel(d, hpet_virt_address + a);
86 static inline void hpet_set_mapping(void)
88 hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE);
91 static inline void hpet_clear_mapping(void)
93 iounmap(hpet_virt_address);
94 hpet_virt_address = NULL;
98 * HPET command line enable / disable
100 static int __init hpet_setup(char *str)
103 char *next = strchr(str, ',');
107 if (!strncmp("disable", str, 7))
108 boot_hpet_disable = true;
109 if (!strncmp("force", str, 5))
110 hpet_force_user = true;
111 if (!strncmp("verbose", str, 7))
117 __setup("hpet=", hpet_setup);
119 static int __init disable_hpet(char *str)
121 boot_hpet_disable = true;
124 __setup("nohpet", disable_hpet);
126 static inline int is_hpet_capable(void)
128 return !boot_hpet_disable && hpet_address;
132 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
134 int is_hpet_enabled(void)
136 return is_hpet_capable() && hpet_legacy_int_enabled;
138 EXPORT_SYMBOL_GPL(is_hpet_enabled);
140 static void _hpet_print_config(const char *function, int line)
142 u32 i, id, period, cfg, status, channels, l, h;
144 pr_info("%s(%d):\n", function, line);
146 id = hpet_readl(HPET_ID);
147 period = hpet_readl(HPET_PERIOD);
148 pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period);
150 cfg = hpet_readl(HPET_CFG);
151 status = hpet_readl(HPET_STATUS);
152 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status);
154 l = hpet_readl(HPET_COUNTER);
155 h = hpet_readl(HPET_COUNTER+4);
156 pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
158 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
160 for (i = 0; i < channels; i++) {
161 l = hpet_readl(HPET_Tn_CFG(i));
162 h = hpet_readl(HPET_Tn_CFG(i)+4);
163 pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h);
165 l = hpet_readl(HPET_Tn_CMP(i));
166 h = hpet_readl(HPET_Tn_CMP(i)+4);
167 pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h);
169 l = hpet_readl(HPET_Tn_ROUTE(i));
170 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
171 pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h);
175 #define hpet_print_config() \
178 _hpet_print_config(__func__, __LINE__); \
182 * When the HPET driver (/dev/hpet) is enabled, we need to reserve
183 * timer 0 and timer 1 in case of RTC emulation.
187 static void __init hpet_reserve_platform_timers(void)
192 memset(&hd, 0, sizeof(hd));
193 hd.hd_phys_address = hpet_address;
194 hd.hd_address = hpet_virt_address;
195 hd.hd_nirqs = hpet_base.nr_channels;
198 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
199 * is wrong for i8259!) not the output IRQ. Many BIOS writers
200 * don't bother configuring *any* comparator interrupts.
202 hd.hd_irq[0] = HPET_LEGACY_8254;
203 hd.hd_irq[1] = HPET_LEGACY_RTC;
205 for (i = 0; i < hpet_base.nr_channels; i++) {
206 struct hpet_channel *hc = hpet_base.channels + i;
209 hd.hd_irq[i] = hc->irq;
212 case HPET_MODE_UNUSED:
213 case HPET_MODE_DEVICE:
214 hc->mode = HPET_MODE_DEVICE;
216 case HPET_MODE_CLOCKEVT:
217 case HPET_MODE_LEGACY:
218 hpet_reserve_timer(&hd, hc->num);
226 static void __init hpet_select_device_channel(void)
230 for (i = 0; i < hpet_base.nr_channels; i++) {
231 struct hpet_channel *hc = hpet_base.channels + i;
233 /* Associate the first unused channel to /dev/hpet */
234 if (hc->mode == HPET_MODE_UNUSED) {
235 hc->mode = HPET_MODE_DEVICE;
242 static inline void hpet_reserve_platform_timers(void) { }
243 static inline void hpet_select_device_channel(void) {}
246 /* Common HPET functions */
247 static void hpet_stop_counter(void)
249 u32 cfg = hpet_readl(HPET_CFG);
251 cfg &= ~HPET_CFG_ENABLE;
252 hpet_writel(cfg, HPET_CFG);
255 static void hpet_reset_counter(void)
257 hpet_writel(0, HPET_COUNTER);
258 hpet_writel(0, HPET_COUNTER + 4);
261 static void hpet_start_counter(void)
263 unsigned int cfg = hpet_readl(HPET_CFG);
265 cfg |= HPET_CFG_ENABLE;
266 hpet_writel(cfg, HPET_CFG);
269 static void hpet_restart_counter(void)
272 hpet_reset_counter();
273 hpet_start_counter();
276 static void hpet_resume_device(void)
281 static void hpet_resume_counter(struct clocksource *cs)
283 hpet_resume_device();
284 hpet_restart_counter();
287 static void hpet_enable_legacy_int(void)
289 unsigned int cfg = hpet_readl(HPET_CFG);
291 cfg |= HPET_CFG_LEGACY;
292 hpet_writel(cfg, HPET_CFG);
293 hpet_legacy_int_enabled = true;
296 static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt)
298 unsigned int channel = clockevent_to_channel(evt)->num;
299 unsigned int cfg, cmp, now;
303 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
304 delta >>= evt->shift;
305 now = hpet_readl(HPET_COUNTER);
306 cmp = now + (unsigned int)delta;
307 cfg = hpet_readl(HPET_Tn_CFG(channel));
308 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
310 hpet_writel(cfg, HPET_Tn_CFG(channel));
311 hpet_writel(cmp, HPET_Tn_CMP(channel));
314 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
315 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
316 * bit is automatically cleared after the first write.
317 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
318 * Publication # 24674)
320 hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel));
321 hpet_start_counter();
327 static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt)
329 unsigned int channel = clockevent_to_channel(evt)->num;
332 cfg = hpet_readl(HPET_Tn_CFG(channel));
333 cfg &= ~HPET_TN_PERIODIC;
334 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
335 hpet_writel(cfg, HPET_Tn_CFG(channel));
340 static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt)
342 unsigned int channel = clockevent_to_channel(evt)->num;
345 cfg = hpet_readl(HPET_Tn_CFG(channel));
346 cfg &= ~HPET_TN_ENABLE;
347 hpet_writel(cfg, HPET_Tn_CFG(channel));
352 static int hpet_clkevt_legacy_resume(struct clock_event_device *evt)
354 hpet_enable_legacy_int();
360 hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt)
362 unsigned int channel = clockevent_to_channel(evt)->num;
366 cnt = hpet_readl(HPET_COUNTER);
368 hpet_writel(cnt, HPET_Tn_CMP(channel));
371 * HPETs are a complete disaster. The compare register is
372 * based on a equal comparison and neither provides a less
373 * than or equal functionality (which would require to take
374 * the wraparound into account) nor a simple count down event
375 * mode. Further the write to the comparator register is
376 * delayed internally up to two HPET clock cycles in certain
377 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
378 * longer delays. We worked around that by reading back the
379 * compare register, but that required another workaround for
380 * ICH9,10 chips where the first readout after write can
381 * return the old stale value. We already had a minimum
382 * programming delta of 5us enforced, but a NMI or SMI hitting
383 * between the counter readout and the comparator write can
384 * move us behind that point easily. Now instead of reading
385 * the compare register back several times, we make the ETIME
386 * decision based on the following: Return ETIME if the
387 * counter value after the write is less than HPET_MIN_CYCLES
388 * away from the event or if the counter is already ahead of
389 * the event. The minimum programming delta for the generic
390 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
392 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
394 return res < HPET_MIN_CYCLES ? -ETIME : 0;
397 static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating)
399 struct clock_event_device *evt = &hc->evt;
401 evt->rating = rating;
403 evt->name = hc->name;
404 evt->cpumask = cpumask_of(hc->cpu);
405 evt->set_state_oneshot = hpet_clkevt_set_state_oneshot;
406 evt->set_next_event = hpet_clkevt_set_next_event;
407 evt->set_state_shutdown = hpet_clkevt_set_state_shutdown;
409 evt->features = CLOCK_EVT_FEAT_ONESHOT;
410 if (hc->boot_cfg & HPET_TN_PERIODIC) {
411 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
412 evt->set_state_periodic = hpet_clkevt_set_state_periodic;
416 static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc)
419 * Start HPET with the boot CPU's cpumask and make it global after
420 * the IO_APIC has been initialized.
422 hc->cpu = boot_cpu_data.cpu_index;
423 strncpy(hc->name, "hpet", sizeof(hc->name));
424 hpet_init_clockevent(hc, 50);
426 hc->evt.tick_resume = hpet_clkevt_legacy_resume;
429 * Legacy horrors and sins from the past. HPET used periodic mode
430 * unconditionally forever on the legacy channel 0. Removing the
431 * below hack and using the conditional in hpet_init_clockevent()
432 * makes at least Qemu and one hardware machine fail to boot.
433 * There are two issues which cause the boot failure:
435 * #1 After the timer delivery test in IOAPIC and the IOAPIC setup
436 * the next interrupt is not delivered despite the HPET channel
437 * being programmed correctly. Reprogramming the HPET after
438 * switching to IOAPIC makes it work again. After fixing this,
439 * the next issue surfaces:
441 * #2 Due to the unconditional periodic mode availability the Local
442 * APIC timer calibration can hijack the global clockevents
443 * event handler without causing damage. Using oneshot at this
444 * stage makes if hang because the HPET does not get
445 * reprogrammed due to the handler hijacking. Duh, stupid me!
447 * Both issues require major surgery and especially the kick HPET
448 * again after enabling IOAPIC results in really nasty hackery.
449 * This 'assume periodic works' magic has survived since HPET
450 * support got added, so it's questionable whether this should be
451 * fixed. Both Qemu and the failing hardware machine support
452 * periodic mode despite the fact that both don't advertise it in
453 * the configuration register and both need that extra kick after
454 * switching to IOAPIC. Seems to be a feature...
456 hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC;
457 hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic;
459 /* Start HPET legacy interrupts */
460 hpet_enable_legacy_int();
462 clockevents_config_and_register(&hc->evt, hpet_freq,
463 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
464 global_clock_event = &hc->evt;
465 pr_debug("Clockevent registered\n");
471 #ifdef CONFIG_PCI_MSI
473 void hpet_msi_unmask(struct irq_data *data)
475 struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
478 cfg = hpet_readl(HPET_Tn_CFG(hc->num));
479 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
480 hpet_writel(cfg, HPET_Tn_CFG(hc->num));
483 void hpet_msi_mask(struct irq_data *data)
485 struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
488 cfg = hpet_readl(HPET_Tn_CFG(hc->num));
489 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
490 hpet_writel(cfg, HPET_Tn_CFG(hc->num));
493 void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg)
495 hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num));
496 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4);
499 static int hpet_clkevt_msi_resume(struct clock_event_device *evt)
501 struct hpet_channel *hc = clockevent_to_channel(evt);
502 struct irq_data *data = irq_get_irq_data(hc->irq);
505 /* Restore the MSI msg and unmask the interrupt */
506 irq_chip_compose_msi_msg(data, &msg);
507 hpet_msi_write(hc, &msg);
508 hpet_msi_unmask(data);
512 static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data)
514 struct hpet_channel *hc = data;
515 struct clock_event_device *evt = &hc->evt;
517 if (!evt->event_handler) {
518 pr_info("Spurious interrupt HPET channel %d\n", hc->num);
522 evt->event_handler(evt);
526 static int hpet_setup_msi_irq(struct hpet_channel *hc)
528 if (request_irq(hc->irq, hpet_msi_interrupt_handler,
529 IRQF_TIMER | IRQF_NOBALANCING,
533 disable_irq(hc->irq);
534 irq_set_affinity(hc->irq, cpumask_of(hc->cpu));
537 pr_debug("%s irq %u for MSI\n", hc->name, hc->irq);
542 /* Invoked from the hotplug callback on @cpu */
543 static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu)
545 struct clock_event_device *evt = &hc->evt;
548 per_cpu(cpu_hpet_channel, cpu) = hc;
549 hpet_setup_msi_irq(hc);
551 hpet_init_clockevent(hc, 110);
552 evt->tick_resume = hpet_clkevt_msi_resume;
554 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
558 static struct hpet_channel *hpet_get_unused_clockevent(void)
562 for (i = 0; i < hpet_base.nr_channels; i++) {
563 struct hpet_channel *hc = hpet_base.channels + i;
565 if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use)
573 static int hpet_cpuhp_online(unsigned int cpu)
575 struct hpet_channel *hc = hpet_get_unused_clockevent();
578 init_one_hpet_msi_clockevent(hc, cpu);
582 static int hpet_cpuhp_dead(unsigned int cpu)
584 struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu);
588 free_irq(hc->irq, hc);
590 per_cpu(cpu_hpet_channel, cpu) = NULL;
594 static void __init hpet_select_clockevents(void)
598 hpet_base.nr_clockevents = 0;
600 /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */
601 if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT))
606 hpet_domain = hpet_create_irq_domain(hpet_blockid);
610 for (i = 0; i < hpet_base.nr_channels; i++) {
611 struct hpet_channel *hc = hpet_base.channels + i;
614 if (hc->mode != HPET_MODE_UNUSED)
617 /* Only consider HPET channel with MSI support */
618 if (!(hc->boot_cfg & HPET_TN_FSB_CAP))
621 sprintf(hc->name, "hpet%d", i);
623 irq = hpet_assign_irq(hpet_domain, hc, hc->num);
628 hc->mode = HPET_MODE_CLOCKEVT;
630 if (++hpet_base.nr_clockevents == num_possible_cpus())
634 pr_info("%d channels of %d reserved for per-cpu timers\n",
635 hpet_base.nr_channels, hpet_base.nr_clockevents);
640 static inline void hpet_select_clockevents(void) { }
642 #define hpet_cpuhp_online NULL
643 #define hpet_cpuhp_dead NULL
648 * Clock source related code
650 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
652 * Reading the HPET counter is a very slow operation. If a large number of
653 * CPUs are trying to access the HPET counter simultaneously, it can cause
654 * massive delays and slow down system performance dramatically. This may
655 * happen when HPET is the default clock source instead of TSC. For a
656 * really large system with hundreds of CPUs, the slowdown may be so
657 * severe, that it can actually crash the system because of a NMI watchdog
658 * soft lockup, for example.
660 * If multiple CPUs are trying to access the HPET counter at the same time,
661 * we don't actually need to read the counter multiple times. Instead, the
662 * other CPUs can use the counter value read by the first CPU in the group.
664 * This special feature is only enabled on x86-64 systems. It is unlikely
665 * that 32-bit x86 systems will have enough CPUs to require this feature
666 * with its associated locking overhead. We also need 64-bit atomic read.
668 * The lock and the HPET value are stored together and can be read in a
669 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
670 * is 32 bits in size.
674 arch_spinlock_t lock;
680 static union hpet_lock hpet __cacheline_aligned = {
681 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
684 static u64 read_hpet(struct clocksource *cs)
687 union hpet_lock old, new;
689 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
692 * Read HPET directly if in NMI.
695 return (u64)hpet_readl(HPET_COUNTER);
698 * Read the current state of the lock and HPET value atomically.
700 old.lockval = READ_ONCE(hpet.lockval);
702 if (arch_spin_is_locked(&old.lock))
705 local_irq_save(flags);
706 if (arch_spin_trylock(&hpet.lock)) {
707 new.value = hpet_readl(HPET_COUNTER);
709 * Use WRITE_ONCE() to prevent store tearing.
711 WRITE_ONCE(hpet.value, new.value);
712 arch_spin_unlock(&hpet.lock);
713 local_irq_restore(flags);
714 return (u64)new.value;
716 local_irq_restore(flags);
722 * Wait until the HPET value change or the lock is free to indicate
723 * its value is up-to-date.
725 * It is possible that old.value has already contained the latest
726 * HPET value while the lock holder was in the process of releasing
727 * the lock. Checking for lock state change will enable us to return
728 * the value immediately instead of waiting for the next HPET reader
733 new.lockval = READ_ONCE(hpet.lockval);
734 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
736 return (u64)new.value;
742 static u64 read_hpet(struct clocksource *cs)
744 return (u64)hpet_readl(HPET_COUNTER);
748 static struct clocksource clocksource_hpet = {
753 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
754 .resume = hpet_resume_counter,
758 * AMD SB700 based systems with spread spectrum enabled use a SMM based
759 * HPET emulation to provide proper frequency setting.
761 * On such systems the SMM code is initialized with the first HPET register
762 * access and takes some time to complete. During this time the config
763 * register reads 0xffffffff. We check for max 1000 loops whether the
764 * config register reads a non-0xffffffff value to make sure that the
765 * HPET is up and running before we proceed any further.
767 * A counting loop is safe, as the HPET access takes thousands of CPU cycles.
769 * On non-SB700 based machines this check is only done once and has no
772 static bool __init hpet_cfg_working(void)
776 for (i = 0; i < 1000; i++) {
777 if (hpet_readl(HPET_CFG) != 0xFFFFFFFF)
781 pr_warn("Config register invalid. Disabling HPET\n");
785 static bool __init hpet_counting(void)
789 hpet_restart_counter();
791 t1 = hpet_readl(HPET_COUNTER);
795 * We don't know the TSC frequency yet, but waiting for
796 * 200000 TSC cycles is safe:
801 if (t1 != hpet_readl(HPET_COUNTER))
804 } while ((now - start) < 200000UL);
806 pr_warn("Counter not counting. HPET disabled\n");
810 static bool __init mwait_pc10_supported(void)
812 unsigned int eax, ebx, ecx, mwait_substates;
814 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
817 if (!cpu_feature_enabled(X86_FEATURE_MWAIT))
820 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
823 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
825 return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) &&
826 (ecx & CPUID5_ECX_INTERRUPT_BREAK) &&
827 (mwait_substates & (0xF << 28));
831 * Check whether the system supports PC10. If so force disable HPET as that
832 * stops counting in PC10. This check is overbroad as it does not take any
833 * of the following into account:
836 * - Enablement of intel_idle
837 * - Command line arguments which limit intel_idle C-state support
839 * That's perfectly fine. HPET is a piece of hardware designed by committee
840 * and the only reasons why it is still in use on modern systems is the
841 * fact that it is impossible to reliably query TSC and CPU frequency via
844 * If HPET is functional it is useful for calibrating TSC, but this can be
845 * done via PMTIMER as well which seems to be the last remaining timer on
846 * X86/INTEL platforms that has not been completely wreckaged by feature
849 * In theory HPET support should be removed altogether, but there are older
850 * systems out there which depend on it because TSC and APIC timer are
851 * dysfunctional in deeper C-states.
853 * It's only 20 years now that hardware people have been asked to provide
854 * reliable and discoverable facilities which can be used for timekeeping
855 * and per CPU timer interrupts.
857 * The probability that this problem is going to be solved in the
858 * forseeable future is close to zero, so the kernel has to be cluttered
859 * with heuristics to keep up with the ever growing amount of hardware and
860 * firmware trainwrecks. Hopefully some day hardware people will understand
861 * that the approach of "This can be fixed in software" is not sustainable.
864 static bool __init hpet_is_pc10_damaged(void)
866 unsigned long long pcfg;
868 /* Check whether PC10 substates are supported */
869 if (!mwait_pc10_supported())
872 /* Check whether PC10 is enabled in PKG C-state limit */
873 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
874 if ((pcfg & 0xF) < 8)
877 if (hpet_force_user) {
878 pr_warn("HPET force enabled via command line, but dysfunctional in PC10.\n");
882 pr_info("HPET dysfunctional in PC10. Force disabled.\n");
883 boot_hpet_disable = true;
888 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
890 int __init hpet_enable(void)
892 u32 hpet_period, cfg, id, irq;
893 unsigned int i, channels;
894 struct hpet_channel *hc;
897 if (!is_hpet_capable())
900 if (hpet_is_pc10_damaged())
904 if (!hpet_virt_address)
907 /* Validate that the config register is working */
908 if (!hpet_cfg_working())
912 * Read the period and check for a sane value:
914 hpet_period = hpet_readl(HPET_PERIOD);
915 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
918 /* The period is a femtoseconds value. Convert it to a frequency. */
920 do_div(freq, hpet_period);
924 * Read the HPET ID register to retrieve the IRQ routing
925 * information and the number of channels
927 id = hpet_readl(HPET_ID);
930 /* This is the HPET channel number which is zero based */
931 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
934 * The legacy routing mode needs at least two channels, tick timer
935 * and the rtc emulation channel.
937 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2)
940 hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL);
942 pr_warn("Disabling HPET.\n");
945 hpet_base.channels = hc;
946 hpet_base.nr_channels = channels;
948 /* Read, store and sanitize the global configuration */
949 cfg = hpet_readl(HPET_CFG);
950 hpet_base.boot_cfg = cfg;
951 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
952 hpet_writel(cfg, HPET_CFG);
954 pr_warn("Global config: Unknown bits %#x\n", cfg);
956 /* Read, store and sanitize the per channel configuration */
957 for (i = 0; i < channels; i++, hc++) {
960 cfg = hpet_readl(HPET_Tn_CFG(i));
962 irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
965 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
966 hpet_writel(cfg, HPET_Tn_CFG(i));
968 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
969 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
970 | HPET_TN_FSB | HPET_TN_FSB_CAP);
972 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg);
977 * Validate that the counter is counting. This needs to be done
978 * after sanitizing the config registers to properly deal with
979 * force enabled HPETs.
981 if (!hpet_counting())
984 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
986 if (id & HPET_ID_LEGSUP) {
987 hpet_legacy_clockevent_register(&hpet_base.channels[0]);
988 hpet_base.channels[0].mode = HPET_MODE_LEGACY;
989 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC))
990 hpet_base.channels[1].mode = HPET_MODE_LEGACY;
996 kfree(hpet_base.channels);
997 hpet_base.channels = NULL;
998 hpet_base.nr_channels = 0;
999 hpet_clear_mapping();
1005 * The late initialization runs after the PCI quirks have been invoked
1006 * which might have detected a system on which the HPET can be enforced.
1008 * Also, the MSI machinery is not working yet when the HPET is initialized
1011 * If the HPET is enabled, then:
1013 * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y
1014 * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents
1015 * 3) Setup /dev/hpet if CONFIG_HPET=y
1016 * 4) Register hotplug callbacks when clockevents are available
1018 static __init int hpet_late_init(void)
1022 if (!hpet_address) {
1023 if (!force_hpet_address)
1026 hpet_address = force_hpet_address;
1030 if (!hpet_virt_address)
1033 hpet_select_device_channel();
1034 hpet_select_clockevents();
1035 hpet_reserve_platform_timers();
1036 hpet_print_config();
1038 if (!hpet_base.nr_clockevents)
1041 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
1042 hpet_cpuhp_online, NULL);
1045 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
1052 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1055 fs_initcall(hpet_late_init);
1057 void hpet_disable(void)
1062 if (!is_hpet_capable() || !hpet_virt_address)
1065 /* Restore boot configuration with the enable bit cleared */
1066 cfg = hpet_base.boot_cfg;
1067 cfg &= ~HPET_CFG_ENABLE;
1068 hpet_writel(cfg, HPET_CFG);
1070 /* Restore the channel boot configuration */
1071 for (i = 0; i < hpet_base.nr_channels; i++)
1072 hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
1074 /* If the HPET was enabled at boot time, reenable it */
1075 if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
1076 hpet_writel(hpet_base.boot_cfg, HPET_CFG);
1079 #ifdef CONFIG_HPET_EMULATE_RTC
1082 * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET
1083 * is enabled, we support RTC interrupt functionality in software.
1085 * RTC has 3 kinds of interrupts:
1087 * 1) Update Interrupt - generate an interrupt, every second, when the
1088 * RTC clock is updated
1089 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1090 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1091 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2)
1093 * (1) and (2) above are implemented using polling at a frequency of 64 Hz:
1094 * DEFAULT_RTC_INT_FREQ.
1096 * The exact frequency is a tradeoff between accuracy and interrupt overhead.
1098 * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency,
1101 #include <linux/mc146818rtc.h>
1102 #include <linux/rtc.h>
1104 #define DEFAULT_RTC_INT_FREQ 64
1105 #define DEFAULT_RTC_SHIFT 6
1106 #define RTC_NUM_INTS 1
1108 static unsigned long hpet_rtc_flags;
1109 static int hpet_prev_update_sec;
1110 static struct rtc_time hpet_alarm_time;
1111 static unsigned long hpet_pie_count;
1112 static u32 hpet_t1_cmp;
1113 static u32 hpet_default_delta;
1114 static u32 hpet_pie_delta;
1115 static unsigned long hpet_pie_limit;
1117 static rtc_irq_handler irq_handler;
1120 * Check that the HPET counter c1 is ahead of c2
1122 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1124 return (s32)(c2 - c1) < 0;
1128 * Registers a IRQ handler.
1130 int hpet_register_irq_handler(rtc_irq_handler handler)
1132 if (!is_hpet_enabled())
1137 irq_handler = handler;
1141 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1144 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1147 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1149 if (!is_hpet_enabled())
1155 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1158 * Channel 1 for RTC emulation. We use one shot mode, as periodic mode
1159 * is not supported by all HPET implementations for channel 1.
1161 * hpet_rtc_timer_init() is called when the rtc is initialized.
1163 int hpet_rtc_timer_init(void)
1165 unsigned int cfg, cnt, delta;
1166 unsigned long flags;
1168 if (!is_hpet_enabled())
1171 if (!hpet_default_delta) {
1172 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1175 clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1176 clc >>= evt->shift + DEFAULT_RTC_SHIFT;
1177 hpet_default_delta = clc;
1180 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1181 delta = hpet_default_delta;
1183 delta = hpet_pie_delta;
1185 local_irq_save(flags);
1187 cnt = delta + hpet_readl(HPET_COUNTER);
1188 hpet_writel(cnt, HPET_T1_CMP);
1191 cfg = hpet_readl(HPET_T1_CFG);
1192 cfg &= ~HPET_TN_PERIODIC;
1193 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1194 hpet_writel(cfg, HPET_T1_CFG);
1196 local_irq_restore(flags);
1200 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1202 static void hpet_disable_rtc_channel(void)
1204 u32 cfg = hpet_readl(HPET_T1_CFG);
1206 cfg &= ~HPET_TN_ENABLE;
1207 hpet_writel(cfg, HPET_T1_CFG);
1211 * The functions below are called from rtc driver.
1212 * Return 0 if HPET is not being used.
1213 * Otherwise do the necessary changes and return 1.
1215 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1217 if (!is_hpet_enabled())
1220 hpet_rtc_flags &= ~bit_mask;
1221 if (unlikely(!hpet_rtc_flags))
1222 hpet_disable_rtc_channel();
1226 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1228 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1230 unsigned long oldbits = hpet_rtc_flags;
1232 if (!is_hpet_enabled())
1235 hpet_rtc_flags |= bit_mask;
1237 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1238 hpet_prev_update_sec = -1;
1241 hpet_rtc_timer_init();
1245 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1247 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
1249 if (!is_hpet_enabled())
1252 hpet_alarm_time.tm_hour = hrs;
1253 hpet_alarm_time.tm_min = min;
1254 hpet_alarm_time.tm_sec = sec;
1258 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1260 int hpet_set_periodic_freq(unsigned long freq)
1264 if (!is_hpet_enabled())
1267 if (freq <= DEFAULT_RTC_INT_FREQ) {
1268 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1270 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1272 clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1275 hpet_pie_delta = clc;
1281 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1283 int hpet_rtc_dropped_irq(void)
1285 return is_hpet_enabled();
1287 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1289 static void hpet_rtc_timer_reinit(void)
1294 if (unlikely(!hpet_rtc_flags))
1295 hpet_disable_rtc_channel();
1297 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1298 delta = hpet_default_delta;
1300 delta = hpet_pie_delta;
1303 * Increment the comparator value until we are ahead of the
1307 hpet_t1_cmp += delta;
1308 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1310 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1313 if (hpet_rtc_flags & RTC_PIE)
1314 hpet_pie_count += lost_ints;
1315 if (printk_ratelimit())
1316 pr_warn("Lost %d RTC interrupts\n", lost_ints);
1320 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1322 struct rtc_time curr_time;
1323 unsigned long rtc_int_flag = 0;
1325 hpet_rtc_timer_reinit();
1326 memset(&curr_time, 0, sizeof(struct rtc_time));
1328 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) {
1329 if (unlikely(mc146818_get_time(&curr_time) < 0)) {
1330 pr_err_ratelimited("unable to read current time from RTC\n");
1335 if (hpet_rtc_flags & RTC_UIE &&
1336 curr_time.tm_sec != hpet_prev_update_sec) {
1337 if (hpet_prev_update_sec >= 0)
1338 rtc_int_flag = RTC_UF;
1339 hpet_prev_update_sec = curr_time.tm_sec;
1342 if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) {
1343 rtc_int_flag |= RTC_PF;
1347 if (hpet_rtc_flags & RTC_AIE &&
1348 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1349 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1350 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1351 rtc_int_flag |= RTC_AF;
1354 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1356 irq_handler(rtc_int_flag, dev_id);
1360 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);