1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
13 #include <linux/linkage.h>
14 #include <linux/threads.h>
15 #include <linux/init.h>
16 #include <linux/pgtable.h>
17 #include <asm/segment.h>
20 #include <asm/cache.h>
21 #include <asm/processor-flags.h>
22 #include <asm/percpu.h>
24 #include "../entry/calling.h"
25 #include <asm/export.h>
26 #include <asm/nospec-branch.h>
27 #include <asm/fixmap.h>
29 #ifdef CONFIG_PARAVIRT_XXL
30 #include <asm/asm-offsets.h>
31 #include <asm/paravirt.h>
32 #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
34 #define INTERRUPT_RETURN iretq
35 #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg
39 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
40 * because we need identity-mapped pages.
42 #define l4_index(x) (((x) >> 39) & 511)
43 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
45 L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
46 L4_START_KERNEL = l4_index(__START_KERNEL_map)
48 L3_START_KERNEL = pud_index(__START_KERNEL_map)
53 SYM_CODE_START_NOALIGN(startup_64)
56 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
57 * and someone has loaded an identity mapped page table
58 * for us. These identity mapped page tables map all of the
59 * kernel pages and possibly all of memory.
61 * %rsi holds a physical pointer to real_mode_data.
63 * We come here either directly from a 64bit bootloader, or from
64 * arch/x86/boot/compressed/head_64.S.
66 * We only come here initially at boot nothing else comes here.
68 * Since we may be loaded at an address different from what we were
69 * compiled to run at we first fixup the physical addresses in our page
70 * tables and then reload them.
73 /* Set up the stack for verify_cpu(), similar to initial_stack below */
74 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
76 leaq _text(%rip), %rdi
79 * initial_gs points to initial fixed_percpu_data struct with storage for
80 * the stack protector canary. Global pointer fixups are needed at this
81 * stage, so apply them as is done in fixup_pointer(), and initialize %gs
82 * such that the canary can be accessed at %gs:40 for subsequent C calls.
84 movl $MSR_GS_BASE, %ecx
85 movq initial_gs(%rip), %rax
94 call startup_64_setup_env
97 /* Now switch to __KERNEL_CS so IRET works reliably */
99 leaq .Lon_kernel_cs(%rip), %rax
106 /* Sanitize CPU configuration */
110 * Perform pagetable fixups. Additionally, if SME is active, encrypt
111 * the kernel and retrieve the modifier (SME encryption mask if SME
112 * is active) to be added to the initial pgdir entry that will be
113 * programmed into CR3.
115 leaq _text(%rip), %rdi
120 /* Form the CR3 value being sure to include the CR3 modifier */
121 addq $(early_top_pgt - __START_KERNEL_map), %rax
123 SYM_CODE_END(startup_64)
125 SYM_CODE_START(secondary_startup_64)
128 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
129 * and someone has loaded a mapped page table.
131 * %rsi holds a physical pointer to real_mode_data.
133 * We come here either from startup_64 (using physical addresses)
134 * or from trampoline.S (using virtual addresses).
136 * Using virtual addresses from trampoline.S removes the need
137 * to have any identity mapped pages in the kernel page table
138 * after the boot processor executes this code.
141 /* Sanitize CPU configuration */
145 * The secondary_startup_64_no_verify entry point is only used by
146 * SEV-ES guests. In those guests the call to verify_cpu() would cause
147 * #VC exceptions which can not be handled at this stage of secondary
150 * All non SEV-ES systems, especially Intel systems, need to execute
151 * verify_cpu() above to make sure NX is enabled.
153 SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
157 * Retrieve the modifier (SME encryption mask if SME is active) to be
158 * added to the initial pgdir entry that will be programmed into CR3.
160 #ifdef CONFIG_AMD_MEM_ENCRYPT
161 movq sme_me_mask, %rax
166 /* Form the CR3 value being sure to include the CR3 modifier */
167 addq $(init_top_pgt - __START_KERNEL_map), %rax
170 /* Enable PAE mode, PGE and LA57 */
171 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
172 #ifdef CONFIG_X86_5LEVEL
173 testl $1, __pgtable_l5_enabled(%rip)
175 orl $X86_CR4_LA57, %ecx
180 /* Setup early boot stage 4-/5-level pagetables. */
181 addq phys_base(%rip), %rax
184 * For SEV guests: Verify that the C-bit is correct. A malicious
185 * hypervisor could lie about the C-bit position to perform a ROP
186 * attack on the guest by writing to the unencrypted stack and wait for
187 * the next RET instruction.
188 * %rsi carries pointer to realmode data and is callee-clobbered. Save
196 /* Switch to new page-table */
199 /* Ensure I am executing from virtual addresses */
201 ANNOTATE_RETPOLINE_SAFE
207 * We must switch to a new descriptor in kernel space for the GDT
208 * because soon the kernel won't have access anymore to the userspace
209 * addresses where we're currently running on. We have to do that here
210 * because in 32bit we couldn't load a 64bit linear address.
212 lgdt early_gdt_descr(%rip)
214 /* set up data segments */
221 * We don't really need to load %fs or %gs, but load them anyway
222 * to kill any stale realmode selectors. This allows execution
230 * The base of %gs always points to fixed_percpu_data. If the
231 * stack protector canary is enabled, it is located at %gs:40.
232 * Note that, on SMP, the boot cpu uses init data section until
233 * the per cpu areas are set up.
235 movl $MSR_GS_BASE,%ecx
236 movl initial_gs(%rip),%eax
237 movl initial_gs+4(%rip),%edx
241 * Setup a boot time stack - Any secondary CPU will have lost its stack
242 * by now because the cr3-switch above unmaps the real-mode stack
244 movq initial_stack(%rip), %rsp
246 /* Setup and Load IDT */
251 /* Check if nx is implemented */
252 movl $0x80000001, %eax
256 /* Setup EFER (Extended Feature Enable Register) */
259 btsl $_EFER_SCE, %eax /* Enable System Call */
260 btl $20,%edi /* No Execute supported? */
263 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
264 1: wrmsr /* Make changes effective */
267 movl $CR0_STATE, %eax
268 /* Make changes effective */
271 /* zero EFLAGS after setting rsp */
275 /* rsi is pointer to real mode structure with interesting info.
281 * Jump to run C code and to be on a real kernel address.
282 * Since we are running on identity-mapped space we have to jump
283 * to the full 64bit address, this is only possible as indirect
284 * jump. In addition we need to ensure %cs is set so we make this
287 * Note: do not change to far jump indirect with 64bit offset.
289 * AMD does not support far jump indirect with 64bit offset.
290 * AMD64 Architecture Programmer's Manual, Volume 3: states only
291 * JMP FAR mem16:16 FF /5 Far jump indirect,
292 * with the target specified by a far pointer in memory.
293 * JMP FAR mem16:32 FF /5 Far jump indirect,
294 * with the target specified by a far pointer in memory.
296 * Intel64 does support 64bit offset.
297 * Software Developer Manual Vol 2: states:
298 * FF /5 JMP m16:16 Jump far, absolute indirect,
299 * address given in m16:16
300 * FF /5 JMP m16:32 Jump far, absolute indirect,
301 * address given in m16:32.
302 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
303 * address given in m16:64.
305 pushq $.Lafter_lret # put return address on stack for unwinder
306 xorl %ebp, %ebp # clear frame pointer
307 movq initial_code(%rip), %rax
308 pushq $__KERNEL_CS # set correct cs
309 pushq %rax # target address in negative space
312 SYM_CODE_END(secondary_startup_64)
314 #include "verify_cpu.S"
315 #include "sev_verify_cbit.S"
317 #ifdef CONFIG_HOTPLUG_CPU
319 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
320 * up already except stack. We just set up stack here. Then call
321 * start_secondary() via .Ljump_to_C_code.
323 SYM_CODE_START(start_cpu0)
325 movq initial_stack(%rip), %rsp
327 SYM_CODE_END(start_cpu0)
330 #ifdef CONFIG_AMD_MEM_ENCRYPT
332 * VC Exception handler used during early boot when running on kernel
333 * addresses, but before the switch to the idt_table can be made.
334 * The early_idt_handler_array can't be used here because it calls into a lot
335 * of __init code and this handler is also used during CPU offlining/onlining.
336 * Therefore this handler ends up in the .text section so that it stays around
337 * when .init.text is freed.
339 SYM_CODE_START_NOALIGN(vc_boot_ghcb)
340 UNWIND_HINT_IRET_REGS offset=8
349 movq ORIG_RAX(%rsp), %rsi
350 movq initial_vc_handler(%rip), %rax
351 ANNOTATE_RETPOLINE_SAFE
357 /* Remove Error Code */
360 /* Pure iret required here - don't use INTERRUPT_RETURN */
362 SYM_CODE_END(vc_boot_ghcb)
365 /* Both SMP bootup and ACPI suspend change these variables */
368 SYM_DATA(initial_code, .quad x86_64_start_kernel)
369 SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data))
370 #ifdef CONFIG_AMD_MEM_ENCRYPT
371 SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb)
375 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel unwinder
376 * reliably detect the end of the stack.
378 SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS)
382 SYM_CODE_START(early_idt_handler_array)
384 .rept NUM_EXCEPTION_VECTORS
385 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
386 UNWIND_HINT_IRET_REGS
387 pushq $0 # Dummy error code, to make stack frame uniform
389 UNWIND_HINT_IRET_REGS offset=8
391 pushq $i # 72(%rsp) Vector number
392 jmp early_idt_handler_common
393 UNWIND_HINT_IRET_REGS
395 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
397 UNWIND_HINT_IRET_REGS offset=16
398 SYM_CODE_END(early_idt_handler_array)
400 SYM_CODE_START_LOCAL(early_idt_handler_common)
403 * The stack is the hardware frame, an error code or zero, and the
408 incl early_recursion_flag(%rip)
410 /* The vector number is currently in the pt_regs->di slot. */
411 pushq %rsi /* pt_regs->si */
412 movq 8(%rsp), %rsi /* RSI = vector number */
413 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
414 pushq %rdx /* pt_regs->dx */
415 pushq %rcx /* pt_regs->cx */
416 pushq %rax /* pt_regs->ax */
417 pushq %r8 /* pt_regs->r8 */
418 pushq %r9 /* pt_regs->r9 */
419 pushq %r10 /* pt_regs->r10 */
420 pushq %r11 /* pt_regs->r11 */
421 pushq %rbx /* pt_regs->bx */
422 pushq %rbp /* pt_regs->bp */
423 pushq %r12 /* pt_regs->r12 */
424 pushq %r13 /* pt_regs->r13 */
425 pushq %r14 /* pt_regs->r14 */
426 pushq %r15 /* pt_regs->r15 */
429 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
430 call do_early_exception
432 decl early_recursion_flag(%rip)
433 jmp restore_regs_and_return_to_kernel
434 SYM_CODE_END(early_idt_handler_common)
436 #ifdef CONFIG_AMD_MEM_ENCRYPT
438 * VC Exception handler used during very early boot. The
439 * early_idt_handler_array can't be used because it returns via the
440 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
442 * This handler will end up in the .init.text section and not be
443 * available to boot secondary CPUs.
445 SYM_CODE_START_NOALIGN(vc_no_ghcb)
446 UNWIND_HINT_IRET_REGS offset=8
455 movq ORIG_RAX(%rsp), %rsi
461 /* Remove Error Code */
464 /* Pure iret required here - don't use INTERRUPT_RETURN */
466 SYM_CODE_END(vc_no_ghcb)
469 #define SYM_DATA_START_PAGE_ALIGNED(name) \
470 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
472 #ifdef CONFIG_PAGE_TABLE_ISOLATION
474 * Each PGD needs to be 8k long and 8k aligned. We do not
475 * ever go out to userspace with these, so we do not
476 * strictly *need* the second page, but this allows us to
477 * have a single set_pgd() implementation that does not
478 * need to worry about whether it has 4k or 8k to work
481 * This ensures PGDs are 8k long:
483 #define PTI_USER_PGD_FILL 512
484 /* This ensures they are 8k-aligned: */
485 #define SYM_DATA_START_PTI_ALIGNED(name) \
486 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
488 #define SYM_DATA_START_PTI_ALIGNED(name) \
489 SYM_DATA_START_PAGE_ALIGNED(name)
490 #define PTI_USER_PGD_FILL 0
493 /* Automate the creation of 1 to 1 mapping pmd entries */
494 #define PMDS(START, PERM, COUNT) \
497 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
504 SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
506 .fill PTI_USER_PGD_FILL,8,0
507 SYM_DATA_END(early_top_pgt)
509 SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
510 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
511 SYM_DATA_END(early_dynamic_pgts)
513 SYM_DATA(early_recursion_flag, .long 0)
517 #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
518 SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
519 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
520 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
521 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
522 .org init_top_pgt + L4_START_KERNEL*8, 0
523 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
524 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
525 .fill PTI_USER_PGD_FILL,8,0
526 SYM_DATA_END(init_top_pgt)
528 SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
529 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
531 SYM_DATA_END(level3_ident_pgt)
532 SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
534 * Since I easily can, map the first 1G.
535 * Don't set NX because code runs from these pages.
537 * Note: This sets _PAGE_GLOBAL despite whether
538 * the CPU supports it or it is enabled. But,
539 * the CPU should ignore the bit.
541 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
542 SYM_DATA_END(level2_ident_pgt)
544 SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
546 .fill PTI_USER_PGD_FILL,8,0
547 SYM_DATA_END(init_top_pgt)
550 #ifdef CONFIG_X86_5LEVEL
551 SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
553 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
554 SYM_DATA_END(level4_kernel_pgt)
557 SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
558 .fill L3_START_KERNEL,8,0
559 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
560 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
561 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
562 SYM_DATA_END(level3_kernel_pgt)
564 SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
566 * 512 MB kernel mapping. We spend a full page on this pagetable
569 * The kernel code+data+bss must not be bigger than that.
571 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
572 * If you want to increase this then increase MODULES_VADDR
575 * This table is eventually used by the kernel during normal
576 * runtime. Care must be taken to clear out undesired bits
577 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
579 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
580 KERNEL_IMAGE_SIZE/PMD_SIZE)
581 SYM_DATA_END(level2_kernel_pgt)
583 SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
584 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
586 .rept (FIXMAP_PMD_NUM)
587 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
591 /* 6 MB reserved space + a 2MB hole */
593 SYM_DATA_END(level2_fixmap_pgt)
595 SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
596 .rept (FIXMAP_PMD_NUM)
599 SYM_DATA_END(level1_fixmap_pgt)
606 SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1)
607 SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page))
610 /* This must match the first entry in level2_kernel_pgt */
611 SYM_DATA(phys_base, .quad 0x0)
612 EXPORT_SYMBOL(phys_base)
614 #include "../../x86/xen/xen-head.S"
617 SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
619 SYM_DATA_END(empty_zero_page)
620 EXPORT_SYMBOL(empty_zero_page)