1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
13 #include <linux/linkage.h>
14 #include <linux/threads.h>
15 #include <linux/init.h>
16 #include <asm/segment.h>
17 #include <asm/pgtable.h>
20 #include <asm/cache.h>
21 #include <asm/processor-flags.h>
22 #include <asm/percpu.h>
24 #include "../entry/calling.h"
25 #include <asm/export.h>
26 #include <asm/nospec-branch.h>
27 #include <asm/fixmap.h>
29 #ifdef CONFIG_PARAVIRT
30 #include <asm/asm-offsets.h>
31 #include <asm/paravirt.h>
32 #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
34 #define GET_CR2_INTO(reg) movq %cr2, reg
35 #define INTERRUPT_RETURN iretq
38 /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
39 * because we need identity-mapped pages.
43 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
45 #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
46 PGD_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE)
47 PGD_START_KERNEL = pgd_index(__START_KERNEL_map)
49 L3_START_KERNEL = pud_index(__START_KERNEL_map)
58 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
59 * and someone has loaded an identity mapped page table
60 * for us. These identity mapped page tables map all of the
61 * kernel pages and possibly all of memory.
63 * %rsi holds a physical pointer to real_mode_data.
65 * We come here either directly from a 64bit bootloader, or from
66 * arch/x86/boot/compressed/head_64.S.
68 * We only come here initially at boot nothing else comes here.
70 * Since we may be loaded at an address different from what we were
71 * compiled to run at we first fixup the physical addresses in our page
72 * tables and then reload them.
75 /* Set up the stack for verify_cpu(), similar to initial_stack below */
76 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
78 /* Sanitize CPU configuration */
82 * Perform pagetable fixups. Additionally, if SME is active, encrypt
83 * the kernel and retrieve the modifier (SME encryption mask if SME
84 * is active) to be added to the initial pgdir entry that will be
85 * programmed into CR3.
87 leaq _text(%rip), %rdi
92 /* Form the CR3 value being sure to include the CR3 modifier */
93 addq $(early_top_pgt - __START_KERNEL_map), %rax
95 ENTRY(secondary_startup_64)
98 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
99 * and someone has loaded a mapped page table.
101 * %rsi holds a physical pointer to real_mode_data.
103 * We come here either from startup_64 (using physical addresses)
104 * or from trampoline.S (using virtual addresses).
106 * Using virtual addresses from trampoline.S removes the need
107 * to have any identity mapped pages in the kernel page table
108 * after the boot processor executes this code.
111 /* Sanitize CPU configuration */
115 * Retrieve the modifier (SME encryption mask if SME is active) to be
116 * added to the initial pgdir entry that will be programmed into CR3.
119 call __startup_secondary_64
122 /* Form the CR3 value being sure to include the CR3 modifier */
123 addq $(init_top_pgt - __START_KERNEL_map), %rax
126 /* Enable PAE mode, PGE and LA57 */
127 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
128 #ifdef CONFIG_X86_5LEVEL
129 orl $X86_CR4_LA57, %ecx
133 /* Setup early boot stage 4-/5-level pagetables. */
134 addq phys_base(%rip), %rax
137 /* Ensure I am executing from virtual addresses */
139 ANNOTATE_RETPOLINE_SAFE
144 /* Check if nx is implemented */
145 movl $0x80000001, %eax
149 /* Setup EFER (Extended Feature Enable Register) */
152 btsl $_EFER_SCE, %eax /* Enable System Call */
153 btl $20,%edi /* No Execute supported? */
156 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
157 1: wrmsr /* Make changes effective */
160 movl $CR0_STATE, %eax
161 /* Make changes effective */
164 /* Setup a boot time stack */
165 movq initial_stack(%rip), %rsp
167 /* zero EFLAGS after setting rsp */
172 * We must switch to a new descriptor in kernel space for the GDT
173 * because soon the kernel won't have access anymore to the userspace
174 * addresses where we're currently running on. We have to do that here
175 * because in 32bit we couldn't load a 64bit linear address.
177 lgdt early_gdt_descr(%rip)
179 /* set up data segments */
186 * We don't really need to load %fs or %gs, but load them anyway
187 * to kill any stale realmode selectors. This allows execution
195 * The base of %gs always points to the bottom of the irqstack
196 * union. If the stack protector canary is enabled, it is
197 * located at %gs:40. Note that, on SMP, the boot cpu uses
198 * init data section till per cpu areas are set up.
200 movl $MSR_GS_BASE,%ecx
201 movl initial_gs(%rip),%eax
202 movl initial_gs+4(%rip),%edx
205 /* rsi is pointer to real mode structure with interesting info.
211 * Jump to run C code and to be on a real kernel address.
212 * Since we are running on identity-mapped space we have to jump
213 * to the full 64bit address, this is only possible as indirect
214 * jump. In addition we need to ensure %cs is set so we make this
217 * Note: do not change to far jump indirect with 64bit offset.
219 * AMD does not support far jump indirect with 64bit offset.
220 * AMD64 Architecture Programmer's Manual, Volume 3: states only
221 * JMP FAR mem16:16 FF /5 Far jump indirect,
222 * with the target specified by a far pointer in memory.
223 * JMP FAR mem16:32 FF /5 Far jump indirect,
224 * with the target specified by a far pointer in memory.
226 * Intel64 does support 64bit offset.
227 * Software Developer Manual Vol 2: states:
228 * FF /5 JMP m16:16 Jump far, absolute indirect,
229 * address given in m16:16
230 * FF /5 JMP m16:32 Jump far, absolute indirect,
231 * address given in m16:32.
232 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
233 * address given in m16:64.
235 pushq $.Lafter_lret # put return address on stack for unwinder
236 xorq %rbp, %rbp # clear frame pointer
237 movq initial_code(%rip), %rax
238 pushq $__KERNEL_CS # set correct cs
239 pushq %rax # target address in negative space
242 END(secondary_startup_64)
244 #include "verify_cpu.S"
246 #ifdef CONFIG_HOTPLUG_CPU
248 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
249 * up already except stack. We just set up stack here. Then call
250 * start_secondary() via .Ljump_to_C_code.
253 movq initial_stack(%rip), %rsp
259 /* Both SMP bootup and ACPI suspend change these variables */
263 .quad x86_64_start_kernel
265 .quad INIT_PER_CPU_VAR(irq_stack_union)
266 GLOBAL(initial_stack)
268 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel
269 * unwinder reliably detect the end of the stack.
271 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS
275 ENTRY(early_idt_handler_array)
277 .rept NUM_EXCEPTION_VECTORS
278 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
279 UNWIND_HINT_IRET_REGS
280 pushq $0 # Dummy error code, to make stack frame uniform
282 UNWIND_HINT_IRET_REGS offset=8
284 pushq $i # 72(%rsp) Vector number
285 jmp early_idt_handler_common
286 UNWIND_HINT_IRET_REGS
288 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
290 UNWIND_HINT_IRET_REGS offset=16
291 END(early_idt_handler_array)
293 early_idt_handler_common:
295 * The stack is the hardware frame, an error code or zero, and the
300 incl early_recursion_flag(%rip)
302 /* The vector number is currently in the pt_regs->di slot. */
303 pushq %rsi /* pt_regs->si */
304 movq 8(%rsp), %rsi /* RSI = vector number */
305 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
306 pushq %rdx /* pt_regs->dx */
307 pushq %rcx /* pt_regs->cx */
308 pushq %rax /* pt_regs->ax */
309 pushq %r8 /* pt_regs->r8 */
310 pushq %r9 /* pt_regs->r9 */
311 pushq %r10 /* pt_regs->r10 */
312 pushq %r11 /* pt_regs->r11 */
313 pushq %rbx /* pt_regs->bx */
314 pushq %rbp /* pt_regs->bp */
315 pushq %r12 /* pt_regs->r12 */
316 pushq %r13 /* pt_regs->r13 */
317 pushq %r14 /* pt_regs->r14 */
318 pushq %r15 /* pt_regs->r15 */
321 cmpq $14,%rsi /* Page fault? */
323 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
324 call early_make_pgtable
326 jz 20f /* All good */
329 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
330 call early_fixup_exception
333 decl early_recursion_flag(%rip)
334 jmp restore_regs_and_return_to_kernel
335 END(early_idt_handler_common)
340 GLOBAL(early_recursion_flag)
343 #define NEXT_PAGE(name) \
347 #ifdef CONFIG_PAGE_TABLE_ISOLATION
349 * Each PGD needs to be 8k long and 8k aligned. We do not
350 * ever go out to userspace with these, so we do not
351 * strictly *need* the second page, but this allows us to
352 * have a single set_pgd() implementation that does not
353 * need to worry about whether it has 4k or 8k to work
356 * This ensures PGDs are 8k long:
358 #define PTI_USER_PGD_FILL 512
359 /* This ensures they are 8k-aligned: */
360 #define NEXT_PGD_PAGE(name) \
361 .balign 2 * PAGE_SIZE; \
364 #define NEXT_PGD_PAGE(name) NEXT_PAGE(name)
365 #define PTI_USER_PGD_FILL 0
368 /* Automate the creation of 1 to 1 mapping pmd entries */
369 #define PMDS(START, PERM, COUNT) \
372 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
377 NEXT_PGD_PAGE(early_top_pgt)
379 #ifdef CONFIG_X86_5LEVEL
380 .quad level4_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
382 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
384 .fill PTI_USER_PGD_FILL,8,0
386 NEXT_PAGE(early_dynamic_pgts)
387 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
391 #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
392 NEXT_PGD_PAGE(init_top_pgt)
393 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
394 .org init_top_pgt + PGD_PAGE_OFFSET*8, 0
395 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
396 .org init_top_pgt + PGD_START_KERNEL*8, 0
397 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
398 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
399 .fill PTI_USER_PGD_FILL,8,0
401 NEXT_PAGE(level3_ident_pgt)
402 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
404 NEXT_PAGE(level2_ident_pgt)
405 /* Since I easily can, map the first 1G.
406 * Don't set NX because code runs from these pages.
408 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
410 NEXT_PGD_PAGE(init_top_pgt)
412 .fill PTI_USER_PGD_FILL,8,0
415 #ifdef CONFIG_X86_5LEVEL
416 NEXT_PAGE(level4_kernel_pgt)
418 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
421 NEXT_PAGE(level3_kernel_pgt)
422 .fill L3_START_KERNEL,8,0
423 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
424 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
425 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
427 NEXT_PAGE(level2_kernel_pgt)
429 * 512 MB kernel mapping. We spend a full page on this pagetable
432 * The kernel code+data+bss must not be bigger than that.
434 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
435 * If you want to increase this then increase MODULES_VADDR
438 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
439 KERNEL_IMAGE_SIZE/PMD_SIZE)
441 NEXT_PAGE(level2_fixmap_pgt)
442 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
444 .rept (FIXMAP_PMD_NUM)
445 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
449 /* 6 MB reserved space + a 2MB hole */
452 NEXT_PAGE(level1_fixmap_pgt)
453 .rept (FIXMAP_PMD_NUM)
461 .globl early_gdt_descr
463 .word GDT_ENTRIES*8-1
464 early_gdt_descr_base:
465 .quad INIT_PER_CPU_VAR(gdt_page)
468 /* This must match the first entry in level2_kernel_pgt */
469 .quad 0x0000000000000000
470 EXPORT_SYMBOL(phys_base)
472 #include "../../x86/xen/xen-head.S"
475 NEXT_PAGE(empty_zero_page)
477 EXPORT_SYMBOL(empty_zero_page)