2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
8 #include <asm/fpu/internal.h>
9 #include <asm/fpu/regset.h>
10 #include <asm/fpu/signal.h>
11 #include <asm/fpu/types.h>
12 #include <asm/traps.h>
13 #include <asm/irq_regs.h>
15 #include <linux/hardirq.h>
16 #include <linux/pkeys.h>
18 #define CREATE_TRACE_POINTS
19 #include <asm/trace/fpu.h>
22 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
23 * depending on the FPU hardware format:
25 union fpregs_state init_fpstate __read_mostly;
28 * Track whether the kernel is using the FPU state
33 * - by IRQ context code to potentially use the FPU
36 * - to debug kernel_fpu_begin()/end() correctness
38 static DEFINE_PER_CPU(bool, in_kernel_fpu);
41 * Track which context is using the FPU on the CPU:
43 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
45 static void kernel_fpu_disable(void)
47 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
48 this_cpu_write(in_kernel_fpu, true);
51 static void kernel_fpu_enable(void)
53 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
54 this_cpu_write(in_kernel_fpu, false);
57 static bool kernel_fpu_disabled(void)
59 return this_cpu_read(in_kernel_fpu);
62 static bool interrupted_kernel_fpu_idle(void)
64 return !kernel_fpu_disabled();
68 * Were we in user mode (or vm86 mode) when we were
71 * Doing kernel_fpu_begin/end() is ok if we are running
72 * in an interrupt context from user mode - we'll just
73 * save the FPU state as required.
75 static bool interrupted_user_mode(void)
77 struct pt_regs *regs = get_irq_regs();
78 return regs && user_mode(regs);
82 * Can we use the FPU in kernel mode with the
83 * whole "kernel_fpu_begin/end()" sequence?
85 * It's always ok in process context (ie "not interrupt")
86 * but it is sometimes ok even from an irq.
88 bool irq_fpu_usable(void)
90 return !in_interrupt() ||
91 interrupted_user_mode() ||
92 interrupted_kernel_fpu_idle();
94 EXPORT_SYMBOL(irq_fpu_usable);
96 void __kernel_fpu_begin(void)
98 struct fpu *fpu = ¤t->thread.fpu;
100 WARN_ON_FPU(!irq_fpu_usable());
102 kernel_fpu_disable();
104 if (fpu->fpregs_active) {
106 * Ignore return value -- we don't care if reg state
109 copy_fpregs_to_fpstate(fpu);
111 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
114 EXPORT_SYMBOL(__kernel_fpu_begin);
116 void __kernel_fpu_end(void)
118 struct fpu *fpu = ¤t->thread.fpu;
120 if (fpu->fpregs_active)
121 copy_kernel_to_fpregs(&fpu->state);
125 EXPORT_SYMBOL(__kernel_fpu_end);
127 void kernel_fpu_begin(void)
130 __kernel_fpu_begin();
132 EXPORT_SYMBOL_GPL(kernel_fpu_begin);
134 void kernel_fpu_end(void)
139 EXPORT_SYMBOL_GPL(kernel_fpu_end);
142 * CR0::TS save/restore functions:
144 int irq_ts_save(void)
147 * If in process context and not atomic, we can take a spurious DNA fault.
148 * Otherwise, doing clts() in process context requires disabling preemption
149 * or some heavy lifting like kernel_fpu_begin()
154 if (read_cr0() & X86_CR0_TS) {
161 EXPORT_SYMBOL_GPL(irq_ts_save);
163 void irq_ts_restore(int TS_state)
168 EXPORT_SYMBOL_GPL(irq_ts_restore);
171 * Save the FPU state (mark it for reload if necessary):
173 * This only ever gets called for the current task.
175 void fpu__save(struct fpu *fpu)
177 WARN_ON_FPU(fpu != ¤t->thread.fpu);
180 trace_x86_fpu_before_save(fpu);
181 if (fpu->fpregs_active) {
182 if (!copy_fpregs_to_fpstate(fpu)) {
183 copy_kernel_to_fpregs(&fpu->state);
186 trace_x86_fpu_after_save(fpu);
189 EXPORT_SYMBOL_GPL(fpu__save);
192 * Legacy x87 fpstate state init:
194 static inline void fpstate_init_fstate(struct fregs_state *fp)
196 fp->cwd = 0xffff037fu;
197 fp->swd = 0xffff0000u;
198 fp->twd = 0xffffffffu;
199 fp->fos = 0xffff0000u;
202 void fpstate_init(union fpregs_state *state)
204 if (!static_cpu_has(X86_FEATURE_FPU)) {
205 fpstate_init_soft(&state->soft);
209 memset(state, 0, fpu_kernel_xstate_size);
212 * XRSTORS requires that this bit is set in xcomp_bv, or
213 * it will #GP. Make sure it is replaced after the memset().
215 if (static_cpu_has(X86_FEATURE_XSAVES))
216 state->xsave.header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT |
219 if (static_cpu_has(X86_FEATURE_FXSR))
220 fpstate_init_fxstate(&state->fxsave);
222 fpstate_init_fstate(&state->fsave);
224 EXPORT_SYMBOL_GPL(fpstate_init);
226 int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
228 dst_fpu->fpregs_active = 0;
229 dst_fpu->last_cpu = -1;
231 if (!src_fpu->fpstate_active || !static_cpu_has(X86_FEATURE_FPU))
234 WARN_ON_FPU(src_fpu != ¤t->thread.fpu);
237 * Don't let 'init optimized' areas of the XSAVE area
238 * leak into the child task:
240 memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size);
243 * Save current FPU registers directly into the child
244 * FPU context, without any memory-to-memory copying.
245 * In lazy mode, if the FPU context isn't loaded into
246 * fpregs, CR0.TS will be set and do_device_not_available
247 * will load the FPU context.
249 * We have to do all this with preemption disabled,
250 * mostly because of the FNSAVE case, because in that
251 * case we must not allow preemption in the window
252 * between the FNSAVE and us marking the context lazy.
254 * It shouldn't be an issue as even FNSAVE is plenty
255 * fast in terms of critical section length.
258 if (!copy_fpregs_to_fpstate(dst_fpu)) {
259 memcpy(&src_fpu->state, &dst_fpu->state,
260 fpu_kernel_xstate_size);
262 copy_kernel_to_fpregs(&src_fpu->state);
266 trace_x86_fpu_copy_src(src_fpu);
267 trace_x86_fpu_copy_dst(dst_fpu);
273 * Activate the current task's in-memory FPU context,
274 * if it has not been used before:
276 void fpu__activate_curr(struct fpu *fpu)
278 WARN_ON_FPU(fpu != ¤t->thread.fpu);
280 if (!fpu->fpstate_active) {
281 fpstate_init(&fpu->state);
282 trace_x86_fpu_init_state(fpu);
284 trace_x86_fpu_activate_state(fpu);
285 /* Safe to do for the current task: */
286 fpu->fpstate_active = 1;
289 EXPORT_SYMBOL_GPL(fpu__activate_curr);
292 * This function must be called before we read a task's fpstate.
294 * If the task has not used the FPU before then initialize its
297 * If the task has used the FPU before then save it.
299 void fpu__activate_fpstate_read(struct fpu *fpu)
302 * If fpregs are active (in the current CPU), then
303 * copy them to the fpstate:
305 if (fpu->fpregs_active) {
308 if (!fpu->fpstate_active) {
309 fpstate_init(&fpu->state);
310 trace_x86_fpu_init_state(fpu);
312 trace_x86_fpu_activate_state(fpu);
313 /* Safe to do for current and for stopped child tasks: */
314 fpu->fpstate_active = 1;
320 * This function must be called before we write a task's fpstate.
322 * If the task has used the FPU before then unlazy it.
323 * If the task has not used the FPU before then initialize its fpstate.
325 * After this function call, after registers in the fpstate are
326 * modified and the child task has woken up, the child task will
327 * restore the modified FPU state from the modified context. If we
328 * didn't clear its lazy status here then the lazy in-registers
329 * state pending on its former CPU could be restored, corrupting
332 void fpu__activate_fpstate_write(struct fpu *fpu)
335 * Only stopped child tasks can be used to modify the FPU
336 * state in the fpstate buffer:
338 WARN_ON_FPU(fpu == ¤t->thread.fpu);
340 if (fpu->fpstate_active) {
341 /* Invalidate any lazy state: */
344 fpstate_init(&fpu->state);
345 trace_x86_fpu_init_state(fpu);
347 trace_x86_fpu_activate_state(fpu);
348 /* Safe to do for stopped child tasks: */
349 fpu->fpstate_active = 1;
354 * This function must be called before we write the current
357 * This call gets the current FPU register state and moves
358 * it in to the 'fpstate'. Preemption is disabled so that
359 * no writes to the 'fpstate' can occur from context
362 * Must be followed by a fpu__current_fpstate_write_end().
364 void fpu__current_fpstate_write_begin(void)
366 struct fpu *fpu = ¤t->thread.fpu;
369 * Ensure that the context-switching code does not write
370 * over the fpstate while we are doing our update.
375 * Move the fpregs in to the fpu's 'fpstate'.
377 fpu__activate_fpstate_read(fpu);
380 * The caller is about to write to 'fpu'. Ensure that no
381 * CPU thinks that its fpregs match the fpstate. This
382 * ensures we will not be lazy and skip a XRSTOR in the
389 * This function must be paired with fpu__current_fpstate_write_begin()
391 * This will ensure that the modified fpstate gets placed back in
392 * the fpregs if necessary.
394 * Note: This function may be called whether or not an _actual_
395 * write to the fpstate occurred.
397 void fpu__current_fpstate_write_end(void)
399 struct fpu *fpu = ¤t->thread.fpu;
402 * 'fpu' now has an updated copy of the state, but the
403 * registers may still be out of date. Update them with
404 * an XRSTOR if they are active.
407 copy_kernel_to_fpregs(&fpu->state);
410 * Our update is done and the fpregs/fpstate are in sync
411 * if necessary. Context switches can happen again.
417 * 'fpu__restore()' is called to copy FPU registers from
418 * the FPU fpstate to the live hw registers and to activate
419 * access to the hardware registers, so that FPU instructions
420 * can be used afterwards.
422 * Must be called with kernel preemption disabled (for example
423 * with local interrupts disabled, as it is in the case of
424 * do_device_not_available()).
426 void fpu__restore(struct fpu *fpu)
428 fpu__activate_curr(fpu);
430 /* Avoid __kernel_fpu_begin() right after fpregs_activate() */
431 kernel_fpu_disable();
432 trace_x86_fpu_before_restore(fpu);
433 fpregs_activate(fpu);
434 copy_kernel_to_fpregs(&fpu->state);
435 trace_x86_fpu_after_restore(fpu);
438 EXPORT_SYMBOL_GPL(fpu__restore);
441 * Drops current FPU state: deactivates the fpregs and
442 * the fpstate. NOTE: it still leaves previous contents
443 * in the fpregs in the eager-FPU case.
445 * This function can be used in cases where we know that
446 * a state-restore is coming: either an explicit one,
449 void fpu__drop(struct fpu *fpu)
453 if (fpu->fpregs_active) {
454 /* Ignore delayed exceptions from user space */
455 asm volatile("1: fwait\n"
457 _ASM_EXTABLE(1b, 2b));
458 fpregs_deactivate(fpu);
461 fpu->fpstate_active = 0;
463 trace_x86_fpu_dropped(fpu);
469 * Clear FPU registers by setting them up from
472 static inline void copy_init_fpstate_to_fpregs(void)
475 copy_kernel_to_xregs(&init_fpstate.xsave, -1);
476 else if (static_cpu_has(X86_FEATURE_FXSR))
477 copy_kernel_to_fxregs(&init_fpstate.fxsave);
479 copy_kernel_to_fregs(&init_fpstate.fsave);
481 if (boot_cpu_has(X86_FEATURE_OSPKE))
482 copy_init_pkru_to_fpregs();
486 * Clear the FPU state back to init state.
488 * Called by sys_execve(), by the signal handler code and by various
491 void fpu__clear(struct fpu *fpu)
493 WARN_ON_FPU(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */
498 * Make sure fpstate is cleared and initialized.
500 if (static_cpu_has(X86_FEATURE_FPU)) {
501 fpu__activate_curr(fpu);
503 copy_init_fpstate_to_fpregs();
508 * x87 math exception handling:
511 int fpu__exception_code(struct fpu *fpu, int trap_nr)
515 if (trap_nr == X86_TRAP_MF) {
516 unsigned short cwd, swd;
518 * (~cwd & swd) will mask out exceptions that are not set to unmasked
519 * status. 0x3f is the exception bits in these regs, 0x200 is the
520 * C1 reg you need in case of a stack fault, 0x040 is the stack
521 * fault bit. We should only be taking one exception at a time,
522 * so if this combination doesn't produce any single exception,
523 * then we have a bad program that isn't synchronizing its FPU usage
524 * and it will suffer the consequences since we won't be able to
525 * fully reproduce the context of the exception.
527 if (boot_cpu_has(X86_FEATURE_FXSR)) {
528 cwd = fpu->state.fxsave.cwd;
529 swd = fpu->state.fxsave.swd;
531 cwd = (unsigned short)fpu->state.fsave.cwd;
532 swd = (unsigned short)fpu->state.fsave.swd;
538 * The SIMD FPU exceptions are handled a little differently, as there
539 * is only a single status/control register. Thus, to determine which
540 * unmasked exception was caught we must mask the exception mask bits
541 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
543 unsigned short mxcsr = MXCSR_DEFAULT;
545 if (boot_cpu_has(X86_FEATURE_XMM))
546 mxcsr = fpu->state.fxsave.mxcsr;
548 err = ~(mxcsr >> 7) & mxcsr;
551 if (err & 0x001) { /* Invalid op */
553 * swd & 0x240 == 0x040: Stack Underflow
554 * swd & 0x240 == 0x240: Stack Overflow
555 * User must clear the SF bit (0x40) if set
558 } else if (err & 0x004) { /* Divide by Zero */
560 } else if (err & 0x008) { /* Overflow */
562 } else if (err & 0x012) { /* Denormal, Underflow */
564 } else if (err & 0x020) { /* Precision */
569 * If we're using IRQ 13, or supposedly even some trap
570 * X86_TRAP_MF implementations, it's possible
571 * we get a spurious trap, which is not an error.