2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
8 #include <asm/fpu/internal.h>
9 #include <asm/fpu/regset.h>
10 #include <asm/fpu/signal.h>
11 #include <asm/traps.h>
13 #include <linux/hardirq.h>
16 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
17 * depending on the FPU hardware format:
19 union fpregs_state init_fpstate __read_mostly;
22 * Track whether the kernel is using the FPU state
27 * - by IRQ context code to potentially use the FPU
30 * - to debug kernel_fpu_begin()/end() correctness
32 static DEFINE_PER_CPU(bool, in_kernel_fpu);
35 * Track which context is using the FPU on the CPU:
37 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
39 static void kernel_fpu_disable(void)
41 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
42 this_cpu_write(in_kernel_fpu, true);
45 static void kernel_fpu_enable(void)
47 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
48 this_cpu_write(in_kernel_fpu, false);
51 static bool kernel_fpu_disabled(void)
53 return this_cpu_read(in_kernel_fpu);
56 static bool interrupted_kernel_fpu_idle(void)
58 return !kernel_fpu_disabled();
62 * Were we in user mode (or vm86 mode) when we were
65 * Doing kernel_fpu_begin/end() is ok if we are running
66 * in an interrupt context from user mode - we'll just
67 * save the FPU state as required.
69 static bool interrupted_user_mode(void)
71 struct pt_regs *regs = get_irq_regs();
72 return regs && user_mode(regs);
76 * Can we use the FPU in kernel mode with the
77 * whole "kernel_fpu_begin/end()" sequence?
79 * It's always ok in process context (ie "not interrupt")
80 * but it is sometimes ok even from an irq.
82 bool irq_fpu_usable(void)
84 return !in_interrupt() ||
85 interrupted_user_mode() ||
86 interrupted_kernel_fpu_idle();
88 EXPORT_SYMBOL(irq_fpu_usable);
90 void __kernel_fpu_begin(void)
92 struct fpu *fpu = ¤t->thread.fpu;
94 WARN_ON_FPU(!irq_fpu_usable());
98 if (fpu->fpregs_active) {
100 * Ignore return value -- we don't care if reg state
103 copy_fpregs_to_fpstate(fpu);
105 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
108 EXPORT_SYMBOL(__kernel_fpu_begin);
110 void __kernel_fpu_end(void)
112 struct fpu *fpu = ¤t->thread.fpu;
114 if (fpu->fpregs_active)
115 copy_kernel_to_fpregs(&fpu->state);
119 EXPORT_SYMBOL(__kernel_fpu_end);
121 void kernel_fpu_begin(void)
124 __kernel_fpu_begin();
126 EXPORT_SYMBOL_GPL(kernel_fpu_begin);
128 void kernel_fpu_end(void)
133 EXPORT_SYMBOL_GPL(kernel_fpu_end);
136 * CR0::TS save/restore functions:
138 int irq_ts_save(void)
141 * If in process context and not atomic, we can take a spurious DNA fault.
142 * Otherwise, doing clts() in process context requires disabling preemption
143 * or some heavy lifting like kernel_fpu_begin()
148 if (read_cr0() & X86_CR0_TS) {
155 EXPORT_SYMBOL_GPL(irq_ts_save);
157 void irq_ts_restore(int TS_state)
162 EXPORT_SYMBOL_GPL(irq_ts_restore);
165 * Save the FPU state (mark it for reload if necessary):
167 * This only ever gets called for the current task.
169 void fpu__save(struct fpu *fpu)
171 WARN_ON_FPU(fpu != ¤t->thread.fpu);
174 if (fpu->fpregs_active) {
175 if (!copy_fpregs_to_fpstate(fpu)) {
176 copy_kernel_to_fpregs(&fpu->state);
181 EXPORT_SYMBOL_GPL(fpu__save);
184 * Legacy x87 fpstate state init:
186 static inline void fpstate_init_fstate(struct fregs_state *fp)
188 fp->cwd = 0xffff037fu;
189 fp->swd = 0xffff0000u;
190 fp->twd = 0xffffffffu;
191 fp->fos = 0xffff0000u;
194 void fpstate_init(union fpregs_state *state)
197 fpstate_init_soft(&state->soft);
201 memset(state, 0, xstate_size);
204 fpstate_init_fxstate(&state->fxsave);
206 fpstate_init_fstate(&state->fsave);
208 EXPORT_SYMBOL_GPL(fpstate_init);
211 * Copy the current task's FPU state to a new task's FPU context.
213 * In both the 'eager' and the 'lazy' case we save hardware registers
214 * directly to the destination buffer.
216 static void fpu_copy(struct fpu *dst_fpu, struct fpu *src_fpu)
218 WARN_ON_FPU(src_fpu != ¤t->thread.fpu);
221 * Don't let 'init optimized' areas of the XSAVE area
222 * leak into the child task:
224 memset(&dst_fpu->state.xsave, 0, xstate_size);
227 * Save current FPU registers directly into the child
228 * FPU context, without any memory-to-memory copying.
230 * If the FPU context got destroyed in the process (FNSAVE
231 * done on old CPUs) then copy it back into the source
232 * context and mark the current task for lazy restore.
234 * We have to do all this with preemption disabled,
235 * mostly because of the FNSAVE case, because in that
236 * case we must not allow preemption in the window
237 * between the FNSAVE and us marking the context lazy.
239 * It shouldn't be an issue as even FNSAVE is plenty
240 * fast in terms of critical section length.
243 if (!copy_fpregs_to_fpstate(dst_fpu)) {
244 memcpy(&src_fpu->state, &dst_fpu->state, xstate_size);
246 copy_kernel_to_fpregs(&src_fpu->state);
251 int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
253 dst_fpu->fpregs_active = 0;
254 dst_fpu->last_cpu = -1;
256 if (src_fpu->fpstate_active && cpu_has_fpu)
257 fpu_copy(dst_fpu, src_fpu);
263 * Activate the current task's in-memory FPU context,
264 * if it has not been used before:
266 void fpu__activate_curr(struct fpu *fpu)
268 WARN_ON_FPU(fpu != ¤t->thread.fpu);
270 if (!fpu->fpstate_active) {
271 fpstate_init(&fpu->state);
273 /* Safe to do for the current task: */
274 fpu->fpstate_active = 1;
277 EXPORT_SYMBOL_GPL(fpu__activate_curr);
280 * This function must be called before we read a task's fpstate.
282 * If the task has not used the FPU before then initialize its
285 * If the task has used the FPU before then save it.
287 void fpu__activate_fpstate_read(struct fpu *fpu)
290 * If fpregs are active (in the current CPU), then
291 * copy them to the fpstate:
293 if (fpu->fpregs_active) {
296 if (!fpu->fpstate_active) {
297 fpstate_init(&fpu->state);
299 /* Safe to do for current and for stopped child tasks: */
300 fpu->fpstate_active = 1;
306 * This function must be called before we write a task's fpstate.
308 * If the task has used the FPU before then unlazy it.
309 * If the task has not used the FPU before then initialize its fpstate.
311 * After this function call, after registers in the fpstate are
312 * modified and the child task has woken up, the child task will
313 * restore the modified FPU state from the modified context. If we
314 * didn't clear its lazy status here then the lazy in-registers
315 * state pending on its former CPU could be restored, corrupting
318 void fpu__activate_fpstate_write(struct fpu *fpu)
321 * Only stopped child tasks can be used to modify the FPU
322 * state in the fpstate buffer:
324 WARN_ON_FPU(fpu == ¤t->thread.fpu);
326 if (fpu->fpstate_active) {
327 /* Invalidate any lazy state: */
330 fpstate_init(&fpu->state);
332 /* Safe to do for stopped child tasks: */
333 fpu->fpstate_active = 1;
338 * 'fpu__restore()' is called to copy FPU registers from
339 * the FPU fpstate to the live hw registers and to activate
340 * access to the hardware registers, so that FPU instructions
341 * can be used afterwards.
343 * Must be called with kernel preemption disabled (for example
344 * with local interrupts disabled, as it is in the case of
345 * do_device_not_available()).
347 void fpu__restore(struct fpu *fpu)
349 fpu__activate_curr(fpu);
351 /* Avoid __kernel_fpu_begin() right after fpregs_activate() */
352 kernel_fpu_disable();
353 fpregs_activate(fpu);
354 copy_kernel_to_fpregs(&fpu->state);
357 EXPORT_SYMBOL_GPL(fpu__restore);
360 * Drops current FPU state: deactivates the fpregs and
361 * the fpstate. NOTE: it still leaves previous contents
362 * in the fpregs in the eager-FPU case.
364 * This function can be used in cases where we know that
365 * a state-restore is coming: either an explicit one,
368 void fpu__drop(struct fpu *fpu)
372 if (fpu->fpregs_active) {
373 /* Ignore delayed exceptions from user space */
374 asm volatile("1: fwait\n"
376 _ASM_EXTABLE(1b, 2b));
377 fpregs_deactivate(fpu);
380 fpu->fpstate_active = 0;
386 * Clear FPU registers by setting them up from
389 static inline void copy_init_fpstate_to_fpregs(void)
392 copy_kernel_to_xregs(&init_fpstate.xsave, -1);
393 else if (static_cpu_has(X86_FEATURE_FXSR))
394 copy_kernel_to_fxregs(&init_fpstate.fxsave);
396 copy_kernel_to_fregs(&init_fpstate.fsave);
400 * Clear the FPU state back to init state.
402 * Called by sys_execve(), by the signal handler code and by various
405 void fpu__clear(struct fpu *fpu)
407 WARN_ON_FPU(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */
409 if (!static_cpu_has(X86_FEATURE_FPU)) {
410 /* FPU state will be reallocated lazily at the first use. */
413 if (!fpu->fpstate_active) {
414 fpu__activate_curr(fpu);
417 copy_init_fpstate_to_fpregs();
422 * x87 math exception handling:
425 static inline unsigned short get_fpu_cwd(struct fpu *fpu)
428 return fpu->state.fxsave.cwd;
430 return (unsigned short)fpu->state.fsave.cwd;
434 static inline unsigned short get_fpu_swd(struct fpu *fpu)
437 return fpu->state.fxsave.swd;
439 return (unsigned short)fpu->state.fsave.swd;
443 static inline unsigned short get_fpu_mxcsr(struct fpu *fpu)
446 return fpu->state.fxsave.mxcsr;
448 return MXCSR_DEFAULT;
452 int fpu__exception_code(struct fpu *fpu, int trap_nr)
456 if (trap_nr == X86_TRAP_MF) {
457 unsigned short cwd, swd;
459 * (~cwd & swd) will mask out exceptions that are not set to unmasked
460 * status. 0x3f is the exception bits in these regs, 0x200 is the
461 * C1 reg you need in case of a stack fault, 0x040 is the stack
462 * fault bit. We should only be taking one exception at a time,
463 * so if this combination doesn't produce any single exception,
464 * then we have a bad program that isn't synchronizing its FPU usage
465 * and it will suffer the consequences since we won't be able to
466 * fully reproduce the context of the exception
468 cwd = get_fpu_cwd(fpu);
469 swd = get_fpu_swd(fpu);
474 * The SIMD FPU exceptions are handled a little differently, as there
475 * is only a single status/control register. Thus, to determine which
476 * unmasked exception was caught we must mask the exception mask bits
477 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
479 unsigned short mxcsr = get_fpu_mxcsr(fpu);
480 err = ~(mxcsr >> 7) & mxcsr;
483 if (err & 0x001) { /* Invalid op */
485 * swd & 0x240 == 0x040: Stack Underflow
486 * swd & 0x240 == 0x240: Stack Overflow
487 * User must clear the SF bit (0x40) if set
490 } else if (err & 0x004) { /* Divide by Zero */
492 } else if (err & 0x008) { /* Overflow */
494 } else if (err & 0x012) { /* Denormal, Underflow */
496 } else if (err & 0x020) { /* Precision */
501 * If we're using IRQ 13, or supposedly even some trap
502 * X86_TRAP_MF implementations, it's possible
503 * we get a spurious trap, which is not an error.