1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Transactional Synchronization Extensions (TSX) control.
5 * Copyright (C) 2019 Intel Corporation
8 * Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
11 #include <linux/cpufeature.h>
13 #include <asm/cmdline.h>
17 enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
19 void tsx_disable(void)
23 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
25 /* Force all transactions to immediately abort */
26 tsx |= TSX_CTRL_RTM_DISABLE;
29 * Ensure TSX support is not enumerated in CPUID.
30 * This is visible to userspace and will ensure they
31 * do not waste resources trying TSX transactions that
34 tsx |= TSX_CTRL_CPUID_CLEAR;
36 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
43 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
45 /* Enable the RTM feature in the cpu */
46 tsx &= ~TSX_CTRL_RTM_DISABLE;
49 * Ensure TSX support is enumerated in CPUID.
50 * This is visible to userspace and will ensure they
51 * can enumerate and use the TSX feature.
53 tsx &= ~TSX_CTRL_CPUID_CLEAR;
55 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
58 static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
60 if (boot_cpu_has_bug(X86_BUG_TAA))
61 return TSX_CTRL_DISABLE;
63 return TSX_CTRL_ENABLE;
66 void __init tsx_init(void)
72 * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
73 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
75 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
76 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
77 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
78 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
79 * tsx= cmdline requests will do nothing on CPUs without
80 * MSR_IA32_TSX_CTRL support.
82 if (!(x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR))
85 setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);
87 ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
89 if (!strcmp(arg, "on")) {
90 tsx_ctrl_state = TSX_CTRL_ENABLE;
91 } else if (!strcmp(arg, "off")) {
92 tsx_ctrl_state = TSX_CTRL_DISABLE;
93 } else if (!strcmp(arg, "auto")) {
94 tsx_ctrl_state = x86_get_tsx_auto_mode();
96 tsx_ctrl_state = TSX_CTRL_DISABLE;
97 pr_err("tsx: invalid option, defaulting to off\n");
100 /* tsx= not provided */
101 if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
102 tsx_ctrl_state = x86_get_tsx_auto_mode();
103 else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
104 tsx_ctrl_state = TSX_CTRL_DISABLE;
106 tsx_ctrl_state = TSX_CTRL_ENABLE;
109 if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
113 * tsx_disable() will change the state of the RTM and HLE CPUID
114 * bits. Clear them here since they are now expected to be not
117 setup_clear_cpu_cap(X86_FEATURE_RTM);
118 setup_clear_cpu_cap(X86_FEATURE_HLE);
119 } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
122 * HW defaults TSX to be enabled at bootup.
123 * We may still need the TSX enable support
124 * during init for special cases like
125 * kexec after TSX is disabled.
130 * tsx_enable() will change the state of the RTM and HLE CPUID
131 * bits. Force them here since they are now expected to be set.
133 setup_force_cpu_cap(X86_FEATURE_RTM);
134 setup_force_cpu_cap(X86_FEATURE_HLE);