1 // SPDX-License-Identifier: GPL-2.0
3 * local apic based NMI watchdog for various CPUs.
5 * This file also handles reservation of performance counters for coordination
8 * Note that these events normally don't tick when the CPU idles. This means
9 * the frequency varies with CPU load.
11 * Original code for K7/P6 written by Keith Owens
15 #include <linux/percpu.h>
16 #include <linux/export.h>
17 #include <linux/kernel.h>
18 #include <linux/bitops.h>
19 #include <linux/smp.h>
21 #include <linux/kprobes.h>
24 #include <asm/perf_event.h>
27 * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
28 * offset from MSR_P4_BSU_ESCR0.
30 * It will be the max for all platforms (for now)
32 #define NMI_MAX_COUNTER_BITS 66
35 * perfctr_nmi_owner tracks the ownership of the perfctr registers:
36 * evtsel_nmi_owner tracks the ownership of the event selection
37 * - different performance counters/ event selection may be reserved for
38 * different subsystems this reservation system just tries to coordinate
41 static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
42 static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
44 /* converts an msr to an appropriate reservation bit */
45 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
47 /* returns the bit offset of the performance counter register */
48 switch (boot_cpu_data.x86_vendor) {
49 case X86_VENDOR_HYGON:
51 if (msr >= MSR_F15H_PERF_CTR)
52 return (msr - MSR_F15H_PERF_CTR) >> 1;
53 return msr - MSR_K7_PERFCTR0;
54 case X86_VENDOR_INTEL:
55 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
56 return msr - MSR_ARCH_PERFMON_PERFCTR0;
58 switch (boot_cpu_data.x86) {
60 return msr - MSR_P6_PERFCTR0;
62 return msr - MSR_KNC_PERFCTR0;
64 return msr - MSR_P4_BPU_PERFCTR0;
67 case X86_VENDOR_ZHAOXIN:
68 case X86_VENDOR_CENTAUR:
69 return msr - MSR_ARCH_PERFMON_PERFCTR0;
75 * converts an msr to an appropriate reservation bit
76 * returns the bit offset of the event selection register
78 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
80 /* returns the bit offset of the event selection register */
81 switch (boot_cpu_data.x86_vendor) {
82 case X86_VENDOR_HYGON:
84 if (msr >= MSR_F15H_PERF_CTL)
85 return (msr - MSR_F15H_PERF_CTL) >> 1;
86 return msr - MSR_K7_EVNTSEL0;
87 case X86_VENDOR_INTEL:
88 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
89 return msr - MSR_ARCH_PERFMON_EVENTSEL0;
91 switch (boot_cpu_data.x86) {
93 return msr - MSR_P6_EVNTSEL0;
95 return msr - MSR_KNC_EVNTSEL0;
97 return msr - MSR_P4_BSU_ESCR0;
100 case X86_VENDOR_ZHAOXIN:
101 case X86_VENDOR_CENTAUR:
102 return msr - MSR_ARCH_PERFMON_EVENTSEL0;
108 int reserve_perfctr_nmi(unsigned int msr)
110 unsigned int counter;
112 counter = nmi_perfctr_msr_to_bit(msr);
113 /* register not managed by the allocator? */
114 if (counter > NMI_MAX_COUNTER_BITS)
117 if (!test_and_set_bit(counter, perfctr_nmi_owner))
121 EXPORT_SYMBOL(reserve_perfctr_nmi);
123 void release_perfctr_nmi(unsigned int msr)
125 unsigned int counter;
127 counter = nmi_perfctr_msr_to_bit(msr);
128 /* register not managed by the allocator? */
129 if (counter > NMI_MAX_COUNTER_BITS)
132 clear_bit(counter, perfctr_nmi_owner);
134 EXPORT_SYMBOL(release_perfctr_nmi);
136 int reserve_evntsel_nmi(unsigned int msr)
138 unsigned int counter;
140 counter = nmi_evntsel_msr_to_bit(msr);
141 /* register not managed by the allocator? */
142 if (counter > NMI_MAX_COUNTER_BITS)
145 if (!test_and_set_bit(counter, evntsel_nmi_owner))
149 EXPORT_SYMBOL(reserve_evntsel_nmi);
151 void release_evntsel_nmi(unsigned int msr)
153 unsigned int counter;
155 counter = nmi_evntsel_msr_to_bit(msr);
156 /* register not managed by the allocator? */
157 if (counter > NMI_MAX_COUNTER_BITS)
160 clear_bit(counter, evntsel_nmi_owner);
162 EXPORT_SYMBOL(release_evntsel_nmi);