1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/kaiser.h>
6 #include <asm/perf_event.h>
9 #include "perf_event.h"
12 DEFINE_PER_CPU_SHARED_ALIGNED_USER_MAPPED(struct debug_store, cpu_debug_store);
14 /* The size of a BTS record in bytes: */
15 #define BTS_RECORD_SIZE 24
17 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
18 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
19 #define PEBS_FIXUP_SIZE PAGE_SIZE
22 * pebs_record_32 for p4 and core not supported
24 struct pebs_record_32 {
32 union intel_x86_pebs_dse {
35 unsigned int ld_dse:4;
36 unsigned int ld_stlb_miss:1;
37 unsigned int ld_locked:1;
38 unsigned int ld_reserved:26;
41 unsigned int st_l1d_hit:1;
42 unsigned int st_reserved1:3;
43 unsigned int st_stlb_miss:1;
44 unsigned int st_locked:1;
45 unsigned int st_reserved2:26;
51 * Map PEBS Load Latency Data Source encodings to generic
52 * memory data source information
54 #define P(a, b) PERF_MEM_S(a, b)
55 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
56 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
58 /* Version for Sandy Bridge and later */
59 static u64 pebs_data_source[] = {
60 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
61 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
62 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
63 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
64 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
65 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
66 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
67 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
68 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
69 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
70 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
71 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
72 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
73 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
74 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
75 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
78 /* Patch up minor differences in the bits */
79 void __init intel_pmu_pebs_data_source_nhm(void)
81 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
82 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
83 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
86 static u64 precise_store_data(u64 status)
88 union intel_x86_pebs_dse dse;
89 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
95 * 1 = stored missed 2nd level TLB
97 * so it either hit the walker or the OS
98 * otherwise hit 2nd level TLB
100 if (dse.st_stlb_miss)
106 * bit 0: hit L1 data cache
107 * if not set, then all we know is that
116 * bit 5: Locked prefix
119 val |= P(LOCK, LOCKED);
124 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
126 union perf_mem_data_src dse;
128 dse.val = PERF_MEM_NA;
130 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
131 dse.mem_op = PERF_MEM_OP_STORE;
132 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
133 dse.mem_op = PERF_MEM_OP_LOAD;
136 * L1 info only valid for following events:
138 * MEM_UOPS_RETIRED.STLB_MISS_STORES
139 * MEM_UOPS_RETIRED.LOCK_STORES
140 * MEM_UOPS_RETIRED.SPLIT_STORES
141 * MEM_UOPS_RETIRED.ALL_STORES
143 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
145 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
147 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
152 static u64 load_latency_data(u64 status)
154 union intel_x86_pebs_dse dse;
156 int model = boot_cpu_data.x86_model;
157 int fam = boot_cpu_data.x86;
162 * use the mapping table for bit 0-3
164 val = pebs_data_source[dse.ld_dse];
167 * Nehalem models do not support TLB, Lock infos
169 if (fam == 0x6 && (model == 26 || model == 30
170 || model == 31 || model == 46)) {
171 val |= P(TLB, NA) | P(LOCK, NA);
176 * 0 = did not miss 2nd level TLB
177 * 1 = missed 2nd level TLB
179 if (dse.ld_stlb_miss)
180 val |= P(TLB, MISS) | P(TLB, L2);
182 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
185 * bit 5: locked prefix
188 val |= P(LOCK, LOCKED);
193 struct pebs_record_core {
197 u64 r8, r9, r10, r11;
198 u64 r12, r13, r14, r15;
201 struct pebs_record_nhm {
205 u64 r8, r9, r10, r11;
206 u64 r12, r13, r14, r15;
207 u64 status, dla, dse, lat;
211 * Same as pebs_record_nhm, with two additional fields.
213 struct pebs_record_hsw {
217 u64 r8, r9, r10, r11;
218 u64 r12, r13, r14, r15;
219 u64 status, dla, dse, lat;
220 u64 real_ip, tsx_tuning;
223 union hsw_tsx_tuning {
225 u32 cycles_last_block : 32,
228 instruction_abort : 1,
229 non_instruction_abort : 1,
238 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
240 /* Same as HSW, plus TSC */
242 struct pebs_record_skl {
246 u64 r8, r9, r10, r11;
247 u64 r12, r13, r14, r15;
248 u64 status, dla, dse, lat;
249 u64 real_ip, tsx_tuning;
253 void init_debug_store_on_cpu(int cpu)
255 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
260 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
261 (u32)((u64)(unsigned long)ds),
262 (u32)((u64)(unsigned long)ds >> 32));
265 void fini_debug_store_on_cpu(int cpu)
267 if (!per_cpu(cpu_hw_events, cpu).ds)
270 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
273 static DEFINE_PER_CPU(void *, insn_buffer);
275 static void *dsalloc(size_t size, gfp_t flags, int node)
277 #ifdef CONFIG_PAGE_TABLE_ISOLATION
278 unsigned int order = get_order(size);
282 page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
285 addr = (unsigned long)page_address(page);
286 if (kaiser_add_mapping(addr, size, __PAGE_KERNEL) < 0) {
287 __free_pages(page, order);
292 return kmalloc_node(size, flags | __GFP_ZERO, node);
296 static void dsfree(const void *buffer, size_t size)
298 #ifdef CONFIG_PAGE_TABLE_ISOLATION
301 kaiser_remove_mapping((unsigned long)buffer, size);
302 free_pages((unsigned long)buffer, get_order(size));
308 static int alloc_pebs_buffer(int cpu)
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
311 int node = cpu_to_node(cpu);
313 void *buffer, *ibuffer;
318 buffer = dsalloc(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
319 if (unlikely(!buffer))
323 * HSW+ already provides us the eventing ip; no need to allocate this
326 if (x86_pmu.intel_cap.pebs_format < 2) {
327 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
329 dsfree(buffer, x86_pmu.pebs_buffer_size);
332 per_cpu(insn_buffer, cpu) = ibuffer;
335 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
337 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
338 ds->pebs_index = ds->pebs_buffer_base;
339 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
340 max * x86_pmu.pebs_record_size;
345 static void release_pebs_buffer(int cpu)
347 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
349 if (!ds || !x86_pmu.pebs)
352 kfree(per_cpu(insn_buffer, cpu));
353 per_cpu(insn_buffer, cpu) = NULL;
355 dsfree((void *)(unsigned long)ds->pebs_buffer_base,
356 x86_pmu.pebs_buffer_size);
357 ds->pebs_buffer_base = 0;
360 static int alloc_bts_buffer(int cpu)
362 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
363 int node = cpu_to_node(cpu);
370 buffer = dsalloc(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
371 if (unlikely(!buffer)) {
372 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
376 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
379 ds->bts_buffer_base = (u64)(unsigned long)buffer;
380 ds->bts_index = ds->bts_buffer_base;
381 ds->bts_absolute_maximum = ds->bts_buffer_base +
382 max * BTS_RECORD_SIZE;
383 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
384 thresh * BTS_RECORD_SIZE;
389 static void release_bts_buffer(int cpu)
391 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
393 if (!ds || !x86_pmu.bts)
396 dsfree((void *)(unsigned long)ds->bts_buffer_base, BTS_BUFFER_SIZE);
397 ds->bts_buffer_base = 0;
400 static int alloc_ds_buffer(int cpu)
402 struct debug_store *ds = per_cpu_ptr(&cpu_debug_store, cpu);
404 memset(ds, 0, sizeof(*ds));
405 per_cpu(cpu_hw_events, cpu).ds = ds;
410 static void release_ds_buffer(int cpu)
412 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
417 per_cpu(cpu_hw_events, cpu).ds = NULL;
420 void release_ds_buffers(void)
424 if (!x86_pmu.bts && !x86_pmu.pebs)
428 for_each_online_cpu(cpu)
429 fini_debug_store_on_cpu(cpu);
431 for_each_possible_cpu(cpu) {
432 release_pebs_buffer(cpu);
433 release_bts_buffer(cpu);
434 release_ds_buffer(cpu);
439 void reserve_ds_buffers(void)
441 int bts_err = 0, pebs_err = 0;
444 x86_pmu.bts_active = 0;
445 x86_pmu.pebs_active = 0;
447 if (!x86_pmu.bts && !x86_pmu.pebs)
458 for_each_possible_cpu(cpu) {
459 if (alloc_ds_buffer(cpu)) {
464 if (!bts_err && alloc_bts_buffer(cpu))
467 if (!pebs_err && alloc_pebs_buffer(cpu))
470 if (bts_err && pebs_err)
475 for_each_possible_cpu(cpu)
476 release_bts_buffer(cpu);
480 for_each_possible_cpu(cpu)
481 release_pebs_buffer(cpu);
484 if (bts_err && pebs_err) {
485 for_each_possible_cpu(cpu)
486 release_ds_buffer(cpu);
488 if (x86_pmu.bts && !bts_err)
489 x86_pmu.bts_active = 1;
491 if (x86_pmu.pebs && !pebs_err)
492 x86_pmu.pebs_active = 1;
494 for_each_online_cpu(cpu)
495 init_debug_store_on_cpu(cpu);
505 struct event_constraint bts_constraint =
506 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
508 void intel_pmu_enable_bts(u64 config)
510 unsigned long debugctlmsr;
512 debugctlmsr = get_debugctlmsr();
514 debugctlmsr |= DEBUGCTLMSR_TR;
515 debugctlmsr |= DEBUGCTLMSR_BTS;
516 if (config & ARCH_PERFMON_EVENTSEL_INT)
517 debugctlmsr |= DEBUGCTLMSR_BTINT;
519 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
520 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
522 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
523 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
525 update_debugctlmsr(debugctlmsr);
528 void intel_pmu_disable_bts(void)
530 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
531 unsigned long debugctlmsr;
536 debugctlmsr = get_debugctlmsr();
539 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
540 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
542 update_debugctlmsr(debugctlmsr);
545 int intel_pmu_drain_bts_buffer(void)
547 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
548 struct debug_store *ds = cpuc->ds;
554 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
555 struct bts_record *at, *base, *top;
556 struct perf_output_handle handle;
557 struct perf_event_header header;
558 struct perf_sample_data data;
559 unsigned long skip = 0;
565 if (!x86_pmu.bts_active)
568 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
569 top = (struct bts_record *)(unsigned long)ds->bts_index;
574 memset(®s, 0, sizeof(regs));
576 ds->bts_index = ds->bts_buffer_base;
578 perf_sample_data_init(&data, 0, event->hw.last_period);
581 * BTS leaks kernel addresses in branches across the cpl boundary,
582 * such as traps or system calls, so unless the user is asking for
583 * kernel tracing (and right now it's not possible), we'd need to
584 * filter them out. But first we need to count how many of those we
585 * have in the current batch. This is an extra O(n) pass, however,
586 * it's much faster than the other one especially considering that
587 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
588 * alloc_bts_buffer()).
590 for (at = base; at < top; at++) {
592 * Note that right now *this* BTS code only works if
593 * attr::exclude_kernel is set, but let's keep this extra
594 * check here in case that changes.
596 if (event->attr.exclude_kernel &&
597 (kernel_ip(at->from) || kernel_ip(at->to)))
602 * Prepare a generic sample, i.e. fill in the invariant fields.
603 * We will overwrite the from and to address before we output
606 perf_prepare_sample(&header, &data, event, ®s);
608 if (perf_output_begin(&handle, event, header.size *
609 (top - base - skip)))
612 for (at = base; at < top; at++) {
613 /* Filter out any records that contain kernel addresses. */
614 if (event->attr.exclude_kernel &&
615 (kernel_ip(at->from) || kernel_ip(at->to)))
621 perf_output_sample(&handle, &header, &data, event);
624 perf_output_end(&handle);
626 /* There's new data available. */
627 event->hw.interrupts++;
628 event->pending_kill = POLL_IN;
632 static inline void intel_pmu_drain_pebs_buffer(void)
636 x86_pmu.drain_pebs(®s);
639 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
642 intel_pmu_drain_pebs_buffer();
648 struct event_constraint intel_core2_pebs_event_constraints[] = {
649 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
650 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
651 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
652 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
653 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
654 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
655 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
659 struct event_constraint intel_atom_pebs_event_constraints[] = {
660 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
661 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
662 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
663 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
664 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
668 struct event_constraint intel_slm_pebs_event_constraints[] = {
669 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
670 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
671 /* Allow all events as PEBS with no flags */
672 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
676 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
677 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
678 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
679 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
680 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
681 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
683 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
684 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
685 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
686 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
687 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
688 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
689 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
693 struct event_constraint intel_westmere_pebs_event_constraints[] = {
694 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
695 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
696 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
697 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
698 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
699 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
700 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
701 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
702 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
703 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
704 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
705 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
706 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
710 struct event_constraint intel_snb_pebs_event_constraints[] = {
711 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
712 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
713 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
714 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
715 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
716 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
717 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
718 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
719 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
720 /* Allow all events as PEBS with no flags */
721 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
725 struct event_constraint intel_ivb_pebs_event_constraints[] = {
726 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
727 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
728 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
729 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
730 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
731 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
732 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
733 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
734 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
735 /* Allow all events as PEBS with no flags */
736 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
740 struct event_constraint intel_hsw_pebs_event_constraints[] = {
741 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
742 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
743 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
744 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
745 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
746 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
747 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
748 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
749 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
750 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
751 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
752 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
753 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
754 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
755 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
756 /* Allow all events as PEBS with no flags */
757 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
761 struct event_constraint intel_skl_pebs_event_constraints[] = {
762 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
763 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
764 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
765 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
766 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
767 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
768 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
769 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
770 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
771 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
772 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
773 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
774 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
775 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
776 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
777 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
778 /* Allow all events as PEBS with no flags */
779 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
783 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
785 struct event_constraint *c;
787 if (!event->attr.precise_ip)
790 if (x86_pmu.pebs_constraints) {
791 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
792 if ((event->hw.config & c->cmask) == c->code) {
793 event->hw.flags |= c->flags;
799 return &emptyconstraint;
802 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
804 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
807 void intel_pmu_pebs_enable(struct perf_event *event)
809 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
810 struct hw_perf_event *hwc = &event->hw;
811 struct debug_store *ds = cpuc->ds;
815 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
817 first_pebs = !pebs_is_enabled(cpuc);
818 cpuc->pebs_enabled |= 1ULL << hwc->idx;
820 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
821 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
822 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
823 cpuc->pebs_enabled |= 1ULL << 63;
826 * When the event is constrained enough we can use a larger
827 * threshold and run the event with less frequent PMI.
829 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
830 threshold = ds->pebs_absolute_maximum -
831 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
834 perf_sched_cb_inc(event->ctx->pmu);
836 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
839 * If not all events can use larger buffer,
840 * roll back to threshold = 1
843 (ds->pebs_interrupt_threshold > threshold))
844 perf_sched_cb_dec(event->ctx->pmu);
847 /* Use auto-reload if possible to save a MSR write in the PMI */
848 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
849 ds->pebs_event_reset[hwc->idx] =
850 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
853 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
854 ds->pebs_interrupt_threshold = threshold;
857 void intel_pmu_pebs_disable(struct perf_event *event)
859 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
860 struct hw_perf_event *hwc = &event->hw;
861 struct debug_store *ds = cpuc->ds;
862 bool large_pebs = ds->pebs_interrupt_threshold >
863 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
866 intel_pmu_drain_pebs_buffer();
868 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
870 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
871 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
872 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
873 cpuc->pebs_enabled &= ~(1ULL << 63);
875 if (large_pebs && !pebs_is_enabled(cpuc))
876 perf_sched_cb_dec(event->ctx->pmu);
879 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
881 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
884 void intel_pmu_pebs_enable_all(void)
886 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
888 if (cpuc->pebs_enabled)
889 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
892 void intel_pmu_pebs_disable_all(void)
894 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
896 if (cpuc->pebs_enabled)
897 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
900 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
902 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
903 unsigned long from = cpuc->lbr_entries[0].from;
904 unsigned long old_to, to = cpuc->lbr_entries[0].to;
905 unsigned long ip = regs->ip;
911 * We don't need to fixup if the PEBS assist is fault like
913 if (!x86_pmu.intel_cap.pebs_trap)
917 * No LBR entry, no basic block, no rewinding
919 if (!cpuc->lbr_stack.nr || !from || !to)
923 * Basic blocks should never cross user/kernel boundaries
925 if (kernel_ip(ip) != kernel_ip(to))
929 * unsigned math, either ip is before the start (impossible) or
930 * the basic block is larger than 1 page (sanity)
932 if ((ip - to) > PEBS_FIXUP_SIZE)
936 * We sampled a branch insn, rewind using the LBR stack
939 set_linear_ip(regs, from);
944 if (!kernel_ip(ip)) {
946 u8 *buf = this_cpu_read(insn_buffer);
948 /* 'size' must fit our buffer, see above */
949 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
964 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
966 insn_init(&insn, kaddr, size, is_64bit);
967 insn_get_length(&insn);
969 * Make sure there was not a problem decoding the
970 * instruction and getting the length. This is
971 * doubly important because we have an infinite
972 * loop if insn.length=0.
978 kaddr += insn.length;
983 set_linear_ip(regs, old_to);
988 * Even though we decoded the basic block, the instruction stream
989 * never matched the given IP, either the TO or the IP got corrupted.
994 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
996 if (pebs->tsx_tuning) {
997 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
998 return tsx.cycles_last_block;
1003 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1005 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1007 /* For RTM XABORTs also log the abort code from AX */
1008 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1009 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1013 static void setup_pebs_sample_data(struct perf_event *event,
1014 struct pt_regs *iregs, void *__pebs,
1015 struct perf_sample_data *data,
1016 struct pt_regs *regs)
1018 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1019 (PERF_X86_EVENT_PEBS_ST_HSW | \
1020 PERF_X86_EVENT_PEBS_LD_HSW | \
1021 PERF_X86_EVENT_PEBS_NA_HSW)
1023 * We cast to the biggest pebs_record but are careful not to
1024 * unconditionally access the 'extra' entries.
1026 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1027 struct pebs_record_skl *pebs = __pebs;
1030 int fl = event->hw.flags;
1035 sample_type = event->attr.sample_type;
1036 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1038 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1039 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1041 perf_sample_data_init(data, 0, event->hw.last_period);
1043 data->period = event->hw.last_period;
1046 * Use latency for weight (only avail with PEBS-LL)
1048 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1049 data->weight = pebs->lat;
1052 * data.data_src encodes the data source
1055 u64 val = PERF_MEM_NA;
1057 val = load_latency_data(pebs->dse);
1058 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1059 val = precise_datala_hsw(event, pebs->dse);
1061 val = precise_store_data(pebs->dse);
1062 data->data_src.val = val;
1066 * We use the interrupt regs as a base because the PEBS record
1067 * does not contain a full regs set, specifically it seems to
1068 * lack segment descriptors, which get used by things like
1071 * In the simple case fix up only the IP and BP,SP regs, for
1072 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1073 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1076 regs->flags = pebs->flags;
1077 set_linear_ip(regs, pebs->ip);
1078 regs->bp = pebs->bp;
1079 regs->sp = pebs->sp;
1081 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1082 regs->ax = pebs->ax;
1083 regs->bx = pebs->bx;
1084 regs->cx = pebs->cx;
1085 regs->dx = pebs->dx;
1086 regs->si = pebs->si;
1087 regs->di = pebs->di;
1088 regs->bp = pebs->bp;
1089 regs->sp = pebs->sp;
1091 regs->flags = pebs->flags;
1092 #ifndef CONFIG_X86_32
1093 regs->r8 = pebs->r8;
1094 regs->r9 = pebs->r9;
1095 regs->r10 = pebs->r10;
1096 regs->r11 = pebs->r11;
1097 regs->r12 = pebs->r12;
1098 regs->r13 = pebs->r13;
1099 regs->r14 = pebs->r14;
1100 regs->r15 = pebs->r15;
1104 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1105 regs->ip = pebs->real_ip;
1106 regs->flags |= PERF_EFLAGS_EXACT;
1107 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1108 regs->flags |= PERF_EFLAGS_EXACT;
1110 regs->flags &= ~PERF_EFLAGS_EXACT;
1112 if ((sample_type & PERF_SAMPLE_ADDR) &&
1113 x86_pmu.intel_cap.pebs_format >= 1)
1114 data->addr = pebs->dla;
1116 if (x86_pmu.intel_cap.pebs_format >= 2) {
1117 /* Only set the TSX weight when no memory weight. */
1118 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1119 data->weight = intel_hsw_weight(pebs);
1121 if (sample_type & PERF_SAMPLE_TRANSACTION)
1122 data->txn = intel_hsw_transaction(pebs);
1126 * v3 supplies an accurate time stamp, so we use that
1127 * for the time stamp.
1129 * We can only do this for the default trace clock.
1131 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1132 event->attr.use_clockid == 0)
1133 data->time = native_sched_clock_from_tsc(pebs->tsc);
1135 if (has_branch_stack(event))
1136 data->br_stack = &cpuc->lbr_stack;
1139 static inline void *
1140 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1142 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1147 * fmt0 does not have a status bitfield (does not use
1148 * perf_record_nhm format)
1150 if (x86_pmu.intel_cap.pebs_format < 1)
1156 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1157 struct pebs_record_nhm *p = at;
1159 if (test_bit(bit, (unsigned long *)&p->status)) {
1160 /* PEBS v3 has accurate status bits */
1161 if (x86_pmu.intel_cap.pebs_format >= 3)
1164 if (p->status == (1 << bit))
1167 /* clear non-PEBS bit and re-check */
1168 pebs_status = p->status & cpuc->pebs_enabled;
1169 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1170 if (pebs_status == (1 << bit))
1177 static void __intel_pmu_pebs_event(struct perf_event *event,
1178 struct pt_regs *iregs,
1179 void *base, void *top,
1182 struct perf_sample_data data;
1183 struct pt_regs regs;
1184 void *at = get_next_pebs_record_by_bit(base, top, bit);
1186 if (!intel_pmu_save_and_restart(event) &&
1187 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1191 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1192 perf_event_output(event, &data, ®s);
1193 at += x86_pmu.pebs_record_size;
1194 at = get_next_pebs_record_by_bit(at, top, bit);
1198 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1201 * All but the last records are processed.
1202 * The last one is left to be able to call the overflow handler.
1204 if (perf_event_overflow(event, &data, ®s)) {
1205 x86_pmu_stop(event, 0);
1211 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1213 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1214 struct debug_store *ds = cpuc->ds;
1215 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1216 struct pebs_record_core *at, *top;
1219 if (!x86_pmu.pebs_active)
1222 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1223 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1226 * Whatever else happens, drain the thing
1228 ds->pebs_index = ds->pebs_buffer_base;
1230 if (!test_bit(0, cpuc->active_mask))
1233 WARN_ON_ONCE(!event);
1235 if (!event->attr.precise_ip)
1242 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1245 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1247 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1248 struct debug_store *ds = cpuc->ds;
1249 struct perf_event *event;
1250 void *base, *at, *top;
1251 short counts[MAX_PEBS_EVENTS] = {};
1252 short error[MAX_PEBS_EVENTS] = {};
1255 if (!x86_pmu.pebs_active)
1258 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1259 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1261 ds->pebs_index = ds->pebs_buffer_base;
1263 if (unlikely(base >= top))
1266 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1267 struct pebs_record_nhm *p = at;
1270 /* PEBS v3 has accurate status bits */
1271 if (x86_pmu.intel_cap.pebs_format >= 3) {
1272 for_each_set_bit(bit, (unsigned long *)&p->status,
1279 pebs_status = p->status & cpuc->pebs_enabled;
1280 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1282 bit = find_first_bit((unsigned long *)&pebs_status,
1283 x86_pmu.max_pebs_events);
1284 if (WARN(bit >= x86_pmu.max_pebs_events,
1285 "PEBS record without PEBS event! status=%Lx pebs_enabled=%Lx active_mask=%Lx",
1286 (unsigned long long)p->status, (unsigned long long)cpuc->pebs_enabled,
1287 *(unsigned long long *)cpuc->active_mask))
1291 * The PEBS hardware does not deal well with the situation
1292 * when events happen near to each other and multiple bits
1293 * are set. But it should happen rarely.
1295 * If these events include one PEBS and multiple non-PEBS
1296 * events, it doesn't impact PEBS record. The record will
1297 * be handled normally. (slow path)
1299 * If these events include two or more PEBS events, the
1300 * records for the events can be collapsed into a single
1301 * one, and it's not possible to reconstruct all events
1302 * that caused the PEBS record. It's called collision.
1303 * If collision happened, the record will be dropped.
1305 if (p->status != (1ULL << bit)) {
1306 for_each_set_bit(i, (unsigned long *)&pebs_status,
1307 x86_pmu.max_pebs_events)
1315 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1316 if ((counts[bit] == 0) && (error[bit] == 0))
1319 event = cpuc->events[bit];
1320 WARN_ON_ONCE(!event);
1321 WARN_ON_ONCE(!event->attr.precise_ip);
1323 /* log dropped samples number */
1325 perf_log_lost_samples(event, error[bit]);
1328 __intel_pmu_pebs_event(event, iregs, base,
1329 top, bit, counts[bit]);
1335 * BTS, PEBS probe and setup
1338 void __init intel_ds_init(void)
1341 * No support for 32bit formats
1343 if (!boot_cpu_has(X86_FEATURE_DTES64))
1346 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1347 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1348 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1350 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1351 int format = x86_pmu.intel_cap.pebs_format;
1355 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1356 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1358 * Using >PAGE_SIZE buffers makes the WRMSR to
1359 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1360 * mysteriously hang on Core2.
1362 * As a workaround, we don't do this.
1364 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1365 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1369 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1370 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1371 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1375 pr_cont("PEBS fmt2%c, ", pebs_type);
1376 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1377 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1381 pr_cont("PEBS fmt3%c, ", pebs_type);
1382 x86_pmu.pebs_record_size =
1383 sizeof(struct pebs_record_skl);
1384 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1385 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1389 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1395 void perf_restore_debug_store(void)
1397 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1399 if (!x86_pmu.bts && !x86_pmu.pebs)
1402 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);