1 // SPDX-License-Identifier: GPL-2.0-only
3 * HyperV Detection code.
5 * Copyright (C) 2010, Novell, Inc.
6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
9 #include <linux/types.h>
10 #include <linux/time.h>
11 #include <linux/clocksource.h>
12 #include <linux/init.h>
13 #include <linux/export.h>
14 #include <linux/hardirq.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kexec.h>
19 #include <linux/i8253.h>
20 #include <linux/random.h>
21 #include <linux/swiotlb.h>
22 #include <asm/processor.h>
23 #include <asm/hypervisor.h>
24 #include <asm/hyperv-tlfs.h>
25 #include <asm/mshyperv.h>
27 #include <asm/idtentry.h>
28 #include <asm/irq_regs.h>
29 #include <asm/i8259.h>
31 #include <asm/timer.h>
32 #include <asm/reboot.h>
34 #include <clocksource/hyperv_timer.h>
38 /* Is Linux running as the root partition? */
39 bool hv_root_partition;
40 struct ms_hyperv_info ms_hyperv;
42 #if IS_ENABLED(CONFIG_HYPERV)
43 static void (*vmbus_handler)(void);
44 static void (*hv_stimer0_handler)(void);
45 static void (*hv_kexec_handler)(void);
46 static void (*hv_crash_handler)(struct pt_regs *regs);
48 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)
50 struct pt_regs *old_regs = set_irq_regs(regs);
52 inc_irq_stat(irq_hv_callback_count);
56 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED)
59 set_irq_regs(old_regs);
62 void hv_setup_vmbus_handler(void (*handler)(void))
64 vmbus_handler = handler;
67 void hv_remove_vmbus_handler(void)
69 /* We have no way to deallocate the interrupt gate */
74 * Routines to do per-architecture handling of stimer0
75 * interrupts when in Direct Mode
77 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)
79 struct pt_regs *old_regs = set_irq_regs(regs);
81 inc_irq_stat(hyperv_stimer0_count);
82 if (hv_stimer0_handler)
84 add_interrupt_randomness(HYPERV_STIMER0_VECTOR);
87 set_irq_regs(old_regs);
90 /* For x86/x64, override weak placeholders in hyperv_timer.c */
91 void hv_setup_stimer0_handler(void (*handler)(void))
93 hv_stimer0_handler = handler;
96 void hv_remove_stimer0_handler(void)
98 /* We have no way to deallocate the interrupt gate */
99 hv_stimer0_handler = NULL;
102 void hv_setup_kexec_handler(void (*handler)(void))
104 hv_kexec_handler = handler;
107 void hv_remove_kexec_handler(void)
109 hv_kexec_handler = NULL;
112 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs))
114 hv_crash_handler = handler;
117 void hv_remove_crash_handler(void)
119 hv_crash_handler = NULL;
122 #ifdef CONFIG_KEXEC_CORE
123 static void hv_machine_shutdown(void)
125 if (kexec_in_progress && hv_kexec_handler)
129 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
130 * corrupts the old VP Assist Pages and can crash the kexec kernel.
132 if (kexec_in_progress && hyperv_init_cpuhp > 0)
133 cpuhp_remove_state(hyperv_init_cpuhp);
135 /* The function calls stop_other_cpus(). */
136 native_machine_shutdown();
138 /* Disable the hypercall page when there is only 1 active CPU. */
139 if (kexec_in_progress)
143 static void hv_machine_crash_shutdown(struct pt_regs *regs)
145 if (hv_crash_handler)
146 hv_crash_handler(regs);
148 /* The function calls crash_smp_send_stop(). */
149 native_machine_crash_shutdown(regs);
151 /* Disable the hypercall page when there is only 1 active CPU. */
154 #endif /* CONFIG_KEXEC_CORE */
155 #endif /* CONFIG_HYPERV */
157 static uint32_t __init ms_hyperv_platform(void)
160 u32 hyp_signature[3];
162 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
165 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS,
166 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]);
168 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX ||
169 memcmp("Microsoft Hv", hyp_signature, 12))
172 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */
173 eax = cpuid_eax(HYPERV_CPUID_FEATURES);
174 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) {
175 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n");
178 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) {
179 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n");
183 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
186 static unsigned char hv_get_nmi_reason(void)
191 #ifdef CONFIG_X86_LOCAL_APIC
193 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
194 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle
195 * unknown NMI on the first CPU which gets it.
197 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
199 static atomic_t nmi_cpu = ATOMIC_INIT(-1);
201 if (!unknown_nmi_panic)
204 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1)
211 static unsigned long hv_get_tsc_khz(void)
215 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
220 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV)
221 static void __init hv_smp_prepare_boot_cpu(void)
223 native_smp_prepare_boot_cpu();
224 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS)
229 static void __init hv_smp_prepare_cpus(unsigned int max_cpus)
236 native_smp_prepare_cpus(max_cpus);
239 for_each_present_cpu(i) {
242 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
246 for_each_present_cpu(i) {
249 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i);
256 static void __init ms_hyperv_init_platform(void)
258 int hv_max_functions_eax;
259 int hv_host_info_eax;
260 int hv_host_info_ebx;
261 int hv_host_info_ecx;
262 int hv_host_info_edx;
264 #ifdef CONFIG_PARAVIRT
265 pv_info.name = "Hyper-V";
269 * Extract the features and hints
271 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES);
272 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES);
273 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES);
274 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO);
276 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS);
278 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n",
279 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints,
280 ms_hyperv.misc_features);
282 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS);
283 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS);
285 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",
286 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
289 * Check CPU management privilege.
291 * To mirror what Windows does we should extract CPU management
292 * features and use the ReservedIdentityBit to detect if Linux is the
293 * root partition. But that requires negotiating CPU management
294 * interface (a process to be finalized).
296 * For now, use the privilege flag as the indicator for running as
299 if (cpuid_ebx(HYPERV_CPUID_FEATURES) & HV_CPU_MANAGEMENT) {
300 hv_root_partition = true;
301 pr_info("Hyper-V: running as root partition\n");
305 * Extract host information.
307 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) {
308 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION);
309 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION);
310 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION);
311 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION);
313 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n",
314 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF,
315 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF,
316 hv_host_info_ecx, hv_host_info_edx >> 24);
319 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
320 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
321 x86_platform.calibrate_tsc = hv_get_tsc_khz;
322 x86_platform.calibrate_cpu = hv_get_tsc_khz;
325 if (ms_hyperv.priv_high & HV_ISOLATION) {
326 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG);
327 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG);
328 ms_hyperv.shared_gpa_boundary =
329 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
331 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",
332 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b);
334 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) {
335 static_branch_enable(&isolation_type_snp);
336 #ifdef CONFIG_SWIOTLB
337 swiotlb_unencrypted_base = ms_hyperv.shared_gpa_boundary;
340 /* Isolation VMs are unenlightened SEV-based VMs, thus this check: */
341 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
342 if (hv_get_isolation_type() != HV_ISOLATION_TYPE_NONE)
343 cc_set_vendor(CC_VENDOR_HYPERV);
347 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) {
348 ms_hyperv.nested_features =
349 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES);
350 pr_info("Hyper-V: Nested features: 0x%x\n",
351 ms_hyperv.nested_features);
354 #ifdef CONFIG_X86_LOCAL_APIC
355 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
356 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
358 * Get the APIC frequency.
360 u64 hv_lapic_frequency;
362 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
363 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
364 lapic_timer_period = hv_lapic_frequency;
365 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
369 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST,
373 #ifdef CONFIG_X86_IO_APIC
377 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE)
378 machine_ops.shutdown = hv_machine_shutdown;
379 machine_ops.crash_shutdown = hv_machine_crash_shutdown;
381 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
383 * Writing to synthetic MSR 0x40000118 updates/changes the
384 * guest visible CPUIDs. Setting bit 0 of this MSR enables
385 * guests to report invariant TSC feature through CPUID
386 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
387 * early_init_intel() where this bit is examined. The
388 * setting of this MSR bit should happen before init_intel()
391 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
392 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
396 * Generation 2 instances don't support reading the NMI status from
399 if (efi_enabled(EFI_BOOT))
400 x86_platform.get_nmi_reason = hv_get_nmi_reason;
403 * Hyper-V VMs have a PIT emulation quirk such that zeroing the
404 * counter register during PIT shutdown restarts the PIT. So it
405 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter
406 * to false tells pit_shutdown() not to zero the counter so that
407 * the PIT really is shutdown. Generation 2 VMs don't have a PIT,
408 * and setting this value has no effect.
410 i8253_clear_counter_on_shutdown = false;
412 #if IS_ENABLED(CONFIG_HYPERV)
414 * Setup the hook to get control post apic initialization.
416 x86_platform.apic_post_init = hyperv_init;
417 hyperv_setup_mmu_ops();
418 /* Setup the IDT for hypervisor callback */
419 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback);
421 /* Setup the IDT for reenlightenment notifications */
422 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) {
423 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR,
424 asm_sysvec_hyperv_reenlightenment);
427 /* Setup the IDT for stimer0 */
428 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) {
429 alloc_intr_gate(HYPERV_STIMER0_VECTOR,
430 asm_sysvec_hyperv_stimer0);
434 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;
435 if (hv_root_partition)
436 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus;
440 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
441 * set x2apic destination mode to physical mode when x2apic is available
442 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs
443 * have 8-bit APIC id.
445 # ifdef CONFIG_X86_X2APIC
446 if (x2apic_supported())
450 /* Register Hyper-V specific clocksource */
451 hv_init_clocksource();
454 * TSC should be marked as unstable only after Hyper-V
455 * clocksource has been initialized. This ensures that the
456 * stability of the sched_clock is not altered.
458 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
459 mark_tsc_unstable("running on Hyper-V");
461 hardlockup_detector_disable();
464 static bool __init ms_hyperv_x2apic_available(void)
466 return x2apic_supported();
470 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping()
471 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
472 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
474 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which
475 * (logically) generates MSIs directly to the system APIC irq domain.
476 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
477 * pci-hyperv host bridge.
479 static bool __init ms_hyperv_msi_ext_dest_id(void)
483 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE);
484 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE)
487 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES);
488 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE;
491 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
492 .name = "Microsoft Hyper-V",
493 .detect = ms_hyperv_platform,
494 .type = X86_HYPER_MS_HYPERV,
495 .init.x2apic_available = ms_hyperv_x2apic_available,
496 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id,
497 .init.init_platform = ms_hyperv_init_platform,