2 * AMD CPU Microcode Update Driver for Linux
4 * This driver allows to upgrade microcode on F10h AMD
7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * Author: Peter Oruba <peter.oruba@amd.com>
12 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
15 * Copyright (C) 2013 Advanced Micro Devices, Inc.
17 * Author: Jacob Shin <jacob.shin@amd.com>
18 * Fixes: Borislav Petkov <bp@suse.de>
20 * Licensed under the terms of the GNU General Public
21 * License version 2. See file COPYING for details.
23 #define pr_fmt(fmt) "microcode: " fmt
25 #include <linux/earlycpio.h>
26 #include <linux/firmware.h>
27 #include <linux/uaccess.h>
28 #include <linux/vmalloc.h>
29 #include <linux/initrd.h>
30 #include <linux/kernel.h>
31 #include <linux/pci.h>
33 #include <asm/microcode_amd.h>
34 #include <asm/microcode.h>
35 #include <asm/processor.h>
36 #include <asm/setup.h>
40 static struct equiv_cpu_entry *equiv_cpu_table;
43 struct list_head plist;
49 static LIST_HEAD(pcache);
52 * This points to the current valid container of microcode patches which we will
53 * save from the initrd before jettisoning its contents.
56 static size_t container_size;
57 static bool ucode_builtin;
59 static u32 ucode_new_rev;
60 static u8 amd_ucode_patch[PATCH_MAX_SIZE];
61 static u16 this_equiv_id;
63 static struct cpio_data ucode_cpio;
65 static struct cpio_data __init find_ucode_in_initrd(void)
67 #ifdef CONFIG_BLK_DEV_INITRD
73 * Microcode patch container file is prepended to the initrd in cpio
74 * format. See Documentation/x86/early-microcode.txt
76 static __initdata char ucode_path[] = "/*(DEBLOBBED)*/";
79 struct boot_params *p;
82 * On 32-bit, early load occurs before paging is turned on so we need
83 * to use physical addresses.
85 p = (struct boot_params *)__pa_nodebug(&boot_params);
86 path = (char *)__pa_nodebug(ucode_path);
87 start = (void *)p->hdr.ramdisk_image;
88 size = p->hdr.ramdisk_size;
91 start = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
92 size = boot_params.hdr.ramdisk_size;
93 #endif /* !CONFIG_X86_32 */
95 return find_cpio_data(path, start, size, NULL);
97 return (struct cpio_data){ NULL, 0, "" };
101 static size_t compute_container_size(u8 *data, u32 total_size)
104 u32 *header = (u32 *)data;
106 if (header[0] != UCODE_MAGIC ||
107 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
108 header[2] == 0) /* size */
111 size = header[2] + CONTAINER_HDR_SZ;
118 header = (u32 *)data;
120 if (header[0] != UCODE_UCODE_TYPE)
124 * Sanity-check patch size.
126 patch_size = header[1];
127 if (patch_size > PATCH_MAX_SIZE)
130 size += patch_size + SECTION_HDR_SIZE;
131 data += patch_size + SECTION_HDR_SIZE;
132 total_size -= patch_size + SECTION_HDR_SIZE;
138 static enum ucode_state
139 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
142 * Early load occurs before we can vmalloc(). So we look for the microcode
143 * patch container file in initrd, traverse equivalent cpu table, look for a
144 * matching microcode patch, and update, all in initrd memory in place.
145 * When vmalloc() is available for use later -- on 64-bit during first AP load,
146 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
147 * load_microcode_amd() to save equivalent cpu table and microcode patches in
148 * kernel heap memory.
150 static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
152 struct equiv_cpu_entry *eq;
156 u8 (*patch)[PATCH_MAX_SIZE];
159 u32 rev, eax, ebx, ecx, edx;
163 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
164 cont_sz = (size_t *)__pa_nodebug(&container_size);
165 cont = (u8 **)__pa_nodebug(&container);
166 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
168 new_rev = &ucode_new_rev;
169 cont_sz = &container_size;
171 patch = &amd_ucode_patch;
176 header = (u32 *)data;
178 /* find equiv cpu table */
179 if (header[0] != UCODE_MAGIC ||
180 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
181 header[2] == 0) /* size */
186 native_cpuid(&eax, &ebx, &ecx, &edx);
189 eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
193 /* Advance past the container header */
194 offset = header[2] + CONTAINER_HDR_SZ;
198 eq_id = find_equiv_id(eq, eax);
200 this_equiv_id = eq_id;
201 *cont_sz = compute_container_size(*cont, left + offset);
204 * truncate how much we need to iterate over in the
205 * ucode update loop below
207 left = *cont_sz - offset;
212 * support multiple container files appended together. if this
213 * one does not have a matching equivalent cpu entry, we fast
214 * forward to the next container file.
217 header = (u32 *)data;
218 if (header[0] == UCODE_MAGIC &&
219 header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
222 offset = header[1] + SECTION_HDR_SIZE;
227 /* mark where the next microcode container file starts */
228 offset = data - (u8 *)ucode;
238 if (check_current_patch_level(&rev, true))
242 struct microcode_amd *mc;
244 header = (u32 *)data;
245 if (header[0] != UCODE_UCODE_TYPE || /* type */
246 header[1] == 0) /* size */
249 mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
251 if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
253 if (!__apply_microcode_amd(mc)) {
254 rev = mc->hdr.patch_id;
259 min_t(u32, header[1], PATCH_MAX_SIZE));
263 offset = header[1] + SECTION_HDR_SIZE;
269 static bool __init load_builtin_amd_microcode(struct cpio_data *cp,
273 char fw_name[36] = "/*(DEBLOBBED)*/";
276 snprintf(fw_name, sizeof(fw_name),
277 "/*(DEBLOBBED)*/", family);
279 return get_builtin_firmware(cp, fw_name);
285 void __init load_ucode_amd_bsp(unsigned int family)
293 data = (void **)__pa_nodebug(&ucode_cpio.data);
294 size = (size_t *)__pa_nodebug(&ucode_cpio.size);
295 builtin = (bool *)__pa_nodebug(&ucode_builtin);
297 data = &ucode_cpio.data;
298 size = &ucode_cpio.size;
299 builtin = &ucode_builtin;
302 *builtin = load_builtin_amd_microcode(&cp, family);
304 cp = find_ucode_in_initrd();
306 if (!(cp.data && cp.size))
312 apply_ucode_in_initrd(cp.data, cp.size, true);
317 * On 32-bit, since AP's early load occurs before paging is turned on, we
318 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
319 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
320 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
321 * which is used upon resume from suspend.
323 void load_ucode_amd_ap(void)
325 struct microcode_amd *mc;
329 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
330 if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
331 __apply_microcode_amd(mc);
335 ucode = (void *)__pa_nodebug(&container);
336 usize = (size_t *)__pa_nodebug(&container_size);
338 if (!*ucode || !*usize)
341 apply_ucode_in_initrd(*ucode, *usize, false);
344 static void __init collect_cpu_sig_on_bsp(void *arg)
346 unsigned int cpu = smp_processor_id();
347 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
349 uci->cpu_sig.sig = cpuid_eax(0x00000001);
352 static void __init get_bsp_sig(void)
354 unsigned int bsp = boot_cpu_data.cpu_index;
355 struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
357 if (!uci->cpu_sig.sig)
358 smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
361 void load_ucode_amd_ap(void)
363 unsigned int cpu = smp_processor_id();
364 struct equiv_cpu_entry *eq;
365 struct microcode_amd *mc;
366 u8 *cont = container;
370 /* Exit if called on the BSP. */
378 * 64-bit runs with paging enabled, thus early==false.
380 if (check_current_patch_level(&rev, false))
383 /* Add CONFIG_RANDOMIZE_MEMORY offset. */
385 cont += PAGE_OFFSET - __PAGE_OFFSET_BASE;
387 eax = cpuid_eax(0x00000001);
388 eq = (struct equiv_cpu_entry *)(cont + CONTAINER_HDR_SZ);
390 eq_id = find_equiv_id(eq, eax);
394 if (eq_id == this_equiv_id) {
395 mc = (struct microcode_amd *)amd_ucode_patch;
397 if (mc && rev < mc->hdr.patch_id) {
398 if (!__apply_microcode_amd(mc))
399 ucode_new_rev = mc->hdr.patch_id;
403 if (!ucode_cpio.data)
407 * AP has a different equivalence ID than BSP, looks like
408 * mixed-steppings silicon so go through the ucode blob anew.
410 apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
415 int __init save_microcode_in_initrd_amd(void)
419 enum ucode_state ret;
428 cont = (unsigned long)container;
429 cont_va = __va(container);
432 * We need the physical address of the container for both bitness since
433 * boot_params.hdr.ramdisk_image is a physical address.
435 cont = __pa_nodebug(container);
440 * Take into account the fact that the ramdisk might get relocated and
441 * therefore we need to recompute the container's position in virtual
444 if (relocated_ramdisk)
445 container = (u8 *)(__va(relocated_ramdisk) +
446 (cont - boot_params.hdr.ramdisk_image));
450 /* Add CONFIG_RANDOMIZE_MEMORY offset. */
452 container += PAGE_OFFSET - __PAGE_OFFSET_BASE;
454 eax = cpuid_eax(0x00000001);
455 eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
457 ret = load_microcode_amd(true, eax, container, container_size);
462 * This will be freed any msec now, stash patches for the current
463 * family and switch to patch cache for cpu hotplug, etc later.
471 void reload_ucode_amd(void)
473 struct microcode_amd *mc;
477 * early==false because this is a syscore ->resume path and by
478 * that time paging is long enabled.
480 if (check_current_patch_level(&rev, false))
483 mc = (struct microcode_amd *)amd_ucode_patch;
485 if (mc && rev < mc->hdr.patch_id) {
486 if (!__apply_microcode_amd(mc)) {
487 ucode_new_rev = mc->hdr.patch_id;
488 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
492 static u16 __find_equiv_id(unsigned int cpu)
494 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
495 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
498 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
502 BUG_ON(!equiv_cpu_table);
504 while (equiv_cpu_table[i].equiv_cpu != 0) {
505 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
506 return equiv_cpu_table[i].installed_cpu;
513 * a small, trivial cache of per-family ucode patches
515 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
517 struct ucode_patch *p;
519 list_for_each_entry(p, &pcache, plist)
520 if (p->equiv_cpu == equiv_cpu)
525 static void update_cache(struct ucode_patch *new_patch)
527 struct ucode_patch *p;
529 list_for_each_entry(p, &pcache, plist) {
530 if (p->equiv_cpu == new_patch->equiv_cpu) {
531 if (p->patch_id >= new_patch->patch_id)
532 /* we already have the latest patch */
535 list_replace(&p->plist, &new_patch->plist);
541 /* no patch found, add it */
542 list_add_tail(&new_patch->plist, &pcache);
545 static void free_cache(void)
547 struct ucode_patch *p, *tmp;
549 list_for_each_entry_safe(p, tmp, &pcache, plist) {
550 __list_del(p->plist.prev, p->plist.next);
556 static struct ucode_patch *find_patch(unsigned int cpu)
560 equiv_id = __find_equiv_id(cpu);
564 return cache_find_patch(equiv_id);
567 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
569 struct cpuinfo_x86 *c = &cpu_data(cpu);
570 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
571 struct ucode_patch *p;
573 csig->sig = cpuid_eax(0x00000001);
574 csig->rev = c->microcode;
577 * a patch could have been loaded early, set uci->mc so that
578 * mc_bp_resume() can call apply_microcode()
581 if (p && (p->patch_id == csig->rev))
584 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
589 static unsigned int verify_patch_size(u8 family, u32 patch_size,
594 #define F1XH_MPB_MAX_SIZE 2048
595 #define F14H_MPB_MAX_SIZE 1824
596 #define F15H_MPB_MAX_SIZE 4096
597 #define F16H_MPB_MAX_SIZE 3458
598 #define F17H_MPB_MAX_SIZE 3200
602 max_size = F14H_MPB_MAX_SIZE;
605 max_size = F15H_MPB_MAX_SIZE;
608 max_size = F16H_MPB_MAX_SIZE;
611 max_size = F17H_MPB_MAX_SIZE;
614 max_size = F1XH_MPB_MAX_SIZE;
618 if (patch_size > min_t(u32, size, max_size)) {
619 pr_err("patch size mismatch\n");
627 * Those patch levels cannot be updated to newer ones and thus should be final.
629 static u32 final_levels[] = {
633 0, /* T-101 terminator */
637 * Check the current patch level on this CPU.
639 * @rev: Use it to return the patch level. It is set to 0 in the case of
643 * - true: if update should stop
646 bool check_current_patch_level(u32 *rev, bool early)
652 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
654 if (IS_ENABLED(CONFIG_X86_32) && early)
655 levels = (u32 *)__pa_nodebug(&final_levels);
657 levels = final_levels;
659 for (i = 0; levels[i]; i++) {
660 if (lvl == levels[i]) {
673 int __apply_microcode_amd(struct microcode_amd *mc_amd)
677 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
679 /* verify patch application was successful */
680 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
681 if (rev != mc_amd->hdr.patch_id)
687 int apply_microcode_amd(int cpu)
689 struct cpuinfo_x86 *c = &cpu_data(cpu);
690 struct microcode_amd *mc_amd;
691 struct ucode_cpu_info *uci;
692 struct ucode_patch *p;
695 BUG_ON(raw_smp_processor_id() != cpu);
697 uci = ucode_cpu_info + cpu;
706 if (check_current_patch_level(&rev, false))
709 /* need to apply patch? */
710 if (rev >= mc_amd->hdr.patch_id)
713 if (__apply_microcode_amd(mc_amd)) {
714 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
715 cpu, mc_amd->hdr.patch_id);
719 rev = mc_amd->hdr.patch_id;
721 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
724 uci->cpu_sig.rev = rev;
727 /* Update boot_cpu_data's revision too, if we're on the BSP: */
728 if (c->cpu_index == boot_cpu_data.cpu_index)
729 boot_cpu_data.microcode = rev;
734 static int install_equiv_cpu_table(const u8 *buf)
736 unsigned int *ibuf = (unsigned int *)buf;
737 unsigned int type = ibuf[1];
738 unsigned int size = ibuf[2];
740 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
741 pr_err("empty section/"
742 "invalid type field in container file section header\n");
746 equiv_cpu_table = vmalloc(size);
747 if (!equiv_cpu_table) {
748 pr_err("failed to allocate equivalent CPU table\n");
752 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
754 /* add header length */
755 return size + CONTAINER_HDR_SZ;
758 static void free_equiv_cpu_table(void)
760 vfree(equiv_cpu_table);
761 equiv_cpu_table = NULL;
764 static void cleanup(void)
766 free_equiv_cpu_table();
771 * We return the current size even if some of the checks failed so that
772 * we can skip over the next patch. If we return a negative value, we
773 * signal a grave error like a memory allocation has failed and the
774 * driver cannot continue functioning normally. In such cases, we tear
775 * down everything we've used up so far and exit.
777 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
779 struct microcode_header_amd *mc_hdr;
780 struct ucode_patch *patch;
781 unsigned int patch_size, crnt_size, ret;
785 patch_size = *(u32 *)(fw + 4);
786 crnt_size = patch_size + SECTION_HDR_SIZE;
787 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
788 proc_id = mc_hdr->processor_rev_id;
790 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
792 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
796 /* check if patch is for the current family */
797 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
798 if (proc_fam != family)
801 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
802 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
807 ret = verify_patch_size(family, patch_size, leftover);
809 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
813 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
815 pr_err("Patch allocation failure.\n");
819 patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL);
821 pr_err("Patch data allocation failure.\n");
826 INIT_LIST_HEAD(&patch->plist);
827 patch->patch_id = mc_hdr->patch_id;
828 patch->equiv_cpu = proc_id;
830 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
831 __func__, patch->patch_id, proc_id);
833 /* ... and add to cache. */
839 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
842 enum ucode_state ret = UCODE_ERROR;
843 unsigned int leftover;
848 offset = install_equiv_cpu_table(data);
850 pr_err("failed to create equivalent cpu table\n");
854 leftover = size - offset;
856 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
857 pr_err("invalid type field in container file section header\n");
858 free_equiv_cpu_table();
863 crnt_size = verify_and_add_patch(family, fw, leftover);
868 leftover -= crnt_size;
874 static enum ucode_state
875 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
877 enum ucode_state ret;
879 /* free old equiv table */
880 free_equiv_cpu_table();
882 ret = __load_microcode_amd(family, data, size);
888 /* save BSP's matching patch for early load */
890 struct ucode_patch *p = find_patch(0);
892 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
893 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
902 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
905 char fw_name[36] = "/*(DEBLOBBED)*/";
906 struct cpuinfo_x86 *c = &cpu_data(cpu);
907 bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
908 enum ucode_state ret = UCODE_NFOUND;
909 const struct firmware *fw;
911 /* reload ucode container only on the boot cpu */
912 if (!refresh_fw || !bsp)
916 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", c->x86);
918 if (reject_firmware_direct(&fw, (const char *)fw_name, device)) {
919 pr_debug("failed to load file %s\n", fw_name);
924 if (*(u32 *)fw->data != UCODE_MAGIC) {
925 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
929 ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
932 release_firmware(fw);
938 static enum ucode_state
939 request_microcode_user(int cpu, const void __user *buf, size_t size)
944 static void microcode_fini_cpu_amd(int cpu)
946 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
951 static struct microcode_ops microcode_amd_ops = {
952 .request_microcode_user = request_microcode_user,
953 .request_microcode_fw = request_microcode_amd,
954 .collect_cpu_info = collect_cpu_info_amd,
955 .apply_microcode = apply_microcode_amd,
956 .microcode_fini_cpu = microcode_fini_cpu_amd,
959 struct microcode_ops * __init init_amd_microcode(void)
961 struct cpuinfo_x86 *c = &boot_cpu_data;
963 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
964 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
969 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
972 return µcode_amd_ops;
975 void __exit exit_amd_microcode(void)