2 * AMD CPU Microcode Update Driver for Linux
4 * This driver allows to upgrade microcode on F10h AMD
7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
8 * 2013-2016 Borislav Petkov <bp@alien8.de>
10 * Author: Peter Oruba <peter.oruba@amd.com>
13 * Tigran Aivazian <aivazian.tigran@gmail.com>
16 * Copyright (C) 2013 Advanced Micro Devices, Inc.
18 * Author: Jacob Shin <jacob.shin@amd.com>
19 * Fixes: Borislav Petkov <bp@suse.de>
21 * Licensed under the terms of the GNU General Public
22 * License version 2. See file COPYING for details.
24 #define pr_fmt(fmt) "microcode: " fmt
26 #include <linux/earlycpio.h>
27 #include <linux/firmware.h>
28 #include <linux/uaccess.h>
29 #include <linux/vmalloc.h>
30 #include <linux/initrd.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
34 #include <asm/microcode_amd.h>
35 #include <asm/microcode.h>
36 #include <asm/processor.h>
37 #include <asm/setup.h>
41 static struct equiv_cpu_entry *equiv_cpu_table;
44 * This points to the current valid container of microcode patches which we will
45 * save from the initrd/builtin before jettisoning its contents. @mc is the
46 * microcode patch we found to match.
49 struct microcode_amd *mc;
56 static u32 ucode_new_rev;
58 /* One blob per node. */
59 static u8 amd_ucode_patch[MAX_NUMNODES][PATCH_MAX_SIZE];
62 * Microcode patch container file is prepended to the initrd in cpio
63 * format. See Documentation/x86/early-microcode.txt
66 ucode_path[] __maybe_unused = "/*(DEBLOBBED)*/";
68 static u16 find_equiv_id(struct equiv_cpu_entry *equiv_table, u32 sig)
70 for (; equiv_table && equiv_table->installed_cpu; equiv_table++) {
71 if (sig == equiv_table->installed_cpu)
72 return equiv_table->equiv_cpu;
79 * This scans the ucode blob for the proper container as we can have multiple
80 * containers glued together. Returns the equivalence ID from the equivalence
81 * table or 0 if none found.
82 * Returns the amount of bytes consumed while scanning. @desc contains all the
83 * data we're going to use in later stages of the application.
85 static ssize_t parse_container(u8 *ucode, ssize_t size, struct cont_desc *desc)
87 struct equiv_cpu_entry *eq;
88 ssize_t orig_size = size;
89 u32 *hdr = (u32 *)ucode;
93 /* Am I looking at an equivalence table header? */
94 if (hdr[0] != UCODE_MAGIC ||
95 hdr[1] != UCODE_EQUIV_CPU_TABLE_TYPE ||
97 return CONTAINER_HDR_SZ;
101 eq = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
103 /* Find the equivalence ID of our CPU in this table: */
104 eq_id = find_equiv_id(eq, desc->cpuid_1_eax);
106 buf += hdr[2] + CONTAINER_HDR_SZ;
107 size -= hdr[2] + CONTAINER_HDR_SZ;
110 * Scan through the rest of the container to find where it ends. We do
111 * some basic sanity-checking too.
114 struct microcode_amd *mc;
119 if (hdr[0] != UCODE_UCODE_TYPE)
122 /* Sanity-check patch size. */
124 if (patch_size > PATCH_MAX_SIZE)
127 /* Skip patch section header: */
128 buf += SECTION_HDR_SIZE;
129 size -= SECTION_HDR_SIZE;
131 mc = (struct microcode_amd *)buf;
132 if (eq_id == mc->hdr.processor_rev_id) {
133 desc->psize = patch_size;
142 * If we have found a patch (desc->mc), it means we're looking at the
143 * container which has a patch for this CPU so return 0 to mean, @ucode
144 * already points to the proper container. Otherwise, we return the size
145 * we scanned so that we can advance to the next container in the
150 desc->size = orig_size - size;
155 return orig_size - size;
159 * Scan the ucode blob for the proper container as we can have multiple
160 * containers glued together.
162 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
167 ssize_t s = parse_container(ucode, rem, desc);
176 static int __apply_microcode_amd(struct microcode_amd *mc)
180 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code);
182 /* verify patch application was successful */
183 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
184 if (rev != mc->hdr.patch_id)
191 * Early load occurs before we can vmalloc(). So we look for the microcode
192 * patch container file in initrd, traverse equivalent cpu table, look for a
193 * matching microcode patch, and update, all in initrd memory in place.
194 * When vmalloc() is available for use later -- on 64-bit during first AP load,
195 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
196 * load_microcode_amd() to save equivalent cpu table and microcode patches in
197 * kernel heap memory.
199 * Returns true if container found (sets @desc), false otherwise.
202 apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch)
204 struct cont_desc desc = { 0 };
205 u8 (*patch)[PATCH_MAX_SIZE];
206 struct microcode_amd *mc;
207 u32 rev, dummy, *new_rev;
211 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
212 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
214 new_rev = &ucode_new_rev;
215 patch = &amd_ucode_patch[0];
218 desc.cpuid_1_eax = cpuid_1_eax;
220 scan_containers(ucode, size, &desc);
226 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
229 * Allow application of the same revision to pick up SMT-specific
230 * changes even if the revision of the other SMT thread is already
233 if (rev > mc->hdr.patch_id)
236 if (!__apply_microcode_amd(mc)) {
237 *new_rev = mc->hdr.patch_id;
241 memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE));
247 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family)
250 char fw_name[36] = "/*(DEBLOBBED)*/";
253 snprintf(fw_name, sizeof(fw_name),
254 "/*(DEBLOBBED)*/", family);
256 return get_builtin_firmware(cp, fw_name);
262 static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret)
264 struct ucode_cpu_info *uci;
269 if (IS_ENABLED(CONFIG_X86_32)) {
270 uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info);
271 path = (const char *)__pa_nodebug(ucode_path);
274 uci = ucode_cpu_info;
279 if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax)))
280 cp = find_microcode_in_initrd(path, use_pa);
282 /* Needed in load_microcode_amd() */
283 uci->cpu_sig.sig = cpuid_1_eax;
288 void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax)
290 struct cpio_data cp = { };
292 __load_ucode_amd(cpuid_1_eax, &cp);
293 if (!(cp.data && cp.size))
296 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, true);
299 void load_ucode_amd_ap(unsigned int cpuid_1_eax)
301 struct microcode_amd *mc;
303 u32 *new_rev, rev, dummy;
305 if (IS_ENABLED(CONFIG_X86_32)) {
306 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
307 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
309 mc = (struct microcode_amd *)amd_ucode_patch;
310 new_rev = &ucode_new_rev;
313 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
316 * Check whether a new patch has been saved already. Also, allow application of
317 * the same revision in order to pick up SMT-thread-specific configuration even
318 * if the sibling SMT thread already has an up-to-date revision.
320 if (*new_rev && rev <= mc->hdr.patch_id) {
321 if (!__apply_microcode_amd(mc)) {
322 *new_rev = mc->hdr.patch_id;
327 __load_ucode_amd(cpuid_1_eax, &cp);
328 if (!(cp.data && cp.size))
331 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false);
334 static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size);
336 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
338 struct cont_desc desc = { 0 };
339 enum ucode_state ret;
342 cp = find_microcode_in_initrd(ucode_path, false);
343 if (!(cp.data && cp.size))
346 desc.cpuid_1_eax = cpuid_1_eax;
348 scan_containers(cp.data, cp.size, &desc);
352 ret = load_microcode_amd(x86_family(cpuid_1_eax), desc.data, desc.size);
353 if (ret > UCODE_UPDATED)
359 void reload_ucode_amd(unsigned int cpu)
362 struct microcode_amd *mc;
364 mc = (struct microcode_amd *)amd_ucode_patch[cpu_to_node(cpu)];
366 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
368 if (rev < mc->hdr.patch_id) {
369 if (!__apply_microcode_amd(mc)) {
370 ucode_new_rev = mc->hdr.patch_id;
371 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
375 static u16 __find_equiv_id(unsigned int cpu)
377 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
378 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
381 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
385 BUG_ON(!equiv_cpu_table);
387 while (equiv_cpu_table[i].equiv_cpu != 0) {
388 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
389 return equiv_cpu_table[i].installed_cpu;
396 * a small, trivial cache of per-family ucode patches
398 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
400 struct ucode_patch *p;
402 list_for_each_entry(p, µcode_cache, plist)
403 if (p->equiv_cpu == equiv_cpu)
408 static void update_cache(struct ucode_patch *new_patch)
410 struct ucode_patch *p;
412 list_for_each_entry(p, µcode_cache, plist) {
413 if (p->equiv_cpu == new_patch->equiv_cpu) {
414 if (p->patch_id >= new_patch->patch_id) {
415 /* we already have the latest patch */
416 kfree(new_patch->data);
421 list_replace(&p->plist, &new_patch->plist);
427 /* no patch found, add it */
428 list_add_tail(&new_patch->plist, µcode_cache);
431 static void free_cache(void)
433 struct ucode_patch *p, *tmp;
435 list_for_each_entry_safe(p, tmp, µcode_cache, plist) {
436 __list_del(p->plist.prev, p->plist.next);
442 static struct ucode_patch *find_patch(unsigned int cpu)
446 equiv_id = __find_equiv_id(cpu);
450 return cache_find_patch(equiv_id);
453 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
455 struct cpuinfo_x86 *c = &cpu_data(cpu);
456 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
457 struct ucode_patch *p;
459 csig->sig = cpuid_eax(0x00000001);
460 csig->rev = c->microcode;
463 * a patch could have been loaded early, set uci->mc so that
464 * mc_bp_resume() can call apply_microcode()
467 if (p && (p->patch_id == csig->rev))
470 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
475 static unsigned int verify_patch_size(u8 family, u32 patch_size,
480 #define F1XH_MPB_MAX_SIZE 2048
481 #define F14H_MPB_MAX_SIZE 1824
482 #define F15H_MPB_MAX_SIZE 4096
483 #define F16H_MPB_MAX_SIZE 3458
484 #define F17H_MPB_MAX_SIZE 3200
488 max_size = F14H_MPB_MAX_SIZE;
491 max_size = F15H_MPB_MAX_SIZE;
494 max_size = F16H_MPB_MAX_SIZE;
497 max_size = F17H_MPB_MAX_SIZE;
500 max_size = F1XH_MPB_MAX_SIZE;
504 if (patch_size > min_t(u32, size, max_size)) {
505 pr_err("patch size mismatch\n");
512 static enum ucode_state apply_microcode_amd(int cpu)
514 struct cpuinfo_x86 *c = &cpu_data(cpu);
515 struct microcode_amd *mc_amd;
516 struct ucode_cpu_info *uci;
517 struct ucode_patch *p;
518 enum ucode_state ret;
521 BUG_ON(raw_smp_processor_id() != cpu);
523 uci = ucode_cpu_info + cpu;
532 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
534 /* need to apply patch? */
535 if (rev > mc_amd->hdr.patch_id) {
540 if (__apply_microcode_amd(mc_amd)) {
541 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
542 cpu, mc_amd->hdr.patch_id);
546 rev = mc_amd->hdr.patch_id;
549 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
552 uci->cpu_sig.rev = rev;
555 /* Update boot_cpu_data's revision too, if we're on the BSP: */
556 if (c->cpu_index == boot_cpu_data.cpu_index)
557 boot_cpu_data.microcode = rev;
562 static int install_equiv_cpu_table(const u8 *buf)
564 unsigned int *ibuf = (unsigned int *)buf;
565 unsigned int type = ibuf[1];
566 unsigned int size = ibuf[2];
568 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
569 pr_err("empty section/"
570 "invalid type field in container file section header\n");
574 equiv_cpu_table = vmalloc(size);
575 if (!equiv_cpu_table) {
576 pr_err("failed to allocate equivalent CPU table\n");
580 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
582 /* add header length */
583 return size + CONTAINER_HDR_SZ;
586 static void free_equiv_cpu_table(void)
588 vfree(equiv_cpu_table);
589 equiv_cpu_table = NULL;
592 static void cleanup(void)
594 free_equiv_cpu_table();
599 * We return the current size even if some of the checks failed so that
600 * we can skip over the next patch. If we return a negative value, we
601 * signal a grave error like a memory allocation has failed and the
602 * driver cannot continue functioning normally. In such cases, we tear
603 * down everything we've used up so far and exit.
605 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
607 struct microcode_header_amd *mc_hdr;
608 struct ucode_patch *patch;
609 unsigned int patch_size, crnt_size, ret;
613 patch_size = *(u32 *)(fw + 4);
614 crnt_size = patch_size + SECTION_HDR_SIZE;
615 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
616 proc_id = mc_hdr->processor_rev_id;
618 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
620 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
624 /* check if patch is for the current family */
625 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
626 if (proc_fam != family)
629 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
630 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
635 ret = verify_patch_size(family, patch_size, leftover);
637 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
641 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
643 pr_err("Patch allocation failure.\n");
647 patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL);
649 pr_err("Patch data allocation failure.\n");
654 INIT_LIST_HEAD(&patch->plist);
655 patch->patch_id = mc_hdr->patch_id;
656 patch->equiv_cpu = proc_id;
658 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
659 __func__, patch->patch_id, proc_id);
661 /* ... and add to cache. */
667 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
670 enum ucode_state ret = UCODE_ERROR;
671 unsigned int leftover;
676 offset = install_equiv_cpu_table(data);
678 pr_err("failed to create equivalent cpu table\n");
682 leftover = size - offset;
684 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
685 pr_err("invalid type field in container file section header\n");
686 free_equiv_cpu_table();
691 crnt_size = verify_and_add_patch(family, fw, leftover);
696 leftover -= crnt_size;
702 static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
704 struct cpuinfo_x86 *c;
705 unsigned int nid, cpu;
706 struct ucode_patch *p;
707 enum ucode_state ret;
709 /* free old equiv table */
710 free_equiv_cpu_table();
712 ret = __load_microcode_amd(family, data, size);
713 if (ret != UCODE_OK) {
719 cpu = cpumask_first(cpumask_of_node(nid));
726 if (c->microcode >= p->patch_id)
731 memset(&amd_ucode_patch[nid], 0, PATCH_MAX_SIZE);
732 memcpy(&amd_ucode_patch[nid], p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));
739 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
742 char fw_name[36] = "/*(DEBLOBBED)*/";
743 struct cpuinfo_x86 *c = &cpu_data(cpu);
744 enum ucode_state ret = UCODE_NFOUND;
745 const struct firmware *fw;
747 /* reload ucode container only on the boot cpu */
752 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", c->x86);
754 if (reject_firmware_direct(&fw, (const char *)fw_name, device)) {
755 pr_debug("failed to load file %s\n", fw_name);
760 if (*(u32 *)fw->data != UCODE_MAGIC) {
761 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
765 ret = load_microcode_amd(c->x86, fw->data, fw->size);
768 release_firmware(fw);
774 static enum ucode_state
775 request_microcode_user(int cpu, const void __user *buf, size_t size)
780 static void microcode_fini_cpu_amd(int cpu)
782 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
787 static struct microcode_ops microcode_amd_ops = {
788 .request_microcode_user = request_microcode_user,
789 .request_microcode_fw = request_microcode_amd,
790 .collect_cpu_info = collect_cpu_info_amd,
791 .apply_microcode = apply_microcode_amd,
792 .microcode_fini_cpu = microcode_fini_cpu_amd,
795 struct microcode_ops * __init init_amd_microcode(void)
797 struct cpuinfo_x86 *c = &boot_cpu_data;
799 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
800 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
805 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
808 return µcode_amd_ops;
811 void __exit exit_amd_microcode(void)